From 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Mon, 2 Mar 2015 05:04:20 -0500 Subject: [PATCH] stats: Update stats to reflect cache and interconnect changes This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU. --- .../ref/alpha/linux/tsunami-minor/stats.txt | 1493 ++-- .../ref/alpha/linux/tsunami-o3-dual/stats.txt | 3848 +++++----- .../ref/alpha/linux/tsunami-o3/stats.txt | 2079 +++--- .../linux/tsunami-switcheroo-full/stats.txt | 3027 ++++---- .../arm/linux/realview-minor-dual/stats.txt | 4418 ++++++------ .../ref/arm/linux/realview-minor/stats.txt | 1832 +++-- .../arm/linux/realview-o3-checker/stats.txt | 2532 ++++--- .../ref/arm/linux/realview-o3-dual/stats.txt | 5864 ++++++++------- .../ref/arm/linux/realview-o3/stats.txt | 2460 ++++--- .../linux/realview-switcheroo-full/stats.txt | 3756 +++++----- .../linux/realview-switcheroo-o3/stats.txt | 4062 ++++++----- .../realview-switcheroo-timing/stats.txt | 2795 ++++---- .../arm/linux/realview64-minor-dual/stats.txt | 4969 +++++++------ .../ref/arm/linux/realview64-minor/stats.txt | 2129 +++--- .../arm/linux/realview64-o3-checker/stats.txt | 2818 ++++---- .../arm/linux/realview64-o3-dual/stats.txt | 6279 ++++++++--------- .../ref/arm/linux/realview64-o3/stats.txt | 2704 ++++--- .../realview64-switcheroo-full/stats.txt | 4291 +++++------ .../linux/realview64-switcheroo-o3/stats.txt | 4414 ++++++------ .../realview64-switcheroo-timing/stats.txt | 3220 +++++---- .../ref/x86/linux/pc-o3-timing/stats.txt | 2555 ++++--- .../x86/linux/pc-switcheroo-full/stats.txt | 3105 ++++---- .../ref/arm/linux/minor-timing/stats.txt | 584 +- .../10.mcf/ref/arm/linux/o3-timing/stats.txt | 1595 +++-- .../ref/arm/linux/simple-atomic/stats.txt | 22 +- .../ref/arm/linux/simple-timing/stats.txt | 228 +- .../ref/sparc/linux/simple-timing/stats.txt | 466 +- .../10.mcf/ref/x86/linux/o3-timing/stats.txt | 1439 ++-- .../ref/x86/linux/simple-timing/stats.txt | 432 +- .../ref/alpha/tru64/minor-timing/stats.txt | 1034 +-- .../ref/arm/linux/minor-timing/stats.txt | 1050 +-- .../ref/arm/linux/o3-timing/stats.txt | 1628 ++--- .../ref/arm/linux/simple-atomic/stats.txt | 22 +- .../ref/arm/linux/simple-timing/stats.txt | 282 +- .../ref/x86/linux/o3-timing/stats.txt | 1657 ++--- .../ref/x86/linux/simple-timing/stats.txt | 452 +- .../ref/alpha/tru64/minor-timing/stats.txt | 500 +- .../ref/alpha/tru64/o3-timing/stats.txt | 1338 ++-- .../ref/alpha/tru64/simple-timing/stats.txt | 430 +- .../ref/arm/linux/minor-timing/stats.txt | 708 +- .../30.eon/ref/arm/linux/o3-timing/stats.txt | 1464 ++-- .../ref/arm/linux/simple-atomic/stats.txt | 22 +- .../ref/arm/linux/simple-timing/stats.txt | 250 +- .../ref/alpha/tru64/minor-timing/stats.txt | 730 +- .../ref/alpha/tru64/o3-timing/stats.txt | 1404 ++-- .../ref/alpha/tru64/simple-timing/stats.txt | 430 +- .../ref/arm/linux/minor-timing/stats.txt | 924 ++- .../ref/arm/linux/o3-timing/stats.txt | 1654 +++-- .../ref/arm/linux/simple-atomic/stats.txt | 22 +- .../ref/arm/linux/simple-timing/stats.txt | 228 +- .../ref/alpha/tru64/minor-timing/stats.txt | 991 ++- .../ref/alpha/tru64/o3-timing/stats.txt | 1573 +++-- .../ref/alpha/tru64/simple-timing/stats.txt | 462 +- .../ref/arm/linux/minor-timing/stats.txt | 976 ++- .../ref/arm/linux/o3-timing/stats.txt | 1668 ++--- .../ref/arm/linux/simple-atomic/stats.txt | 22 +- .../ref/arm/linux/simple-timing/stats.txt | 346 +- .../ref/sparc/linux/simple-timing/stats.txt | 492 +- .../ref/alpha/tru64/minor-timing/stats.txt | 1023 +-- .../ref/alpha/tru64/o3-timing/stats.txt | 1563 ++-- .../ref/alpha/tru64/simple-timing/stats.txt | 456 +- .../ref/arm/linux/minor-timing/stats.txt | 1039 ++- .../ref/arm/linux/o3-timing/stats.txt | 1682 +++-- .../ref/arm/linux/simple-atomic/stats.txt | 22 +- .../ref/arm/linux/simple-timing/stats.txt | 286 +- .../ref/x86/linux/simple-timing/stats.txt | 438 +- .../ref/alpha/tru64/minor-timing/stats.txt | 454 +- .../ref/alpha/tru64/o3-timing/stats.txt | 1337 ++-- .../ref/alpha/tru64/simple-timing/stats.txt | 430 +- .../ref/arm/linux/minor-timing/stats.txt | 720 +- .../ref/arm/linux/o3-timing/stats.txt | 1350 ++-- .../ref/arm/linux/simple-atomic/stats.txt | 22 +- .../ref/arm/linux/simple-timing/stats.txt | 224 +- .../ref/sparc/linux/simple-timing/stats.txt | 468 +- .../ref/x86/linux/o3-timing/stats.txt | 1347 ++-- .../ref/x86/linux/simple-timing/stats.txt | 432 +- .../tsunami-simple-timing-dual/stats.txt | 2772 ++++---- .../linux/tsunami-simple-timing/stats.txt | 1511 ++-- .../realview-simple-atomic-dual/stats.txt | 1342 ++-- .../linux/realview-simple-atomic/stats.txt | 410 +- .../realview-simple-timing-dual/stats.txt | 4460 ++++++------ .../linux/realview-simple-timing/stats.txt | 1799 +++-- .../realview-switcheroo-atomic/stats.txt | 760 +- .../realview64-simple-atomic-dual/stats.txt | 2202 +++--- .../linux/realview64-simple-atomic/stats.txt | 861 ++- .../realview64-simple-timing-dual/stats.txt | 5179 +++++++------- .../linux/realview64-simple-timing/stats.txt | 2190 +++--- .../realview64-switcheroo-atomic/stats.txt | 1399 ++-- .../ref/x86/linux/pc-simple-timing/stats.txt | 1994 +++--- .../ref/alpha/linux/minor-timing/stats.txt | 548 +- .../ref/alpha/linux/o3-timing/stats.txt | 1105 ++- .../ref/alpha/linux/simple-timing/stats.txt | 436 +- .../ref/alpha/tru64/minor-timing/stats.txt | 454 +- .../ref/alpha/tru64/o3-timing/stats.txt | 956 +-- .../ref/alpha/tru64/simple-timing/stats.txt | 438 +- .../ref/arm/linux/minor-timing/stats.txt | 507 +- .../ref/arm/linux/o3-timing-checker/stats.txt | 967 ++- .../ref/arm/linux/o3-timing/stats.txt | 1148 ++- .../simple-atomic-dummychecker/stats.txt | 20 +- .../ref/arm/linux/simple-atomic/stats.txt | 20 +- .../ref/arm/linux/simple-timing/stats.txt | 242 +- .../ref/mips/linux/o3-timing/stats.txt | 952 +-- .../ref/mips/linux/simple-timing/stats.txt | 438 +- .../ref/power/linux/o3-timing/stats.txt | 912 +-- .../ref/sparc/linux/simple-timing/stats.txt | 436 +- .../ref/x86/linux/o3-timing/stats.txt | 908 +-- .../ref/x86/linux/simple-timing/stats.txt | 440 +- .../ref/alpha/linux/o3-timing/stats.txt | 1416 ++-- .../ref/sparc/linux/o3-timing/stats.txt | 926 +-- .../ref/sparc/linux/simple-timing/stats.txt | 450 +- .../ref/sparc/linux/o3-timing-mp/stats.txt | 4607 ++++++------ .../sparc/linux/simple-timing-mp/stats.txt | 2904 ++++---- .../ref/null/none/memtest-filter/stats.txt | 3128 ++++---- .../ref/null/none/memtest/stats.txt | 3087 ++++---- .../ref/null/none/tgen-dram-ctrl/stats.txt | 126 +- 115 files changed, 84702 insertions(+), 85216 deletions(-) diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt index e432f371b..421497f85 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-minor/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.884236 # Number of seconds simulated -sim_ticks 1884235597000 # Number of ticks simulated -final_tick 1884235597000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.887184 # Number of seconds simulated +sim_ticks 1887184463000 # Number of ticks simulated +final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 167027 # Simulator instruction rate (inst/s) -host_op_rate 167027 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5607682389 # Simulator tick rate (ticks/s) -host_mem_usage 359752 # Number of bytes of host memory used -host_seconds 336.01 # Real time elapsed on the host -sim_insts 56122640 # Number of instructions simulated -sim_ops 56122640 # Number of ops (including micro ops) simulated +host_inst_rate 275099 # Simulator instruction rate (inst/s) +host_op_rate 275099 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9249537203 # Simulator tick rate (ticks/s) +host_mem_usage 373576 # Number of bytes of host memory used +host_seconds 204.03 # Real time elapsed on the host +sim_insts 56128524 # Number of instructions simulated +sim_ops 56128524 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 1053184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24861632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1052352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24860224 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25915776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1053184 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1053184 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7561856 # Number of bytes written to this memory -system.physmem.bytes_written::total 7561856 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 16456 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388463 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25913536 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1052352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1052352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7558400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7558400 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 16443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388441 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 404934 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118154 # Number of write requests responded to by this memory -system.physmem.num_writes::total 118154 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 558945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13194545 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 404899 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 118100 # Number of write requests responded to by this memory +system.physmem.num_writes::total 118100 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 557631 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13173182 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13754000 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 558945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 558945 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4013222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4013222 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4013222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 558945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13194545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13731321 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557631 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4005120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4005120 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4005120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13173182 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17767222 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 404934 # Number of read requests accepted -system.physmem.writeReqs 159706 # Number of write requests accepted -system.physmem.readBursts 404934 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159706 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25910208 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5568 # Total number of bytes read from write queue -system.physmem.bytesWritten 10081344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25915776 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10221184 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 87 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2165 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 154 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25481 # Per bank write bursts -system.physmem.perBankRdBursts::1 25742 # Per bank write bursts -system.physmem.perBankRdBursts::2 25839 # Per bank write bursts -system.physmem.perBankRdBursts::3 25784 # Per bank write bursts -system.physmem.perBankRdBursts::4 25228 # Per bank write bursts -system.physmem.perBankRdBursts::5 24953 # Per bank write bursts -system.physmem.perBankRdBursts::6 24817 # Per bank write bursts -system.physmem.perBankRdBursts::7 24560 # Per bank write bursts -system.physmem.perBankRdBursts::8 25102 # Per bank write bursts -system.physmem.perBankRdBursts::9 25274 # Per bank write bursts -system.physmem.perBankRdBursts::10 25530 # Per bank write bursts -system.physmem.perBankRdBursts::11 24856 # Per bank write bursts -system.physmem.perBankRdBursts::12 24523 # Per bank write bursts -system.physmem.perBankRdBursts::13 25574 # Per bank write bursts -system.physmem.perBankRdBursts::14 25845 # Per bank write bursts +system.physmem.bw_total::total 17736441 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 404899 # Number of read requests accepted +system.physmem.writeReqs 159652 # Number of write requests accepted +system.physmem.readBursts 404899 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue +system.physmem.bytesWritten 8556800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25922 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25492 # Per bank write bursts +system.physmem.perBankRdBursts::1 25732 # Per bank write bursts +system.physmem.perBankRdBursts::2 25844 # Per bank write bursts +system.physmem.perBankRdBursts::3 25788 # Per bank write bursts +system.physmem.perBankRdBursts::4 25096 # Per bank write bursts +system.physmem.perBankRdBursts::5 25019 # Per bank write bursts +system.physmem.perBankRdBursts::6 24724 # Per bank write bursts +system.physmem.perBankRdBursts::7 24556 # Per bank write bursts +system.physmem.perBankRdBursts::8 25196 # Per bank write bursts +system.physmem.perBankRdBursts::9 25300 # Per bank write bursts +system.physmem.perBankRdBursts::10 25394 # Per bank write bursts +system.physmem.perBankRdBursts::11 24993 # Per bank write bursts +system.physmem.perBankRdBursts::12 24525 # Per bank write bursts +system.physmem.perBankRdBursts::13 25570 # Per bank write bursts +system.physmem.perBankRdBursts::14 25834 # Per bank write bursts system.physmem.perBankRdBursts::15 25739 # Per bank write bursts -system.physmem.perBankWrBursts::0 10323 # Per bank write bursts -system.physmem.perBankWrBursts::1 10094 # Per bank write bursts -system.physmem.perBankWrBursts::2 10597 # Per bank write bursts -system.physmem.perBankWrBursts::3 9998 # Per bank write bursts -system.physmem.perBankWrBursts::4 9794 # Per bank write bursts -system.physmem.perBankWrBursts::5 9430 # Per bank write bursts -system.physmem.perBankWrBursts::6 9122 # Per bank write bursts -system.physmem.perBankWrBursts::7 8746 # Per bank write bursts -system.physmem.perBankWrBursts::8 9866 # Per bank write bursts -system.physmem.perBankWrBursts::9 8965 # Per bank write bursts -system.physmem.perBankWrBursts::10 9841 # Per bank write bursts -system.physmem.perBankWrBursts::11 9391 # Per bank write bursts -system.physmem.perBankWrBursts::12 9895 # Per bank write bursts -system.physmem.perBankWrBursts::13 10602 # Per bank write bursts -system.physmem.perBankWrBursts::14 10396 # Per bank write bursts -system.physmem.perBankWrBursts::15 10461 # Per bank write bursts +system.physmem.perBankWrBursts::0 8904 # Per bank write bursts +system.physmem.perBankWrBursts::1 8550 # Per bank write bursts +system.physmem.perBankWrBursts::2 9125 # Per bank write bursts +system.physmem.perBankWrBursts::3 8822 # Per bank write bursts +system.physmem.perBankWrBursts::4 8179 # Per bank write bursts +system.physmem.perBankWrBursts::5 8016 # Per bank write bursts +system.physmem.perBankWrBursts::6 7555 # Per bank write bursts +system.physmem.perBankWrBursts::7 7379 # Per bank write bursts +system.physmem.perBankWrBursts::8 8271 # Per bank write bursts +system.physmem.perBankWrBursts::9 7751 # Per bank write bursts +system.physmem.perBankWrBursts::10 8147 # Per bank write bursts +system.physmem.perBankWrBursts::11 7873 # Per bank write bursts +system.physmem.perBankWrBursts::12 8188 # Per bank write bursts +system.physmem.perBankWrBursts::13 9058 # Per bank write bursts +system.physmem.perBankWrBursts::14 9003 # Per bank write bursts +system.physmem.perBankWrBursts::15 8879 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1884226862500 # Total gap between requests +system.physmem.numWrRetry 49 # Number of times write queue was full causing retry +system.physmem.totGap 1887175688500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 404934 # Read request sizes (log2) +system.physmem.readPktSize::6 404899 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159706 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 402541 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 69 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159652 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 402512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -148,193 +148,182 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10844 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11832 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10697 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 258 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65747 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 547.425008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 336.336786 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.790126 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14590 22.19% 22.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10813 16.45% 38.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4856 7.39% 46.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3188 4.85% 50.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2531 3.85% 54.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1959 2.98% 57.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1455 2.21% 59.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1675 2.55% 62.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24680 37.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65747 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5741 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.518028 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2788.038880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5738 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5540 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5633 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5486 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5467 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5831 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6092 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7561 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6436 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1622 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1975 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 531.935916 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 325.040765 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 415.485108 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10955 16.91% 39.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3097 4.78% 52.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2483 3.83% 56.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1877 2.90% 59.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1493 2.30% 61.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1431 2.21% 64.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 82.608776 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3017.174786 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4897 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5741 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5741 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.437903 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.774518 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.753883 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4686 81.62% 81.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 175 3.05% 84.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 305 5.31% 89.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 60 1.05% 91.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 91 1.59% 92.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 55 0.96% 93.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 13 0.23% 93.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 10 0.17% 93.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 19 0.33% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 5 0.09% 94.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 16 0.28% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 10 0.17% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 11 0.19% 95.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 3 0.05% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 17 0.30% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 40 0.70% 96.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 20 0.35% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 16 0.28% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 94 1.64% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 33 0.57% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 16 0.28% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 17 0.30% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 9 0.16% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.09% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5741 # Writes before turning the bus around for reads -system.physmem.totQLat 2143675250 # Total ticks spent queuing -system.physmem.totMemAccLat 9734556500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2024235000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5295.03 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.285714 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.337905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 63.692079 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 11 0.22% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 6 0.12% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 26 0.53% 97.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 25 0.51% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 16 0.33% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 2 0.04% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 6 0.12% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 21 0.43% 99.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 2 0.04% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 6 0.12% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 7 0.14% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 9 0.18% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 5 0.10% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads +system.physmem.totQLat 2145870750 # Total ticks spent queuing +system.physmem.totMemAccLat 9735908250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5301.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24045.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.75 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.35 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.75 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.42 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24051.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.41 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.52 # Average write queue length when enqueuing -system.physmem.readRowHits 364210 # Number of row buffer hits during reads -system.physmem.writeRowHits 132411 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.05 # Row buffer hit rate for writes -system.physmem.avgGap 3337041.06 # Average gap between requests -system.physmem.pageHitRate 88.31 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 243152280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132672375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1578751200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 506113920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 59789504475 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1078093355250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1263412526700 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.517914 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1793297401750 # Time in different power states -system.physmem_0.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing +system.physmem.readRowHits 363622 # Number of row buffer hits during reads +system.physmem.writeRowHits 110090 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes +system.physmem.avgGap 3342790.44 # Average gap between requests +system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 238971600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 130391250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 431114400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 60578040195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1079167578750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1265384866875 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.517315 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1795079554966 # Time in different power states +system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28017727000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29080496284 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 253895040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 138534000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1579055400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 514622160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 123068977200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 60612218820 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1077371684250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1263538986870 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.585024 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1792097761500 # Time in different power states -system.physmem_1.memoryStateTime::REF 62918700000 # Time in different power states +system.physmem_1.actEnergy 250840800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136867500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 435261600 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 61601133195 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1078270137000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1265535350775 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.597050 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1793586337716 # Time in different power states +system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29217381000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30573727284 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 15006303 # Number of BP lookups -system.cpu.branchPred.condPredicted 13014667 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 375459 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9787101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5202858 # Number of BTB hits +system.cpu.branchPred.lookups 15007831 # Number of BP lookups +system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9968114 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 53.160359 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 808926 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 32598 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 52.204971 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9241313 # DTB read hits -system.cpu.dtb.read_misses 17796 # DTB read misses +system.cpu.dtb.read_hits 9242509 # DTB read hits +system.cpu.dtb.read_misses 17824 # DTB read misses system.cpu.dtb.read_acv 211 # DTB read access violations -system.cpu.dtb.read_accesses 766310 # DTB read accesses -system.cpu.dtb.write_hits 6385986 # DTB write hits -system.cpu.dtb.write_misses 2327 # DTB write misses -system.cpu.dtb.write_acv 160 # DTB write access violations -system.cpu.dtb.write_accesses 298447 # DTB write accesses -system.cpu.dtb.data_hits 15627299 # DTB hits -system.cpu.dtb.data_misses 20123 # DTB misses -system.cpu.dtb.data_acv 371 # DTB access violations -system.cpu.dtb.data_accesses 1064757 # DTB accesses -system.cpu.itb.fetch_hits 4016976 # ITB hits -system.cpu.itb.fetch_misses 6883 # ITB misses -system.cpu.itb.fetch_acv 674 # ITB acv -system.cpu.itb.fetch_accesses 4023859 # ITB accesses +system.cpu.dtb.read_accesses 766347 # DTB read accesses +system.cpu.dtb.write_hits 6385998 # DTB write hits +system.cpu.dtb.write_misses 2322 # DTB write misses +system.cpu.dtb.write_acv 159 # DTB write access violations +system.cpu.dtb.write_accesses 298454 # DTB write accesses +system.cpu.dtb.data_hits 15628507 # DTB hits +system.cpu.dtb.data_misses 20146 # DTB misses +system.cpu.dtb.data_acv 370 # DTB access violations +system.cpu.dtb.data_accesses 1064801 # DTB accesses +system.cpu.itb.fetch_hits 4019475 # ITB hits +system.cpu.itb.fetch_misses 6849 # ITB misses +system.cpu.itb.fetch_acv 693 # ITB acv +system.cpu.itb.fetch_accesses 4026324 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -347,39 +336,39 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 175257245 # number of cpu cycles simulated +system.cpu.numCycles 180833283 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56122640 # Number of instructions committed -system.cpu.committedOps 56122640 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2496382 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 5595 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 3593213949 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 3.122755 # CPI: cycles per instruction -system.cpu.ipc 0.320230 # IPC: instructions per cycle +system.cpu.committedInsts 56128524 # Number of instructions committed +system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed +system.cpu.discardedOps 2493053 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 3593535643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 3.221772 # CPI: cycles per instruction +system.cpu.ipc 0.310388 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6377 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211475 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74790 40.94% 40.94% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211489 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74799 40.94% 40.94% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.01% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1901 1.04% 42.05% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105864 57.95% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182686 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73423 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105874 57.95% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182705 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73432 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73423 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148878 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1833807390500 97.32% 97.32% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 80545000 0.00% 97.33% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 673176000 0.04% 97.36% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 49673506000 2.64% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1884234617500 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981722 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1834551091000 97.21% 97.21% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 51875728000 2.75% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693560 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814939 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.693579 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814953 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -415,115 +404,115 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::swpctx 4170 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175527 91.22% 93.43% # number of callpals executed -system.cpu.kern.callpal::rdps 6804 3.54% 96.96% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed +system.cpu.kern.callpal::swpipl 175546 91.23% 93.43% # number of callpals executed +system.cpu.kern.callpal::rdps 6805 3.54% 96.96% # number of callpals executed +system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::rti 5126 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192413 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5870 # number of protection mode switches -system.cpu.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1910 -system.cpu.kern.mode_good::user 1740 -system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.325383 # fraction of useful protection mode switches +system.cpu.kern.callpal::total 192427 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5873 # number of protection mode switches +system.cpu.kern.mode_switch::user 1739 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2089 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1906 +system.cpu.kern.mode_good::user 1739 +system.cpu.kern.mode_good::idle 167 +system.cpu.kern.mode_switch_good::kernel 0.324536 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.393490 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 36258202500 1.92% 1.92% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 4079939000 0.22% 2.14% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1843896466000 97.86% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.tickCycles 84474734 # Number of cycles that the object actually ticked -system.cpu.idleCycles 90782511 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1395383 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.982334 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 13772439 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1395895 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.866386 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 86820250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.982334 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999965 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 36591764000 1.94% 1.94% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 4134630500 0.22% 2.16% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1846457071000 97.84% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4171 # number of times the context was actually changed +system.cpu.tickCycles 84552258 # Number of cycles that the object actually ticked +system.cpu.idleCycles 96281025 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1395325 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 13774282 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1395837 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.868116 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999964 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 231 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63656284 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63656284 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7814297 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7814297 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5576378 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5576378 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 182732 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 182732 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 198999 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 198999 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13390675 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13390675 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13390675 # number of overall hits -system.cpu.dcache.overall_hits::total 13390675 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1201640 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1201640 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 573763 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 573763 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17288 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17288 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1775403 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1775403 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1775403 # number of overall misses -system.cpu.dcache.overall_misses::total 1775403 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31034654250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31034654250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20679395543 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20679395543 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 231275750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 231275750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 51714049793 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 51714049793 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 51714049793 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 51714049793 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9015937 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9015937 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6150141 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6150141 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200020 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200020 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 198999 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15166078 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15166078 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15166078 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15166078 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133280 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133280 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093293 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.093293 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086431 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086431 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117064 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117064 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117064 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117064 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25826.915091 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 25826.915091 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36041.702834 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36041.702834 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13377.819875 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13377.819875 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29128.062639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29128.062639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29128.062639 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63660758 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63660758 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7815437 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815437 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5576995 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5576995 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182818 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 198995 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 198995 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13392432 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13392432 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13392432 # number of overall hits +system.cpu.dcache.overall_hits::total 13392432 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1201539 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1201539 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 573249 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 573249 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17197 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17197 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1774788 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1774788 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1774788 # number of overall misses +system.cpu.dcache.overall_misses::total 1774788 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32999838250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32999838250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22461596052 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22461596052 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 230671750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 230671750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 55461434302 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 55461434302 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 55461434302 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 55461434302 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9016976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9016976 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6150244 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200015 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200015 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 198995 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 198995 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15167220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15167220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15167220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15167220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.093208 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.093208 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085979 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085979 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117015 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117015 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117015 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27464.641805 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 27464.641805 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39182.965957 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39182.965957 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31249.610828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.610828 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31249.610828 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,64 +521,64 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 838265 # number of writebacks -system.cpu.dcache.writebacks::total 838265 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127268 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 127268 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 269487 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 269487 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 838171 # number of writebacks +system.cpu.dcache.writebacks::total 838171 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 127108 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 127108 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268996 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 268996 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 396755 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 396755 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 396755 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 396755 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074372 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1074372 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304276 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304276 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17285 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17285 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1378648 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1378648 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1378648 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1378648 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26917637000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26917637000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10249005096 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10249005096 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196537750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196537750 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 37166642096 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 37166642096 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 37166642096 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 37166642096 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423897500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423897500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2002909000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2002909000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3426806500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3426806500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119164 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119164 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049475 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049475 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086416 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086416 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090903 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.090903 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090903 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.090903 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25054.298697 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25054.298697 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33683.251706 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33683.251706 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11370.422332 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11370.422332 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26958.761117 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26958.761117 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26958.761117 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 396104 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 396104 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1074431 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1074431 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304253 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304253 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17194 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17194 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1378684 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1378684 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1378684 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1378684 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29341442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29341442500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11237495843 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11237495843 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 204691750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 204691750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40578938343 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40578938343 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40578938343 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40578938343 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433304500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433304500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2018255500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2018255500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3451560000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3451560000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049470 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085964 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085964 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090899 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090899 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27308.819738 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27308.819738 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36934.708427 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36934.708427 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.835989 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.835989 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29433.095868 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29433.095868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29433.095868 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29433.095868 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -597,58 +586,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1459474 # number of replacements -system.cpu.icache.tags.tagsinuse 509.626385 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 18964719 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1459985 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12.989667 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31607466250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.626385 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.995364 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.995364 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1459080 # number of replacements +system.cpu.icache.tags.tagsinuse 509.440068 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 18968295 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1459591 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12.995623 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 33851094250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.440068 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.995000 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.995000 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 399 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 21885040 # Number of tag accesses -system.cpu.icache.tags.data_accesses 21885040 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 18964722 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 18964722 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 18964722 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 18964722 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 18964722 # number of overall hits -system.cpu.icache.overall_hits::total 18964722 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1460159 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1460159 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1460159 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1460159 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1460159 # number of overall misses -system.cpu.icache.overall_misses::total 1460159 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20038728384 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20038728384 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20038728384 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20038728384 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20038728384 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20038728384 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 20424881 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 20424881 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 20424881 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 20424881 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 20424881 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 20424881 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071489 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.071489 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.071489 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.071489 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.071489 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.071489 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13723.661864 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13723.661864 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13723.661864 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13723.661864 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13723.661864 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13723.661864 # average overall miss latency +system.cpu.icache.tags.tag_accesses 21887836 # Number of tag accesses +system.cpu.icache.tags.data_accesses 21887836 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 18968298 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 18968298 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 18968298 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 18968298 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 18968298 # number of overall hits +system.cpu.icache.overall_hits::total 18968298 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1459769 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1459769 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1459769 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1459769 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1459769 # number of overall misses +system.cpu.icache.overall_misses::total 1459769 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20155087658 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20155087658 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20155087658 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20155087658 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20155087658 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20155087658 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 20428067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 20428067 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 20428067 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 20428067 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 20428067 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 20428067 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.071459 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.071459 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.071459 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.071459 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.071459 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.071459 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13807.039099 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13807.039099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13807.039099 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13807.039099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13807.039099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13807.039099 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -657,135 +646,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1460159 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1460159 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1460159 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1460159 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1460159 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1460159 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17111152616 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17111152616 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17111152616 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17111152616 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17111152616 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17111152616 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071489 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.071489 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071489 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.071489 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11718.691332 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11718.691332 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11718.691332 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11718.691332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11718.691332 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11718.691332 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1459769 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1459769 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1459769 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1459769 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1459769 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1459769 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17958185842 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17958185842 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17958185842 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17958185842 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17958185842 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17958185842 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.071459 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.071459 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.071459 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.071459 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12302.073713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12302.073713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12302.073713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12302.073713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12302.073713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12302.073713 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 339433 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65325.334655 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2983211 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 404595 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 7.373326 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5873248750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 54499.677348 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5826.101052 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4999.556256 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.831599 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088899 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.076287 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996786 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 230 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1456 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2809 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55530 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 30263477 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 30263477 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1443639 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 819413 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2263052 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 838265 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 838265 # number of Writeback hits +system.cpu.l2cache.tags.replacements 339394 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65314.689309 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2982707 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 404554 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 7.372828 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6335415750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 54416.774547 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5825.207065 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5072.707697 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.830334 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088886 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.077403 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996623 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65160 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1413 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 5172 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2816 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55531 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994263 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 30259084 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 30259084 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1443260 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 819387 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2262647 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 838171 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 838171 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187609 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187609 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1443639 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1007022 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2450661 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1443639 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1007022 # number of overall hits -system.cpu.l2cache.overall_hits::total 2450661 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 16457 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 272214 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288671 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 17 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 17 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116676 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116676 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 16457 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388890 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405347 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 16457 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388890 # number of overall misses -system.cpu.l2cache.overall_misses::total 405347 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1197673500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17722888500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18920562000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 214497 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 214497 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8064568611 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8064568611 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1197673500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 25787457111 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26985130611 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1197673500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 25787457111 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26985130611 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1460096 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1091627 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2551723 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 838265 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 838265 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 21 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304285 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304285 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1460096 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1395912 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2856008 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1460096 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1395912 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2856008 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.011271 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.249365 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.113128 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.809524 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.809524 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383443 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.383443 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011271 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.278592 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.141928 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011271 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.278592 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.141928 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72775.931215 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65106.454848 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65543.688143 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12617.470588 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12617.470588 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69119.344261 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69119.344261 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72775.931215 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66310.414541 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66572.913111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72775.931215 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66310.414541 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66572.913111 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 187599 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187599 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1443260 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1006986 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2450246 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1443260 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1006986 # number of overall hits +system.cpu.l2cache.overall_hits::total 2450246 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 16444 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 272210 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 288654 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 20 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 20 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 116658 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116658 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 16444 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388868 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405312 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 16444 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388868 # number of overall misses +system.cpu.l2cache.overall_misses::total 405312 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1322916250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19744352250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21067268500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 253997 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 253997 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8959337611 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8959337611 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1322916250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28703689861 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30026606111 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1322916250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28703689861 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30026606111 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1459704 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1091597 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2551301 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 838171 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 838171 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 24 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 24 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304257 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304257 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1459704 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1395854 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2855558 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1459704 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1395854 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2855558 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.011265 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.249369 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.113140 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.833333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.833333 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383419 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383419 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.011265 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.278588 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.141938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.011265 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.278588 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.141938 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80449.784116 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72533.530179 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72984.502207 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12699.850000 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12699.850000 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76800.027525 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76800.027525 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80449.784116 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73813.453051 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74082.697061 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80449.784116 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73813.453051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74082.697061 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -794,66 +783,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 76642 # number of writebacks -system.cpu.l2cache.writebacks::total 76642 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16457 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272214 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288671 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 17 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116676 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116676 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16457 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388890 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 405347 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16457 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388890 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 405347 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 990967000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14320677500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15311644500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 271014 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 271014 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6596786889 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6596786889 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 990967000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20917464389 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21908431389 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 990967000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20917464389 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21908431389 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333789500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333789500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887480500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887480500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3221270000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3221270000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249365 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113128 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.809524 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383443 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.141928 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011271 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278592 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.141928 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60215.531385 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52608.159389 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53041.852143 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15942 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15942 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56539.364471 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56539.364471 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60215.531385 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53787.611893 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54048.584026 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 76588 # number of writebacks +system.cpu.l2cache.writebacks::total 76588 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16444 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 272210 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 288654 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 20 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 20 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116658 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116658 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16444 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388868 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 405312 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16444 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388868 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 405312 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1116961750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16343103250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17460065000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 455517 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 455517 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500878889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500878889 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1116961750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23843982139 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24960943889 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1116961750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23843982139 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24960943889 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336266500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893208000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893208000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3229474500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3229474500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.249369 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.113140 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.833333 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383419 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383419 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.141938 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.278588 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.141938 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67925.185478 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60038.585100 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60487.867828 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 22775.850000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 22775.850000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64298.024045 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64298.024045 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67925.185478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61316.390495 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61584.517332 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -861,42 +850,42 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2558889 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2558856 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2558469 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2558436 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9619 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 838265 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 21 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304285 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304285 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 838171 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41593 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2920255 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663385 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6583640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93446144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143040604 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 236486748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41944 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3736082 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.011168 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105088 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2919473 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3663181 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6582654 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143030876 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 236451932 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41987 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3735584 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.011181 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105146 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3694357 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3693818 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41766 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3736082 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2698528498 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3735584 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2698164499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2193867384 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2193277658 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2194759654 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2194690407 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -969,23 +958,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406197789 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242093194 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23479000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.296028 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.302259 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1728025570000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.296028 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.081002 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.081002 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1729989085000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.302259 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.081391 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.081391 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -999,14 +988,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635920906 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635920906 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8777958811 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8777958811 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1023,19 +1012,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328165.212409 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328165.212409 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206267 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211252.378008 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211252.378008 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 73082 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23556 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10004 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.756453 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.305278 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1049,14 +1038,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11475216906 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11475216906 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6617254811 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6617254811 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1065,61 +1054,61 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276165.212409 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276165.212409 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159252.378008 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159252.378008 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 295774 # Transaction distribution -system.membus.trans_dist::ReadResp 295758 # Transaction distribution +system.membus.trans_dist::ReadReq 295757 # Transaction distribution +system.membus.trans_dist::ReadResp 295741 # Transaction distribution system.membus.trans_dist::WriteReq 9619 # Transaction distribution system.membus.trans_dist::WriteResp 9619 # Transaction distribution -system.membus.trans_dist::Writeback 118154 # Transaction distribution +system.membus.trans_dist::Writeback 118100 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 156 # Transaction distribution -system.membus.trans_dist::ReadExReq 116537 # Transaction distribution -system.membus.trans_dist::ReadExResp 116537 # Transaction distribution +system.membus.trans_dist::UpgradeReq 159 # Transaction distribution +system.membus.trans_dist::UpgradeResp 159 # Transaction distribution +system.membus.trans_dist::ReadExReq 116519 # Transaction distribution +system.membus.trans_dist::ReadExResp 116519 # Transaction distribution system.membus.trans_dist::BadAddressError 16 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 887063 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 886945 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920193 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920075 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1044997 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1044879 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30819904 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30864220 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36181276 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 433 # Total snoops (count) -system.membus.snoop_fanout::samples 565243 # Request fanout histogram +system.membus.snoop_fanout::samples 565206 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 565243 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 565206 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 565243 # Request fanout histogram -system.membus.reqLayer0.occupancy 30308000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 565206 # Request fanout histogram +system.membus.reqLayer0.occupancy 30238000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1878196000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1230315562 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3792332596 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2160768093 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt index 38c6e11f9..24a65d69d 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt @@ -1,123 +1,123 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.901175 # Number of seconds simulated -sim_ticks 1901175003500 # Number of ticks simulated -final_tick 1901175003500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.904438 # Number of seconds simulated +sim_ticks 1904437574000 # Number of ticks simulated +final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154934 # Simulator instruction rate (inst/s) -host_op_rate 154934 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5197600055 # Simulator tick rate (ticks/s) -host_mem_usage 378544 # Number of bytes of host memory used -host_seconds 365.78 # Real time elapsed on the host -sim_insts 56671579 # Number of instructions simulated -sim_ops 56671579 # Number of ops (including micro ops) simulated +host_inst_rate 150033 # Simulator instruction rate (inst/s) +host_op_rate 150033 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5049661741 # Simulator tick rate (ticks/s) +host_mem_usage 379720 # Number of bytes of host memory used +host_seconds 377.14 # Real time elapsed on the host +sim_insts 56583768 # Number of instructions simulated +sim_ops 56583768 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 885824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24795264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 95808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 496320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 878144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24662016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 107328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 745792 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26274176 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 885824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 95808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 981632 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7885056 # Number of bytes written to this memory -system.physmem.bytes_written::total 7885056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 13841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 387426 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1497 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 7755 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26394240 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 878144 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 107328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 985472 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7983616 # Number of bytes written to this memory +system.physmem.bytes_written::total 7983616 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13721 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 385344 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1677 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11653 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 410534 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 123204 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123204 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 465935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 13042073 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 261060 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13819967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 465935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 516329 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4147465 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4147465 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4147465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 465935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 13042073 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 261060 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 505 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17967432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 410534 # Number of read requests accepted -system.physmem.writeReqs 164756 # Number of write requests accepted -system.physmem.readBursts 410534 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 164756 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26267904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6272 # Total number of bytes read from write queue -system.physmem.bytesWritten 10393408 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26274176 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10544384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 98 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2335 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4921 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25742 # Per bank write bursts -system.physmem.perBankRdBursts::1 25822 # Per bank write bursts -system.physmem.perBankRdBursts::2 25939 # Per bank write bursts -system.physmem.perBankRdBursts::3 25643 # Per bank write bursts -system.physmem.perBankRdBursts::4 25873 # Per bank write bursts -system.physmem.perBankRdBursts::5 25657 # Per bank write bursts -system.physmem.perBankRdBursts::6 25709 # Per bank write bursts -system.physmem.perBankRdBursts::7 25201 # Per bank write bursts -system.physmem.perBankRdBursts::8 25222 # Per bank write bursts -system.physmem.perBankRdBursts::9 26115 # Per bank write bursts -system.physmem.perBankRdBursts::10 25677 # Per bank write bursts -system.physmem.perBankRdBursts::11 25575 # Per bank write bursts -system.physmem.perBankRdBursts::12 25800 # Per bank write bursts -system.physmem.perBankRdBursts::13 26085 # Per bank write bursts -system.physmem.perBankRdBursts::14 25301 # Per bank write bursts -system.physmem.perBankRdBursts::15 25075 # Per bank write bursts -system.physmem.perBankWrBursts::0 10194 # Per bank write bursts -system.physmem.perBankWrBursts::1 10103 # Per bank write bursts -system.physmem.perBankWrBursts::2 10030 # Per bank write bursts -system.physmem.perBankWrBursts::3 9736 # Per bank write bursts -system.physmem.perBankWrBursts::4 9490 # Per bank write bursts -system.physmem.perBankWrBursts::5 10167 # Per bank write bursts -system.physmem.perBankWrBursts::6 10200 # Per bank write bursts -system.physmem.perBankWrBursts::7 9338 # Per bank write bursts -system.physmem.perBankWrBursts::8 9741 # Per bank write bursts -system.physmem.perBankWrBursts::9 10459 # Per bank write bursts -system.physmem.perBankWrBursts::10 10157 # Per bank write bursts -system.physmem.perBankWrBursts::11 10688 # Per bank write bursts -system.physmem.perBankWrBursts::12 11170 # Per bank write bursts -system.physmem.perBankWrBursts::13 11200 # Per bank write bursts -system.physmem.perBankWrBursts::14 10147 # Per bank write bursts -system.physmem.perBankWrBursts::15 9577 # Per bank write bursts +system.physmem.num_reads::total 412410 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124744 # Number of write requests responded to by this memory +system.physmem.num_writes::total 124744 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 461104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12949763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 56357 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 391607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 504 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13859336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 461104 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 56357 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 517461 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4192112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4192112 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4192112 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 461104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12949763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 56357 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 391607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 504 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18051448 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412410 # Number of read requests accepted +system.physmem.writeReqs 166296 # Number of write requests accepted +system.physmem.readBursts 412410 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 166296 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26387648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 9015296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26394240 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10642944 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25417 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4739 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25681 # Per bank write bursts +system.physmem.perBankRdBursts::1 26031 # Per bank write bursts +system.physmem.perBankRdBursts::2 26262 # Per bank write bursts +system.physmem.perBankRdBursts::3 25929 # Per bank write bursts +system.physmem.perBankRdBursts::4 25778 # Per bank write bursts +system.physmem.perBankRdBursts::5 25597 # Per bank write bursts +system.physmem.perBankRdBursts::6 26273 # Per bank write bursts +system.physmem.perBankRdBursts::7 25295 # Per bank write bursts +system.physmem.perBankRdBursts::8 25970 # Per bank write bursts +system.physmem.perBankRdBursts::9 26150 # Per bank write bursts +system.physmem.perBankRdBursts::10 25721 # Per bank write bursts +system.physmem.perBankRdBursts::11 25208 # Per bank write bursts +system.physmem.perBankRdBursts::12 25640 # Per bank write bursts +system.physmem.perBankRdBursts::13 25768 # Per bank write bursts +system.physmem.perBankRdBursts::14 25547 # Per bank write bursts +system.physmem.perBankRdBursts::15 25457 # Per bank write bursts +system.physmem.perBankWrBursts::0 9358 # Per bank write bursts +system.physmem.perBankWrBursts::1 9077 # Per bank write bursts +system.physmem.perBankWrBursts::2 9200 # Per bank write bursts +system.physmem.perBankWrBursts::3 8756 # Per bank write bursts +system.physmem.perBankWrBursts::4 8419 # Per bank write bursts +system.physmem.perBankWrBursts::5 8251 # Per bank write bursts +system.physmem.perBankWrBursts::6 9072 # Per bank write bursts +system.physmem.perBankWrBursts::7 8046 # Per bank write bursts +system.physmem.perBankWrBursts::8 8692 # Per bank write bursts +system.physmem.perBankWrBursts::9 8978 # Per bank write bursts +system.physmem.perBankWrBursts::10 8574 # Per bank write bursts +system.physmem.perBankWrBursts::11 8968 # Per bank write bursts +system.physmem.perBankWrBursts::12 8555 # Per bank write bursts +system.physmem.perBankWrBursts::13 9260 # Per bank write bursts +system.physmem.perBankWrBursts::14 8896 # Per bank write bursts +system.physmem.perBankWrBursts::15 8762 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 1901170614000 # Total gap between requests +system.physmem.numWrRetry 50 # Number of times write queue was full causing retry +system.physmem.totGap 1904433039500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 410534 # Read request sizes (log2) +system.physmem.readPktSize::6 412410 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 164756 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 317401 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 40588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 43093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9265 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 166296 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 317706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 39027 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 30801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24670 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 80 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -158,193 +158,200 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9498 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6622 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 448 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 5 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 67203 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 545.527075 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 333.566914 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.530844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 14928 22.21% 22.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11337 16.87% 39.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5205 7.75% 46.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2937 4.37% 51.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2377 3.54% 54.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1798 2.68% 57.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1602 2.38% 59.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1684 2.51% 62.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25335 37.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 67203 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6020 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 68.178073 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2721.311016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 6017 99.95% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3688 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4340 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6158 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7735 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1699 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1758 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 225 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 92 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66375 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 533.371902 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 326.032515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.702689 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14841 22.36% 22.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11366 17.12% 39.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5910 8.90% 48.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2909 4.38% 52.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2416 3.64% 56.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1747 2.63% 59.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1634 2.46% 61.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1312 1.98% 63.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 24240 36.52% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66375 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5272 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 78.206942 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2891.855588 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 5269 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6020 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6020 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.976246 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.646869 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.117275 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4955 82.31% 82.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 186 3.09% 85.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 316 5.25% 90.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 58 0.96% 91.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 93 1.54% 93.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 41 0.68% 93.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 21 0.35% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.18% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 26 0.43% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.28% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 95.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 7 0.12% 95.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.03% 95.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 20 0.33% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 42 0.70% 96.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 17 0.28% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 7 0.12% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 80 1.33% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 45 0.75% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 12 0.20% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 27 0.45% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 6 0.10% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.08% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.07% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 4 0.07% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6020 # Writes before turning the bus around for reads -system.physmem.totQLat 3885054500 # Total ticks spent queuing -system.physmem.totMemAccLat 11580729500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9465.68 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5272 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5272 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 26.719272 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.348145 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 60.306865 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5026 95.33% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 55 1.04% 96.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 6 0.11% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 3 0.06% 96.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 6 0.11% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 3 0.06% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 6 0.11% 96.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 24 0.46% 97.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 10 0.19% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 9 0.17% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 16 0.30% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 98.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.06% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 4 0.08% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.02% 98.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.08% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 6 0.11% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 11 0.21% 98.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 13 0.25% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.13% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 10 0.19% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.06% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.04% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 11 0.21% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.06% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 5 0.09% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 2 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 3 0.06% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-911 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5272 # Writes before turning the bus around for reads +system.physmem.totQLat 4111304500 # Total ticks spent queuing +system.physmem.totMemAccLat 11842060750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2061535000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9971.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28215.68 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.47 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.82 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28721.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.86 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.86 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.15 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing -system.physmem.readRowHits 370181 # Number of row buffer hits during reads -system.physmem.writeRowHits 135448 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.39 # Row buffer hit rate for writes -system.physmem.avgGap 3304716.95 # Average gap between requests -system.physmem.pageHitRate 88.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 253260000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138187500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1603570800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 513591840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 57090888495 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1090621618500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1274396212335 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.322456 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1814181645000 # Time in different power states -system.physmem_0.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem.avgRdQLen 2.27 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing +system.physmem.readRowHits 371693 # Number of row buffer hits during reads +system.physmem.writeRowHits 115102 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.70 # Row buffer hit rate for writes +system.physmem.avgGap 3290847.23 # Average gap between requests +system.physmem.pageHitRate 88.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 251551440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 137255250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1613398800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 454759920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 57693505320 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1092050470500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1276589123070 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.325620 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1816548038492 # Time in different power states +system.physmem_0.memoryStateTime::REF 63593140000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 23503077500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 24290182758 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 254688840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 138967125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597455600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 538429680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 124175095200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 57028143465 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1090676670000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1274409449910 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.329412 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1814277217000 # Time in different power states -system.physmem_1.memoryStateTime::REF 63484200000 # Time in different power states +system.physmem_1.actEnergy 250137720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 136483875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1602190200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 457604640 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 124388181840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 57661176915 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1092078837000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1276574612190 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.317995 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1816597555496 # Time in different power states +system.physmem_1.memoryStateTime::REF 63593140000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23408681000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 24242350004 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 16131633 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14074847 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 326763 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 9526803 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 5411642 # Number of BTB hits +system.cpu0.branchPred.lookups 16050181 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14012515 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 321303 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 9883832 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 5384164 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 56.804387 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 814199 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 17678 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 54.474459 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 809394 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 17633 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 9231009 # DTB read hits -system.cpu0.dtb.read_misses 34580 # DTB read misses -system.cpu0.dtb.read_acv 535 # DTB read access violations -system.cpu0.dtb.read_accesses 687791 # DTB read accesses -system.cpu0.dtb.write_hits 5940395 # DTB write hits -system.cpu0.dtb.write_misses 7538 # DTB write misses -system.cpu0.dtb.write_acv 382 # DTB write access violations -system.cpu0.dtb.write_accesses 237219 # DTB write accesses -system.cpu0.dtb.data_hits 15171404 # DTB hits -system.cpu0.dtb.data_misses 42118 # DTB misses -system.cpu0.dtb.data_acv 917 # DTB access violations -system.cpu0.dtb.data_accesses 925010 # DTB accesses -system.cpu0.itb.fetch_hits 1435355 # ITB hits -system.cpu0.itb.fetch_misses 29386 # ITB misses -system.cpu0.itb.fetch_acv 625 # ITB acv -system.cpu0.itb.fetch_accesses 1464741 # ITB accesses +system.cpu0.dtb.read_hits 9185685 # DTB read hits +system.cpu0.dtb.read_misses 31794 # DTB read misses +system.cpu0.dtb.read_acv 464 # DTB read access violations +system.cpu0.dtb.read_accesses 674724 # DTB read accesses +system.cpu0.dtb.write_hits 5856177 # DTB write hits +system.cpu0.dtb.write_misses 6642 # DTB write misses +system.cpu0.dtb.write_acv 308 # DTB write access violations +system.cpu0.dtb.write_accesses 220970 # DTB write accesses +system.cpu0.dtb.data_hits 15041862 # DTB hits +system.cpu0.dtb.data_misses 38436 # DTB misses +system.cpu0.dtb.data_acv 772 # DTB access violations +system.cpu0.dtb.data_accesses 895694 # DTB accesses +system.cpu0.itb.fetch_hits 1413849 # ITB hits +system.cpu0.itb.fetch_misses 27924 # ITB misses +system.cpu0.itb.fetch_acv 522 # ITB acv +system.cpu0.itb.fetch_accesses 1441773 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -357,466 +364,465 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 112944275 # number of cpu cycles simulated +system.cpu0.numCycles 115311619 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 26734623 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 70871158 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 16131633 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 6225841 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 78572167 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1087344 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 938 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 28136 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1452901 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 461019 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 278 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 8195583 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 233790 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 107793734 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.657470 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.965319 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 26308115 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 70327057 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 16050181 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 6193558 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 81501759 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1071492 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 564 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 28477 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1405877 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 453989 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 199 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 8110639 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 231031 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 110234726 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.637976 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.938280 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 94531257 87.70% 87.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 858509 0.80% 88.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1823492 1.69% 90.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 785861 0.73% 90.91% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2602190 2.41% 93.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 590625 0.55% 93.88% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 664328 0.62% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 839547 0.78% 95.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 5097925 4.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 97059343 88.05% 88.05% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 844439 0.77% 88.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1832569 1.66% 90.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 778966 0.71% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2587591 2.35% 93.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 590382 0.54% 94.07% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 655112 0.59% 94.66% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 842956 0.76% 95.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 5043368 4.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 107793734 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.142828 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.627488 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 21731474 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 75223274 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 8544304 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1787077 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 507604 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 524648 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 36495 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 62167212 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 115754 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 507604 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 22589385 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 48401768 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 19164228 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9376952 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 7753795 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 60013920 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 204923 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2024034 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 144343 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3822558 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 40119139 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 72975711 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 72834321 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 131688 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 35221894 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 4897237 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1480119 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 216056 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12920416 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 9368350 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6206352 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1340557 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 962340 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 53512619 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1895957 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 52599778 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 52230 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6392747 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 3006442 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 1305426 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 107793734 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.487967 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.221871 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 110234726 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.139190 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.609887 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 21404943 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 78060690 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 8511786 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1756604 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 500702 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 518589 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 35397 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 61724420 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 110442 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 500702 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 22241314 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 51035680 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 18875449 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9340106 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 8241473 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 59592973 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 194522 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2018079 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 142482 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 4327383 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 39868450 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 72416227 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 72269697 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 136600 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 34997307 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 4871143 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1466604 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 213801 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12439963 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 9310742 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6112181 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1342468 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 951279 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 53110388 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1887245 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 52243998 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 50112 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6322079 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 2924940 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 1298251 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 110234726 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.473934 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.210494 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 86044446 79.82% 79.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 9475309 8.79% 88.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3928815 3.64% 92.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2790586 2.59% 94.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2836372 2.63% 97.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1349941 1.25% 98.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 893970 0.83% 99.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 358292 0.33% 99.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 116003 0.11% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 88757561 80.52% 80.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 9303542 8.44% 88.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3888317 3.53% 92.48% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2690563 2.44% 94.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2829805 2.57% 97.49% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1399486 1.27% 98.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 891988 0.81% 99.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 364157 0.33% 99.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 109307 0.10% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 107793734 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 110234726 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 177733 18.25% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 18.25% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 467063 47.95% 66.19% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 329340 33.81% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 184539 19.02% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 19.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 463483 47.76% 66.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 322428 33.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 3770 0.01% 0.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 36087462 68.61% 68.61% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57222 0.11% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.72% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 28709 0.05% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 1883 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.78% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9582527 18.22% 87.00% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6011046 11.43% 98.43% # Type of FU issued -system.cpu0.iq.FU_type_0::IprAccess 827159 1.57% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 4481 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 35873428 68.67% 68.67% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57323 0.11% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 68.78% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 30345 0.06% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.84% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 2234 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9533353 18.25% 87.09% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5924969 11.34% 98.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 817865 1.57% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 52599778 # Type of FU issued -system.cpu0.iq.rate 0.465714 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 974136 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.018520 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 213441030 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61548330 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 51220095 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 578625 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 270952 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 265721 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 53258517 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 311627 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 583786 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 52243998 # Type of FU issued +system.cpu0.iq.rate 0.453068 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 970450 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.018575 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 215148578 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61059123 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 50866456 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 594706 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 278076 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 273817 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 52889876 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 320091 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 579148 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1112279 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 5019 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18330 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 503254 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1102308 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 4274 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 17841 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 488268 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 18853 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 369989 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 18769 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362429 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 507604 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 44339596 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 1604348 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 58817574 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 124782 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 9368350 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6206352 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 1675353 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 48473 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 1332642 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18330 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 164161 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 356822 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 520983 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 52091421 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9288991 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 508356 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 500702 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 47770294 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 975694 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 58389413 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 117266 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 9310742 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6112181 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 1666926 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 38737 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 734939 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 17841 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 161758 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 354564 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 516322 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 51738600 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9239994 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 505398 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 3408998 # number of nop insts executed -system.cpu0.iew.exec_refs 15250639 # number of memory reference insts executed -system.cpu0.iew.exec_branches 8273174 # Number of branches executed -system.cpu0.iew.exec_stores 5961648 # Number of stores executed -system.cpu0.iew.exec_rate 0.461213 # Inst execution rate -system.cpu0.iew.wb_sent 51600991 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 51485816 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 26436063 # num instructions producing a value -system.cpu0.iew.wb_consumers 36546981 # num instructions consuming a value +system.cpu0.iew.exec_nop 3391780 # number of nop insts executed +system.cpu0.iew.exec_refs 15116199 # number of memory reference insts executed +system.cpu0.iew.exec_branches 8225133 # Number of branches executed +system.cpu0.iew.exec_stores 5876205 # Number of stores executed +system.cpu0.iew.exec_rate 0.448685 # Inst execution rate +system.cpu0.iew.wb_sent 51252595 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 51140273 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 26435135 # num instructions producing a value +system.cpu0.iew.wb_consumers 36676301 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.455851 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.723345 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.443496 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.720769 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7016261 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 590531 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 476969 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 106554717 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.485172 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.424408 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6957791 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 588994 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 471378 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 109009912 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.470894 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.405994 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 88252662 82.82% 82.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 7298996 6.85% 89.67% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 3974083 3.73% 93.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2090799 1.96% 95.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1561874 1.47% 96.83% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 585444 0.55% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 439090 0.41% 97.79% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 445608 0.42% 98.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1906161 1.79% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 90895183 83.38% 83.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 7166067 6.57% 89.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 3956975 3.63% 93.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2029230 1.86% 95.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1623676 1.49% 96.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 582620 0.53% 97.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 429957 0.39% 97.87% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 432812 0.40% 98.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1893392 1.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 106554717 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 51697359 # Number of instructions committed -system.cpu0.commit.committedOps 51697359 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 109009912 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 51332073 # Number of instructions committed +system.cpu0.commit.committedOps 51332073 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 13959169 # Number of memory references committed -system.cpu0.commit.loads 8256071 # Number of loads committed -system.cpu0.commit.membars 200989 # Number of memory barriers committed -system.cpu0.commit.branches 7816314 # Number of branches committed -system.cpu0.commit.fp_insts 262681 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 47879291 # Number of committed integer instructions. -system.cpu0.commit.function_calls 663768 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 2971590 5.75% 5.75% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 33646334 65.08% 70.83% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55999 0.11% 70.94% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.94% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 28236 0.05% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 70.99% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 1883 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.00% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 8457060 16.36% 87.36% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 5709098 11.04% 98.40% # Class of committed instruction -system.cpu0.commit.op_class_0::IprAccess 827159 1.60% 100.00% # Class of committed instruction +system.cpu0.commit.refs 13832347 # Number of memory references committed +system.cpu0.commit.loads 8208434 # Number of loads committed +system.cpu0.commit.membars 200823 # Number of memory barriers committed +system.cpu0.commit.branches 7767218 # Number of branches committed +system.cpu0.commit.fp_insts 270478 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 47526784 # Number of committed integer instructions. +system.cpu0.commit.function_calls 660195 # Number of function calls committed. +system.cpu0.commit.op_class_0::No_OpClass 2960587 5.77% 5.77% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 33426068 65.12% 70.88% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 56116 0.11% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 70.99% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 30044 0.06% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 71.05% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 2234 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 71.06% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 8409257 16.38% 87.44% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 5629902 10.97% 98.41% # Class of committed instruction +system.cpu0.commit.op_class_0::IprAccess 817865 1.59% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 51697359 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1906161 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 51332073 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1893392 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 163161097 # The number of ROB reads -system.cpu0.rob.rob_writes 118660594 # The number of ROB writes -system.cpu0.timesIdled 501791 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5150541 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 3689405733 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 48729536 # Number of Instructions Simulated -system.cpu0.committedOps 48729536 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 2.317779 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.317779 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.431448 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.431448 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 68466406 # number of integer regfile reads -system.cpu0.int_regfile_writes 37249066 # number of integer regfile writes -system.cpu0.fp_regfile_reads 130692 # number of floating regfile reads -system.cpu0.fp_regfile_writes 131766 # number of floating regfile writes -system.cpu0.misc_regfile_reads 1811017 # number of misc regfile reads -system.cpu0.misc_regfile_writes 827352 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 1291740 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.889209 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 10636670 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1292252 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 8.231111 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 25151000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.889209 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988065 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988065 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 217 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 245 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 57483025 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 57483025 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6556019 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6556019 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3715997 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3715997 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164872 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 164872 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189733 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 189733 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 10272016 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10272016 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 10272016 # number of overall hits -system.cpu0.dcache.overall_hits::total 10272016 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 1615331 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1615331 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1779982 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1779982 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21282 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21282 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2627 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2627 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3395313 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 3395313 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 3395313 # number of overall misses -system.cpu0.dcache.overall_misses::total 3395313 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 40801843239 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 40801843239 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 80191363617 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 80191363617 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336613990 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 336613990 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 19436381 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 19436381 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 120993206856 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 120993206856 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 120993206856 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 120993206856 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8171350 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8171350 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 5495979 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5495979 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 186154 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 186154 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 192360 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 192360 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13667329 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13667329 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13667329 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13667329 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.197682 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.197682 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.323870 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.323870 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.114325 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.114325 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.013657 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.013657 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.248425 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.248425 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.248425 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.248425 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25259.122272 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25259.122272 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45051.783455 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45051.783455 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.840053 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.840053 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7398.698515 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7398.698515 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35635.361705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35635.361705 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35635.361705 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 3895440 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3799 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 167914 # number of cycles access was blocked +system.cpu0.rob.rob_reads 165216916 # The number of ROB reads +system.cpu0.rob.rob_writes 117798939 # The number of ROB writes +system.cpu0.timesIdled 506110 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5076893 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 3693292578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 48375955 # Number of Instructions Simulated +system.cpu0.committedOps 48375955 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 2.383656 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.383656 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.419524 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.419524 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 67964697 # number of integer regfile reads +system.cpu0.int_regfile_writes 37032803 # number of integer regfile writes +system.cpu0.fp_regfile_reads 135608 # number of floating regfile reads +system.cpu0.fp_regfile_writes 136877 # number of floating regfile writes +system.cpu0.misc_regfile_reads 1822860 # number of misc regfile reads +system.cpu0.misc_regfile_writes 821150 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 1283357 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.867544 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 10588066 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1283792 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 8.247493 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.867544 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988023 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.988023 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 435 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 435 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.849609 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 56965784 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 56965784 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6531926 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6531926 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3699481 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3699481 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 164387 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 164387 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 189172 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 189172 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 10231407 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 10231407 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 10231407 # number of overall hits +system.cpu0.dcache.overall_hits::total 10231407 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 1592146 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1592146 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1718300 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1718300 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20836 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20836 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2478 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 2478 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3310446 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 3310446 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 3310446 # number of overall misses +system.cpu0.dcache.overall_misses::total 3310446 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39294199360 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39294199360 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 76231824796 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 76231824796 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 326020750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 326020750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 20798848 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 20798848 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 115526024156 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 115526024156 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 115526024156 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 115526024156 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 8124072 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8124072 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5417781 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5417781 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 185223 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 185223 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 191650 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 191650 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13541853 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 13541853 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13541853 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 13541853 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.195979 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.195979 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.317159 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.317159 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.112491 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.112491 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.012930 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.012930 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.244460 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.244460 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.244460 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.244460 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 24680.022661 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 24680.022661 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44364.677179 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44364.677179 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15646.993185 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15646.993185 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8393.401130 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8393.401130 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34897.419911 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34897.419911 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34897.419911 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 4226969 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4392 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 103766 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 94 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.199019 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 40.414894 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 40.735588 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 46.723404 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 762456 # number of writebacks -system.cpu0.dcache.writebacks::total 762456 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 593909 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 593909 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1512221 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1512221 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 5168 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 5168 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 2106130 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 2106130 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 2106130 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 2106130 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1021422 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 1021422 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 267761 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 267761 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 16114 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 16114 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2626 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2626 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1289183 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1289183 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1289183 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1289183 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27591103326 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27591103326 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11693886534 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11693886534 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 178834256 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 178834256 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 14183619 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 14183619 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 39284989860 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 39284989860 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 39284989860 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 39284989860 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1458359000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1458359000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2137811998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2137811998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3596170998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3596170998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125000 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125000 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048719 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048719 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086563 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086563 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.013651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.013651 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.094326 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094326 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.094326 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27012.442777 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27012.442777 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43672.852036 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43672.852036 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11098.067271 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11098.067271 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5401.225819 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5401.225819 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30472.779939 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30472.779939 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 752753 # number of writebacks +system.cpu0.dcache.writebacks::total 752753 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 572031 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 572031 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1457971 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1457971 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4881 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4881 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 2030002 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 2030002 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 2030002 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 2030002 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 1020115 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 1020115 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 260329 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 260329 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15955 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15955 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2477 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2477 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1280444 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11887451669 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 177873500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 177873500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 17082652 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 17082652 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 40869593877 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 40869593877 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 40869593877 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 40869593877 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1464167000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1464167000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129748498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2129748498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3593915498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3593915498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.125567 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.125567 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.048051 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.048051 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.086139 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.086139 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.012925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.012925 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.094555 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.094555 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.094555 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28410.661747 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28410.661747 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45663.186464 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45663.186464 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11148.448762 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11148.448762 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6896.508680 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6896.508680 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -824,126 +830,124 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 914535 # number of replacements -system.cpu0.icache.tags.tagsinuse 509.589702 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 7236389 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 915045 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 7.908233 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 26485919250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.589702 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.995292 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.995292 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 427 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 9110810 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 9110810 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 7236389 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 7236389 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 7236389 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 7236389 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 7236389 # number of overall hits -system.cpu0.icache.overall_hits::total 7236389 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 959193 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 959193 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 959193 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 959193 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 959193 # number of overall misses -system.cpu0.icache.overall_misses::total 959193 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13598697683 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13598697683 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13598697683 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13598697683 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13598697683 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13598697683 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 8195582 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 8195582 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 8195582 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 8195582 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 8195582 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 8195582 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117038 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.117038 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117038 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.117038 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117038 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.117038 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14177.227819 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14177.227819 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14177.227819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14177.227819 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14177.227819 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4960 # number of cycles access was blocked +system.cpu0.icache.tags.replacements 911417 # number of replacements +system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 7153262 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 911929 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 7.844100 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 28352545250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 509.418391 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.994958 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.994958 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 9022750 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 9022750 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 7153262 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7153262 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7153262 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7153262 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7153262 # number of overall hits +system.cpu0.icache.overall_hits::total 7153262 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 957376 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 957376 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 957376 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 957376 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 957376 # number of overall misses +system.cpu0.icache.overall_misses::total 957376 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13452406105 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13452406105 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13452406105 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13452406105 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13452406105 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13452406105 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 8110638 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 8110638 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 8110638 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 8110638 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 8110638 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 8110638 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.118040 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.118040 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.118040 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.118040 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.118040 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.118040 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14051.329995 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14051.329995 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14051.329995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14051.329995 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14051.329995 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5687 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 197 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 25.177665 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.164103 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43965 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43965 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43965 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43965 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43965 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43965 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 915228 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 915228 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 915228 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 915228 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 915228 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 915228 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11221708315 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11221708315 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11221708315 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11221708315 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11221708315 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11221708315 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.111673 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.111673 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.111673 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.111673 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12261.106866 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12261.106866 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12261.106866 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 45264 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 45264 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 45264 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 45264 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 45264 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 45264 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 912112 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 912112 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 912112 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 912112 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 912112 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 912112 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11511971092 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11511971092 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11511971092 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11511971092 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11511971092 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11511971092 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.112459 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.112459 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.112459 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.112459 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12621.225345 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12621.225345 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12621.225345 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 3410499 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2981782 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 63006 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 1861186 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 813170 # Number of BTB hits +system.cpu1.branchPred.lookups 3445639 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3003437 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 69264 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 1910439 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 836162 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 43.690958 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 161954 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 4822 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 43.768055 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 167186 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 4809 # Number of incorrect RAS predictions. system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1800297 # DTB read hits -system.cpu1.dtb.read_misses 9623 # DTB read misses -system.cpu1.dtb.read_acv 4 # DTB read access violations -system.cpu1.dtb.read_accesses 290908 # DTB read accesses -system.cpu1.dtb.write_hits 1120103 # DTB write hits -system.cpu1.dtb.write_misses 2035 # DTB write misses -system.cpu1.dtb.write_acv 37 # DTB write access violations -system.cpu1.dtb.write_accesses 109629 # DTB write accesses -system.cpu1.dtb.data_hits 2920400 # DTB hits -system.cpu1.dtb.data_misses 11658 # DTB misses -system.cpu1.dtb.data_acv 41 # DTB access violations -system.cpu1.dtb.data_accesses 400537 # DTB accesses -system.cpu1.itb.fetch_hits 513208 # ITB hits -system.cpu1.itb.fetch_misses 5417 # ITB misses -system.cpu1.itb.fetch_acv 59 # ITB acv -system.cpu1.itb.fetch_accesses 518625 # ITB accesses +system.cpu1.dtb.read_hits 1858276 # DTB read hits +system.cpu1.dtb.read_misses 10905 # DTB read misses +system.cpu1.dtb.read_acv 64 # DTB read access violations +system.cpu1.dtb.read_accesses 300263 # DTB read accesses +system.cpu1.dtb.write_hits 1193771 # DTB write hits +system.cpu1.dtb.write_misses 2902 # DTB write misses +system.cpu1.dtb.write_acv 104 # DTB write access violations +system.cpu1.dtb.write_accesses 125157 # DTB write accesses +system.cpu1.dtb.data_hits 3052047 # DTB hits +system.cpu1.dtb.data_misses 13807 # DTB misses +system.cpu1.dtb.data_acv 168 # DTB access violations +system.cpu1.dtb.data_accesses 425420 # DTB accesses +system.cpu1.itb.fetch_hits 529068 # ITB hits +system.cpu1.itb.fetch_misses 7485 # ITB misses +system.cpu1.itb.fetch_acv 158 # ITB acv +system.cpu1.itb.fetch_accesses 536553 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -956,463 +960,467 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 13834996 # number of cpu cycles simulated +system.cpu1.numCycles 14296923 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 5742756 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 13201278 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 3410499 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 975124 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 7052078 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 251690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.MiscStallCycles 24829 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 212437 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 51117 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 1482208 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 50416 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 13209086 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.999409 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.408470 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 5827989 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 13624759 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 3445639 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 1003348 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 7312463 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 270756 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 304 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 25051 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 299772 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 60327 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1551048 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 55046 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 13661307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.997325 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.404073 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 10898169 82.51% 82.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 144102 1.09% 83.60% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 239022 1.81% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 173764 1.32% 86.72% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 293834 2.22% 88.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 119928 0.91% 89.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 132080 1.00% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 175112 1.33% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 1033075 7.82% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 11273523 82.52% 82.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 149434 1.09% 83.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 236962 1.73% 85.35% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 182278 1.33% 86.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 319422 2.34% 89.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 124907 0.91% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 138046 1.01% 90.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 169812 1.24% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 1066923 7.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 13209086 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.246512 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.954195 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 4781490 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 6446001 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 1665086 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 196515 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 119993 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 102189 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 5928 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 10739248 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 19374 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 119993 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 4918512 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 544557 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 5139003 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 1724887 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 762132 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 10178184 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 4877 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 68265 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 13199 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 289695 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 6692544 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 12133960 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 12078154 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 50250 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 5671659 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1020885 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 419664 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 38232 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 1772644 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 1865226 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1191683 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 210655 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 119712 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 8963290 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 478811 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 8726606 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 20522 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1437541 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 698510 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 352654 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 13209086 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.660652 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.378469 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 13661307 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.241006 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.952985 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 4848979 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 6756897 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 1724085 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 202692 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 128653 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 104901 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 6833 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 11127112 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21450 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 128653 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 4991483 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 690115 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 5206241 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 1784475 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 860338 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 10551561 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 3558 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 63390 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 12017 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 381484 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 6914568 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 12620115 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 12571129 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 43721 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 5829921 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1084639 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 430965 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 39644 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 1821487 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 1910201 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1273290 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 221141 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 146764 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 9284732 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 487174 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 9053277 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 20996 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1498950 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 731721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 360528 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 13661307 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.662695 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.384311 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 9547804 72.28% 72.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 1625741 12.31% 84.59% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 686242 5.20% 89.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 474957 3.60% 93.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 417301 3.16% 96.54% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 221804 1.68% 98.22% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 145793 1.10% 99.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 65024 0.49% 99.82% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 24420 0.18% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 9895925 72.44% 72.44% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 1648518 12.07% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 704790 5.16% 89.66% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 494622 3.62% 93.28% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 437905 3.21% 96.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 233549 1.71% 98.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 155573 1.14% 99.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 64890 0.47% 99.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 25535 0.19% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 13209086 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 13661307 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 22353 9.61% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 126163 54.23% 63.84% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 84116 36.16% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 22279 8.85% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 136629 54.29% 63.14% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 92774 36.86% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 3518 0.04% 0.04% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 5425627 62.17% 62.21% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 15090 0.17% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.39% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 10661 0.12% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.51% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 1759 0.02% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.53% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 1878240 21.52% 84.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 1141614 13.08% 97.13% # Type of FU issued -system.cpu1.iq.FU_type_0::IprAccess 250097 2.87% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 2817 0.03% 0.03% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 5609130 61.96% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 14890 0.16% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.15% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 8778 0.10% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.25% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 1408 0.02% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.27% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 1940639 21.44% 83.70% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1217689 13.45% 97.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 257926 2.85% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 8726606 # Type of FU issued -system.cpu1.iq.rate 0.630763 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 232632 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.026658 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 30722514 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 10791679 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 8409842 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 192938 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 91772 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 89511 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 8852667 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 103053 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 90033 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 9053277 # Type of FU issued +system.cpu1.iq.rate 0.633233 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 251682 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.027800 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 31870123 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 11194643 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 8718718 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 170415 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 80450 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 78899 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 9210850 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 91292 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 92092 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 271460 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 498 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 3940 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 125337 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 283440 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 879 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 4333 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 136775 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 380 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 50736 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 421 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 73078 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 119993 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 268498 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 245239 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 9936241 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 29107 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 1865226 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 1191683 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 435120 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 4465 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 239666 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 3940 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 28286 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 93108 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 121394 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 8606074 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 1816179 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 120532 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 128653 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 295868 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 364148 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 10275512 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 29401 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 1910201 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1273290 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 443383 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 3815 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 359581 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 4333 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 31404 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 95843 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 127247 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 8933578 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 1876162 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 119698 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 494140 # number of nop insts executed -system.cpu1.iew.exec_refs 2943760 # number of memory reference insts executed -system.cpu1.iew.exec_branches 1279494 # Number of branches executed -system.cpu1.iew.exec_stores 1127581 # Number of stores executed -system.cpu1.iew.exec_rate 0.622051 # Inst execution rate -system.cpu1.iew.wb_sent 8526125 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 8499353 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 4051784 # num instructions producing a value -system.cpu1.iew.wb_consumers 5752933 # num instructions consuming a value +system.cpu1.iew.exec_nop 503606 # number of nop insts executed +system.cpu1.iew.exec_refs 3078439 # number of memory reference insts executed +system.cpu1.iew.exec_branches 1318456 # Number of branches executed +system.cpu1.iew.exec_stores 1202277 # Number of stores executed +system.cpu1.iew.exec_rate 0.624860 # Inst execution rate +system.cpu1.iew.wb_sent 8830913 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 8797617 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 4148200 # num instructions producing a value +system.cpu1.iew.wb_consumers 5856949 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.614337 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.704299 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.615350 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.708253 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 1506985 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 126157 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 110245 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 12932417 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.645119 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.622232 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 1592161 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 126646 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 116539 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 13369044 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.644454 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.620421 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 9905025 76.59% 76.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 1407731 10.89% 87.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 501740 3.88% 91.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 308618 2.39% 93.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 224670 1.74% 95.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 96970 0.75% 96.23% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 89070 0.69% 96.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 100805 0.78% 97.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 297788 2.30% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 10245809 76.64% 76.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 1446725 10.82% 87.46% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 518907 3.88% 91.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 315988 2.36% 93.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 242120 1.81% 95.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 97246 0.73% 96.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 91600 0.69% 96.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 106270 0.79% 97.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 304379 2.28% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 12932417 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 8342954 # Number of instructions committed -system.cpu1.commit.committedOps 8342954 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 13369044 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 8615735 # Number of instructions committed +system.cpu1.commit.committedOps 8615735 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 2660112 # Number of memory references committed -system.cpu1.commit.loads 1593766 # Number of loads committed -system.cpu1.commit.membars 39768 # Number of memory barriers committed -system.cpu1.commit.branches 1189273 # Number of branches committed -system.cpu1.commit.fp_insts 87820 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 7729091 # Number of committed integer instructions. -system.cpu1.commit.function_calls 132492 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 404429 4.85% 4.85% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 4960733 59.46% 64.31% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 14917 0.18% 64.49% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.49% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 10656 0.13% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.61% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 1759 0.02% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.64% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 1633534 19.58% 84.22% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 1066829 12.79% 97.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IprAccess 250097 3.00% 100.00% # Class of committed instruction +system.cpu1.commit.refs 2763276 # Number of memory references committed +system.cpu1.commit.loads 1626761 # Number of loads committed +system.cpu1.commit.membars 39485 # Number of memory barriers committed +system.cpu1.commit.branches 1225974 # Number of branches committed +system.cpu1.commit.fp_insts 77544 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 7995429 # Number of committed integer instructions. +system.cpu1.commit.function_calls 135018 # Number of function calls committed. +system.cpu1.commit.op_class_0::No_OpClass 410738 4.77% 4.77% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 5119196 59.42% 64.18% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 14466 0.17% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 64.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 8774 0.10% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 64.45% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 1408 0.02% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.47% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 1666246 19.34% 83.81% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 1136981 13.20% 97.01% # Class of committed instruction +system.cpu1.commit.op_class_0::IprAccess 257926 2.99% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 8342954 # Class of committed instruction -system.cpu1.commit.bw_lim_events 297788 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 8615735 # Class of committed instruction +system.cpu1.commit.bw_lim_events 304379 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 22401053 # The number of ROB reads -system.cpu1.rob.rob_writes 19972727 # The number of ROB writes -system.cpu1.timesIdled 110858 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 625910 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 3787862669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 7942043 # Number of Instructions Simulated -system.cpu1.committedOps 7942043 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.741995 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.741995 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.574055 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.574055 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 11080172 # number of integer regfile reads -system.cpu1.int_regfile_writes 6056867 # number of integer regfile writes -system.cpu1.fp_regfile_reads 49492 # number of floating regfile reads -system.cpu1.fp_regfile_writes 48750 # number of floating regfile writes -system.cpu1.misc_regfile_reads 911686 # number of misc regfile reads -system.cpu1.misc_regfile_writes 198554 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 93396 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.127271 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 2362095 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 93708 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 25.206973 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1032235519500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 491.127271 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.959233 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.959233 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.609375 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 11044469 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 11044469 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 1462423 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1462423 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 846221 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 846221 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29364 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 29364 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 27945 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 27945 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 2308644 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2308644 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 2308644 # number of overall hits -system.cpu1.dcache.overall_hits::total 2308644 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 178507 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 178507 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 183677 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 183677 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4603 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 4603 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2762 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 2762 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 362184 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 362184 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 362184 # number of overall misses -system.cpu1.dcache.overall_misses::total 362184 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2741731463 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2741731463 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 7132330313 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 7132330313 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 45481992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 45481992 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 20461911 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 20461911 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 9874061776 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 9874061776 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 9874061776 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 9874061776 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 1640930 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 1640930 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1029898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1029898 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 33967 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 33967 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 30707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 30707 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 2670828 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 2670828 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 2670828 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 2670828 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108784 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.108784 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.178345 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.178345 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.135514 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.135514 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.089947 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.089947 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135607 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135607 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135607 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135607 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15359.237806 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15359.237806 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 38830.829734 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 38830.829734 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9880.945470 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9880.945470 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7408.367487 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7408.367487 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 27262.556535 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27262.556535 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27262.556535 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 351094 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 268 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 15302 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 22.944321 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 17.866667 # average number of cycles each access was blocked +system.cpu1.rob.rob_reads 23176968 # The number of ROB reads +system.cpu1.rob.rob_writes 20704388 # The number of ROB writes +system.cpu1.timesIdled 112605 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 635616 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 3794578226 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 8207813 # Number of Instructions Simulated +system.cpu1.committedOps 8207813 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.741868 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.741868 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.574096 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.574096 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 11535994 # number of integer regfile reads +system.cpu1.int_regfile_writes 6250844 # number of integer regfile writes +system.cpu1.fp_regfile_reads 43175 # number of floating regfile reads +system.cpu1.fp_regfile_writes 42684 # number of floating regfile writes +system.cpu1.misc_regfile_reads 891820 # number of misc regfile reads +system.cpu1.misc_regfile_writes 203240 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 102439 # number of replacements +system.cpu1.dcache.tags.tagsinuse 489.756832 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 2417231 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 102951 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 23.479432 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 1034185261500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 489.756832 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.956556 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.956556 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 224 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 11476458 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 11476458 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 1494681 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1494681 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 855193 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 855193 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 29899 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 29899 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 28520 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 28520 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 2349874 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 2349874 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 2349874 # number of overall hits +system.cpu1.dcache.overall_hits::total 2349874 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 181396 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 181396 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 244262 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 244262 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4731 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4731 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 2607 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 2607 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 425658 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 425658 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 425658 # number of overall misses +system.cpu1.dcache.overall_misses::total 425658 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2290258065 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2290258065 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9952106154 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9952106154 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 46237999 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 46237999 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 22188385 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 22188385 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12242364219 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12242364219 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12242364219 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12242364219 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 1676077 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 1676077 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1099455 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1099455 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 34630 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 34630 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 31127 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 31127 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 2775532 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 2775532 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 2775532 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 2775532 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.108227 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.108227 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.222166 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.222166 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.136616 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.136616 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.083754 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.083754 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.153361 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.153361 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.153361 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.153361 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12625.736317 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12625.736317 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40743.571059 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 40743.571059 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9773.409216 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9773.409216 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8511.079785 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8511.079785 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 28761.034020 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 28761.034020 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 28761.034020 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 574336 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 346 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 18255 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 31.461846 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 43.250000 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 60059 # number of writebacks -system.cpu1.dcache.writebacks::total 60059 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 108966 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 108966 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 150714 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 150714 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 427 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 259680 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 259680 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 259680 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 259680 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 69541 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 69541 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 32963 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 32963 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4176 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4176 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2762 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 2762 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 102504 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 102504 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 102504 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 102504 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 829052502 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 829052502 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1081287205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1081287205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 31817008 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 31817008 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 14937089 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 14937089 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1910339707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 1910339707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1910339707 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 1910339707 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 24846500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 24846500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 618764500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 618764500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 643611000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 643611000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042379 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042379 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032006 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.032006 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.122943 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.122943 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.089947 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.089947 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.038379 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.038379 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.038379 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11921.779986 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11921.779986 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32803.058126 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32803.058126 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7619.015326 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7619.015326 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5408.069877 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5408.069877 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18636.733269 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18636.733269 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 70134 # number of writebacks +system.cpu1.dcache.writebacks::total 70134 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 110614 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 110614 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 203686 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 203686 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 700 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 700 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 314300 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 314300 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 314300 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 314300 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 70782 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 70782 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 40576 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 40576 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4031 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4031 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 2607 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 2607 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 111358 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1580599049 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 32399501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 32399501 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 18277115 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 18277115 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2395960567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2395960567 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2395960567 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2395960567 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 29330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 29330000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 630993000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 630993000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 660323000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 660323000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042231 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042231 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036906 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036906 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.116402 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.116402 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.083754 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.083754 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.040121 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.040121 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.040121 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11519.334266 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11519.334266 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38954.038077 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 38954.038077 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8037.583974 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8037.583974 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7010.784427 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7010.784427 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1420,95 +1428,97 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 205003 # number of replacements -system.cpu1.icache.tags.tagsinuse 470.613699 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 1269898 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 205514 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 6.179131 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1878408675250 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 470.613699 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.919167 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.919167 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 510 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 1687783 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 1687783 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 1269898 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1269898 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 1269898 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1269898 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 1269898 # number of overall hits -system.cpu1.icache.overall_hits::total 1269898 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 212310 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 212310 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 212310 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 212310 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 212310 # number of overall misses -system.cpu1.icache.overall_misses::total 212310 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2888653039 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 2888653039 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 2888653039 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 2888653039 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 2888653039 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 2888653039 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 1482208 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1482208 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 1482208 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1482208 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 1482208 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1482208 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.143239 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.143239 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.143239 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.143239 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.143239 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.143239 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13605.826570 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13605.826570 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13605.826570 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13605.826570 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13605.826570 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 412 # number of cycles access was blocked +system.cpu1.icache.tags.replacements 211356 # number of replacements +system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 1331062 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 211865 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 6.282595 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1880244277250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 472.195820 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.922257 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.922257 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 392 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 1762968 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 1762968 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 1331062 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1331062 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1331062 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1331062 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1331062 # number of overall hits +system.cpu1.icache.overall_hits::total 1331062 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 219986 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 219986 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 219986 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 219986 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 219986 # number of overall misses +system.cpu1.icache.overall_misses::total 219986 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2974295730 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2974295730 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2974295730 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2974295730 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2974295730 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2974295730 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1551048 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1551048 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1551048 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1551048 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1551048 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1551048 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.141831 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.141831 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.141831 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.141831 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.141831 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.141831 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13520.386434 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13520.386434 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13520.386434 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13520.386434 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13520.386434 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 613 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 40 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.846154 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 15.325000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 6735 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 6735 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 6735 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 6735 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 6735 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 6735 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 205575 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 205575 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 205575 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 205575 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 205575 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 205575 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2403236890 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 2403236890 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2403236890 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 2403236890 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2403236890 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 2403236890 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.138695 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.138695 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.138695 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.138695 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11690.316867 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11690.316867 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11690.316867 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 8066 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 8066 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 8066 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 8066 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 8066 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 8066 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 211920 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 211920 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 211920 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 211920 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 211920 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 211920 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 2567742004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 2567742004 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 2567742004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 2567742004 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 2567742004 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 2567742004 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.136630 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.136630 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.136630 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.136630 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12116.562873 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12116.562873 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 12116.562873 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1522,58 +1532,58 @@ system.disk2.dma_read_txs 0 # Nu system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.iobus.trans_dist::ReadReq 7377 # Transaction distribution -system.iobus.trans_dist::ReadResp 7377 # Transaction distribution -system.iobus.trans_dist::WriteReq 54536 # Transaction distribution -system.iobus.trans_dist::WriteResp 12984 # Transaction distribution +system.iobus.trans_dist::ReadReq 7375 # Transaction distribution +system.iobus.trans_dist::ReadResp 7375 # Transaction distribution +system.iobus.trans_dist::WriteReq 54477 # Transaction distribution +system.iobus.trans_dist::WriteResp 12925 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11756 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 11660 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18148 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 172 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18142 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 2468 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6674 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 40360 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 123826 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 47024 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 40244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 123704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 46640 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9074 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 149 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9071 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 9852 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4194 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 73266 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661672 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661672 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2734938 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 11111000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 72837 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661648 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2734485 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 11011000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 155000 # Layer occupancy (ticks) +system.iobus.reqLayer22.occupancy 148000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 13505000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 13500000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 2450000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 5166000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 5167000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 184000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) @@ -1581,52 +1591,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406222784 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242105442 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 27376000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 27319000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42026793 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42037503 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41701 # number of replacements -system.iocache.tags.tagsinuse 0.465228 # Cycle average of tags in use +system.iocache.tags.replacements 41698 # number of replacements +system.iocache.tags.tagsinuse 0.483577 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41717 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41714 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1710337218000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.465228 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.029077 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.029077 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711318407000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.483577 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.030224 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.030224 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375597 # Number of tag accesses -system.iocache.tags.data_accesses 375597 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 181 # number of ReadReq misses -system.iocache.ReadReq_misses::total 181 # number of ReadReq misses +system.iocache.tags.tag_accesses 375570 # Number of tag accesses +system.iocache.tags.data_accesses 375570 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 178 # number of ReadReq misses +system.iocache.ReadReq_misses::total 178 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 181 # number of demand (read+write) misses -system.iocache.demand_misses::total 181 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 181 # number of overall misses -system.iocache.overall_misses::total 181 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 22038383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 22038383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13652440608 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13652440608 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 22038383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 22038383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 22038383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 22038383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 181 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 181 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 178 # number of demand (read+write) misses +system.iocache.demand_misses::total 178 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 178 # number of overall misses +system.iocache.overall_misses::total 178 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 22300881 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 22300881 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8783600058 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8783600058 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 22300881 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 22300881 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 22300881 # number of overall miss cycles +system.iocache.overall_miss_latency::total 22300881 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 178 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 178 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 181 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 181 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 181 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 181 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 178 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 178 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 178 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 178 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1635,40 +1645,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 121759.022099 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 121759.022099 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328562.779361 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328562.779361 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 121759.022099 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 121759.022099 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 121759.022099 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206720 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125285.848315 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125285.848315 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211388.141558 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211388.141558 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125285.848315 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125285.848315 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125285.848315 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 73351 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23552 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10036 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.777174 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.308788 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 181 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 178 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 178 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 181 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 181 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 181 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 181 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12625383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12625383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11491649194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11491649194 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12625383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12625383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12625383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12625383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 178 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 178 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 178 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 178 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12879885 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12879885 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6622894060 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6622894060 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12879885 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12879885 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12879885 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12879885 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1677,189 +1687,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 69753.497238 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276560.675635 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276560.675635 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 69753.497238 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 69753.497238 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72358.904494 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159388.093473 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159388.093473 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72358.904494 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72358.904494 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 345072 # number of replacements -system.l2c.tags.tagsinuse 65237.196274 # Cycle average of tags in use -system.l2c.tags.total_refs 2611817 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 410198 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.367210 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 7093665750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 53609.898857 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5305.766317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6049.152476 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 209.737010 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 62.641613 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.818022 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080960 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.092303 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.003200 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000956 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995441 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65126 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 216 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 2602 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5798 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5210 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51300 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.993744 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27343076 # Number of tag accesses -system.l2c.tags.data_accesses 27343076 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 901250 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 743094 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 204045 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 62863 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1911252 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 822515 # number of Writeback hits -system.l2c.Writeback_hits::total 822515 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 174 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 236 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 410 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 50 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 28 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 157590 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 21227 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 178817 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 901250 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 900684 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 204045 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 84090 # number of demand (read+write) hits -system.l2c.demand_hits::total 2090069 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 901250 # number of overall hits -system.l2c.overall_hits::cpu0.data 900684 # number of overall hits -system.l2c.overall_hits::cpu1.inst 204045 # number of overall hits -system.l2c.overall_hits::cpu1.data 84090 # number of overall hits -system.l2c.overall_hits::total 2090069 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 13855 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 273150 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1501 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 784 # number of ReadReq misses -system.l2c.ReadReq_misses::total 289290 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2701 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1143 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 3844 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 381 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 416 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 797 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 114840 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 7053 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 121893 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 13855 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 387990 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1501 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 7837 # number of demand (read+write) misses -system.l2c.demand_misses::total 411183 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 13855 # number of overall misses -system.l2c.overall_misses::cpu0.data 387990 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1501 # number of overall misses -system.l2c.overall_misses::cpu1.data 7837 # number of overall misses -system.l2c.overall_misses::total 411183 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 1053790500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17926629500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 116949250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 69771500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 19167140750 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1289954 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 4510297 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 5800251 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 801966 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 70497 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 872463 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 9554653251 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 752768967 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10307422218 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1053790500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 27481282751 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 116949250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 822540467 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 29474562968 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1053790500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 27481282751 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 116949250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 822540467 # number of overall miss cycles -system.l2c.overall_miss_latency::total 29474562968 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 915105 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1016244 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 205546 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 63647 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2200542 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 822515 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 822515 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2875 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1379 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4254 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 431 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 444 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 875 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 272430 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28280 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300710 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 915105 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1288674 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 205546 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 91927 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2501252 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 915105 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1288674 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 205546 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 91927 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2501252 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015140 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.268784 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007303 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.012318 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.131463 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.939478 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828861 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.903620 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.883991 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.936937 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.910857 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.421539 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.249399 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.405351 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015140 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.301077 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007303 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.085252 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.164391 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015140 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.301077 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007303 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.085252 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.164391 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76058.498737 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65629.249497 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77914.223851 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 88994.260204 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 66255.801272 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 477.583858 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3946.016623 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1508.910250 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2104.897638 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 169.463942 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1094.683814 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83199.697414 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 106730.322841 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 84561.231720 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 76058.498737 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 70829.873840 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 77914.223851 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 104956.037642 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71682.348171 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 76058.498737 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 70829.873840 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 77914.223851 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 104956.037642 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71682.348171 # average overall miss latency +system.l2c.tags.replacements 346915 # number of replacements +system.l2c.tags.tagsinuse 65246.496404 # Cycle average of tags in use +system.l2c.tags.total_refs 2614060 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 412065 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.343805 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7589002750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 53536.501359 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5301.488199 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6124.882413 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 215.988746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 67.635688 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.816902 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.080894 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.093458 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003296 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.001032 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.995583 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 2446 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5392 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7744 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 49345 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27379617 # Number of tag accesses +system.l2c.tags.data_accesses 27379617 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 898215 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 742471 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 210198 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 63927 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1914811 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 822887 # number of Writeback hits +system.l2c.Writeback_hits::total 822887 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 176 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 246 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 422 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 53 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 30 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 83 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 152332 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 25116 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 177448 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 898215 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 894803 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 210198 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 89043 # number of demand (read+write) hits +system.l2c.demand_hits::total 2092259 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 898215 # number of overall hits +system.l2c.overall_hits::cpu0.data 894803 # number of overall hits +system.l2c.overall_hits::cpu1.inst 210198 # number of overall hits +system.l2c.overall_hits::cpu1.data 89043 # number of overall hits +system.l2c.overall_hits::total 2092259 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13731 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 273058 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1686 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 819 # number of ReadReq misses +system.l2c.ReadReq_misses::total 289294 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2683 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1043 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3726 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 349 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 386 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 735 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 112818 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 10944 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 123762 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13731 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 385876 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1686 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 11763 # number of demand (read+write) misses +system.l2c.demand_misses::total 413056 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13731 # number of overall misses +system.l2c.overall_misses::cpu0.data 385876 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1686 # number of overall misses +system.l2c.overall_misses::cpu1.data 11763 # number of overall misses +system.l2c.overall_misses::total 413056 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1146699750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 19948507750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 143666750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 75193250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 21314067500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1596458 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5835814 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 7432272 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1194963 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 187494 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1382457 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 9983790515 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1229173205 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11212963720 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1146699750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 29932298265 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 143666750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1304366455 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 32527031220 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1146699750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 29932298265 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 143666750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1304366455 # number of overall miss cycles +system.l2c.overall_miss_latency::total 32527031220 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 911946 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1015529 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 211884 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 64746 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2204105 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 822887 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 822887 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2859 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1289 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4148 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 402 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 416 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 818 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 265150 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 36060 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 301210 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 911946 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1280679 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 211884 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 100806 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2505315 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 911946 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1280679 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 211884 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 100806 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2505315 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015057 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.268883 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007957 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.012649 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.131252 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.938440 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.809154 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.898264 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.868159 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.927885 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.898533 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.425487 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.303494 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.410883 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015057 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.301306 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007957 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.116689 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.164872 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015057 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.301306 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007957 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.116689 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.164872 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 83511.743500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 73055.935918 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85211.595492 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 91811.050061 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 73676.147794 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 595.027208 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5595.219559 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1994.705314 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3423.962751 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 485.735751 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1880.893878 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88494.659673 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 112314.803088 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90601.022285 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 83511.743500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 77569.732932 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 85211.595492 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 110887.227323 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78747.267247 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 83511.743500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 77569.732932 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 85211.595492 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 110887.227323 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78747.267247 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1868,125 +1878,125 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 81684 # number of writebacks -system.l2c.writebacks::total 81684 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 13 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 18 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 18 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 13842 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 273149 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1497 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 784 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 289272 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2701 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1143 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 3844 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 381 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 416 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 797 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 114840 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 7053 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 121893 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 13842 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 387989 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1497 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 7837 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 411165 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 13842 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 387989 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1497 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 7837 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 411165 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 878413500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14522738500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 97828500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 60106500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15559087000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 27191193 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 11450632 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 38641825 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 3833377 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4164911 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 7998288 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8153414747 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 665986031 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8819400778 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 878413500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 22676153247 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 97828500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 726092531 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 24378487778 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 878413500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 22676153247 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 97828500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 726092531 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 24378487778 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1366462500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 23156500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1389619000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2015759500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 582978000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2598737500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3382222000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 606134500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 3988356500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268783 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012318 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.131455 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.939478 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828861 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.903620 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.883991 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.936937 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.910857 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.421539 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.249399 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.405351 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.164384 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015126 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.301076 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007283 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.085252 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.164384 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 53167.825985 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76666.454082 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 53787.048176 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10067.083673 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10018.050744 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.503902 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10061.356955 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.805288 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10035.493099 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70998.038549 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 94425.922444 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 72353.628002 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63460.013004 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58445.350891 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65349.699399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 92649.295776 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59291.252363 # average overall mshr miss latency +system.l2c.writebacks::writebacks 83224 # number of writebacks +system.l2c.writebacks::total 83224 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 19 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 19 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 13722 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 273058 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1677 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 818 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 289275 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2683 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1043 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 3726 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 349 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 386 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 735 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 112818 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 10944 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 123762 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13722 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 385876 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1677 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 11762 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 413037 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13722 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 385876 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 65122250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17706943750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 47889169 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 18491538 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 66380707 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6218348 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 6847885 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 13066233 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 8604034485 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1094197795 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9698232280 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 974652500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 25149140735 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 122062750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1159320045 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 27405176030 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 974652500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 25149140735 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 122062750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1159320045 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 27405176030 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1365620000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27118000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392738000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1999167500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 591543000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2590710500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3364787500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 618661000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 3983448500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.268883 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.012634 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.131244 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.938440 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.809154 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.898264 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.868159 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.927885 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.898533 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.425487 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.303494 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.410883 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.164864 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015047 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.301306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007915 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.116680 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.164864 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60591.911792 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79611.552567 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 61211.455363 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.112561 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17729.183126 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17815.541331 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17817.616046 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17740.634715 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17777.187755 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76264.731559 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99981.523666 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 78361.955043 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71028.457951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65174.151113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1997,101 +2007,101 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296649 # Transaction distribution -system.membus.trans_dist::ReadResp 296568 # Transaction distribution -system.membus.trans_dist::WriteReq 12984 # Transaction distribution -system.membus.trans_dist::WriteResp 12984 # Transaction distribution -system.membus.trans_dist::Writeback 123204 # Transaction distribution +system.membus.trans_dist::ReadReq 296650 # Transaction distribution +system.membus.trans_dist::ReadResp 296572 # Transaction distribution +system.membus.trans_dist::WriteReq 12925 # Transaction distribution +system.membus.trans_dist::WriteResp 12925 # Transaction distribution +system.membus.trans_dist::Writeback 124744 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 9668 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 5310 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4924 # Transaction distribution -system.membus.trans_dist::ReadExReq 121989 # Transaction distribution -system.membus.trans_dist::ReadExResp 121610 # Transaction distribution -system.membus.trans_dist::BadAddressError 81 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40360 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 923282 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 162 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 963804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1088624 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 73266 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31500992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31574258 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 9402 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5001 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4742 # Transaction distribution +system.membus.trans_dist::ReadExReq 123808 # Transaction distribution +system.membus.trans_dist::ReadExResp 123481 # Transaction distribution +system.membus.trans_dist::BadAddressError 78 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 40244 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927766 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 156 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 968166 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124817 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1092983 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 72837 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31719616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31792453 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36891826 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 10884 # Total snoops (count) -system.membus.snoop_fanout::samples 591178 # Request fanout histogram +system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 10437 # Total snoops (count) +system.membus.snoop_fanout::samples 594010 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 591178 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 591178 # Request fanout histogram -system.membus.reqLayer0.occupancy 38973998 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 594010 # Request fanout histogram +system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1927807998 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) system.membus.reqLayer2.occupancy 100000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3829664091 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43225207 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2197321028 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42525497 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2228449 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2228352 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 12984 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 12984 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 822515 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 9795 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 5388 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 15183 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 301926 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 301926 # Transaction distribution -system.toL2Bus.trans_dist::BadAddressError 81 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1830333 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3396960 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 411121 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 269188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5907602 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58566720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 131328844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13154944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 9749222 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 212799730 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 73699 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3402430 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012266 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110070 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2231372 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2231278 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 12925 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 12925 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 822887 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41587 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 9543 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 5084 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 14627 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302295 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302295 # Transaction distribution +system.toL2Bus.trans_dist::BadAddressError 78 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1824058 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3369862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 423804 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 296769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5914493 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 58364544 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 130195442 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 13560576 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 72565 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3360696 98.77% 98.77% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41734 1.23% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3402430 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4987291538 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 742500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4124247177 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5936070669 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 925874109 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1371805405 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 2024294017 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 318303496 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 467054772 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 173244936 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2125,161 +2135,171 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6564 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 186274 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 65832 40.54% 40.54% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.08% 40.62% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1922 1.18% 41.81% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 173 0.11% 41.91% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 94323 58.09% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 162381 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 64799 49.22% 49.22% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::21 131 0.10% 49.32% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1922 1.46% 50.78% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 173 0.13% 50.91% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 64626 49.09% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 131651 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1859979639500 97.83% 97.83% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 61305500 0.00% 97.84% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 538798500 0.03% 97.86% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 78674500 0.00% 97.87% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 40515747500 2.13% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1901174165500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.984309 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.inst.quiesce 6519 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 185119 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 65685 40.48% 40.48% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 132 0.08% 40.56% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1924 1.19% 41.75% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 154 0.09% 41.84% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 94359 58.16% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 162254 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 64617 49.22% 49.22% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::21 132 0.10% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::22 1924 1.47% 50.78% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 154 0.12% 50.90% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 64464 49.10% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 131291 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1861341200000 97.74% 97.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 60253000 0.00% 97.75% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 540538500 0.03% 97.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 69963500 0.00% 97.78% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 42290129000 2.22% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1904302084000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.983741 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.685156 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.810754 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.45% 3.45% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.62% 12.07% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.72% 13.79% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.22% 28.02% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.45% # number of syscalls executed -system.cpu0.kern.syscall::17 9 3.88% 32.33% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.31% 36.64% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.59% 39.22% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.66% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.29% 40.95% # number of syscalls executed -system.cpu0.kern.syscall::33 7 3.02% 43.97% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.86% 44.83% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.81% 61.64% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.29% 62.93% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.31% 67.24% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.31% 71.55% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 71.98% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.59% 74.57% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.64% 86.21% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.29% 87.50% # number of syscalls executed -system.cpu0.kern.syscall::74 7 3.02% 90.52% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 90.95% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.29% 92.24% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.88% 96.12% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.86% 96.98% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.86% 97.84% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.28% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.86% 99.14% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.86% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 232 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.683178 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.809170 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 6 2.79% 2.79% # number of syscalls executed +system.cpu0.kern.syscall::3 18 8.37% 11.16% # number of syscalls executed +system.cpu0.kern.syscall::4 3 1.40% 12.56% # number of syscalls executed +system.cpu0.kern.syscall::6 29 13.49% 26.05% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.47% 26.51% # number of syscalls executed +system.cpu0.kern.syscall::15 1 0.47% 26.98% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.19% 31.16% # number of syscalls executed +system.cpu0.kern.syscall::19 6 2.79% 33.95% # number of syscalls executed +system.cpu0.kern.syscall::20 4 1.86% 35.81% # number of syscalls executed +system.cpu0.kern.syscall::23 2 0.93% 36.74% # number of syscalls executed +system.cpu0.kern.syscall::24 4 1.86% 38.60% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.26% 41.86% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.93% 42.79% # number of syscalls executed +system.cpu0.kern.syscall::45 35 16.28% 59.07% # number of syscalls executed +system.cpu0.kern.syscall::47 4 1.86% 60.93% # number of syscalls executed +system.cpu0.kern.syscall::48 7 3.26% 64.19% # number of syscalls executed +system.cpu0.kern.syscall::54 9 4.19% 68.37% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.47% 68.84% # number of syscalls executed +system.cpu0.kern.syscall::59 5 2.33% 71.16% # number of syscalls executed +system.cpu0.kern.syscall::71 32 14.88% 86.05% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.40% 87.44% # number of syscalls executed +system.cpu0.kern.syscall::74 9 4.19% 91.63% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.47% 92.09% # number of syscalls executed +system.cpu0.kern.syscall::90 1 0.47% 92.56% # number of syscalls executed +system.cpu0.kern.syscall::92 7 3.26% 95.81% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.93% 96.74% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.93% 97.67% # number of syscalls executed +system.cpu0.kern.syscall::132 2 0.93% 98.60% # number of syscalls executed +system.cpu0.kern.syscall::144 1 0.47% 99.07% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.93% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 215 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 266 0.16% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrmces 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrfen 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.16% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3573 2.09% 2.25% # number of callpals executed -system.cpu0.kern.callpal::tbi 50 0.03% 2.28% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 155550 90.98% 93.26% # number of callpals executed -system.cpu0.kern.callpal::rdps 6382 3.73% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::wrusp 3 0.00% 96.99% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 97.00% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 97.00% # number of callpals executed -system.cpu0.kern.callpal::rti 4604 2.69% 99.69% # number of callpals executed -system.cpu0.kern.callpal::callsys 391 0.23% 99.92% # number of callpals executed -system.cpu0.kern.callpal::imb 138 0.08% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 170980 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7167 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1355 # number of protection mode switches +system.cpu0.kern.callpal::wripir 255 0.15% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrmces 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrfen 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.15% # number of callpals executed +system.cpu0.kern.callpal::swpctx 3502 2.05% 2.20% # number of callpals executed +system.cpu0.kern.callpal::tbi 43 0.03% 2.23% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.23% # number of callpals executed +system.cpu0.kern.callpal::swpipl 155594 91.14% 93.38% # number of callpals executed +system.cpu0.kern.callpal::rdps 6351 3.72% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rdusp 7 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 97.10% # number of callpals executed +system.cpu0.kern.callpal::rti 4450 2.61% 99.71% # number of callpals executed +system.cpu0.kern.callpal::callsys 347 0.20% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 148 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 170714 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6908 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1181 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1354 -system.cpu0.kern.mode_good::user 1355 +system.cpu0.kern.mode_good::kernel 1181 +system.cpu0.kern.mode_good::user 1181 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.188921 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170961 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.317883 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1899194834000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1979323500 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.292001 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1901823094000 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1927479500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3574 # number of times the context was actually changed +system.cpu0.kern.swap_context 3503 # number of times the context was actually changed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2428 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 53091 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 16423 36.25% 36.25% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1920 4.24% 40.49% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 266 0.59% 41.08% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 26695 58.92% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 45304 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 16079 47.18% 47.18% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1920 5.63% 52.82% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 266 0.78% 53.60% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 15813 46.40% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 34078 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870417466500 98.40% 98.40% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 530332500 0.03% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 120265000 0.01% 98.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29780754000 1.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900848818000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.979054 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2448 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 54000 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 16487 36.42% 36.42% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 4.25% 40.66% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 255 0.56% 41.23% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 26607 58.77% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 45271 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 16178 47.20% 47.20% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1922 5.61% 52.80% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 255 0.74% 53.55% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 15923 46.45% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 34278 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1872287559000 98.31% 98.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 533777500 0.03% 98.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 116465000 0.01% 98.35% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 31498958000 1.65% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1904436759500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.981258 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.592358 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.752207 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.64% 10.64% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.57% 20.21% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.06% 21.28% # number of syscalls executed -system.cpu1.kern.syscall::17 6 6.38% 27.66% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.19% 30.85% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.19% 34.04% # number of syscalls executed -system.cpu1.kern.syscall::33 4 4.26% 38.30% # number of syscalls executed -system.cpu1.kern.syscall::45 15 15.96% 54.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.19% 57.45% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.06% 58.51% # number of syscalls executed -system.cpu1.kern.syscall::71 27 28.72% 87.23% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.57% 96.81% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.19% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 94 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.598452 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.757173 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::2 2 1.80% 1.80% # number of syscalls executed +system.cpu1.kern.syscall::3 12 10.81% 12.61% # number of syscalls executed +system.cpu1.kern.syscall::4 1 0.90% 13.51% # number of syscalls executed +system.cpu1.kern.syscall::6 13 11.71% 25.23% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.41% 30.63% # number of syscalls executed +system.cpu1.kern.syscall::19 4 3.60% 34.23% # number of syscalls executed +system.cpu1.kern.syscall::20 2 1.80% 36.04% # number of syscalls executed +system.cpu1.kern.syscall::23 2 1.80% 37.84% # number of syscalls executed +system.cpu1.kern.syscall::24 2 1.80% 39.64% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.60% 43.24% # number of syscalls executed +system.cpu1.kern.syscall::45 19 17.12% 60.36% # number of syscalls executed +system.cpu1.kern.syscall::47 2 1.80% 62.16% # number of syscalls executed +system.cpu1.kern.syscall::48 3 2.70% 64.86% # number of syscalls executed +system.cpu1.kern.syscall::54 1 0.90% 65.77% # number of syscalls executed +system.cpu1.kern.syscall::59 2 1.80% 67.57% # number of syscalls executed +system.cpu1.kern.syscall::71 22 19.82% 87.39% # number of syscalls executed +system.cpu1.kern.syscall::74 7 6.31% 93.69% # number of syscalls executed +system.cpu1.kern.syscall::90 2 1.80% 95.50% # number of syscalls executed +system.cpu1.kern.syscall::92 2 1.80% 97.30% # number of syscalls executed +system.cpu1.kern.syscall::132 2 1.80% 99.10% # number of syscalls executed +system.cpu1.kern.syscall::144 1 0.90% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 111 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 173 0.37% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.37% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.38% # number of callpals executed -system.cpu1.kern.callpal::swpctx 989 2.11% 2.49% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.01% 2.49% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 2.51% # number of callpals executed -system.cpu1.kern.callpal::swpipl 40205 85.85% 88.36% # number of callpals executed -system.cpu1.kern.callpal::rdps 2366 5.05% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 93.41% # number of callpals executed -system.cpu1.kern.callpal::wrusp 4 0.01% 93.42% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.01% 93.43% # number of callpals executed -system.cpu1.kern.callpal::rti 2912 6.22% 99.64% # number of callpals executed -system.cpu1.kern.callpal::callsys 124 0.26% 99.91% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.09% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 154 0.33% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.33% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.33% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1023 2.18% 2.52% # number of callpals executed +system.cpu1.kern.callpal::tbi 10 0.02% 2.54% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 2.55% # number of callpals executed +system.cpu1.kern.callpal::swpipl 40053 85.39% 87.95% # number of callpals executed +system.cpu1.kern.callpal::rdps 2403 5.12% 93.07% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 93.07% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 93.08% # number of callpals executed +system.cpu1.kern.callpal::rdusp 2 0.00% 93.08% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.01% 93.09% # number of callpals executed +system.cpu1.kern.callpal::rti 3040 6.48% 99.57% # number of callpals executed +system.cpu1.kern.callpal::callsys 168 0.36% 99.93% # number of callpals executed +system.cpu1.kern.callpal::imb 32 0.07% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 46833 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1197 # number of protection mode switches -system.cpu1.kern.mode_switch::user 384 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2372 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 574 -system.cpu1.kern.mode_good::user 384 -system.cpu1.kern.mode_good::idle 190 -system.cpu1.kern.mode_switch_good::kernel 0.479532 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 46904 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 1413 # number of protection mode switches +system.cpu1.kern.mode_switch::user 554 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2352 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 733 +system.cpu1.kern.mode_good::user 554 +system.cpu1.kern.mode_good::idle 179 +system.cpu1.kern.mode_switch_good::kernel 0.518754 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.080101 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.290412 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 3852720500 0.20% 0.20% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 690217500 0.04% 0.24% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1895996394000 99.76% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 990 # number of times the context was actually changed +system.cpu1.kern.mode_switch_good::idle 0.076105 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.339430 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 4023798000 0.21% 0.21% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 775821000 0.04% 0.25% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1899637132500 99.75% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1024 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt index aba3b9944..12a10aeec 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt @@ -1,113 +1,113 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.859045 # Number of seconds simulated -sim_ticks 1859045389000 # Number of ticks simulated -final_tick 1859045389000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.861006 # Number of seconds simulated +sim_ticks 1861005569500 # Number of ticks simulated +final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 155751 # Simulator instruction rate (inst/s) -host_op_rate 155751 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5470499619 # Simulator tick rate (ticks/s) -host_mem_usage 374716 # Number of bytes of host memory used -host_seconds 339.83 # Real time elapsed on the host -sim_insts 52929026 # Number of instructions simulated -sim_ops 52929026 # Number of ops (including micro ops) simulated +host_inst_rate 153218 # Simulator instruction rate (inst/s) +host_op_rate 153218 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5386630373 # Simulator tick rate (ticks/s) +host_mem_usage 376136 # Number of bytes of host memory used +host_seconds 345.49 # Real time elapsed on the host +sim_insts 52934565 # Number of instructions simulated +sim_ops 52934565 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 968128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24876416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 968000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24876864 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25845504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 968128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 968128 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7516800 # Number of bytes written to this memory -system.physmem.bytes_written::total 7516800 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 15127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388694 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25845824 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 968000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 968000 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7517248 # Number of bytes written to this memory +system.physmem.bytes_written::total 7517248 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 15125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388701 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403836 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 117450 # Number of write requests responded to by this memory -system.physmem.num_writes::total 117450 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 520766 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 13381285 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403841 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 117457 # Number of write requests responded to by this memory +system.physmem.num_writes::total 117457 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 520149 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 13367431 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13902567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 520766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 520766 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4043366 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4043366 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4043366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 520766 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 13381285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13888096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 520149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 520149 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4039347 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4039347 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4039347 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 520149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 13367431 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17945933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 403836 # Number of read requests accepted -system.physmem.writeReqs 159002 # Number of write requests accepted -system.physmem.readBursts 403836 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159002 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25838848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 10042304 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25845504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10176128 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2068 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 208 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25744 # Per bank write bursts -system.physmem.perBankRdBursts::1 25557 # Per bank write bursts -system.physmem.perBankRdBursts::2 25510 # Per bank write bursts -system.physmem.perBankRdBursts::3 25348 # Per bank write bursts -system.physmem.perBankRdBursts::4 25387 # Per bank write bursts -system.physmem.perBankRdBursts::5 24799 # Per bank write bursts +system.physmem.bw_total::total 17927443 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 403841 # Number of read requests accepted +system.physmem.writeReqs 159009 # Number of write requests accepted +system.physmem.readBursts 403841 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 159009 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25839488 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6336 # Total number of bytes read from write queue +system.physmem.bytesWritten 8519424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25845824 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25748 # Per bank write bursts +system.physmem.perBankRdBursts::1 25559 # Per bank write bursts +system.physmem.perBankRdBursts::2 25508 # Per bank write bursts +system.physmem.perBankRdBursts::3 25346 # Per bank write bursts +system.physmem.perBankRdBursts::4 25393 # Per bank write bursts +system.physmem.perBankRdBursts::5 24806 # Per bank write bursts system.physmem.perBankRdBursts::6 25027 # Per bank write bursts -system.physmem.perBankRdBursts::7 25129 # Per bank write bursts -system.physmem.perBankRdBursts::8 24928 # Per bank write bursts -system.physmem.perBankRdBursts::9 25032 # Per bank write bursts +system.physmem.perBankRdBursts::7 25127 # Per bank write bursts +system.physmem.perBankRdBursts::8 24925 # Per bank write bursts +system.physmem.perBankRdBursts::9 25034 # Per bank write bursts system.physmem.perBankRdBursts::10 25436 # Per bank write bursts -system.physmem.perBankRdBursts::11 24784 # Per bank write bursts +system.physmem.perBankRdBursts::11 24774 # Per bank write bursts system.physmem.perBankRdBursts::12 24551 # Per bank write bursts -system.physmem.perBankRdBursts::13 25235 # Per bank write bursts -system.physmem.perBankRdBursts::14 25659 # Per bank write bursts -system.physmem.perBankRdBursts::15 25606 # Per bank write bursts -system.physmem.perBankWrBursts::0 10485 # Per bank write bursts -system.physmem.perBankWrBursts::1 10108 # Per bank write bursts -system.physmem.perBankWrBursts::2 10574 # Per bank write bursts -system.physmem.perBankWrBursts::3 9632 # Per bank write bursts -system.physmem.perBankWrBursts::4 9668 # Per bank write bursts -system.physmem.perBankWrBursts::5 9137 # Per bank write bursts -system.physmem.perBankWrBursts::6 9064 # Per bank write bursts -system.physmem.perBankWrBursts::7 8900 # Per bank write bursts -system.physmem.perBankWrBursts::8 9821 # Per bank write bursts -system.physmem.perBankWrBursts::9 8750 # Per bank write bursts -system.physmem.perBankWrBursts::10 9677 # Per bank write bursts -system.physmem.perBankWrBursts::11 9460 # Per bank write bursts -system.physmem.perBankWrBursts::12 10019 # Per bank write bursts -system.physmem.perBankWrBursts::13 10709 # Per bank write bursts -system.physmem.perBankWrBursts::14 10502 # Per bank write bursts -system.physmem.perBankWrBursts::15 10405 # Per bank write bursts +system.physmem.perBankRdBursts::13 25233 # Per bank write bursts +system.physmem.perBankRdBursts::14 25663 # Per bank write bursts +system.physmem.perBankRdBursts::15 25612 # Per bank write bursts +system.physmem.perBankWrBursts::0 9148 # Per bank write bursts +system.physmem.perBankWrBursts::1 8514 # Per bank write bursts +system.physmem.perBankWrBursts::2 8998 # Per bank write bursts +system.physmem.perBankWrBursts::3 8298 # Per bank write bursts +system.physmem.perBankWrBursts::4 8214 # Per bank write bursts +system.physmem.perBankWrBursts::5 7705 # Per bank write bursts +system.physmem.perBankWrBursts::6 7696 # Per bank write bursts +system.physmem.perBankWrBursts::7 7707 # Per bank write bursts +system.physmem.perBankWrBursts::8 8055 # Per bank write bursts +system.physmem.perBankWrBursts::9 7602 # Per bank write bursts +system.physmem.perBankWrBursts::10 8149 # Per bank write bursts +system.physmem.perBankWrBursts::11 7799 # Per bank write bursts +system.physmem.perBankWrBursts::12 8377 # Per bank write bursts +system.physmem.perBankWrBursts::13 9062 # Per bank write bursts +system.physmem.perBankWrBursts::14 8903 # Per bank write bursts +system.physmem.perBankWrBursts::15 8889 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 1859040142000 # Total gap between requests +system.physmem.numWrRetry 85 # Number of times write queue was full causing retry +system.physmem.totGap 1861000236500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 403836 # Read request sizes (log2) +system.physmem.readPktSize::6 403841 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 159002 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 314988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 37560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 42944 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 8167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 159009 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 314763 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 36627 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -148,193 +148,199 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5463 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 179 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 164 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 111 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63696 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 563.318764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 349.809758 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 419.596932 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13378 21.00% 21.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10306 16.18% 37.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4860 7.63% 44.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2855 4.48% 49.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2272 3.57% 52.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1671 2.62% 55.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1518 2.38% 57.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1616 2.54% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 25220 39.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63696 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.190619 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2803.945627 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5668 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1767 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3672 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4827 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5591 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5498 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5773 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9031 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5988 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1703 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1726 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1790 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 323 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 62685 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 548.114030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 339.010384 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.134053 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13424 21.42% 21.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10425 16.63% 38.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5386 8.59% 46.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2710 4.32% 50.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2462 3.93% 54.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1644 2.62% 57.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1512 2.41% 59.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1300 2.07% 62.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23822 38.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62685 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4847 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 83.295234 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3032.862596 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4844 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5671 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5671 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.669018 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.928355 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.069194 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4623 81.52% 81.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 171 3.02% 84.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 302 5.33% 89.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 63 1.11% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 97 1.71% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 43 0.76% 93.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 19 0.34% 93.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 6 0.11% 93.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 22 0.39% 94.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.30% 94.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 4 0.07% 94.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 6 0.11% 95.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 18 0.32% 95.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 43 0.76% 96.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 8 0.14% 96.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 17 0.30% 96.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 89 1.57% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 36 0.63% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 17 0.30% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 22 0.39% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 13 0.23% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 3 0.05% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 5 0.09% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5671 # Writes before turning the bus around for reads -system.physmem.totQLat 3621320000 # Total ticks spent queuing -system.physmem.totMemAccLat 11191295000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2018660000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8969.61 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4847 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4847 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.463586 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.516932 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.014286 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4601 94.92% 94.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 56 1.16% 96.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 4 0.08% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 1 0.02% 96.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 13 0.27% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 3 0.06% 96.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 6 0.12% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 21 0.43% 97.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 18 0.37% 97.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 8 0.17% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 12 0.25% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.04% 98.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.10% 98.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 17 0.35% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 13 0.27% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 3 0.06% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 11 0.23% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 4 0.08% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 2 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 4 0.08% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.08% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 8 0.17% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.04% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::624-639 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 2 0.04% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads +system.physmem.totQLat 3741903500 # Total ticks spent queuing +system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27719.61 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.90 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.90 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28018.06 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.58 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 5.47 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.15 # Data bus utilization in percentage +system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.11 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.54 # Average write queue length when enqueuing -system.physmem.readRowHits 364717 # Number of row buffer hits during reads -system.physmem.writeRowHits 132230 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.26 # Row buffer hit rate for writes -system.physmem.avgGap 3302975.53 # Average gap between requests -system.physmem.pageHitRate 88.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 239009400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 130411875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1579507800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 502640640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 55671864660 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1066592208750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1246139428725 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.311493 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1774205493250 # Time in different power states -system.physmem_0.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem.avgRdQLen 1.48 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.77 # Average write queue length when enqueuing +system.physmem.readRowHits 364326 # Number of row buffer hits during reads +system.physmem.writeRowHits 109846 # Number of row buffer hits during writes +system.physmem.readRowHitRate 90.24 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.50 # Row buffer hit rate for writes +system.physmem.avgGap 3306387.56 # Average gap between requests +system.physmem.pageHitRate 88.32 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 235516680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 128506125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1579609200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 429494400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 56182721175 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1067316698250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1247423979990 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.297807 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1775410357162 # Time in different power states +system.physmem_0.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22762216750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 23446441588 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 242532360 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 132334125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1569601800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 514142640 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 121423785600 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 55569327930 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1066682161500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1246133885955 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.308507 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1774360012750 # Time in different power states -system.physmem_1.memoryStateTime::REF 62077600000 # Time in different power states +system.physmem_1.actEnergy 238381920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 130069500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1569531600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 433097280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 121551434160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 56034129015 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1067447050500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1247403693975 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.286901 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1775626000168 # Time in different power states +system.physmem_1.memoryStateTime::REF 62142860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22607711000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23231077332 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17755011 # Number of BP lookups -system.cpu.branchPred.condPredicted 15447257 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 380557 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11928628 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5915753 # Number of BTB hits +system.cpu.branchPred.lookups 17721924 # Number of BP lookups +system.cpu.branchPred.condPredicted 15403228 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 380344 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11703979 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5913014 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 49.592904 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 917507 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21428 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 50.521400 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 923784 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 21447 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 10297861 # DTB read hits -system.cpu.dtb.read_misses 41459 # DTB read misses -system.cpu.dtb.read_acv 502 # DTB read access violations -system.cpu.dtb.read_accesses 968382 # DTB read accesses -system.cpu.dtb.write_hits 6648165 # DTB write hits -system.cpu.dtb.write_misses 9537 # DTB write misses -system.cpu.dtb.write_acv 407 # DTB write access violations -system.cpu.dtb.write_accesses 342637 # DTB write accesses -system.cpu.dtb.data_hits 16946026 # DTB hits -system.cpu.dtb.data_misses 50996 # DTB misses +system.cpu.dtb.read_hits 10269214 # DTB read hits +system.cpu.dtb.read_misses 41261 # DTB read misses +system.cpu.dtb.read_acv 507 # DTB read access violations +system.cpu.dtb.read_accesses 967301 # DTB read accesses +system.cpu.dtb.write_hits 6648637 # DTB write hits +system.cpu.dtb.write_misses 9303 # DTB write misses +system.cpu.dtb.write_acv 402 # DTB write access violations +system.cpu.dtb.write_accesses 342644 # DTB write accesses +system.cpu.dtb.data_hits 16917851 # DTB hits +system.cpu.dtb.data_misses 50564 # DTB misses system.cpu.dtb.data_acv 909 # DTB access violations -system.cpu.dtb.data_accesses 1311019 # DTB accesses -system.cpu.itb.fetch_hits 1769037 # ITB hits -system.cpu.itb.fetch_misses 35976 # ITB misses -system.cpu.itb.fetch_acv 675 # ITB acv -system.cpu.itb.fetch_accesses 1805013 # ITB accesses +system.cpu.dtb.data_accesses 1309945 # DTB accesses +system.cpu.itb.fetch_hits 1769158 # ITB hits +system.cpu.itb.fetch_misses 36068 # ITB misses +system.cpu.itb.fetch_acv 660 # ITB acv +system.cpu.itb.fetch_accesses 1805226 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -347,254 +353,253 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 118253854 # number of cpu cycles simulated +system.cpu.numCycles 122572361 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29528041 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 78024704 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17755011 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 6833260 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 80443267 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1255548 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1917 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27791 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1737879 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 457742 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 201 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9020958 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 272859 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 112824612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.691557 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.011053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29541441 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 78093998 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17721924 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 6836798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 84630340 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1254210 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1349 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26888 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1745325 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 441267 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 294 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9051182 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 273719 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 117014009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.667390 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.979034 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 98261708 87.09% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 933543 0.83% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1973411 1.75% 89.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 908515 0.81% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2794922 2.48% 92.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 638903 0.57% 93.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 728605 0.65% 94.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1007079 0.89% 95.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 5577926 4.94% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 102427448 87.53% 87.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 934169 0.80% 88.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1984138 1.70% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 910061 0.78% 90.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2793690 2.39% 93.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 647956 0.55% 93.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 739168 0.63% 94.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1007210 0.86% 95.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 5570169 4.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 112824612 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.150143 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.659807 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 24062318 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 76790103 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 9490656 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1896068 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 585466 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 586954 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 42767 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 68209057 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 130935 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 585466 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24987088 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 47248716 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 20734654 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 10372019 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8896667 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 65782894 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 200446 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2040001 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 143212 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4746299 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 43863584 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 79748694 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 79567373 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 168869 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 38138490 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5725086 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1691130 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 241601 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13583154 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 10423192 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6953251 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1496634 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1073096 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 58558441 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2136854 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 57535876 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 59225 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7428094 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3503981 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1475675 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 112824612 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.509959 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.252016 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 117014009 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.144583 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.637126 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 24038562 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 80987042 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 9497307 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 1906242 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 584855 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 586733 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 42672 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 68295720 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 168436 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 38142428 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 62715 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7497440 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3554737 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1474907 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 117014009 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 89346173 79.19% 79.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 10029271 8.89% 88.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 4305402 3.82% 91.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 2956038 2.62% 94.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 3073019 2.72% 97.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 1592834 1.41% 98.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1003723 0.89% 99.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 396113 0.35% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 122039 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 112824612 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 117014009 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 206156 18.23% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.23% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 547934 48.46% 66.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 376604 33.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 210088 18.84% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 39037949 67.85% 67.86% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 61847 0.11% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 38375 0.07% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 10709010 18.61% 86.66% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 6728743 11.69% 98.35% # Type of FU issued -system.cpu.iq.FU_type_0::IprAccess 949030 1.65% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 39070075 67.90% 67.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 61902 0.11% 68.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.02% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 38396 0.07% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 3636 0.01% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.09% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 10678994 18.56% 86.65% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 6730550 11.70% 98.35% # Type of FU issued +system.cpu.iq.FU_type_0::IprAccess 948942 1.65% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 57535876 # Type of FU issued -system.cpu.iq.rate 0.486545 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1130694 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019652 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 228371695 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 67806986 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 55854530 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 714587 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 336328 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 329574 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 58275622 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 383662 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 641458 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued +system.cpu.iq.rate 0.469435 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 67941522 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 334790 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 58264568 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1338736 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3932 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20392 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 579549 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1345105 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 3404 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 20302 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 587155 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 18260 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 537508 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 585466 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 44292826 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 620223 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 64391845 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145304 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 10423192 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 6953251 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1888969 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 42563 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 374293 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20392 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 192990 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 410068 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 603058 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 56949005 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 10367007 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 586870 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 600742 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 56947023 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 10338131 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 592757 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 3696550 # number of nop insts executed -system.cpu.iew.exec_refs 17039818 # number of memory reference insts executed -system.cpu.iew.exec_branches 8972525 # Number of branches executed -system.cpu.iew.exec_stores 6672811 # Number of stores executed -system.cpu.iew.exec_rate 0.481583 # Inst execution rate -system.cpu.iew.wb_sent 56323297 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 56184104 # cumulative count of insts written-back -system.cpu.iew.wb_producers 28889312 # num instructions producing a value -system.cpu.iew.wb_consumers 40263081 # num instructions consuming a value +system.cpu.iew.exec_nop 3706829 # number of nop insts executed +system.cpu.iew.exec_refs 17011176 # number of memory reference insts executed +system.cpu.iew.exec_branches 8976912 # Number of branches executed +system.cpu.iew.exec_stores 6673045 # Number of stores executed +system.cpu.iew.exec_rate 0.464599 # Inst execution rate +system.cpu.iew.wb_sent 56353404 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 56212492 # cumulative count of insts written-back +system.cpu.iew.wb_producers 28792537 # num instructions producing a value +system.cpu.iew.wb_consumers 40027235 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.475114 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.717514 # average fanout of values written-back +system.cpu.iew.wb_rate 0.458607 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.719324 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 8158001 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 661179 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 549251 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 111396128 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.503767 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.456242 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 8228560 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 661115 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 549076 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 115576332 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.485596 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.428292 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 91779533 82.39% 82.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 7802293 7.00% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4122327 3.70% 93.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2151634 1.93% 95.03% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1854051 1.66% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 612708 0.55% 97.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 470628 0.42% 97.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 511278 0.46% 98.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2091676 1.88% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4272054 3.70% 93.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1764307 1.53% 96.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 473670 0.41% 97.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2085445 1.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 111396128 # Number of insts commited each cycle -system.cpu.commit.committedInsts 56117715 # Number of instructions committed -system.cpu.commit.committedOps 56117715 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 115576332 # Number of insts commited each cycle +system.cpu.commit.committedInsts 56123349 # Number of instructions committed +system.cpu.commit.committedOps 56123349 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 15458158 # Number of memory references committed -system.cpu.commit.loads 9084456 # Number of loads committed -system.cpu.commit.membars 226347 # Number of memory barriers committed -system.cpu.commit.branches 8434758 # Number of branches committed +system.cpu.commit.refs 15459994 # Number of memory references committed +system.cpu.commit.loads 9085408 # Number of loads committed +system.cpu.commit.membars 226308 # Number of memory barriers committed +system.cpu.commit.branches 8435685 # Number of branches committed system.cpu.commit.fp_insts 324451 # Number of committed floating point instructions. -system.cpu.commit.int_insts 51969244 # Number of committed integer instructions. -system.cpu.commit.function_calls 739915 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 3195962 5.70% 5.70% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 36179881 64.47% 70.17% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 60661 0.11% 70.27% # Class of committed instruction +system.cpu.commit.int_insts 51974864 # Number of committed integer instructions. +system.cpu.commit.function_calls 740049 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 3196057 5.69% 5.69% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 36183700 64.47% 70.17% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 60673 0.11% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 70.27% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 38087 0.07% 70.34% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 70.34% # Class of committed instruction @@ -622,192 +627,192 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 70.35% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 70.35% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 70.35% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 9310803 16.59% 86.94% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 6379655 11.37% 98.31% # Class of committed instruction -system.cpu.commit.op_class_0::IprAccess 949030 1.69% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 9311716 16.59% 86.94% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 6380538 11.37% 98.31% # Class of committed instruction +system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 56117715 # Class of committed instruction -system.cpu.commit.bw_lim_events 2091676 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction +system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 173330307 # The number of ROB reads -system.cpu.rob.rob_writes 129976168 # The number of ROB writes -system.cpu.timesIdled 574999 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5429242 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 3599836925 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 52929026 # Number of Instructions Simulated -system.cpu.committedOps 52929026 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.234197 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.234197 # CPI: Total CPI of All Threads -system.cpu.ipc 0.447588 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.447588 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 74582639 # number of integer regfile reads -system.cpu.int_regfile_writes 40531859 # number of integer regfile writes -system.cpu.fp_regfile_reads 167323 # number of floating regfile reads -system.cpu.fp_regfile_writes 167888 # number of floating regfile writes -system.cpu.misc_regfile_reads 2030592 # number of misc regfile reads -system.cpu.misc_regfile_writes 939419 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1404198 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.994647 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 11876238 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1404710 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.454584 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25219000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.994647 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 177593269 # The number of ROB reads +system.cpu.rob.rob_writes 130137832 # The number of ROB writes +system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 3599438779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 52934565 # Number of Instructions Simulated +system.cpu.committedOps 52934565 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.315545 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.315545 # CPI: Total CPI of All Threads +system.cpu.ipc 0.431864 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.431864 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 74599299 # number of integer regfile reads +system.cpu.int_regfile_writes 40560409 # number of integer regfile writes +system.cpu.fp_regfile_reads 167171 # number of floating regfile reads +system.cpu.fp_regfile_writes 167579 # number of floating regfile writes +system.cpu.misc_regfile_reads 2029670 # number of misc regfile reads +system.cpu.misc_regfile_writes 939349 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1403663 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.994456 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 11858482 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1404175 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.445160 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 26416000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.994456 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999989 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 413 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63918355 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63918355 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7286393 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7286393 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4187319 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4187319 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 186500 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 186500 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 215720 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 215720 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 11473712 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 11473712 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 11473712 # number of overall hits -system.cpu.dcache.overall_hits::total 11473712 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1773211 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1773211 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1955934 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1955934 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 23306 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 23306 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 28 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 28 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3729145 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3729145 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3729145 # number of overall misses -system.cpu.dcache.overall_misses::total 3729145 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 39410540501 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 39410540501 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 77932908678 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 77932908678 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 363692999 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 363692999 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 466008 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 466008 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 117343449179 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 117343449179 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 117343449179 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 117343449179 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 9059604 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9059604 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6143253 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6143253 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209806 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 209806 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 215748 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 215748 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15202857 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15202857 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15202857 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15202857 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195727 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.195727 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318387 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.318387 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111084 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111084 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000130 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.245292 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.245292 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.245292 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.245292 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22225.522231 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22225.522231 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39844.344788 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39844.344788 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15605.123101 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15605.123101 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16643.142857 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16643.142857 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31466.582602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31466.582602 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31466.582602 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 3975824 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 1887 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 179816 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 63936372 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63936372 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7267066 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7267066 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4189300 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4189300 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 186111 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 186111 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 215710 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 215710 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 11456366 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 11456366 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 11456366 # number of overall hits +system.cpu.dcache.overall_hits::total 11456366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1796718 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1796718 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1954848 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1954848 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 23269 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 23269 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 27 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 27 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3751566 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3751566 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3751566 # number of overall misses +system.cpu.dcache.overall_misses::total 3751566 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 80890671511 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 80890671511 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 376182249 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 455005 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 122732025826 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 122732025826 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 122732025826 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 122732025826 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 9063784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9063784 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6144148 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6144148 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 209380 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 209380 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 215737 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 215737 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15207932 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15207932 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15207932 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15207932 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.198230 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.198230 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.318164 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.318164 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.111133 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.111133 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000125 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000125 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.246685 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.246685 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.246685 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.246685 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 23287.658005 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41379.519794 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41379.519794 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16166.670205 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 32714.878487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 32714.878487 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 32714.878487 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4477815 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 123579 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.110513 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 82.043478 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.234433 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 842396 # number of writebacks -system.cpu.dcache.writebacks::total 842396 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 677447 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 677447 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664842 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1664842 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 5278 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2342289 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2342289 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2342289 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2342289 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1095764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 291092 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 291092 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 18028 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 18028 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 28 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1386856 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1386856 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1386856 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1386856 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27504145773 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 27504145773 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11747551273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11747551273 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 205106501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 205106501 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 409992 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 409992 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 39251697046 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 39251697046 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 39251697046 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 39251697046 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1423712500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1423712500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1999632498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1999632498 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3423344998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3423344998 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120951 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047384 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085927 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085927 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000130 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091223 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091223 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091223 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25100.428352 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25100.428352 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40356.833142 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40356.833142 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11377.107888 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11377.107888 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14642.571429 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14642.571429 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28302.647893 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 28302.647893 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 842087 # number of writebacks +system.cpu.dcache.writebacks::total 842087 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 701160 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 701160 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1664055 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1664055 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5272 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 5272 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2365215 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2365215 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2365215 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2365215 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1095558 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1095558 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 290793 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 290793 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17997 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17997 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 27 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1386351 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1386351 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1386351 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1386351 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29996933023 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29996933023 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12482487876 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12482487876 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 214354001 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 214354001 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 414495 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 414495 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42479420899 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42479420899 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42479420899 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42479420899 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433706500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433706500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2011966000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2011966000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3445672500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3445672500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120872 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120872 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047328 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047328 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085954 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085954 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000125 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000125 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091160 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091160 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091160 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27380.506576 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27380.506576 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42925.682104 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42925.682104 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11910.540701 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11910.540701 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 15351.666667 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 15351.666667 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30641.173050 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 30641.173050 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -815,213 +820,213 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1034381 # number of replacements -system.cpu.icache.tags.tagsinuse 509.395054 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 7933874 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1034889 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.666401 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 26421984250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.395054 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994912 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994912 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1032757 # number of replacements +system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7965141 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1033265 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.708711 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 28360334250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 509.197301 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.994526 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.994526 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 508 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 71 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.992188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10056110 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10056110 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 7933875 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7933875 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 7933875 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7933875 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 7933875 # number of overall hits -system.cpu.icache.overall_hits::total 7933875 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1087081 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1087081 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1087081 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1087081 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1087081 # number of overall misses -system.cpu.icache.overall_misses::total 1087081 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15110067823 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15110067823 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15110067823 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15110067823 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15110067823 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15110067823 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9020956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9020956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9020956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9020956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9020956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9020956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.120506 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.120506 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.120506 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.120506 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.120506 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.120506 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13899.670607 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13899.670607 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13899.670607 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13899.670607 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13899.670607 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3991 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 10084699 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10084699 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7965142 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7965142 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7965142 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7965142 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7965142 # number of overall hits +system.cpu.icache.overall_hits::total 7965142 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1086038 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1086038 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1086038 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1086038 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1086038 # number of overall misses +system.cpu.icache.overall_misses::total 1086038 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15222356868 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15222356868 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15222356868 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15222356868 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15222356868 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15222356868 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9051180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9051180 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9051180 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9051180 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9051180 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9051180 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.119989 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.119989 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.119989 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.119989 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.119989 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.119989 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14016.412748 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14016.412748 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14016.412748 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14016.412748 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14016.412748 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5848 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 208 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 21.808743 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 28.115385 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51927 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 51927 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 51927 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 51927 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 51927 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 51927 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1035154 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1035154 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1035154 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1035154 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1035154 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1035154 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12419429847 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12419429847 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12419429847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12419429847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12419429847 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12419429847 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114750 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.114750 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114750 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.114750 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11997.663968 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11997.663968 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11997.663968 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11997.663968 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 52519 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 52519 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 52519 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 52519 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 52519 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 52519 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1033519 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1033519 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1033519 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1033519 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1033519 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1033519 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13013904297 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13013904297 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13013904297 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13013904297 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13013904297 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13013904297 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.114186 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.114186 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.114186 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.114186 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12591.838464 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12591.838464 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12591.838464 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12591.838464 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 338332 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65337.269998 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2574624 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 403501 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.380713 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5538371750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 53714.137748 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 5350.111230 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 6273.021020 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.819613 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081636 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095719 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996968 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65169 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 498 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3501 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3328 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2420 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55422 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994400 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26963891 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26963891 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 1019836 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 829079 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1848915 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 842396 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 842396 # number of Writeback hits +system.cpu.l2cache.tags.tagsinuse 65331.413764 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2572439 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 403497 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.375361 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 5986676750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 53648.492013 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 5347.510273 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6335.411477 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.818611 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.081597 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.096671 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996878 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65165 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 491 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3500 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3327 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2403 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55444 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994339 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 26943938 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26943938 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 1018225 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 828726 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1846951 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 842087 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 842087 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 31 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 20 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 20 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 186519 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 186519 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 1019836 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1015598 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2035434 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 1019836 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1015598 # number of overall hits -system.cpu.l2cache.overall_hits::total 2035434 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 15129 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 273823 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 288952 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 57 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 57 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 8 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 8 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 115376 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 115376 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 15129 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 389199 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404328 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 15129 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 389199 # number of overall misses -system.cpu.l2cache.overall_misses::total 404328 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1155504000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17984856500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19140360500 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 331495 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 331495 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 92996 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 92996 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9647937355 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9647937355 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1155504000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27632793855 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28788297855 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1155504000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27632793855 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28788297855 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1034965 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1102902 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2137867 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 842396 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 842396 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 88 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 88 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 28 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 28 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 301895 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 301895 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1034965 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1404797 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2439762 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1034965 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1404797 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2439762 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014618 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248275 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.135159 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.647727 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.647727 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382173 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.382173 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014618 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.277050 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.165724 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014618 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.277050 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.165724 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76376.759865 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65680.591112 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66240.623010 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 5815.701754 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 5815.701754 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 11624.500000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 11624.500000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83621.700830 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83621.700830 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71200.356777 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76376.759865 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70999.138885 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71200.356777 # average overall miss latency +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 22 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 22 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 186339 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 186339 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 1018225 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1015065 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2033290 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 1018225 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1015065 # number of overall hits +system.cpu.l2cache.overall_hits::total 2033290 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 15127 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 273931 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 289058 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 48 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 48 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 5 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 5 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 115274 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 115274 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 15127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 389205 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 404332 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 15127 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 389205 # number of overall misses +system.cpu.l2cache.overall_misses::total 404332 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1264836999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 20020012000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21284848999 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 395995 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 395995 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 62498 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 62498 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10271336364 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10271336364 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1264836999 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30291348364 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31556185363 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1264836999 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30291348364 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31556185363 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1033352 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1102657 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2136009 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 842087 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 842087 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 79 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 27 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 27 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 301613 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 301613 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1033352 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1404270 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2437622 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1033352 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1404270 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2437622 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014639 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.248428 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.135326 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.607595 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.607595 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.185185 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.185185 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.382192 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.382192 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014639 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.277158 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.165871 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014639 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.277158 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.165871 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83614.530244 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73084.141627 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 73635.218534 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 8249.895833 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 8249.895833 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 12499.600000 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 12499.600000 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89103.669206 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89103.669206 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78045.233528 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83614.530244 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77828.774975 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78045.233528 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1030,80 +1035,80 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 75938 # number of writebacks -system.cpu.l2cache.writebacks::total 75938 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 75945 # number of writebacks +system.cpu.l2cache.writebacks::total 75945 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15128 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273823 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 288951 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 57 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 57 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 8 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 8 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115376 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 115376 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 15128 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 389199 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 404327 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 15128 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 389199 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 404327 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 964671250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14573298500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15537969750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 720554 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 720554 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 80008 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 80008 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8241634145 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8241634145 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 964671250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22814932645 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23779603895 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 964671250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22814932645 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23779603895 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1333622500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1333622500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1884454000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1884454000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3218076500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3218076500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248275 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135159 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.647727 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.647727 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382173 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382173 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277050 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.165724 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014617 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277050 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.165724 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63767.269302 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53221.601180 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53773.718554 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 12641.298246 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 12641.298246 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71432.829575 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71432.829575 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63767.269302 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58620.224217 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58812.802249 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 15126 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 273931 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 289057 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 48 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 48 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 5 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 5 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 115274 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 115274 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 15126 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 389205 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 404331 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 15126 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 389205 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 404331 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1075826749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16607896000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17683722749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1000544 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1000544 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 89005 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 89005 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8861608136 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8861608136 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1075826749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25469504136 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26545330885 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1075826749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25469504136 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26545330885 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336686500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1336686500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1887182500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1887182500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3223869000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3223869000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.248428 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.135326 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.607595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.607595 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.185185 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.185185 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.382192 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.382192 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.165871 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014638 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.277158 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.165871 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71124.338821 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61177.285964 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20844.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20844.666667 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17801 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76874.300675 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76874.300675 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71124.338821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65439.817412 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65652.475039 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1111,43 +1116,43 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2145159 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2145056 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9597 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9597 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 842396 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41553 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 88 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 28 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 116 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 301895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 301895 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 86 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2070119 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3685432 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5755551 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66237760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143868972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 210106732 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 42071 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3324189 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.012552 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.111331 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 842087 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41601 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 79 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 106 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 301613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 301613 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 94 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2066871 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3684049 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5750920 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 66134528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 143814956 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 42097 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3321757 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.012576 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.111435 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3282463 98.74% 98.74% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41726 1.26% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3279983 98.74% 98.74% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41774 1.26% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3324189 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2496690997 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3321757 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1556745400 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2189304171 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2190379384 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1220,23 +1225,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406216778 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242053963 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23457000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42011283 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024003 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.260535 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.259192 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1709356303000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.260535 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078783 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078783 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1711311066000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.259192 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078699 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078699 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1250,14 +1255,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21133383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21133383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13645647112 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13645647112 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21133383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21133383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21133383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21133383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21719383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21719383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8765491577 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8765491577 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21719383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21719383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21719383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21719383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1274,19 +1279,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122158.283237 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122158.283237 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328399.285522 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328399.285522 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122158.283237 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122158.283237 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206436 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125545.566474 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125545.566474 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210952.338684 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 210952.338684 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125545.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125545.566474 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125545.566474 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 73146 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23523 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10015 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.775921 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.303645 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1300,14 +1305,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12136383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12136383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11484876678 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11484876678 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12136383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12136383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12136383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12567383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12567383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6604781583 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6604781583 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12567383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12567383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12567383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12567383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1316,62 +1321,62 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70152.502890 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276397.686706 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276397.686706 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70152.502890 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70152.502890 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72643.832370 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158952.194431 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158952.194431 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72643.832370 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72643.832370 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 296054 # Transaction distribution -system.membus.trans_dist::ReadResp 295968 # Transaction distribution +system.membus.trans_dist::ReadReq 296160 # Transaction distribution +system.membus.trans_dist::ReadResp 296066 # Transaction distribution system.membus.trans_dist::WriteReq 9597 # Transaction distribution system.membus.trans_dist::WriteResp 9597 # Transaction distribution -system.membus.trans_dist::Writeback 117450 # Transaction distribution +system.membus.trans_dist::Writeback 117457 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 203 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 8 # Transaction distribution -system.membus.trans_dist::UpgradeResp 211 # Transaction distribution -system.membus.trans_dist::ReadExReq 115230 # Transaction distribution -system.membus.trans_dist::ReadExResp 115230 # Transaction distribution -system.membus.trans_dist::BadAddressError 86 # Transaction distribution +system.membus.trans_dist::UpgradeReq 185 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.membus.trans_dist::UpgradeResp 190 # Transaction distribution +system.membus.trans_dist::ReadExReq 115137 # Transaction distribution +system.membus.trans_dist::ReadExResp 115137 # Transaction distribution +system.membus.trans_dist::BadAddressError 94 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33054 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884273 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 172 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917499 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 884248 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 188 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 917490 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1042303 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1042294 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30704576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30748716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30749484 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36065772 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 435 # Total snoops (count) -system.membus.snoop_fanout::samples 563568 # Request fanout histogram +system.membus.snoop_fanout::samples 563651 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 563568 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 563568 # Request fanout histogram -system.membus.reqLayer0.occupancy 31570500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 563651 # Request fanout histogram +system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1858044250 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1226048062 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer2.occupancy 107000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3754720043 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43142717 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1405,28 +1410,28 @@ system.tsunami.ethernet.coalescedTotal nan # av system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6440 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211002 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74661 40.97% 40.97% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6445 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 210982 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74654 40.97% 40.97% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 41.04% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1879 1.03% 42.07% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105562 57.93% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182233 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73294 49.32% 49.32% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 105549 57.93% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182213 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73287 49.32% 49.32% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.41% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1879 1.26% 50.68% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73294 49.32% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 148598 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1817332157500 97.76% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 61952500 0.00% 97.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 528077500 0.03% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41122369500 2.21% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1859044557000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981691 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73287 49.32% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 148584 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1817355802000 97.65% 97.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 62075500 0.00% 97.66% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 532990500 0.03% 97.69% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 43053863500 2.31% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1861004731500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981689 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694322 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.815429 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694341 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.815441 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -1465,7 +1470,7 @@ system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # nu system.cpu.kern.callpal::swpctx 4177 2.18% 2.18% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.21% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu.kern.callpal::swpipl 175118 91.23% 93.44% # number of callpals executed +system.cpu.kern.callpal::swpipl 175098 91.22% 93.43% # number of callpals executed system.cpu.kern.callpal::rdps 6783 3.53% 96.97% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.97% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.97% # number of callpals executed @@ -1474,20 +1479,20 @@ system.cpu.kern.callpal::whami 2 0.00% 96.98% # nu system.cpu.kern.callpal::rti 5104 2.66% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 191962 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5851 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.callpal::total 191942 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5850 # number of protection mode switches +system.cpu.kern.mode_switch::user 1741 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1911 +system.cpu.kern.mode_good::user 1741 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.326953 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.326667 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.394840 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 29081819500 1.56% 1.56% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 2655993500 0.14% 1.71% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1827306736000 98.29% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.081068 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.394509 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 29153631500 1.57% 1.57% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2692582500 0.14% 1.71% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1829158509500 98.29% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt index b0cdac391..43a4f79aa 100644 --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.842592 # Number of seconds simulated -sim_ticks 1842591955000 # Number of ticks simulated -final_tick 1842591955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.841539 # Number of seconds simulated +sim_ticks 1841538755500 # Number of ticks simulated +final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 212167 # Simulator instruction rate (inst/s) -host_op_rate 212167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5858461865 # Simulator tick rate (ticks/s) -host_mem_usage 373744 # Number of bytes of host memory used -host_seconds 314.52 # Real time elapsed on the host -sim_insts 66730424 # Number of instructions simulated -sim_ops 66730424 # Number of ops (including micro ops) simulated +host_inst_rate 221552 # Simulator instruction rate (inst/s) +host_op_rate 221552 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5785089232 # Simulator tick rate (ticks/s) +host_mem_usage 374344 # Number of bytes of host memory used +host_seconds 318.33 # Real time elapsed on the host +sim_insts 70525499 # Number of instructions simulated +sim_ops 70525499 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 480192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 20072256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 146880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2246976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 294016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2555648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 467648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 20091072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 147008 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 2148032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 308096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2634304 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25796928 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 480192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 146880 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 294016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 921088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7481920 # Number of bytes written to this memory -system.physmem.bytes_written::total 7481920 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 7503 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 313629 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2295 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 35109 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 4594 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 39932 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25797120 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 467648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 147008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 308096 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 922752 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7481856 # Number of bytes written to this memory +system.physmem.bytes_written::total 7481856 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 7307 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 313923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2297 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 33563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 4814 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 41161 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 403077 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 116905 # Number of write requests responded to by this memory -system.physmem.num_writes::total 116905 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 260607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 10893489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 79714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1219465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 159567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1386985 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 403080 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116904 # Number of write requests responded to by this memory +system.physmem.num_writes::total 116904 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 253944 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 10909937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 79829 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1166433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 167304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1430491 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14000348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 260607 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 79714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 159567 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 499887 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 4060541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 4060541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 4060541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 10893489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 79714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1219465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 159567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1386985 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 14008459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 253944 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 79829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 167304 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 501077 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4062828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 4062828 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4062828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 253944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 10909937 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 79829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1166433 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 167304 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1430491 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18060889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 81945 # Number of read requests accepted -system.physmem.writeReqs 62218 # Number of write requests accepted -system.physmem.readBursts 81945 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 62218 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5243136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 1344 # Total number of bytes read from write queue -system.physmem.bytesWritten 3931008 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5244480 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 3981952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 21 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 773 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 65 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5216 # Per bank write bursts -system.physmem.perBankRdBursts::1 4952 # Per bank write bursts -system.physmem.perBankRdBursts::2 4966 # Per bank write bursts -system.physmem.perBankRdBursts::3 5032 # Per bank write bursts -system.physmem.perBankRdBursts::4 5011 # Per bank write bursts -system.physmem.perBankRdBursts::5 5077 # Per bank write bursts -system.physmem.perBankRdBursts::6 5139 # Per bank write bursts -system.physmem.perBankRdBursts::7 5153 # Per bank write bursts -system.physmem.perBankRdBursts::8 5336 # Per bank write bursts -system.physmem.perBankRdBursts::9 5012 # Per bank write bursts -system.physmem.perBankRdBursts::10 5284 # Per bank write bursts -system.physmem.perBankRdBursts::11 5137 # Per bank write bursts -system.physmem.perBankRdBursts::12 4814 # Per bank write bursts -system.physmem.perBankRdBursts::13 5083 # Per bank write bursts -system.physmem.perBankRdBursts::14 5582 # Per bank write bursts -system.physmem.perBankRdBursts::15 5130 # Per bank write bursts -system.physmem.perBankWrBursts::0 3820 # Per bank write bursts -system.physmem.perBankWrBursts::1 3672 # Per bank write bursts -system.physmem.perBankWrBursts::2 3762 # Per bank write bursts -system.physmem.perBankWrBursts::3 4075 # Per bank write bursts -system.physmem.perBankWrBursts::4 3759 # Per bank write bursts -system.physmem.perBankWrBursts::5 3520 # Per bank write bursts -system.physmem.perBankWrBursts::6 4123 # Per bank write bursts -system.physmem.perBankWrBursts::7 3706 # Per bank write bursts -system.physmem.perBankWrBursts::8 4379 # Per bank write bursts -system.physmem.perBankWrBursts::9 3471 # Per bank write bursts -system.physmem.perBankWrBursts::10 3889 # Per bank write bursts -system.physmem.perBankWrBursts::11 3981 # Per bank write bursts -system.physmem.perBankWrBursts::12 3541 # Per bank write bursts -system.physmem.perBankWrBursts::13 3879 # Per bank write bursts -system.physmem.perBankWrBursts::14 4169 # Per bank write bursts -system.physmem.perBankWrBursts::15 3676 # Per bank write bursts +system.physmem.bw_total::total 18071287 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 81850 # Number of read requests accepted +system.physmem.writeReqs 64472 # Number of write requests accepted +system.physmem.readBursts 81850 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 64472 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5236928 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 1472 # Total number of bytes read from write queue +system.physmem.bytesWritten 3416192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5238400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4126208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 23 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11076 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 49 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 4878 # Per bank write bursts +system.physmem.perBankRdBursts::1 4919 # Per bank write bursts +system.physmem.perBankRdBursts::2 4947 # Per bank write bursts +system.physmem.perBankRdBursts::3 4947 # Per bank write bursts +system.physmem.perBankRdBursts::4 5010 # Per bank write bursts +system.physmem.perBankRdBursts::5 5136 # Per bank write bursts +system.physmem.perBankRdBursts::6 5318 # Per bank write bursts +system.physmem.perBankRdBursts::7 5111 # Per bank write bursts +system.physmem.perBankRdBursts::8 5349 # Per bank write bursts +system.physmem.perBankRdBursts::9 4830 # Per bank write bursts +system.physmem.perBankRdBursts::10 5530 # Per bank write bursts +system.physmem.perBankRdBursts::11 5119 # Per bank write bursts +system.physmem.perBankRdBursts::12 4880 # Per bank write bursts +system.physmem.perBankRdBursts::13 5044 # Per bank write bursts +system.physmem.perBankRdBursts::14 5637 # Per bank write bursts +system.physmem.perBankRdBursts::15 5172 # Per bank write bursts +system.physmem.perBankWrBursts::0 3097 # Per bank write bursts +system.physmem.perBankWrBursts::1 3264 # Per bank write bursts +system.physmem.perBankWrBursts::2 3389 # Per bank write bursts +system.physmem.perBankWrBursts::3 3378 # Per bank write bursts +system.physmem.perBankWrBursts::4 3165 # Per bank write bursts +system.physmem.perBankWrBursts::5 3060 # Per bank write bursts +system.physmem.perBankWrBursts::6 3647 # Per bank write bursts +system.physmem.perBankWrBursts::7 3165 # Per bank write bursts +system.physmem.perBankWrBursts::8 3847 # Per bank write bursts +system.physmem.perBankWrBursts::9 3079 # Per bank write bursts +system.physmem.perBankWrBursts::10 3680 # Per bank write bursts +system.physmem.perBankWrBursts::11 3339 # Per bank write bursts +system.physmem.perBankWrBursts::12 2997 # Per bank write bursts +system.physmem.perBankWrBursts::13 3248 # Per bank write bursts +system.physmem.perBankWrBursts::14 3739 # Per bank write bursts +system.physmem.perBankWrBursts::15 3284 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1841579678500 # Total gap between requests +system.physmem.numWrRetry 18 # Number of times write queue was full causing retry +system.physmem.totGap 1840526879500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 81945 # Read request sizes (log2) +system.physmem.readPktSize::6 81850 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 62218 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 65839 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 7250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 7148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 64472 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 63937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7813 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 5603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -153,216 +153,196 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 78 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1778 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4782 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 3896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 3337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 3243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2582 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22279 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 411.784371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 233.119875 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 394.569349 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 7102 31.88% 31.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 4721 21.19% 53.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 1798 8.07% 61.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1010 4.53% 65.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 955 4.29% 69.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 478 2.15% 72.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 370 1.66% 73.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 364 1.63% 75.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5481 24.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22279 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2129 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 38.475810 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 1006.180082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 2127 99.91% 99.91% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::3 45 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 40 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 624 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 3121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 525 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 416 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 660 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 807 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1014 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 22135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 390.924780 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 222.627349 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 384.024543 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7145 32.28% 32.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 4994 22.56% 54.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 1972 8.91% 63.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1000 4.52% 68.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 834 3.77% 72.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 471 2.13% 74.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 534 2.41% 76.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 337 1.52% 78.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4848 21.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 22135 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1909 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 42.863279 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 1017.016663 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 1907 99.90% 99.90% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.05% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2129 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2129 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 28.850164 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.675931 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 36.499081 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 34 1.60% 1.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 7 0.33% 1.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 1 0.05% 1.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 1 0.05% 2.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 1615 75.86% 77.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 35 1.64% 79.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 10 0.47% 79.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 84 3.95% 83.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 64 3.01% 86.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 45 2.11% 89.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 9 0.42% 89.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 11 0.52% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 35 1.64% 91.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 5 0.23% 91.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 21 0.99% 92.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 2 0.09% 92.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 3 0.14% 93.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 2 0.09% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.23% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 1 0.05% 93.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.19% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.05% 93.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.14% 93.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.19% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.05% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.05% 94.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.28% 94.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.09% 94.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.05% 94.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 15 0.70% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 3 0.14% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.09% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.05% 95.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.19% 95.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 43 2.02% 97.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.05% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 11 0.52% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.14% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.14% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.09% 98.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 6 0.28% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.19% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 5 0.23% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.14% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.14% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.14% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2129 # Writes before turning the bus around for reads -system.physmem.totQLat 814366500 # Total ticks spent queuing -system.physmem.totMemAccLat 2350441500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 409620000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9940.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::43008-45055 1 0.05% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 1909 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.961236 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.965205 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.780578 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 45 2.36% 2.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 1768 92.61% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 14 0.73% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 2 0.10% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 2 0.10% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 1 0.05% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 1 0.05% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 2 0.10% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.58% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.63% 97.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 5 0.26% 97.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 8 0.42% 98.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 1 0.05% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.05% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.10% 98.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.10% 98.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.31% 98.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.26% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 2 0.10% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.10% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.05% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.05% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.10% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.10% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.16% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 4 0.21% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 2 0.10% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1909 # Writes before turning the bus around for reads +system.physmem.totQLat 884680000 # Total ticks spent queuing +system.physmem.totMemAccLat 2418936250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 409135000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10811.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28690.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.85 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.85 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.16 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29561.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.84 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.24 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.04 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 8.28 # Average write queue length when enqueuing -system.physmem.readRowHits 70260 # Number of row buffer hits during reads -system.physmem.writeRowHits 50807 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.76 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 82.69 # Row buffer hit rate for writes -system.physmem.avgGap 12774287.98 # Average gap between requests -system.physmem.pageHitRate 84.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 83779920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 45618375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 316258800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 197231760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 35724246975 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 802806617250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 928299910200 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.726630 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1309959191250 # Time in different power states -system.physmem_0.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.99 # Average write queue length when enqueuing +system.physmem.readRowHits 70087 # Number of row buffer hits during reads +system.physmem.writeRowHits 42983 # Number of row buffer hits during writes +system.physmem.readRowHitRate 85.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.50 # Row buffer hit rate for writes +system.physmem.avgGap 12578606.63 # Average gap between requests +system.physmem.pageHitRate 83.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 81814320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 44558250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 314074800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 169549200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 35647575705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 798651060750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 923964608865 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.989912 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1309028017250 # Time in different power states +system.physmem_0.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9222216250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9101184500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 84649320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 46030875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 322748400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 200782800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 89126157120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 35431940430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 799831550250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 925043859195 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.972279 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1310405285500 # Time in different power states -system.physmem_1.memoryStateTime::REF 45565260000 # Time in different power states +system.physmem_1.actEnergy 85526280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 46513500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 324175800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 176340240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 89055975840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 35475772860 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 801505403250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 926669707770 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.770193 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1309231204000 # Time in different power states +system.physmem_1.memoryStateTime::REF 45529640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 8771812500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 8903896000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 4841130 # DTB read hits -system.cpu0.dtb.read_misses 6162 # DTB read misses -system.cpu0.dtb.read_acv 126 # DTB read access violations -system.cpu0.dtb.read_accesses 429577 # DTB read accesses -system.cpu0.dtb.write_hits 3448228 # DTB write hits -system.cpu0.dtb.write_misses 688 # DTB write misses -system.cpu0.dtb.write_acv 85 # DTB write access violations -system.cpu0.dtb.write_accesses 165228 # DTB write accesses -system.cpu0.dtb.data_hits 8289358 # DTB hits -system.cpu0.dtb.data_misses 6850 # DTB misses -system.cpu0.dtb.data_acv 211 # DTB access violations -system.cpu0.dtb.data_accesses 594805 # DTB accesses -system.cpu0.itb.fetch_hits 2744473 # ITB hits -system.cpu0.itb.fetch_misses 3071 # ITB misses -system.cpu0.itb.fetch_acv 104 # ITB acv -system.cpu0.itb.fetch_accesses 2747544 # ITB accesses +system.cpu0.dtb.read_hits 4781172 # DTB read hits +system.cpu0.dtb.read_misses 6058 # DTB read misses +system.cpu0.dtb.read_acv 118 # DTB read access violations +system.cpu0.dtb.read_accesses 428328 # DTB read accesses +system.cpu0.dtb.write_hits 3391530 # DTB write hits +system.cpu0.dtb.write_misses 675 # DTB write misses +system.cpu0.dtb.write_acv 82 # DTB write access violations +system.cpu0.dtb.write_accesses 163639 # DTB write accesses +system.cpu0.dtb.data_hits 8172702 # DTB hits +system.cpu0.dtb.data_misses 6733 # DTB misses +system.cpu0.dtb.data_acv 200 # DTB access violations +system.cpu0.dtb.data_accesses 591967 # DTB accesses +system.cpu0.itb.fetch_hits 2720050 # ITB hits +system.cpu0.itb.fetch_misses 3046 # ITB misses +system.cpu0.itb.fetch_acv 99 # ITB acv +system.cpu0.itb.fetch_accesses 2723096 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -375,87 +355,87 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 929111283 # number of cpu cycles simulated +system.cpu0.numCycles 930048733 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 30392058 # Number of instructions committed -system.cpu0.committedOps 30392058 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 28296981 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 165313 # Number of float alu accesses -system.cpu0.num_func_calls 800920 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 3653475 # number of instructions that are conditional controls -system.cpu0.num_int_insts 28296981 # number of integer instructions -system.cpu0.num_fp_insts 165313 # number of float instructions -system.cpu0.num_int_register_reads 38988704 # number of times the integer registers were read -system.cpu0.num_int_register_writes 20831324 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 85482 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 86956 # number of times the floating registers were written -system.cpu0.num_mem_refs 8319320 # number of memory refs -system.cpu0.num_load_insts 4862427 # Number of load instructions -system.cpu0.num_store_insts 3456893 # Number of store instructions -system.cpu0.num_idle_cycles 905971177.002448 # Number of idle cycles -system.cpu0.num_busy_cycles 23140105.997552 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024906 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975094 # Percentage of idle cycles -system.cpu0.Branches 4712544 # Number of branches fetched -system.cpu0.op_class::No_OpClass 1584509 5.21% 5.21% # Class of executed instruction -system.cpu0.op_class::IntAlu 19793641 65.11% 70.32% # Class of executed instruction -system.cpu0.op_class::IntMult 31883 0.10% 70.43% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 70.43% # Class of executed instruction -system.cpu0.op_class::FloatAdd 12951 0.04% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 70.47% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1606 0.01% 70.48% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 70.48% # Class of executed instruction -system.cpu0.op_class::MemRead 4993701 16.43% 86.90% # Class of executed instruction -system.cpu0.op_class::MemWrite 3459999 11.38% 98.29% # Class of executed instruction -system.cpu0.op_class::IprAccess 520829 1.71% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31504183 # Number of instructions committed +system.cpu0.committedOps 31504183 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 29439494 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 162688 # Number of float alu accesses +system.cpu0.num_func_calls 792913 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4107229 # number of instructions that are conditional controls +system.cpu0.num_int_insts 29439494 # number of integer instructions +system.cpu0.num_fp_insts 162688 # number of float instructions +system.cpu0.num_int_register_reads 41004383 # number of times the integer registers were read +system.cpu0.num_int_register_writes 21582488 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 84172 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 85625 # number of times the floating registers were written +system.cpu0.num_mem_refs 8202083 # number of memory refs +system.cpu0.num_load_insts 4802046 # Number of load instructions +system.cpu0.num_store_insts 3400037 # Number of store instructions +system.cpu0.num_idle_cycles 907048310.649553 # Number of idle cycles +system.cpu0.num_busy_cycles 23000422.350447 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024730 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975270 # Percentage of idle cycles +system.cpu0.Branches 5154717 # Number of branches fetched +system.cpu0.op_class::No_OpClass 1560474 4.95% 4.95% # Class of executed instruction +system.cpu0.op_class::IntAlu 21056937 66.82% 71.78% # Class of executed instruction +system.cpu0.op_class::IntMult 31354 0.10% 71.88% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.88% # Class of executed instruction +system.cpu0.op_class::FloatAdd 12843 0.04% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1601 0.01% 71.92% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.92% # Class of executed instruction +system.cpu0.op_class::MemRead 4932088 15.65% 87.57% # Class of executed instruction +system.cpu0.op_class::MemWrite 3403118 10.80% 98.37% # Class of executed instruction +system.cpu0.op_class::IprAccess 512701 1.63% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 30399119 # Class of executed instruction +system.cpu0.op_class::total 31511116 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6424 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 211373 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 74797 40.97% 40.97% # number of times we switched to this ipl +system.cpu0.kern.inst.quiesce 6421 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 211361 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 74795 40.97% 40.97% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 203 0.11% 41.08% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1879 1.03% 42.11% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 105693 57.89% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 182572 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 73430 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count::22 1878 1.03% 42.11% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 105682 57.89% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 182558 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 73428 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 203 0.14% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1879 1.26% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 73430 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 148942 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1819763275500 98.76% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 38885000 0.00% 98.76% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 357575500 0.02% 98.78% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 22431449500 1.22% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1842591185500 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1878 1.26% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 73428 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 148937 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1818811073000 98.77% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 38572000 0.00% 98.77% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 355311500 0.02% 98.79% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 22333065000 1.21% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1841538021500 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.981723 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.694748 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.815799 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.694801 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.815834 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu0.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu0.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -491,278 +471,276 @@ system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu0.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed +system.cpu0.kern.callpal::swpctx 4174 2.17% 2.17% # number of callpals executed system.cpu0.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed -system.cpu0.kern.callpal::swpipl 175313 91.20% 93.41% # number of callpals executed -system.cpu0.kern.callpal::rdps 6783 3.53% 96.94% # number of callpals executed +system.cpu0.kern.callpal::swpipl 175301 91.20% 93.41% # number of callpals executed +system.cpu0.kern.callpal::rdps 6782 3.53% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::wrusp 7 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::rdusp 9 0.00% 96.94% # number of callpals executed system.cpu0.kern.callpal::whami 2 0.00% 96.95% # number of callpals executed -system.cpu0.kern.callpal::rti 5176 2.69% 99.64% # number of callpals executed +system.cpu0.kern.callpal::rti 5175 2.69% 99.64% # number of callpals executed system.cpu0.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 192228 # number of callpals executed +system.cpu0.kern.callpal::total 192212 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5922 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1740 # number of protection mode switches -system.cpu0.kern.mode_switch::idle 2096 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1910 -system.cpu0.kern.mode_good::user 1740 -system.cpu0.kern.mode_good::idle 170 -system.cpu0.kern.mode_switch_good::kernel 0.322526 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch::user 1737 # number of protection mode switches +system.cpu0.kern.mode_switch::idle 2093 # number of protection mode switches +system.cpu0.kern.mode_good::kernel 1906 +system.cpu0.kern.mode_good::user 1737 +system.cpu0.kern.mode_good::idle 169 +system.cpu0.kern.mode_switch_good::kernel 0.321851 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::idle 0.081107 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.391474 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 29641344500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 2562591500 0.14% 1.75% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::idle 1810387245000 98.25% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 4177 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1393017 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.997818 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 13281490 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1393529 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.530831 # Average number of references to valid blocks. +system.cpu0.kern.mode_switch_good::idle 0.080745 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::total 0.390894 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 29730845000 1.61% 1.61% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 2571229000 0.14% 1.75% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::idle 1809235945500 98.25% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.swap_context 4175 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1393219 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997816 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 13266024 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1393731 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.518353 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 260.752731 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 75.043138 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 176.201949 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.509283 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.146569 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.344144 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 178.252416 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 164.663502 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 169.081899 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.348149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.321608 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.330238 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 266 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63366474 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63366474 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4014509 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1053432 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 2506621 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7574562 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3156846 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 808200 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 1357961 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5323007 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 114880 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 18791 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 50813 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 184484 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 123743 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 20765 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 54820 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 199328 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 7171355 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 1861632 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 3864582 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 12897569 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 7171355 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 1861632 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 3864582 # number of overall hits -system.cpu0.dcache.overall_hits::total 12897569 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 713110 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 94552 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 558128 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1365790 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 166356 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 43595 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 617033 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 826984 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9412 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2104 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7556 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19072 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 7 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 9 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 879466 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 138147 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1175161 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2192774 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 879466 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 138147 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1175161 # number of overall misses -system.cpu0.dcache.overall_misses::total 2192774 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2193347250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 9664547340 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 11857894590 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1652894510 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19391335975 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 21044230485 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27729500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 125483249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 153212749 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 91000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 91000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 3846241760 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 29055883315 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 32902125075 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 3846241760 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 29055883315 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 32902125075 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 4727619 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1147984 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 3064749 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8940352 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3323202 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 851795 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 1974994 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6149991 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 124292 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 20895 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 203556 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123745 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 20765 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 54827 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 199337 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8050821 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 1999779 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 5039743 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 15090343 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8050821 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 1999779 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 5039743 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 15090343 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.150839 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082364 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.182112 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.152767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.050059 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.051180 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.312423 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.134469 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075725 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.100694 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.129452 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093694 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000016 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000128 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000045 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109239 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.069081 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.233179 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.145310 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109239 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.069081 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.233179 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.145310 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23197.259180 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17316.005182 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 8682.077472 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37914.772566 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31426.740507 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 25446.962075 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13179.420152 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16607.100185 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8033.386588 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 10111.111111 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15004.795330 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 27841.659681 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 24725.023478 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15004.795330 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 825255 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1343 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 61465 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 9 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.426422 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 149.222222 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 63377040 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63377040 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 3961674 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1077685 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 2542197 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 7581556 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3105087 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 828848 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 1366589 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5300524 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 113741 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 19662 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 51148 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 184551 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122328 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 21764 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 55225 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 199317 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 7066761 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 1906533 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 3908786 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12882080 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 7066761 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 1906533 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 3908786 # number of overall hits +system.cpu0.dcache.overall_hits::total 12882080 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 706841 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 96965 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 557653 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1361459 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 162721 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 43998 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 642629 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 849348 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9135 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2231 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 7695 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19061 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 11 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 11 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 869562 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 140963 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1200282 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2210807 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 869562 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 140963 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1200282 # number of overall misses +system.cpu0.dcache.overall_misses::total 2210807 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2267399500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 8210771504 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 10478171004 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1754611010 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19498280034 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 21252891044 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 29510000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 125540000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 155050000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 185002 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 185002 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4022010510 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27709051538 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 31731062048 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4022010510 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 27709051538 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 31731062048 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 4668515 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1174650 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 3099850 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8943015 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3267808 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 872846 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2009218 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 6149872 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 122876 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 21893 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 58843 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 203612 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 122328 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 21764 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 55236 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 199328 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 7936323 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 2047496 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 5109068 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 15092887 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 7936323 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 2047496 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 5109068 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 15092887 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.151406 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.082548 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.179897 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.152237 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049795 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.050408 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.319840 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.138108 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.074343 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.101905 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.130772 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.093614 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000199 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000055 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.109567 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.068847 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.234932 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.146480 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.109567 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.068847 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.234932 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.146480 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 23383.689991 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14723.800471 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 7696.280978 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 39879.335652 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30341.425666 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25022.595031 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13227.252353 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 16314.489929 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 8134.410577 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16818.363636 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16818.363636 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 28532.384455 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23085.451201 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14352.705617 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 28532.384455 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 23085.451201 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14352.705617 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 977120 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1794 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 54184 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 18 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.033368 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 99.666667 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 835667 # number of writebacks -system.cpu0.dcache.writebacks::total 835667 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 292188 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 292188 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 524505 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 524505 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1570 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1570 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 816693 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 816693 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 816693 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 816693 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 94552 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 265940 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 360492 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43595 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 92528 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 136123 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2104 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 5986 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8090 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 7 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 138147 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 358468 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 496615 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 138147 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 358468 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 496615 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1996702750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4449426882 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6446129632 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1557368490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2781486410 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4338854900 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 23520500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72740751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96261251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 77000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 77000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3554071240 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7230913292 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10784984532 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3554071240 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7230913292 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10784984532 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 249355000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 342279000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 591634000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320316500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 419818000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740134500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 569671500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 762097000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1331768500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082364 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086774 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.040322 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.051180 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.046850 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022134 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.100694 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102554 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.039743 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000128 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.032909 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.069081 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071128 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032909 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21117.509413 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16730.942626 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17881.477625 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35723.557518 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 30061.023798 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31874.517165 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11178.944867 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12151.812730 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11898.794932 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25726.734855 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20171.712097 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21716.993107 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 835707 # number of writebacks +system.cpu0.dcache.writebacks::total 835707 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 287560 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 287560 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 546849 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 546849 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 1691 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1691 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 834409 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 834409 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 834409 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 834409 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 96965 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 270093 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 367058 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 43998 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 95780 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 139778 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 2231 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 6004 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8235 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 11 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 140963 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 365873 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 506836 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 140963 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 365873 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 506836 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2114965000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4270329509 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6385294509 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1680467990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3020406043 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4700874033 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 26161500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 72039750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 98201250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 168498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 168498 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 3795432990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7290735552 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11086168542 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 3795432990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 7290735552 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11086168542 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 222473500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 331326000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 553799500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 293979000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 446199000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 740178000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 516452500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 777525000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1293977500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.082548 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087131 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041044 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.050408 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.047670 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022729 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.101905 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.102034 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.040445 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000199 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000055 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.033581 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.068847 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.071612 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.033581 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 21811.633063 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15810.589349 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 17395.873429 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38194.190418 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 31534.830267 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33631.000823 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11726.355894 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11998.625916 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11924.863388 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 15318 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15318 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -773,163 +751,163 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 964323 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.193139 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39678129 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 964834 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 41.124306 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10191163250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 263.937948 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 65.959779 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 181.295411 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.515504 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.128828 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.354093 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998424 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 964809 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.919385 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 41279952 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 965320 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 42.762972 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10189587250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 147.730782 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 136.243694 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 226.944909 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.288537 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.266101 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.443252 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997889 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 447 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 41624427 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 41624427 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 29884884 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 7331949 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 2461296 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39678129 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29884884 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 7331949 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 2461296 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39678129 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29884884 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 7331949 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 2461296 # number of overall hits -system.cpu0.icache.overall_hits::total 39678129 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 514235 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 124188 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 342842 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 981265 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 514235 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 124188 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 342842 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 981265 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 514235 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 124188 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 342842 # number of overall misses -system.cpu0.icache.overall_misses::total 981265 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1771676000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4819389197 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6591065197 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1771676000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4819389197 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6591065197 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1771676000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4819389197 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6591065197 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 30399119 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 7456137 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 2804138 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 40659394 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 30399119 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 7456137 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 2804138 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 40659394 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 30399119 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 7456137 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 2804138 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 40659394 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016916 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016656 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122263 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.024134 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016916 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016656 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122263 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.024134 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016916 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016656 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122263 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.024134 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14266.080459 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14057.172683 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6716.906439 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14266.080459 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14057.172683 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6716.906439 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14266.080459 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14057.172683 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6716.906439 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2709 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43227698 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43227698 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 31004099 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 7794052 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 2481801 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 41279952 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31004099 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 7794052 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 2481801 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 41279952 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31004099 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 7794052 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 2481801 # number of overall hits +system.cpu0.icache.overall_hits::total 41279952 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 507017 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 128848 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 346369 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 982234 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 507017 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 128848 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 346369 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 982234 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 507017 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 128848 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 346369 # number of overall misses +system.cpu0.icache.overall_misses::total 982234 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1839260250 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4838788318 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 6678048568 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1839260250 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4838788318 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 6678048568 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1839260250 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4838788318 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 6678048568 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 31511116 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 7922900 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 2828170 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 42262186 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 31511116 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 7922900 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 2828170 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 42262186 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 31511116 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 7922900 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 2828170 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 42262186 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016090 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016263 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.122471 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023241 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016090 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016263 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.122471 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023241 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016090 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016263 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.122471 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023241 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14274.651139 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13970.038652 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6798.836701 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14274.651139 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13970.038652 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6798.836701 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14274.651139 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13970.038652 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6798.836701 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4002 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 225 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.705882 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.786667 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16232 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 16232 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 16232 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 16232 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 16232 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 16232 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 124188 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 326610 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 450798 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 124188 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 326610 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 450798 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 124188 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 326610 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 450798 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1522394000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3982795175 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5505189175 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1522394000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3982795175 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5505189175 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1522394000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3982795175 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5505189175 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011087 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011087 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016656 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116474 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011087 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12212.097602 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12258.785068 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12194.345473 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12212.097602 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 16722 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 16722 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 16722 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 16722 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 16722 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 16722 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128848 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 329647 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 458495 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 128848 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 329647 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 458495 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 128848 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 329647 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 458495 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1645092750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4148478396 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5793571146 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1645092750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4148478396 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5793571146 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1645092750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4148478396 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5793571146 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010849 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010849 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016263 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.116558 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010849 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12636.061780 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12767.701090 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12584.608372 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12636.061780 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 1166781 # DTB read hits -system.cpu1.dtb.read_misses 1314 # DTB read misses -system.cpu1.dtb.read_acv 34 # DTB read access violations -system.cpu1.dtb.read_accesses 141633 # DTB read accesses -system.cpu1.dtb.write_hits 872888 # DTB write hits -system.cpu1.dtb.write_misses 168 # DTB write misses +system.cpu1.dtb.read_hits 1194215 # DTB read hits +system.cpu1.dtb.read_misses 1316 # DTB read misses +system.cpu1.dtb.read_acv 35 # DTB read access violations +system.cpu1.dtb.read_accesses 141030 # DTB read accesses +system.cpu1.dtb.write_hits 894755 # DTB write hits +system.cpu1.dtb.write_misses 169 # DTB write misses system.cpu1.dtb.write_acv 22 # DTB write access violations -system.cpu1.dtb.write_accesses 57088 # DTB write accesses -system.cpu1.dtb.data_hits 2039669 # DTB hits -system.cpu1.dtb.data_misses 1482 # DTB misses -system.cpu1.dtb.data_acv 56 # DTB access violations -system.cpu1.dtb.data_accesses 198721 # DTB accesses -system.cpu1.itb.fetch_hits 848090 # ITB hits -system.cpu1.itb.fetch_misses 662 # ITB misses -system.cpu1.itb.fetch_acv 32 # ITB acv -system.cpu1.itb.fetch_accesses 848752 # ITB accesses +system.cpu1.dtb.write_accesses 57515 # DTB write accesses +system.cpu1.dtb.data_hits 2088970 # DTB hits +system.cpu1.dtb.data_misses 1485 # DTB misses +system.cpu1.dtb.data_acv 57 # DTB access violations +system.cpu1.dtb.data_accesses 198545 # DTB accesses +system.cpu1.itb.fetch_hits 856400 # ITB hits +system.cpu1.itb.fetch_misses 653 # ITB misses +system.cpu1.itb.fetch_acv 34 # ITB acv +system.cpu1.itb.fetch_accesses 857053 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -942,64 +920,64 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 953408444 # number of cpu cycles simulated +system.cpu1.numCycles 953255662 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7454598 # Number of instructions committed -system.cpu1.committedOps 7454598 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 6929268 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 43953 # Number of float alu accesses -system.cpu1.num_func_calls 203515 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 903765 # number of instructions that are conditional controls -system.cpu1.num_int_insts 6929268 # number of integer instructions -system.cpu1.num_fp_insts 43953 # number of float instructions -system.cpu1.num_int_register_reads 9641119 # number of times the integer registers were read -system.cpu1.num_int_register_writes 5054145 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 23746 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 24129 # number of times the floating registers were written -system.cpu1.num_mem_refs 2046592 # number of memory refs -system.cpu1.num_load_insts 1171450 # Number of load instructions -system.cpu1.num_store_insts 875142 # Number of store instructions -system.cpu1.num_idle_cycles 924951081.946169 # Number of idle cycles -system.cpu1.num_busy_cycles 28457362.053831 # Number of busy cycles -system.cpu1.not_idle_fraction 0.029848 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.970152 # Percentage of idle cycles -system.cpu1.Branches 1171881 # Number of branches fetched -system.cpu1.op_class::No_OpClass 398972 5.35% 5.35% # Class of executed instruction -system.cpu1.op_class::IntAlu 4837309 64.88% 70.23% # Class of executed instruction -system.cpu1.op_class::IntMult 8193 0.11% 70.34% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu1.op_class::FloatAdd 5097 0.07% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 70.41% # Class of executed instruction -system.cpu1.op_class::FloatDiv 810 0.01% 70.42% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 70.42% # Class of executed instruction -system.cpu1.op_class::MemRead 1199545 16.09% 86.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 876356 11.75% 98.26% # Class of executed instruction -system.cpu1.op_class::IprAccess 129854 1.74% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7921357 # Number of instructions committed +system.cpu1.committedOps 7921357 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 7380748 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 45896 # Number of float alu accesses +system.cpu1.num_func_calls 207012 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1022630 # number of instructions that are conditional controls +system.cpu1.num_int_insts 7380748 # number of integer instructions +system.cpu1.num_fp_insts 45896 # number of float instructions +system.cpu1.num_int_register_reads 10351742 # number of times the integer registers were read +system.cpu1.num_int_register_writes 5363285 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 24726 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 25085 # number of times the floating registers were written +system.cpu1.num_mem_refs 2096070 # number of memory refs +system.cpu1.num_load_insts 1198996 # Number of load instructions +system.cpu1.num_store_insts 897074 # Number of store instructions +system.cpu1.num_idle_cycles 923177922.874727 # Number of idle cycles +system.cpu1.num_busy_cycles 30077739.125273 # Number of busy cycles +system.cpu1.not_idle_fraction 0.031553 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.968447 # Percentage of idle cycles +system.cpu1.Branches 1296149 # Number of branches fetched +system.cpu1.op_class::No_OpClass 410448 5.18% 5.18% # Class of executed instruction +system.cpu1.op_class::IntAlu 5236817 66.10% 71.28% # Class of executed instruction +system.cpu1.op_class::IntMult 8727 0.11% 71.39% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 71.39% # Class of executed instruction +system.cpu1.op_class::FloatAdd 5162 0.07% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 71.45% # Class of executed instruction +system.cpu1.op_class::FloatDiv 810 0.01% 71.46% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 71.46% # Class of executed instruction +system.cpu1.op_class::MemRead 1228055 15.50% 86.96% # Class of executed instruction +system.cpu1.op_class::MemWrite 898300 11.34% 98.30% # Class of executed instruction +system.cpu1.op_class::IprAccess 134580 1.70% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 7456136 # Class of executed instruction +system.cpu1.op_class::total 7922899 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed system.cpu1.kern.inst.hwrei 0 # number of hwrei instructions executed @@ -1017,35 +995,35 @@ system.cpu1.kern.mode_ticks::kernel 0 # nu system.cpu1.kern.mode_ticks::user 0 # number of ticks spent at the given mode system.cpu1.kern.mode_ticks::idle 0 # number of ticks spent at the given mode system.cpu1.kern.swap_context 0 # number of times the context was actually changed -system.cpu2.branchPred.lookups 9673449 # Number of BP lookups -system.cpu2.branchPred.condPredicted 8936896 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 125098 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 7569787 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 5584968 # Number of BTB hits +system.cpu2.branchPred.lookups 10412478 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9668294 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 126557 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 8251745 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 6275895 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 73.779725 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 299823 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 7809 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 76.055368 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 302998 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 7851 # Number of incorrect RAS predictions. system.cpu2.dtb.fetch_hits 0 # ITB hits system.cpu2.dtb.fetch_misses 0 # ITB misses system.cpu2.dtb.fetch_acv 0 # ITB acv system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.read_hits 3461968 # DTB read hits -system.cpu2.dtb.read_misses 12174 # DTB read misses -system.cpu2.dtb.read_acv 114 # DTB read access violations -system.cpu2.dtb.read_accesses 224881 # DTB read accesses -system.cpu2.dtb.write_hits 2122047 # DTB write hits -system.cpu2.dtb.write_misses 2563 # DTB write misses -system.cpu2.dtb.write_acv 106 # DTB write access violations -system.cpu2.dtb.write_accesses 83942 # DTB write accesses -system.cpu2.dtb.data_hits 5584015 # DTB hits -system.cpu2.dtb.data_misses 14737 # DTB misses -system.cpu2.dtb.data_acv 220 # DTB access violations -system.cpu2.dtb.data_accesses 308823 # DTB accesses -system.cpu2.itb.fetch_hits 534012 # ITB hits -system.cpu2.itb.fetch_misses 5788 # ITB misses -system.cpu2.itb.fetch_acv 158 # ITB acv -system.cpu2.itb.fetch_accesses 539800 # ITB accesses +system.cpu2.dtb.read_hits 3529660 # DTB read hits +system.cpu2.dtb.read_misses 12347 # DTB read misses +system.cpu2.dtb.read_acv 141 # DTB read access violations +system.cpu2.dtb.read_accesses 225697 # DTB read accesses +system.cpu2.dtb.write_hits 2155841 # DTB write hits +system.cpu2.dtb.write_misses 2820 # DTB write misses +system.cpu2.dtb.write_acv 143 # DTB write access violations +system.cpu2.dtb.write_accesses 84900 # DTB write accesses +system.cpu2.dtb.data_hits 5685501 # DTB hits +system.cpu2.dtb.data_misses 15167 # DTB misses +system.cpu2.dtb.data_acv 284 # DTB access violations +system.cpu2.dtb.data_accesses 310597 # DTB accesses +system.cpu2.itb.fetch_hits 538073 # ITB hits +system.cpu2.itb.fetch_misses 5955 # ITB misses +system.cpu2.itb.fetch_acv 169 # ITB acv +system.cpu2.itb.fetch_accesses 544028 # ITB accesses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.read_acv 0 # DTB read access violations @@ -1058,305 +1036,305 @@ system.cpu2.itb.data_hits 0 # DT system.cpu2.itb.data_misses 0 # DTB misses system.cpu2.itb.data_acv 0 # DTB access violations system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.numCycles 30013580 # number of cpu cycles simulated +system.cpu2.numCycles 30702821 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9363383 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 37425902 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 9673449 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 5884791 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 18558568 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 408186 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 247 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 10133 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1974 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 231517 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 99918 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 308 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 2804138 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 92736 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 28469903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.314578 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.374234 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9319148 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 39738878 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 10412478 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 6578893 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 19243837 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 412304 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 656 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9648 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1927 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 233877 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 108804 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 445 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 2828172 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 93139 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 29124256 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.364460 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.368556 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 20072313 70.50% 70.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 312422 1.10% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 471724 1.66% 73.26% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3982470 13.99% 87.25% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 833365 2.93% 90.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 193345 0.68% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 238464 0.84% 91.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 434747 1.53% 93.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 1931053 6.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 20002999 68.68% 68.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 306830 1.05% 69.74% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 477568 1.64% 71.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4658363 15.99% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 855343 2.94% 90.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 200502 0.69% 90.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 234860 0.81% 91.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 433547 1.49% 93.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1954244 6.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 28469903 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.322302 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.246966 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 7673000 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 13050358 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6778876 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 530616 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 191226 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 175016 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 13225 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 34075356 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 43360 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 191226 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 7953535 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4758129 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 6310003 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 6998808 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 2012380 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 33260601 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 68695 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 404029 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 57097 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 943831 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 22264761 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 41311324 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 41251440 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 56013 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 20369021 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 1895740 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 527174 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 63098 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3903100 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 3489643 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 2214871 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 462169 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 329723 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 30742037 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 676819 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 30393110 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 17376 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 2421658 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 1144384 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 483915 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 28469903 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.067552 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.605150 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 29124256 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.339138 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.294307 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 7666487 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 12991565 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 7744961 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 527663 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 193001 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 177358 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 13514 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36364188 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 42851 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 193001 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 7942048 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 4601261 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 6305683 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 7969678 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2112012 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35538074 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 62867 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 396006 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 59218 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 1045972 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 23773076 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 44310063 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 44249815 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 56335 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 21846032 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 1927044 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 532665 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 63556 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3796199 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 3529311 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 2248768 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 470664 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 333419 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32987424 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 681806 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 32666998 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 16031 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 2457717 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1151235 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 487594 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 29124256 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.121642 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.623821 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 17422923 61.20% 61.20% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 2767864 9.72% 70.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 1373994 4.83% 75.75% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4735624 16.63% 92.38% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1013556 3.56% 95.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 570411 2.00% 97.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 382804 1.34% 99.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 154533 0.54% 99.83% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 48194 0.17% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 17381860 59.68% 59.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 2746661 9.43% 69.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 1371662 4.71% 73.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 5386342 18.49% 92.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1029310 3.53% 95.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 605779 2.08% 97.93% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 390861 1.34% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 167562 0.58% 99.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 44219 0.15% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 28469903 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 29124256 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 82144 21.47% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.47% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 176872 46.24% 67.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 123495 32.29% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 85214 22.02% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 22.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 179569 46.41% 68.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 122132 31.57% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 2440 0.01% 0.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 24311305 79.99% 80.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 21079 0.07% 80.07% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 80.07% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 20485 0.07% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 80.13% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 1220 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.14% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 3589842 11.81% 91.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 2146129 7.06% 99.01% # Type of FU issued -system.cpu2.iq.FU_type_0::IprAccess 300610 0.99% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 2450 0.01% 0.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 26477502 81.05% 81.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 21078 0.06% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 81.12% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 20355 0.06% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 1225 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 81.19% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 3659635 11.20% 92.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 2180799 6.68% 99.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 303954 0.93% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 30393110 # Type of FU issued -system.cpu2.iq.rate 1.012645 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 382511 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.012585 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 89403074 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 33727235 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 29817840 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 252936 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 119279 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 116815 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 30637549 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 135632 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205530 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 32666998 # Type of FU issued +system.cpu2.iq.rate 1.063974 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 386915 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.011844 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 94607462 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 36013478 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 32054290 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 253736 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 119374 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 117198 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 32915380 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 136083 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205891 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 436638 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1484 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 6154 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 181627 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 443704 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1465 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6049 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 180746 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 4994 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 170094 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5094 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 200289 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 191226 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3996466 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 295299 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32798710 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 54858 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 3489643 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 2214871 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 602209 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 15595 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 231865 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 6154 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 62873 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 134195 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197068 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 30195469 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 3482644 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 197641 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 193001 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3976817 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 219021 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 35063617 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 53776 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 3529311 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 2248768 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 606766 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 12977 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 164349 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6049 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 63932 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 135830 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 199762 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 32464526 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 3550760 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 202472 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 1379854 # number of nop insts executed -system.cpu2.iew.exec_refs 5611883 # number of memory reference insts executed -system.cpu2.iew.exec_branches 6643679 # Number of branches executed -system.cpu2.iew.exec_stores 2129239 # Number of stores executed -system.cpu2.iew.exec_rate 1.006060 # Inst execution rate -system.cpu2.iew.wb_sent 29976342 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 29934655 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 17254819 # num instructions producing a value -system.cpu2.iew.wb_consumers 20895222 # num instructions consuming a value +system.cpu2.iew.exec_nop 1394387 # number of nop insts executed +system.cpu2.iew.exec_refs 5714159 # number of memory reference insts executed +system.cpu2.iew.exec_branches 7350868 # Number of branches executed +system.cpu2.iew.exec_stores 2163399 # Number of stores executed +system.cpu2.iew.exec_rate 1.057379 # Inst execution rate +system.cpu2.iew.wb_sent 32215343 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 32171488 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 18756374 # num instructions producing a value +system.cpu2.iew.wb_consumers 22505351 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.997370 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.825778 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.047835 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.833418 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 2658447 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 192904 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 180111 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 28004103 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.074728 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.862098 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 2693673 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 194212 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 181849 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 28653786 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.128143 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.870801 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 18216020 65.05% 65.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 2235913 7.98% 73.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1176646 4.20% 77.23% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 4445185 15.87% 93.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 540129 1.93% 95.04% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 200547 0.72% 95.75% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 166033 0.59% 96.34% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 176455 0.63% 96.97% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 847175 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 18143596 63.32% 63.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 2243135 7.83% 71.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1187950 4.15% 75.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 5112990 17.84% 93.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 566123 1.98% 95.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 201198 0.70% 95.82% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 164794 0.58% 96.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 163684 0.57% 96.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 870316 3.04% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 28004103 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 30096794 # Number of instructions committed -system.cpu2.commit.committedOps 30096794 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 28653786 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 32325567 # Number of instructions committed +system.cpu2.commit.committedOps 32325567 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 5086249 # Number of memory references committed -system.cpu2.commit.loads 3053005 # Number of loads committed -system.cpu2.commit.membars 67981 # Number of memory barriers committed -system.cpu2.commit.branches 6474041 # Number of branches committed -system.cpu2.commit.fp_insts 115125 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 28589001 # Number of committed integer instructions. -system.cpu2.commit.function_calls 239427 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 1215466 4.04% 4.04% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 23382957 77.69% 81.73% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 20643 0.07% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 81.80% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 20037 0.07% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 1220 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 81.87% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 3120986 10.37% 92.24% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2034876 6.76% 99.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IprAccess 300609 1.00% 100.00% # Class of committed instruction +system.cpu2.commit.refs 5153629 # Number of memory references committed +system.cpu2.commit.loads 3085607 # Number of loads committed +system.cpu2.commit.membars 68228 # Number of memory barriers committed +system.cpu2.commit.branches 7176692 # Number of branches committed +system.cpu2.commit.fp_insts 115672 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 30802580 # Number of committed integer instructions. +system.cpu2.commit.function_calls 241655 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 1228058 3.80% 3.80% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 25528107 78.97% 82.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 20647 0.06% 82.83% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 82.83% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 20076 0.06% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 1225 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 82.90% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 3153835 9.76% 92.66% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 2069665 6.40% 99.06% # Class of committed instruction +system.cpu2.commit.op_class_0::IprAccess 303954 0.94% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 30096794 # Class of committed instruction -system.cpu2.commit.bw_lim_events 847175 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 32325567 # Class of committed instruction +system.cpu2.commit.bw_lim_events 870316 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 59838509 # The number of ROB reads -system.cpu2.rob.rob_writes 65974697 # The number of ROB writes -system.cpu2.timesIdled 175016 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1543677 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 1747747743 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 28883768 # Number of Instructions Simulated -system.cpu2.committedOps 28883768 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.039116 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.039116 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.962357 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.962357 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 39632695 # number of integer regfile reads -system.cpu2.int_regfile_writes 21162382 # number of integer regfile writes -system.cpu2.fp_regfile_reads 70702 # number of floating regfile reads -system.cpu2.fp_regfile_writes 70843 # number of floating regfile writes -system.cpu2.misc_regfile_reads 4340126 # number of misc regfile reads -system.cpu2.misc_regfile_writes 270474 # number of misc regfile writes +system.cpu2.rob.rob_reads 62726939 # The number of ROB reads +system.cpu2.rob.rob_writes 70507401 # The number of ROB writes +system.cpu2.timesIdled 178497 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1578565 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 1745106872 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 31099959 # Number of Instructions Simulated +system.cpu2.committedOps 31099959 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.987230 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.987230 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.012935 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.012935 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 42640475 # number of integer regfile reads +system.cpu2.int_regfile_writes 22658201 # number of integer regfile writes +system.cpu2.fp_regfile_reads 70901 # number of floating regfile reads +system.cpu2.fp_regfile_writes 71243 # number of floating regfile writes +system.cpu2.misc_regfile_reads 5010785 # number of misc regfile reads +system.cpu2.misc_regfile_writes 273099 # number of misc regfile writes system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1371,10 +1349,10 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7317 # Transaction distribution system.iobus.trans_dist::ReadResp 7317 # Transaction distribution -system.iobus.trans_dist::WriteReq 51363 # Transaction distribution -system.iobus.trans_dist::WriteResp 9811 # Transaction distribution +system.iobus.trans_dist::WriteReq 51362 # Transaction distribution +system.iobus.trans_dist::WriteResp 9810 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5194 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5192 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) @@ -1386,11 +1364,11 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 33910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 33908 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83450 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.tsunami.ide.dma::total 83450 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 117360 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20776 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 117358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20768 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) @@ -1402,37 +1380,41 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 45576 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 45568 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661608 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.tsunami.ide.dma::total 2661608 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2707184 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2201000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2707176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2232000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 105000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer22.occupancy 48000 # Layer occupancy (ticks) system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5529000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5364000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 2073000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 1863000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer26.occupancy 58000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 7000 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 166547212 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 100878274 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 9356000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 8843000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 17276500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 17495500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.262651 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.254165 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1693890143000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.262651 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.078916 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.078916 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1693892917000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.254165 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.078385 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.078385 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1446,14 +1428,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 9417462 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 9417462 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 5628764250 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 5628764250 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 9417462 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 9417462 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 9417462 # number of overall miss cycles -system.iocache.overall_miss_latency::total 9417462 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 9444962 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 9444962 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 3667270812 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 3667270812 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 9444962 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 9444962 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 9444962 # number of overall miss cycles +system.iocache.overall_miss_latency::total 9444962 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1470,19 +1452,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54436.196532 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 54436.196532 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 135463.136552 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 135463.136552 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 54436.196532 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 54436.196532 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 86158 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 54595.156069 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 54595.156069 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 88257.383808 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 88257.383808 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 54595.156069 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 54595.156069 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 54595.156069 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 31008 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9840 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4243 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.755894 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.308037 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1490,234 +1472,237 @@ system.iocache.writebacks::writebacks 41512 # nu system.iocache.writebacks::total 41512 # number of writebacks system.iocache.ReadReq_mshr_misses::tsunami.ide 70 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 70 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17024 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 17024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 17280 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 17280 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::tsunami.ide 70 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 70 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 70 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 70 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5776462 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 5776462 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 4743516250 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4743516250 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5776462 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5776462 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5776462 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5776462 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 5749962 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 5749962 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 2768710812 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2768710812 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5749962 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5749962 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5749962 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5749962 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 0.404624 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.409704 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.409704 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 0.415864 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.415864 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 0.404624 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 0.404624 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 0.404624 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82520.885714 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 278636.997768 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 278636.997768 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82520.885714 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82520.885714 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 82142.314286 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 160226.320139 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 160226.320139 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 82142.314286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82142.314286 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 82142.314286 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 337565 # number of replacements -system.l2c.tags.tagsinuse 65420.967844 # Cycle average of tags in use -system.l2c.tags.total_refs 2486640 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 402728 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.174490 # Average number of references to valid blocks. +system.l2c.tags.replacements 337569 # number of replacements +system.l2c.tags.tagsinuse 65419.566617 # Cycle average of tags in use +system.l2c.tags.total_refs 2487366 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 402731 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.176247 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 54725.451973 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2331.479005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2701.186077 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 572.371097 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 609.192683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2285.385373 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 2195.901635 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.835044 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.035576 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.041217 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.008734 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.009296 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.034872 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.033507 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.998245 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 1013 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5954 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2697 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55331 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26259538 # Number of tag accesses -system.l2c.tags.data_accesses 26259538 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 506712 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 484023 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 121893 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 79858 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 321963 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 253653 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1768102 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835667 # number of Writeback hits -system.l2c.Writeback_hits::total 835667 # number of Writeback hits +system.l2c.tags.occ_blocks::writebacks 54619.974232 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2262.532885 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2731.767010 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 536.522208 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 599.592732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2415.786794 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 2253.390757 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.833435 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.034524 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.041683 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.008187 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.009149 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.036862 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.034384 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.998223 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 974 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 6067 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2636 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55307 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26265257 # Number of tag accesses +system.l2c.tags.data_accesses 26265257 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 499689 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 475179 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 126551 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 83555 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 324793 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 258988 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1768755 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835707 # number of Writeback hits +system.l2c.Writeback_hits::total 835707 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 7 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 7 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 7 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 90939 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 25234 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 70756 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 186929 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 506712 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 574962 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 121893 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 105092 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 321963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 324409 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955031 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 506712 # number of overall hits -system.l2c.overall_hits::cpu0.data 574962 # number of overall hits -system.l2c.overall_hits::cpu1.inst 121893 # number of overall hits -system.l2c.overall_hits::cpu1.data 105092 # number of overall hits -system.l2c.overall_hits::cpu2.inst 321963 # number of overall hits -system.l2c.overall_hits::cpu2.data 324409 # number of overall hits -system.l2c.overall_hits::total 1955031 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 7503 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 238499 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2295 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 16798 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 4594 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 17926 # number of ReadReq misses -system.l2c.ReadReq_misses::total 287615 # number of ReadReq misses +system.l2c.UpgradeReq_hits::cpu2.data 8 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 12 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 9 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 9 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 89325 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 26026 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 71615 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 186966 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 499689 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 564504 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 126551 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 109581 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 324793 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 330603 # number of demand (read+write) hits +system.l2c.demand_hits::total 1955721 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 499689 # number of overall hits +system.l2c.overall_hits::cpu0.data 564504 # number of overall hits +system.l2c.overall_hits::cpu1.inst 126551 # number of overall hits +system.l2c.overall_hits::cpu1.data 109581 # number of overall hits +system.l2c.overall_hits::cpu2.inst 324793 # number of overall hits +system.l2c.overall_hits::cpu2.data 330603 # number of overall hits +system.l2c.overall_hits::total 1955721 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 7307 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 240797 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2297 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 15641 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 4814 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 16829 # number of ReadReq misses +system.l2c.ReadReq_misses::total 287685 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 29 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 37 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 11 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 19 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu2.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 75406 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 18360 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 22084 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 115850 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 7503 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 313905 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2295 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 35158 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 4594 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 40010 # number of demand (read+write) misses -system.l2c.demand_misses::total 403465 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 7503 # number of overall misses -system.l2c.overall_misses::cpu0.data 313905 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2295 # number of overall misses -system.l2c.overall_misses::cpu1.data 35158 # number of overall misses -system.l2c.overall_misses::cpu2.inst 4594 # number of overall misses -system.l2c.overall_misses::cpu2.data 40010 # number of overall misses -system.l2c.overall_misses::total 403465 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.inst 172333500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 1121869750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 347709750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 1196370250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2838283250 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 294497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 294497 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 1260800990 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1814777221 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 3075578211 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.inst 172333500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2382670740 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 347709750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3011147471 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 5913861461 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.inst 172333500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2382670740 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 347709750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3011147471 # number of overall miss cycles -system.l2c.overall_miss_latency::total 5913861461 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 514215 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 722522 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 124188 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 96656 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 326557 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 271579 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2055717 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835667 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835667 # number of Writeback accesses(hits+misses) +system.l2c.ReadExReq_misses::cpu0.data 73385 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 17971 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 24427 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 115783 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 7307 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 314182 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2297 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 33612 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 4814 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 41256 # number of demand (read+write) misses +system.l2c.demand_misses::total 403468 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 7307 # number of overall misses +system.l2c.overall_misses::cpu0.data 314182 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2297 # number of overall misses +system.l2c.overall_misses::cpu1.data 33612 # number of overall misses +system.l2c.overall_misses::cpu2.inst 4814 # number of overall misses +system.l2c.overall_misses::cpu2.data 41256 # number of overall misses +system.l2c.overall_misses::total 403468 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 187459250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 1164603000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 400569000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1256121750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 3008753000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 337497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 337497 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu2.data 62998 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 62998 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1363186490 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2153546721 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 3516733211 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 187459250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2527789490 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 400569000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 3409668471 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6525486211 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 187459250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2527789490 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 400569000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 3409668471 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6525486211 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 506996 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 715976 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 128848 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 99196 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 329607 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 275817 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2056440 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835707 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835707 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 11 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 36 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 48 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 9 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166345 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 43594 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 92840 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 302779 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 514215 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 888867 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 124188 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 140250 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 326557 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 364419 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2358496 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 514215 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 888867 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 124188 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 140250 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 326557 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 364419 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2358496 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.014591 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.330092 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.018480 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.173792 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.014068 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.066007 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.139910 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 31 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 11 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 11 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 162710 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 43997 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 96042 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 302749 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 506996 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 878686 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 128848 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 143193 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 329607 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 371859 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2359189 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 506996 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 878686 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 128848 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 143193 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 329607 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 371859 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2359189 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014412 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.336320 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.017827 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.157678 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.014605 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.061015 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.139895 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.727273 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.805556 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.770833 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.222222 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.453311 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.421159 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.237872 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.382622 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.014591 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.353152 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.018480 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.250681 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014068 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.109791 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.171069 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.014591 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.353152 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.018480 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.250681 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014068 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.109791 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.171069 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75090.849673 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 66785.912013 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 75687.799303 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 66739.386924 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 9868.342228 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 10155.068966 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 7959.378378 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68671.077887 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 82176.110351 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 26547.934493 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75090.849673 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 67770.372035 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 75687.799303 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 75259.871807 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 14657.681487 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75090.849673 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 67770.372035 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 75687.799303 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 75259.871807 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 14657.681487 # average overall miss latency +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.578947 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.612903 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.181818 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.181818 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.451017 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.408460 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.254337 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.382439 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014412 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.357559 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.017827 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.234732 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.014605 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.110945 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.171020 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014412 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.357559 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.017827 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.234732 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.014605 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.110945 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.171020 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81610.470178 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 74458.346653 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 83209.181554 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 74640.308396 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 10458.498010 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 30681.545455 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 17763 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 31499 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 31499 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75854.793278 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 88162.554591 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 30373.484976 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81610.470178 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 75204.971141 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 83209.181554 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 82646.608275 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 16173.491357 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81610.470178 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 75204.971141 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 83209.181554 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 82646.608275 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 16173.491357 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1726,97 +1711,105 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 75393 # number of writebacks -system.l2c.writebacks::total 75393 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu1.inst 2295 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 16798 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 4594 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 17926 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 41613 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 29 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 29 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 18360 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 22084 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 40444 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2295 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 35158 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 4594 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 40010 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 82057 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2295 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 35158 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 4594 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 40010 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 82057 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 143128000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 911545250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 289854250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 972645250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2317172750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 449026 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 449026 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1030142510 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1544955279 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 2575097789 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 143128000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1941687760 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 289854250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2517600529 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 4892270539 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 143128000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1941687760 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 289854250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2517600529 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 4892270539 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 233455500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 320261000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 553716500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 302243500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 395601500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 697845000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 535699000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 715862500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 1251561500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173792 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.066007 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.020243 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.805556 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.604167 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.421159 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.237872 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.133576 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.250681 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.109791 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034792 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.018480 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.250681 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014068 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.109791 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034792 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 54265.105965 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 54258.911637 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 55683.866820 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 15483.655172 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 15483.655172 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56107.979847 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69958.127106 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63670.699955 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62365.141612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 55227.480517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63094.090118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62924.282154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59620.392398 # average overall mshr miss latency +system.l2c.writebacks::writebacks 75392 # number of writebacks +system.l2c.writebacks::total 75392 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2297 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 15641 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 4814 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 16829 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 39581 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 11 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 17971 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 24427 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 42398 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2297 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 33612 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 4814 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 41256 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 81979 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2297 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 33612 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 4814 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 41256 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 81979 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 158665250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 968947500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 340372000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 1046522250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2514507000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 347508 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 347508 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 36002 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 36002 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1138484010 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1854617279 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 2993101289 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 158665250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 2107431510 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 340372000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 2901139529 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5507608289 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 158665250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 2107431510 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 340372000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 2901139529 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5507608289 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 207045500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 309444000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 516489500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 276013000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 418496000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 694509000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 483058500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 727940000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 1210998500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.157678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.061015 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.019247 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.578947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.354839 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.181818 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.408460 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.254337 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.140043 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034749 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.017827 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.234732 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014605 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.110945 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034749 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61949.204015 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62185.646800 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63528.132185 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 31591.636364 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 31591.636364 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 18001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63351.177453 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 75924.889630 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70595.341502 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69074.989116 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62698.783470 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1827,92 +1820,92 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 294932 # Transaction distribution -system.membus.trans_dist::ReadResp 294926 # Transaction distribution -system.membus.trans_dist::WriteReq 9811 # Transaction distribution -system.membus.trans_dist::WriteResp 9811 # Transaction distribution -system.membus.trans_dist::Writeback 116905 # Transaction distribution +system.membus.trans_dist::ReadReq 295002 # Transaction distribution +system.membus.trans_dist::ReadResp 294996 # Transaction distribution +system.membus.trans_dist::WriteReq 9810 # Transaction distribution +system.membus.trans_dist::WriteResp 9810 # Transaction distribution +system.membus.trans_dist::Writeback 116904 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 163 # Transaction distribution +system.membus.trans_dist::UpgradeReq 145 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 165 # Transaction distribution -system.membus.trans_dist::ReadExReq 115724 # Transaction distribution -system.membus.trans_dist::ReadExResp 115724 # Transaction distribution +system.membus.trans_dist::UpgradeResp 147 # Transaction distribution +system.membus.trans_dist::ReadExReq 115657 # Transaction distribution +system.membus.trans_dist::ReadExResp 115657 # Transaction distribution system.membus.trans_dist::BadAddressError 6 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33910 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 33908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 882256 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 12 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 916226 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 916176 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124907 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124907 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1041133 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30633216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 30678792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 1041083 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 45568 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 30632256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 30677824 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5323648 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36002440 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 140 # Total snoops (count) -system.membus.snoop_fanout::samples 562134 # Request fanout histogram +system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 157 # Total snoops (count) +system.membus.snoop_fanout::samples 562136 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 562134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 562136 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 562134 # Request fanout histogram -system.membus.reqLayer0.occupancy 11832500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 562136 # Request fanout histogram +system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 654960000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 770434435 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 438835201 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 17654500 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 17657500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2063004 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2062983 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 9811 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 9811 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 835667 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 17024 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 48 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 9 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 57 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 302779 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 302779 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2063715 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2063694 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 9810 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 9810 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 835707 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 17293 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 31 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 42 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 302749 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 302749 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 6 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930013 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3656818 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5586831 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61758720 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142717704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 204476424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1930984 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3657230 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5588214 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 61790208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 41934 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3236018 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012894 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112817 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3236737 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012895 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112822 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 3194293 98.71% 98.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 41725 1.29% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 3194999 98.71% 98.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 41738 1.29% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3236018 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2201638999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3236737 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 247500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2030846564 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2289452792 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 689338845 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 790311532 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index f1c3d0229..57022429e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,158 +1,158 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.845843 # Number of seconds simulated -sim_ticks 2845842660500 # Number of ticks simulated -final_tick 2845842660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846001 # Number of seconds simulated +sim_ticks 2846001096000 # Number of ticks simulated +final_tick 2846001096000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92448 # Simulator instruction rate (inst/s) -host_op_rate 111941 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2101025547 # Simulator tick rate (ticks/s) -host_mem_usage 635156 # Number of bytes of host memory used -host_seconds 1354.50 # Real time elapsed on the host -sim_insts 125221621 # Number of instructions simulated -sim_ops 151624712 # Number of ops (including micro ops) simulated +host_inst_rate 163513 # Simulator instruction rate (inst/s) +host_op_rate 197998 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3697981305 # Simulator tick rate (ticks/s) +host_mem_usage 648920 # Number of bytes of host memory used +host_seconds 769.61 # Real time elapsed on the host +sim_insts 125841424 # Number of instructions simulated +sim_ops 152380857 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 10368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1722304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1285116 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8732480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 153024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 621216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1676864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1253436 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8602112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 217536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 601248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 396864 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1722304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 153024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1875328 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8977344 # Number of bytes written to this memory +system.physmem.bytes_read::total 12760092 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1676864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 217536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1894400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8825856 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8995088 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 162 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8843600 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26911 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 136445 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2391 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9730 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26201 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20110 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134408 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6201 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 202521 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 140271 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199925 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137904 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144707 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3643 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142340 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3396 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 605200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 451577 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3068504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 53771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 218289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 140533 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 589200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 440420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3022526 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 76436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 211261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 139446 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 605200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 53771 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 658971 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3154547 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4483516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 589200 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 76436 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 665636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3101143 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3154547 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3643 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3107378 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3101143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3396 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 605200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 457798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3068504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 53771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 218303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 140533 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 589200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 446641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3022526 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 76436 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 211275 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 139446 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7702929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 202521 # Number of read requests accepted -system.physmem.writeReqs 180931 # Number of write requests accepted -system.physmem.readBursts 202521 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 180931 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12951936 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9408 # Total number of bytes read from write queue -system.physmem.bytesWritten 11206784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12926236 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11313424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 147 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5797 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13571 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12806 # Per bank write bursts -system.physmem.perBankRdBursts::1 12696 # Per bank write bursts -system.physmem.perBankRdBursts::2 13455 # Per bank write bursts -system.physmem.perBankRdBursts::3 13223 # Per bank write bursts -system.physmem.perBankRdBursts::4 15141 # Per bank write bursts -system.physmem.perBankRdBursts::5 12251 # Per bank write bursts -system.physmem.perBankRdBursts::6 12720 # Per bank write bursts -system.physmem.perBankRdBursts::7 12666 # Per bank write bursts -system.physmem.perBankRdBursts::8 12396 # Per bank write bursts -system.physmem.perBankRdBursts::9 12410 # Per bank write bursts -system.physmem.perBankRdBursts::10 12030 # Per bank write bursts -system.physmem.perBankRdBursts::11 11077 # Per bank write bursts -system.physmem.perBankRdBursts::12 12224 # Per bank write bursts -system.physmem.perBankRdBursts::13 12978 # Per bank write bursts -system.physmem.perBankRdBursts::14 12239 # Per bank write bursts -system.physmem.perBankRdBursts::15 12062 # Per bank write bursts -system.physmem.perBankWrBursts::0 11243 # Per bank write bursts -system.physmem.perBankWrBursts::1 11520 # Per bank write bursts -system.physmem.perBankWrBursts::2 11868 # Per bank write bursts -system.physmem.perBankWrBursts::3 11342 # Per bank write bursts -system.physmem.perBankWrBursts::4 10753 # Per bank write bursts -system.physmem.perBankWrBursts::5 10659 # Per bank write bursts -system.physmem.perBankWrBursts::6 11197 # Per bank write bursts -system.physmem.perBankWrBursts::7 10854 # Per bank write bursts -system.physmem.perBankWrBursts::8 10720 # Per bank write bursts -system.physmem.perBankWrBursts::9 10780 # Per bank write bursts -system.physmem.perBankWrBursts::10 10917 # Per bank write bursts -system.physmem.perBankWrBursts::11 10553 # Per bank write bursts -system.physmem.perBankWrBursts::12 10892 # Per bank write bursts -system.physmem.perBankWrBursts::13 10850 # Per bank write bursts -system.physmem.perBankWrBursts::14 10512 # Per bank write bursts -system.physmem.perBankWrBursts::15 10446 # Per bank write bursts +system.physmem.bw_total::total 7590894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199925 # Number of read requests accepted +system.physmem.writeReqs 178564 # Number of write requests accepted +system.physmem.readBursts 199925 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 178564 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12787648 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7552 # Total number of bytes read from write queue +system.physmem.bytesWritten 9914112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12760092 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11161936 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 118 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23627 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14395 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11804 # Per bank write bursts +system.physmem.perBankRdBursts::1 12403 # Per bank write bursts +system.physmem.perBankRdBursts::2 13173 # Per bank write bursts +system.physmem.perBankRdBursts::3 12915 # Per bank write bursts +system.physmem.perBankRdBursts::4 15440 # Per bank write bursts +system.physmem.perBankRdBursts::5 12419 # Per bank write bursts +system.physmem.perBankRdBursts::6 12541 # Per bank write bursts +system.physmem.perBankRdBursts::7 12439 # Per bank write bursts +system.physmem.perBankRdBursts::8 12804 # Per bank write bursts +system.physmem.perBankRdBursts::9 13107 # Per bank write bursts +system.physmem.perBankRdBursts::10 11847 # Per bank write bursts +system.physmem.perBankRdBursts::11 11130 # Per bank write bursts +system.physmem.perBankRdBursts::12 12155 # Per bank write bursts +system.physmem.perBankRdBursts::13 12699 # Per bank write bursts +system.physmem.perBankRdBursts::14 11526 # Per bank write bursts +system.physmem.perBankRdBursts::15 11405 # Per bank write bursts +system.physmem.perBankWrBursts::0 9464 # Per bank write bursts +system.physmem.perBankWrBursts::1 9978 # Per bank write bursts +system.physmem.perBankWrBursts::2 10476 # Per bank write bursts +system.physmem.perBankWrBursts::3 10111 # Per bank write bursts +system.physmem.perBankWrBursts::4 9384 # Per bank write bursts +system.physmem.perBankWrBursts::5 9602 # Per bank write bursts +system.physmem.perBankWrBursts::6 9874 # Per bank write bursts +system.physmem.perBankWrBursts::7 9552 # Per bank write bursts +system.physmem.perBankWrBursts::8 9896 # Per bank write bursts +system.physmem.perBankWrBursts::9 10357 # Per bank write bursts +system.physmem.perBankWrBursts::10 9473 # Per bank write bursts +system.physmem.perBankWrBursts::11 9143 # Per bank write bursts +system.physmem.perBankWrBursts::12 9886 # Per bank write bursts +system.physmem.perBankWrBursts::13 9717 # Per bank write bursts +system.physmem.perBankWrBursts::14 9232 # Per bank write bursts +system.physmem.perBankWrBursts::15 8763 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2845842079500 # Total gap between requests +system.physmem.numWrRetry 62 # Number of times write queue was full causing retry +system.physmem.totGap 2846000520000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 201934 # Read request sizes (log2) +system.physmem.readPktSize::6 199338 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 176495 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 98520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 50579 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12267 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9843 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6337 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5553 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4965 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 735 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 174128 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 99213 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 10017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6072 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 168 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -184,158 +184,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 7768 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8767 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10076 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12804 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 12238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 693 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 94139 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 256.627498 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 142.457232 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 317.924062 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 48795 51.83% 51.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18347 19.49% 71.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6488 6.89% 78.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3770 4.00% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2738 2.91% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1619 1.72% 86.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 964 1.02% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1076 1.14% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10342 10.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 94139 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7479 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.058430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 520.327968 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7478 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7479 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7479 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.413023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.870843 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.578889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 6390 85.44% 85.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 248 3.32% 88.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 198 2.65% 91.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 77 1.03% 92.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 144 1.93% 94.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 30 0.40% 94.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 35 0.47% 95.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 33 0.44% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 72 0.96% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 21 0.28% 96.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 96 1.28% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 18 0.24% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 22 0.29% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 12 0.16% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 35 0.47% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 12 0.16% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.05% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 8 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.04% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7479 # Writes before turning the bus around for reads -system.physmem.totQLat 5783977250 # Total ticks spent queuing -system.physmem.totMemAccLat 9578489750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1011870000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28580.63 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7330 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8378 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8774 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1846 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1818 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 771 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 117 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90945 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.620056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.134877 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.994619 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47499 52.23% 52.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17879 19.66% 71.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6335 6.97% 78.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3699 4.07% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2819 3.10% 86.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1518 1.67% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 969 1.07% 88.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1044 1.15% 89.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9183 10.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90945 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6522 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.635388 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.912572 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6520 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6522 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6522 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.751610 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.656400 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.548658 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6178 94.73% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 86 1.32% 96.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 19 0.29% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.18% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 33 0.51% 97.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 33 0.51% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 29 0.44% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.20% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 13 0.20% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 4 0.06% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 22 0.34% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.28% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 8 0.12% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.09% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.08% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.08% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 7 0.11% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 9 0.14% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-911 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6522 # Writes before turning the bus around for reads +system.physmem.totQLat 5658505376 # Total ticks spent queuing +system.physmem.totMemAccLat 9404886626 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 999035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28319.86 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47330.63 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.94 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.54 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.98 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 47069.86 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 168404 # Number of row buffer hits during reads -system.physmem.writeRowHits 114936 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 65.63 # Row buffer hit rate for writes -system.physmem.avgGap 7421638.38 # Average gap between requests -system.physmem.pageHitRate 75.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 372813840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 203420250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 818672400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 579545280 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83421293220 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634324841000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905596723190 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.608836 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2718714861000 # Time in different power states -system.physmem_0.memoryStateTime::REF 95028700000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing +system.physmem.readRowHits 166469 # Number of row buffer hits during reads +system.physmem.writeRowHits 97300 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.31 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.80 # Row buffer hit rate for writes +system.physmem.avgGap 7519374.46 # Average gap between requests +system.physmem.pageHitRate 74.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 351842400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 191977500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 804437400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 508297680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83070715860 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634730471750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905544559550 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.552036 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719396100671 # Time in different power states +system.physmem_0.memoryStateTime::REF 95034160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32092142750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31570722329 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 338877000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 184903125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 759837000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 555141600 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185876137200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82372109895 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635245177250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905332183070 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.515879 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720254769500 # Time in different power states -system.physmem_1.memoryStateTime::REF 95028700000 # Time in different power states +system.physmem_1.actEnergy 335701800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 183170625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 754049400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 495506160 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185886816960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82302536835 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635404313000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905362094780 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.487923 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720522847414 # Time in different power states +system.physmem_1.memoryStateTime::REF 95034160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30559102000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30442207586 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory @@ -361,15 +365,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 35059389 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17250705 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1579435 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20094508 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14609065 # Number of BTB hits +system.cpu0.branchPred.lookups 20635824 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13602989 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1045571 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13187813 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9323038 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.701780 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10810171 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 733013 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 70.694345 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3366354 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 208367 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -400,58 +404,59 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 67889 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67889 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44852 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23037 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 67889 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 67889 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 67889 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6673 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 8598.195564 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7320.525431 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6106.619536 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6491 97.27% 97.27% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 168 2.52% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 6 0.09% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6673 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 287368000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 287368000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 287368000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5164 77.39% 77.39% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1509 22.61% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6673 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67889 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 68383 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 68383 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45560 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22823 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 68383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 68383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 68383 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6747 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9430.747147 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8234.841596 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6251.099816 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6572 97.41% 97.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 158 2.34% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6747 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5180 76.77% 76.77% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1567 23.23% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6747 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 68383 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67889 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6673 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 68383 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6747 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6673 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 74562 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6747 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 75130 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23969568 # DTB read hits -system.cpu0.dtb.read_misses 61820 # DTB read misses -system.cpu0.dtb.write_hits 17946825 # DTB write hits -system.cpu0.dtb.write_misses 6069 # DTB write misses +system.cpu0.dtb.read_hits 17310932 # DTB read hits +system.cpu0.dtb.read_misses 62315 # DTB read misses +system.cpu0.dtb.write_hits 14537397 # DTB write hits +system.cpu0.dtb.write_misses 6068 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1251 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2004 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1366 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1946 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24031388 # DTB read accesses -system.cpu0.dtb.write_accesses 17952894 # DTB write accesses +system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17373247 # DTB read accesses +system.cpu0.dtb.write_accesses 14543465 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41916393 # DTB hits -system.cpu0.dtb.misses 67889 # DTB misses -system.cpu0.dtb.accesses 41984282 # DTB accesses +system.cpu0.dtb.hits 31848329 # DTB hits +system.cpu0.dtb.misses 68383 # DTB misses +system.cpu0.dtb.accesses 31916712 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -481,38 +486,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3825 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3825 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3518 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3825 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3825 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3825 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 8874.535345 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 7628.532351 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4888.994435 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1491 61.64% 61.64% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 888 36.71% 98.35% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.51% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 286941000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 286941000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 286941000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3838 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3838 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3532 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3838 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3838 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3838 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9817.861169 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8667.312532 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5173.169908 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 854 35.39% 35.39% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1509 62.54% 97.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.12% 98.05% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 46 1.91% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2114 87.61% 87.61% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 299 12.39% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2413 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3825 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3825 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3838 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3838 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 70462798 # ITB inst hits -system.cpu0.itb.inst_misses 3825 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2413 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2413 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6251 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38726658 # ITB inst hits +system.cpu0.itb.inst_misses 3838 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -521,123 +526,123 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7291 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7377 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 70466623 # ITB inst accesses -system.cpu0.itb.hits 70462798 # DTB hits -system.cpu0.itb.misses 3825 # DTB misses -system.cpu0.itb.accesses 70466623 # DTB accesses -system.cpu0.numCycles 234985394 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 38730496 # ITB inst accesses +system.cpu0.itb.hits 38726658 # DTB hits +system.cpu0.itb.misses 3838 # DTB misses +system.cpu0.itb.accesses 38730496 # DTB accesses +system.cpu0.numCycles 164623207 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 109265327 # Number of instructions committed -system.cpu0.committedOps 132114239 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8364757 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1821 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5456715361 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.150594 # CPI: cycles per instruction -system.cpu0.ipc 0.464988 # IPC: instructions per cycle +system.cpu0.committedInsts 79533802 # Number of instructions committed +system.cpu0.committedOps 95718607 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5045973 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1856 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5527394503 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.069852 # CPI: cycles per instruction +system.cpu0.ipc 0.483126 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1824 # number of quiesce instructions executed -system.cpu0.tickCycles 195318282 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 39667112 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 718541 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.305697 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 40476936 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 719053 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.292006 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 306903000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.305697 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965441 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965441 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed +system.cpu0.tickCycles 128554371 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 36068836 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 714653 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.517650 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30439123 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 715165 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.562378 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.517650 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.977574 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.977574 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 344 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 83802985 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 83802985 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 22808347 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22808347 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16863099 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16863099 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 381264 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 381264 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362825 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362825 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 39671446 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 39671446 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 39671446 # number of overall hits -system.cpu0.dcache.overall_hits::total 39671446 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 540080 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 540080 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 532227 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 532227 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6489 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6489 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19898 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 19898 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1072307 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1072307 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1072307 # number of overall misses -system.cpu0.dcache.overall_misses::total 1072307 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6648434719 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6648434719 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8319872197 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8319872197 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104923750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 104923750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 438142885 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 438142885 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 309000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 309000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 14968306916 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14968306916 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 14968306916 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14968306916 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23348427 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23348427 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17395326 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17395326 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387753 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387753 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382723 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382723 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 40743753 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 40743753 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 40743753 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40743753 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023131 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.023131 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030596 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030596 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016735 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016735 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026318 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026318 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026318 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026318 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12310.092429 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15632.187388 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16169.479119 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22019.443411 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63710880 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63710880 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 16167111 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 16167111 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13468154 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13468154 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 380067 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 380067 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361342 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361342 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29635265 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29635265 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29635265 # number of overall hits +system.cpu0.dcache.overall_hits::total 29635265 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 537159 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 537159 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 529716 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 529716 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6447 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6447 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20264 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20264 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1066875 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1066875 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1066875 # number of overall misses +system.cpu0.dcache.overall_misses::total 1066875 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6690812322 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6690812322 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8678584493 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8678584493 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104630740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 104630740 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454305285 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 454305285 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 153000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 153000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 15369396815 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15369396815 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 15369396815 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15369396815 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16704270 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16704270 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13997870 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13997870 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386514 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386514 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381606 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381606 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30702140 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30702140 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30702140 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30702140 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032157 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.032157 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.037843 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.037843 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016680 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016680 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053102 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053102 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034749 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034749 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.034749 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.034749 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12455.925195 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12455.925195 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16383.466788 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 16383.466788 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16229.368699 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16229.368699 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22419.329106 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22419.329106 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14405.995843 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14405.995843 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14405.995843 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,74 +651,74 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 523102 # number of writebacks -system.cpu0.dcache.writebacks::total 523102 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42658 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 42658 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 230433 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 230433 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 273091 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 273091 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 273091 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 273091 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 497422 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 497422 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 301794 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 301794 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6489 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6489 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19898 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 19898 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 799216 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 799216 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 799216 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 799216 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149793898 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149793898 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4423706193 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4423706193 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91926250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91926250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 397751115 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397751115 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 291000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 291000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9573500091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9573500091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9573500091 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9573500091 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6190990749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6190990749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4804555500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4804555500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10995546249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995546249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021304 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021304 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016735 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016735 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051991 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051991 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.019616 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019616 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10352.967697 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10352.967697 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14658.032277 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14658.032277 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14166.474033 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14166.474033 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19989.502211 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19989.502211 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 516062 # number of writebacks +system.cpu0.dcache.writebacks::total 516062 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42087 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 42087 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 229086 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 229086 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 271173 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 271173 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 271173 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 271173 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 495072 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 495072 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 300630 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 300630 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6447 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20264 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20264 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 795702 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 795702 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 795702 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 795702 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5420342985 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5420342985 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4742244244 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4742244244 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94933760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94933760 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 423201715 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 423201715 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 147000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 147000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10162587229 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10162587229 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10162587229 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10162587229 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276747000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276747000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261903001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261903001 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538650001 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538650001 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029637 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029637 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021477 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021477 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016680 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053102 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053102 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.025917 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.025917 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.025917 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10948.595326 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10948.595326 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15774.354669 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15774.354669 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14725.261362 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14725.261362 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20884.411518 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20884.411518 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12771.850805 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12771.850805 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -721,58 +726,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1982441 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.792915 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 68472197 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1982953 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.530419 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6378447750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.792915 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999596 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999596 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1970130 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.783768 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36748265 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1970642 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.647865 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6452193250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.783768 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999578 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999578 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 108 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 91 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 142893294 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 142893294 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 68472197 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 68472197 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 68472197 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 68472197 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 68472197 # number of overall hits -system.cpu0.icache.overall_hits::total 68472197 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1982967 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1982967 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1982967 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1982967 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1982967 # number of overall misses -system.cpu0.icache.overall_misses::total 1982967 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18641895952 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18641895952 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18641895952 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18641895952 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18641895952 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18641895952 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 70455164 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 70455164 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 70455164 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 70455164 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 70455164 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 70455164 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028145 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028145 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028145 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028145 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028145 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028145 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9401.011692 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9401.011692 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9401.011692 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9401.011692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9401.011692 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9401.011692 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79408512 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79408512 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36748265 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36748265 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36748265 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36748265 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36748265 # number of overall hits +system.cpu0.icache.overall_hits::total 36748265 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1970661 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1970661 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1970661 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1970661 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1970661 # number of overall misses +system.cpu0.icache.overall_misses::total 1970661 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18596838762 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18596838762 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18596838762 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18596838762 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18596838762 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18596838762 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38718926 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38718926 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38718926 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38718926 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38718926 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38718926 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050897 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050897 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050897 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050897 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050897 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050897 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9436.853300 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9436.853300 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9436.853300 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9436.853300 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9436.853300 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -781,224 +786,225 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1982967 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1982967 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1982967 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1982967 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1982967 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1982967 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 15657207046 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 15657207046 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 15657207046 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 15657207046 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 15657207046 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 15657207046 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 278031000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 278031000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 278031000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 278031000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028145 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028145 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028145 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028145 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 7895.848517 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 7895.848517 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 7895.848517 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1970661 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1970661 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1970661 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1970661 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1970661 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1970661 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16616813240 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16616813240 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16616813240 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16616813240 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16616813240 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16616813240 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 312357250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 312357250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 312357250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 312357250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050897 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050897 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050897 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050897 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8432.101330 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8432.101330 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8432.101330 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 2292717 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 2293221 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 436 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 2299938 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 2300657 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 626 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 284211 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 303376 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16141.726832 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2969035 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 319611 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 9.289527 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2825848630000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 6310.295058 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.412646 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.063392 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5929.101601 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1862.423160 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1981.430976 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.385150 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003565 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.361884 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.113673 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.120937 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.985213 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1941 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14280 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 509 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 923 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 497 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 288151 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 300423 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16135.818285 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2948802 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 316647 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 9.312585 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2825975663500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6474.830142 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 56.840728 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.090495 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5820.472159 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1850.674004 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1932.910757 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.395192 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003469 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.355253 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.112956 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.117976 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984852 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1935 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14276 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 526 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 949 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 452 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4022 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7455 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2494 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.118469 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.871582 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 55347065 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 55347065 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80493 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4332 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1910084 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 434260 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 2429169 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 523100 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 523100 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4781 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 4781 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1890 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1890 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226532 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 226532 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80493 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4332 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1910084 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 660792 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2655701 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80493 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4332 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1910084 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 660792 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2655701 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 854 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 113 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 72883 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 69644 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 143494 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26406 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26406 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18006 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18006 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44082 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 44082 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 854 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 113 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 72883 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 113726 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 187576 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 854 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 113 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 72883 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 113726 # number of overall misses -system.cpu0.l2cache.overall_misses::total 187576 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 30085500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2495499 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3197828979 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2112725700 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 5343135678 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 462181513 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 462181513 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 354964789 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 354964789 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 282000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 282000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2099231484 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2099231484 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 30085500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2495499 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3197828979 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4211957184 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7442367162 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 30085500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2495499 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3197828979 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4211957184 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7442367162 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81347 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4445 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1982967 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 503904 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 2572663 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 523100 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 523100 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 31187 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 31187 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19896 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19896 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270614 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 270614 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81347 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4445 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1982967 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 774518 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2843277 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81347 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4445 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1982967 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 774518 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2843277 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025422 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036755 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.138209 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.055776 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.846699 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.846699 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905006 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905006 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 261 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3958 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7592 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2420 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.118103 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.871338 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 54983870 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 54983870 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80556 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4286 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1899770 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 431338 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 2415950 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 516061 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 516061 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4718 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 4718 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1821 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1821 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 223877 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 223877 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80556 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4286 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1899770 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 655215 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2639827 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80556 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4286 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1899770 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 655215 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2639827 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 849 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 121 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 70891 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 70175 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 142036 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27075 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27075 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18442 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18442 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44966 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 44966 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 849 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 121 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 70891 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 115141 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 187002 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 849 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 121 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 70891 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 115141 # number of overall misses +system.cpu0.l2cache.overall_misses::total 187002 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 30876250 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2731998 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3274401699 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2190541082 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 5498551029 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 500181256 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 500181256 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 372946806 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 372946806 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 142499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 142499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2230359389 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2230359389 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 30876250 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2731998 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3274401699 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4420900471 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7728910418 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 30876250 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2731998 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3274401699 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4420900471 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7728910418 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81405 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4407 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1970661 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 501513 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 2557986 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 516061 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 516061 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 31793 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 31793 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20263 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20263 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 268843 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 268843 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81405 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4407 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1970661 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 770356 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2826829 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81405 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4407 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1970661 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 770356 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2826829 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010429 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.027456 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.035973 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.139927 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.055526 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.851603 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.851603 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.910132 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.910132 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.162896 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.162896 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025422 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036755 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.146835 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.065972 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025422 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036755 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.146835 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.065972 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22084.061947 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 43876.198551 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30336.076331 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37235.951873 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17502.897561 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17502.897561 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19713.694824 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19713.694824 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 141000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 141000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47621.058119 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47621.058119 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 43876.198551 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37036.009215 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 39676.542639 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 43876.198551 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37036.009215 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 39676.542639 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.167257 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.167257 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010429 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.027456 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.035973 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.149465 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.066153 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010429 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.027456 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.035973 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.149465 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.066153 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36367.785630 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22578.495868 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46189.244037 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 31215.405515 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 38712.375940 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18473.915272 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18473.915272 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20222.687669 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20222.687669 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 142499 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 142499 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 49601.018303 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 49601.018303 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36367.785630 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22578.495868 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46189.244037 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38395.536525 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 41330.629715 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36367.785630 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22578.495868 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46189.244037 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38395.536525 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 41330.629715 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1007,134 +1013,131 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 201133 # number of writebacks -system.cpu0.l2cache.writebacks::total 201133 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 65 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 446 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3265 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 3265 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 65 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3711 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 3777 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 65 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3711 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 3777 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 854 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 112 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 72818 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 69198 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 142982 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 280772 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26406 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26406 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18006 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18006 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40817 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 40817 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 854 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 112 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 72818 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 110015 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 183799 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 854 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 112 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 72818 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 110015 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 464571 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1685499 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2677133771 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1602381204 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4305290474 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15488924735 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 449600763 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 449600763 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 240569359 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 240569359 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 219000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 219000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1467254248 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1467254248 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1685499 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2677133771 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3069635452 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 5772544722 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1685499 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2677133771 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3069635452 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 21261469457 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 242870500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5934206491 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6177076991 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4588309497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4588309497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 242870500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10522515988 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10765386488 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.137324 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055577 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 200203 # number of writebacks +system.cpu0.l2cache.writebacks::total 200203 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 78 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 437 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 515 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 2951 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 2951 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 78 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3388 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3466 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 78 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3388 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3466 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 849 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 121 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 70813 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 69738 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 141521 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 280214 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 280214 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27075 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27075 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18442 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18442 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42015 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 42015 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 849 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 121 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 70813 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 111753 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 183536 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 849 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 121 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 70813 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 111753 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 280214 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 463750 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25343250 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1944500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2803376051 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1710921798 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4541585599 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14990911200 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14990911200 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 547256396 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 547256396 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 271139812 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 271139812 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 116499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 116499 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1628836464 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1628836464 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25343250 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1944500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2803376051 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3339758262 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6170422063 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25343250 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1944500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2803376051 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3339758262 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14990911200 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21161333263 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 283700250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4113316250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4397016500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3118122000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3118122000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 283700250 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7231438250 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7515138500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010429 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027456 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.139055 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055325 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.846699 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.846699 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905006 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905006 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.851603 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.851603 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.910132 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.910132 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150831 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150831 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064643 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.156281 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.156281 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010429 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027456 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.145067 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064926 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010429 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027456 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.035934 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.145067 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163393 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23156.467008 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17026.462281 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13360.510885 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 35947.135948 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.164053 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24533.565603 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 32091.248642 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53498.080753 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 53498.080753 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20212.609271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20212.609271 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14702.299751 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14702.299751 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 116499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 116499 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38767.974866 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38767.974866 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33619.682585 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29850.706714 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16070.247934 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39588.437872 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29885.177687 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 53498.080753 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45630.907306 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1144,67 +1147,65 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2726808 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2669763 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 523100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 388140 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 64720 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42432 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 88655 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 299964 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 286773 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3972081 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2399294 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11788 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172273 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6555436 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127106560 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 87442327 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17780 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325388 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 214892055 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 732010 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4046250 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.152317 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.359328 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2704309 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2644372 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 516061 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 357573 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 65952 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43054 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 89535 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298181 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284517 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3948091 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2342949 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11777 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 172611 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6475428 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126338880 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86633336 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17628 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 325620 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 213315464 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 705686 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3997625 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.147566 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.354669 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 3429939 84.77% 84.77% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 616311 15.23% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 3407711 85.24% 85.24% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 589914 14.76% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4046250 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2284841999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 3997625 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2250942493 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 117254000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 117029497 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2984852953 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2966538511 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1241569539 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1219549045 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7347491 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7373994 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 90940738 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 91216246 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4088735 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2366310 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 253216 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2663045 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1651600 # Number of BTB hits +system.cpu1.branchPred.lookups 18670420 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6078179 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 807720 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9612678 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 6998038 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 62.019230 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 809555 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 58673 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.800088 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8300224 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 592338 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1234,58 +1235,59 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 25571 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 25571 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18521 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7050 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 25571 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 25571 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 25571 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2708 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 8701.256278 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7631.681902 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5745.938863 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 2093 77.29% 77.29% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 481 17.76% 95.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 26198 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26198 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19047 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7151 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26198 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26198 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26198 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2710 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9322.699631 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8294.308784 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5681.860876 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1066 39.34% 39.34% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1510 55.72% 95.06% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::16384-24575 65 2.40% 97.45% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.52% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 9 0.33% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 4 0.15% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2708 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1108722264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1108722264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1108722264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1997 73.74% 73.74% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 711 26.26% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2708 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 25571 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.14% 99.59% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 6 0.22% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 3 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2710 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1205143764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1205143764 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1205143764 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2001 73.84% 73.84% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 709 26.16% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2710 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26198 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 25571 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2708 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26198 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2710 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2708 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28279 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2710 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 28908 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4075725 # DTB read hits -system.cpu1.dtb.read_misses 23546 # DTB read misses -system.cpu1.dtb.write_hits 3346999 # DTB write hits -system.cpu1.dtb.write_misses 2025 # DTB write misses +system.cpu1.dtb.read_hits 10899944 # DTB read hits +system.cpu1.dtb.read_misses 24664 # DTB read misses +system.cpu1.dtb.write_hits 6857896 # DTB write hits +system.cpu1.dtb.write_misses 1534 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2069 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 121 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 325 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2060 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 145 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 340 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 279 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4099271 # DTB read accesses -system.cpu1.dtb.write_accesses 3349024 # DTB write accesses +system.cpu1.dtb.read_accesses 10924608 # DTB read accesses +system.cpu1.dtb.write_accesses 6859430 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7422724 # DTB hits -system.cpu1.dtb.misses 25571 # DTB misses -system.cpu1.dtb.accesses 7448295 # DTB accesses +system.cpu1.dtb.hits 17757840 # DTB hits +system.cpu1.dtb.misses 26198 # DTB misses +system.cpu1.dtb.accesses 17784038 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1315,42 +1317,41 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2243 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2243 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2062 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2243 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2243 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2243 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 8831.106061 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 7825.020839 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4777.823788 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 160 14.26% 14.26% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 676 60.25% 74.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 3 0.27% 74.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 248 22.10% 96.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 98.13% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.69% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1108154264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1108154264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1108154264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 954 85.03% 85.03% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 14.97% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2253 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2253 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 177 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2076 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2253 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2253 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2253 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9627.345845 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8644.762201 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4978.900312 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.44% 16.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 161 14.39% 30.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 501 44.77% 75.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 236 21.09% 96.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 96.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 13 1.16% 97.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.88% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1204569264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1204569264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1204569264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 955 85.34% 85.34% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 164 14.66% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2243 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2243 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2253 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2253 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3365 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 7772051 # ITB inst hits -system.cpu1.itb.inst_misses 2243 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3372 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39818327 # ITB inst hits +system.cpu1.itb.inst_misses 2253 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1359,122 +1360,122 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1160 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1845 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1840 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7774294 # ITB inst accesses -system.cpu1.itb.hits 7772051 # DTB hits -system.cpu1.itb.misses 2243 # DTB misses -system.cpu1.itb.accesses 7774294 # DTB accesses -system.cpu1.numCycles 42246986 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 39820580 # ITB inst accesses +system.cpu1.itb.hits 39818327 # DTB hits +system.cpu1.itb.misses 2253 # DTB misses +system.cpu1.itb.accesses 39820580 # DTB accesses +system.cpu1.numCycles 115094455 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15956294 # Number of instructions committed -system.cpu1.committedOps 19510473 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1491389 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2792 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5648821854 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.647669 # CPI: cycles per instruction -system.cpu1.ipc 0.377691 # IPC: instructions per cycle +system.cpu1.committedInsts 46307622 # Number of instructions committed +system.cpu1.committedOps 56662250 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 4905736 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2805 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5576292649 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.485432 # CPI: cycles per instruction +system.cpu1.ipc 0.402345 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2795 # number of quiesce instructions executed -system.cpu1.tickCycles 30354295 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 11892691 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 187758 # number of replacements -system.cpu1.dcache.tags.tagsinuse 478.493571 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 7034054 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 188124 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.390519 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 108317904000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.493571 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934558 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.934558 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14914460 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14914460 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3762812 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3762812 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3070723 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3070723 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 89288 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 89288 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69262 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 69262 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6833535 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6833535 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6833535 # number of overall hits -system.cpu1.dcache.overall_hits::total 6833535 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 181434 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 181434 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 139542 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139542 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5058 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5058 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23425 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23425 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 320976 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 320976 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 320976 # number of overall misses -system.cpu1.dcache.overall_misses::total 320976 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2698134351 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2698134351 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3673411367 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3673411367 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91654251 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 91654251 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 540931813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 540931813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 185500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 185500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6371545718 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6371545718 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6371545718 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6371545718 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3944246 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3944246 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3210265 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3210265 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 94346 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 94346 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92687 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92687 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7154511 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7154511 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7154511 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7154511 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046000 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046000 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043467 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.043467 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053611 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.053611 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.252732 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.252732 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044863 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.044863 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044863 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044863 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14871.161695 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.161695 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26324.772233 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 26324.772233 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18120.650652 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18120.650652 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23092.073127 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23092.073127 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2806 # number of quiesce instructions executed +system.cpu1.tickCycles 98408596 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 16685859 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 195662 # number of replacements +system.cpu1.dcache.tags.tagsinuse 474.092793 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17323078 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 195999 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 88.383502 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90082708500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.092793 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.925962 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.925962 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 337 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 249 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 88 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.658203 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 35540406 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 35540406 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 10562839 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10562839 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6561699 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6561699 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 92378 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 92378 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71754 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71754 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 17124538 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 17124538 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 17124538 # number of overall hits +system.cpu1.dcache.overall_hits::total 17124538 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 188265 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 188265 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 144615 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 144615 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 4906 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 4906 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23743 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23743 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 332880 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 332880 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 332880 # number of overall misses +system.cpu1.dcache.overall_misses::total 332880 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2782453534 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2782453534 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3892497330 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3892497330 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 87637747 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 87637747 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 559501111 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 559501111 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 370500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 370500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6674950864 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6674950864 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6674950864 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6674950864 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10751104 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10751104 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6706314 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6706314 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97284 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97284 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95497 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95497 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 17457418 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 17457418 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 17457418 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 17457418 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.017511 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.017511 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021564 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.021564 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050430 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.050430 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248626 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248626 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.019068 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.019068 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.019068 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.019068 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14779.452017 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14779.452017 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26916.276527 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26916.276527 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 17863.380962 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 17863.380962 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23564.886956 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23564.886956 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20052.123480 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20052.123480 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20052.123480 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1483,74 +1484,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 113901 # number of writebacks -system.cpu1.dcache.writebacks::total 113901 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15137 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 15137 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 49794 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 49794 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 64931 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 64931 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 64931 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 64931 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166297 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 166297 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89748 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 89748 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5058 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5058 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23425 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23425 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 256045 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 256045 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 256045 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 256045 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2162409829 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2162409829 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2163633710 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2163633710 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81526749 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81526749 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 492905187 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492905187 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 177500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 177500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326043539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4326043539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4326043539 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4326043539 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 330271000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 330271000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 203208500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 203208500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 533479500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 533479500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042162 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042162 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027957 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027957 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053611 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053611 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.252732 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.252732 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.035788 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035788 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13003.300294 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13003.300294 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24107.876610 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24107.876610 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16118.376631 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16118.376631 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21041.843629 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21041.843629 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 120164 # number of writebacks +system.cpu1.dcache.writebacks::total 120164 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15759 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15759 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52033 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52033 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 67792 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 67792 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 67792 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 67792 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 172506 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 172506 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92582 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92582 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4906 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23743 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23743 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 265088 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 265088 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 265088 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 265088 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2304438945 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2304438945 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2314812844 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2314812844 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80267253 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80267253 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522512389 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522512389 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 358500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 358500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4619251789 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4619251789 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4619251789 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4619251789 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322402500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322402500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1844154499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1844154499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166556999 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166556999 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016045 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.016045 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013805 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013805 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050430 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050430 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248626 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248626 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.015185 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015185 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015185 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13358.601701 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13358.601701 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25002.839040 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25002.839040 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16361.038117 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16361.038117 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22007.007918 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22007.007918 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17425.352294 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17425.352294 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17425.352294 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17425.352294 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1558,57 +1559,57 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 908016 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.415703 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6861520 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 908528 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.552348 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 71602668000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.415703 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975421 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975421 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 948962 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.398770 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38866849 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 949474 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.935138 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 71724827500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.398770 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975388 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975388 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 16448624 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 16448624 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6861520 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6861520 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6861520 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6861520 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6861520 # number of overall hits -system.cpu1.icache.overall_hits::total 6861520 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 908528 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 908528 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 908528 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 908528 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 908528 # number of overall misses -system.cpu1.icache.overall_misses::total 908528 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7748571238 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7748571238 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7748571238 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7748571238 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7748571238 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7748571238 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7770048 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7770048 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7770048 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7770048 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7770048 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7770048 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116927 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.116927 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116927 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.116927 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116927 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.116927 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8528.709339 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8528.709339 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8528.709339 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8528.709339 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8528.709339 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8528.709339 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 80582120 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 80582120 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 38866849 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 38866849 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 38866849 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 38866849 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 38866849 # number of overall hits +system.cpu1.icache.overall_hits::total 38866849 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 949474 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 949474 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 949474 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 949474 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 949474 # number of overall misses +system.cpu1.icache.overall_misses::total 949474 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8197479438 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8197479438 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8197479438 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8197479438 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8197479438 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8197479438 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39816323 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39816323 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39816323 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39816323 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 39816323 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 39816323 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023846 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023846 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023846 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023846 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023846 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023846 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8633.706071 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.706071 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8633.706071 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8633.706071 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.706071 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8633.706071 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1617,215 +1618,215 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 908528 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 908528 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 908528 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 908528 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 908528 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 908528 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6381932762 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6381932762 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6381932762 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6381932762 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6381932762 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6381932762 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10331250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10331250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10331250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10331250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116927 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.116927 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116927 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.116927 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7024.475593 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7024.475593 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7024.475593 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 949474 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 949474 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 949474 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 949474 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 949474 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 949474 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7246706562 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7246706562 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7246706562 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7246706562 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7246706562 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7246706562 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10208000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10208000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10208000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10208000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023846 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023846 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023846 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.023846 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023846 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.023846 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7632.338076 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7632.338076 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.338076 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.338076 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.338076 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7632.338076 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 255012 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 255045 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 26 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 263000 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 263018 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 67427 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 54264 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15327.785502 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1131516 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 69292 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 16.329677 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 69926 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 55260 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15340.181807 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1180273 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 70026 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 16.854783 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8763.818423 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.824644 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.109281 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3126.745417 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2197.034801 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1213.252936 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.534901 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001637 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 7920.573124 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 36.864575 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.107624 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4396.054830 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2144.688544 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 841.893110 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.483433 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002250 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.190841 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.134096 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.074051 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.935534 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2056 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 45 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12927 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 84 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 880 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1092 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.268314 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.130901 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.051385 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.936290 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2047 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 12670 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 77 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 853 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1117 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 271 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5756 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6900 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.125488 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002747 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.789001 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21629208 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21629208 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28145 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2626 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 889570 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 104349 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1024690 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 113900 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 113900 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1602 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1602 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 885 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 24979 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 24979 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28145 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2626 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 889570 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 129328 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1049669 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28145 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2626 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 889570 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 129328 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1049669 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 614 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 219 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 18958 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 67006 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 86797 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28133 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28133 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22540 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22540 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35034 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35034 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 614 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 219 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 18958 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 102040 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 121831 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 614 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 219 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 18958 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 102040 # number of overall misses -system.cpu1.l2cache.overall_misses::total 121831 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13117250 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4335498 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 588499240 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1440160422 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 2046112410 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 524558345 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 524558345 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 440871540 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440871540 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 173000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 173000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1316941950 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1316941950 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13117250 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4335498 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 588499240 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2757102372 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3363054360 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13117250 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4335498 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 588499240 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2757102372 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3363054360 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28759 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2845 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 908528 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171355 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1111487 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 113900 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 113900 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29735 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29735 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23425 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23425 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60013 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 60013 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28759 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2845 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 908528 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 231368 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1171500 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28759 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2845 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 908528 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 231368 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1171500 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.076977 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020867 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.391036 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.078091 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.946124 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.946124 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962220 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962220 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.583774 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.583774 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.076977 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020867 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.441029 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.103996 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.076977 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020867 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.441029 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.103996 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19796.794521 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31042.263952 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21493.006925 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23573.538371 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18645.659723 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18645.659723 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19559.518190 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19559.518190 # average SCUpgradeReq miss latency +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5605 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6801 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.124939 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002991 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.773315 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 22538505 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 22538505 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28252 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2535 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 928580 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 109415 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 1068782 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120163 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120163 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1523 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1523 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 944 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 944 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27335 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27335 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28252 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2535 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 928580 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 136750 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1096117 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28252 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2535 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 928580 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 136750 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1096117 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 647 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 218 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 20894 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 67997 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 89756 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28472 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28472 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22799 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22799 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35252 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 35252 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 647 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 218 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 20894 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 103249 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 125008 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 647 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 218 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 20894 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 103249 # number of overall misses +system.cpu1.l2cache.overall_misses::total 125008 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15366481 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4392000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 733956985 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1489534989 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 2243250455 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 540730906 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 540730906 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 460330587 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 460330587 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 350500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 350500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1393602664 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1393602664 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15366481 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4392000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 733956985 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2883137653 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3636853119 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15366481 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4392000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 733956985 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2883137653 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3636853119 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28899 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2753 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 949474 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 177412 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 1158538 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120163 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120163 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29995 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29995 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23743 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23743 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 62587 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 62587 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28899 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2753 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 949474 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 239999 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1221125 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28899 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2753 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 949474 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 239999 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1221125 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022388 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.079186 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.022006 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.383272 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.077474 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.949225 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.949225 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.960241 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.960241 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.563248 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.563248 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022388 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.079186 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.022006 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.430206 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.102371 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022388 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.079186 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.022006 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.430206 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.102371 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 23750.357032 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20146.788991 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35127.643582 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21905.892745 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24992.763214 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18991.672731 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18991.672731 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20190.823589 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20190.823589 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37590.396472 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37590.396472 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31042.263952 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27019.819404 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 27604.258030 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31042.263952 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27019.819404 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 27604.258030 # average overall miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39532.584364 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39532.584364 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 23750.357032 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20146.788991 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35127.643582 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27924.121812 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 29092.963002 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 23750.357032 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20146.788991 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35127.643582 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27924.121812 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 29092.963002 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1834,127 +1835,127 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks -system.cpu1.l2cache.writebacks::total 33019 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 18 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 88 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 284 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 284 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 372 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 372 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 390 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 614 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 219 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 18940 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66918 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 86691 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 25785 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28133 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28133 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22540 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22540 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34750 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34750 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 614 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 219 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 18940 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 101668 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 121441 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 614 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 219 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 18940 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 101668 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 147226 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2802498 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 454726510 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 969167182 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1435514940 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1025770621 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 399929245 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 399929245 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306606785 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306606785 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 145000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 145000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1042779776 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1042779776 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2802498 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454726510 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2011946958 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2478294716 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2802498 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454726510 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2011946958 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3504065337 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9029750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 307917500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316947250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 187186000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 187186000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9029750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 495103500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 504133250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.390523 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.077996 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 32039 # number of writebacks +system.cpu1.l2cache.writebacks::total 32039 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 17 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 99 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 227 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 227 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 17 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 326 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 343 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 17 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 326 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 343 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 647 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 218 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 20877 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 67898 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 89640 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 27323 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 27323 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28472 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28472 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22799 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22799 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35025 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 35025 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 647 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 218 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 20877 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 102923 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 124665 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 647 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 218 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 20877 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 102923 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 27323 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 151988 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 11152993 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2975000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 596579765 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1045445755 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1656153513 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 967597598 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 967597598 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 454341493 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 454341493 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 344269721 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 344269721 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 298500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 298500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1133512279 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1133512279 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 11152993 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2975000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 596579765 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2178958034 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2789665792 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11152993 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2975000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 596579765 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2178958034 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 967597598 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3757263390 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9248000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2205503500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2214751500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1754476501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1754476501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9248000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3959980001 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3969228001 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.382714 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.077373 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946124 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946124 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962220 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962220 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.579041 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.579041 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103663 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.949225 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.949225 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.960241 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.960241 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.559621 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.559621 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.102090 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022388 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079186 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.021988 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428848 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125673 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14482.907170 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14215.662923 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13602.785492 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.124466 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15397.298227 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18475.608133 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 35413.300077 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15957.484300 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15957.484300 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15100.211457 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15100.211457 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30008.051108 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783 # average overall mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32362.948722 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32362.948722 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22377.297493 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17238.010819 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13646.788991 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28575.933563 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21170.759053 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 35413.300077 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24720.789733 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1964,64 +1965,62 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1492249 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1157222 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2126 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2126 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 113900 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 36842 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74786 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41424 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85596 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 82199 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 64364 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1817284 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 767101 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7150 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 61380 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2652915 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 58153088 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24793955 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11380 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115036 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 83073459 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 610470 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1874725 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.283158 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.450533 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1549513 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1217389 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120163 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 34752 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76638 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42182 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86369 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85047 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67036 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1899176 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 835933 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7082 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62248 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2804439 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60773632 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25876936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11012 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 115596 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86777176 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 610005 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1929839 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.274006 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.446012 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1343882 71.68% 71.68% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 530843 28.32% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 1401052 72.60% 72.60% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 528787 27.40% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1874725 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 789561722 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1929839 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 840003478 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79017500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80148998 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1364909988 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 381206023 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1425055438 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 412471555 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4307495 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4329500 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 32623745 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33365476 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31012 # Transaction distribution -system.iobus.trans_dist::ReadResp 31012 # Transaction distribution -system.iobus.trans_dist::WriteReq 59440 # Transaction distribution -system.iobus.trans_dist::WriteResp 23216 # Transaction distribution +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59422 # Transaction distribution +system.iobus.trans_dist::WriteResp 23198 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2042,11 +2041,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2067,11 +2066,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2111,52 +2110,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347036169 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 199065929 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36822569 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36796533 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36417 # number of replacements -system.iocache.tags.tagsinuse 0.997930 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.480362 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 269849823000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.997930 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062371 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062371 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270133806000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.480362 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.905023 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.905023 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328311 # Number of tag accesses +system.iocache.tags.data_accesses 328311 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses -system.iocache.demand_misses::total 243 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 243 # number of overall misses -system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 30354377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 30354377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9625347223 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9625347223 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 30354377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 30354377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 30354377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 30354377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32660377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32660377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6669320019 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6669320019 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32660377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32660377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32660377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32660377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2165,40 +2164,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124915.131687 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124915.131687 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265717.403462 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265717.403462 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124915.131687 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124915.131687 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124915.131687 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56938 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128079.909804 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128079.909804 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184113.295578 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 184113.295578 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128079.909804 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128079.909804 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128079.909804 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23275 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7266 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3594 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.836224 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.476071 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36174 # number of writebacks -system.iocache.writebacks::total 36174 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17717377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17717377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7741561361 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7741561361 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17717377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17717377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17717377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17717377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19371377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19371377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4785606085 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4785606085 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19371377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19371377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19371377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19371377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2207,304 +2206,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72911.016461 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72911.016461 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213713.597642 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213713.597642 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72911.016461 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72911.016461 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 75966.184314 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 75966.184314 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132111.475403 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132111.475403 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 75966.184314 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 75966.184314 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 75966.184314 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 75966.184314 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 139153 # number of replacements -system.l2c.tags.tagsinuse 64176.379405 # Cycle average of tags in use -system.l2c.tags.total_refs 380612 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 203608 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.869337 # Average number of references to valid blocks. +system.l2c.tags.replacements 135784 # number of replacements +system.l2c.tags.tagsinuse 63989.836026 # Cycle average of tags in use +system.l2c.tags.total_refs 379813 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200303 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.896192 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11502.485032 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 90.401142 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 9505.348435 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2919.846446 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36413.661117 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.683124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1274.245745 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 582.633884 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1880.036266 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.175514 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001379 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.145040 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044553 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.555628 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.019443 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008890 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.028687 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979254 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31795 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 67 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32593 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 145 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5678 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25972 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 12166.183008 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 73.341692 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8672.913636 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2762.328324 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35676.457886 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.004073 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2139.434191 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 561.920463 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1923.222583 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.185641 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.132338 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042150 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.544380 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.032645 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.029346 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.976407 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31538 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 56 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32925 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 124 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5437 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25977 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 66 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3295 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 28977 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.485153 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001022 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.497330 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5313847 # Number of tag accesses -system.l2c.tags.data_accesses 5313847 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 426 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 48963 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 21691 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 75814 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 118 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 32 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 16648 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 7359 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7439 # number of ReadReq hits -system.l2c.ReadReq_hits::total 178553 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 234152 # number of Writeback hits -system.l2c.Writeback_hits::total 234152 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2938 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 658 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3596 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 142 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 176 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3842 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1332 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5174 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 426 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 48963 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 25533 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 75814 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 118 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 16648 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 8691 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 7439 # number of demand (read+write) hits -system.l2c.demand_hits::total 183727 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 426 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 48963 # number of overall hits -system.l2c.overall_hits::cpu0.data 25533 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 75814 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 118 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits -system.l2c.overall_hits::cpu1.inst 16648 # number of overall hits -system.l2c.overall_hits::cpu1.data 8691 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 7439 # number of overall hits -system.l2c.overall_hits::total 183727 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 162 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1023::4 55 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 29429 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.481232 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.502396 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5287676 # Number of tag accesses +system.l2c.tags.data_accesses 5287676 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 420 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 71 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 47985 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 21581 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 76019 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 126 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 31 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 17578 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 7426 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7556 # number of ReadReq hits +system.l2c.ReadReq_hits::total 178793 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 232242 # number of Writeback hits +system.l2c.Writeback_hits::total 232242 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 3124 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 764 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3888 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 156 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 320 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4039 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1693 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5732 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 420 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 71 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 47985 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 25620 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 76019 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 126 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 31 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 17578 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9119 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 7556 # number of demand (read+write) hits +system.l2c.demand_hits::total 184525 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 420 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 71 # number of overall hits +system.l2c.overall_hits::cpu0.inst 47985 # number of overall hits +system.l2c.overall_hits::cpu0.data 25620 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 76019 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 126 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 31 # number of overall hits +system.l2c.overall_hits::cpu1.inst 17578 # number of overall hits +system.l2c.overall_hits::cpu1.data 9119 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 7556 # number of overall hits +system.l2c.overall_hits::total 184525 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 23855 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8693 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2292 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1041 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq misses -system.l2c.ReadReq_misses::total 178995 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2734 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11704 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 618 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1189 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1807 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11575 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8676 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 20251 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 162 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 22827 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8447 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134637 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 21 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3299 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1023 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6207 # number of ReadReq misses +system.l2c.ReadReq_misses::total 176613 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 9362 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2973 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12335 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 691 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1280 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1971 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11331 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8391 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19722 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 23855 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20268 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2292 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9717 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) misses -system.l2c.demand_misses::total 199246 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 162 # number of overall misses +system.l2c.demand_misses::cpu0.inst 22827 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19778 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 134637 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 21 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3299 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9414 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 6207 # number of demand (read+write) misses +system.l2c.demand_misses::total 196335 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 23855 # number of overall misses -system.l2c.overall_misses::cpu0.data 20268 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 136690 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2292 # number of overall misses -system.l2c.overall_misses::cpu1.data 9717 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 6249 # number of overall misses -system.l2c.overall_misses::total 199246 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 12996250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1747991991 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 697325498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 960250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 172995499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 85266750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 17612731920 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 7054791 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 1587933 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 8642724 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 937466 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 512978 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1450444 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 952737665 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 639334486 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1592072151 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 12996250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1747991991 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1650063163 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 960250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 172995499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 724601236 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19204804071 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 12996250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1747991991 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1650063163 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 960250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 172995499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 724601236 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19204804071 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 588 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 64 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 72818 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 30384 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 212504 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 130 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 32 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 18940 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 8400 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 13688 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 357548 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 234152 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 234152 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 11908 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3392 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 15300 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 760 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1365 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2125 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15417 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10008 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25425 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 588 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 72818 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 45801 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 212504 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 130 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 18940 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 18408 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13688 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 382973 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 588 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 72818 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 45801 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 212504 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 130 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 18940 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 18408 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13688 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 382973 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.015625 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.327598 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.286105 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.121014 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.123929 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.500618 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.753275 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.806014 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.764967 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.813158 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.871062 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.850353 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.750795 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.866906 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.796500 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.015625 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.327598 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.442523 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.121014 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.527868 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.520261 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.015625 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.327598 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.442523 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.121014 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.527868 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.520261 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73275.707022 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 80216.898424 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75477.966405 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 81908.501441 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 98397.898936 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 786.487291 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 580.809437 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 738.441900 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1516.935275 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 431.436501 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 802.680686 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82309.949460 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73690.005302 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 78616.964644 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 73275.707022 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 81412.234212 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75477.966405 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74570.467840 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 96387.400856 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 73275.707022 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 81412.234212 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75477.966405 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74570.467840 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 96387.400856 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 22827 # number of overall misses +system.l2c.overall_misses::cpu0.data 19778 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 134637 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 21 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3299 # number of overall misses +system.l2c.overall_misses::cpu1.data 9414 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 6207 # number of overall misses +system.l2c.overall_misses::total 196335 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 13524750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 82500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1838995046 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 735224800 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13878942092 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 2299500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 276071257 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 88476763 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 819085145 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 17652701853 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8759261 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2783911 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11543172 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1313463 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1279959 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2593422 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1048895931 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 690519981 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1739415912 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 13524750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 82500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1838995046 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1784120731 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13878942092 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 2299500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 276071257 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 778996744 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 819085145 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 19392117765 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 13524750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 82500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1838995046 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1784120731 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13878942092 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 2299500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 276071257 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 778996744 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 819085145 # number of overall miss cycles +system.l2c.overall_miss_latency::total 19392117765 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 571 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 72 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 70812 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 30028 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 210656 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 147 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 31 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 20877 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 8449 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 13763 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 355406 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 232242 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 232242 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 12486 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3737 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 16223 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 855 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1436 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2291 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15370 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10084 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25454 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 571 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 70812 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 45398 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 210656 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 147 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 31 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 20877 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 18533 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13763 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 380860 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 571 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 70812 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 45398 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 210656 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 147 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 31 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 20877 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 18533 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13763 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 380860 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.264448 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.013889 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.322361 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.281304 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.639132 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.158021 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.121079 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.450992 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.496933 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.749800 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.795558 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.760340 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.808187 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.891365 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.860323 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.737215 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.832110 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.774809 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.264448 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.013889 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.322361 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.435658 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.639132 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.158021 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.507959 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.450992 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.515504 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.264448 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.013889 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.322361 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.435658 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.639132 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.158021 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.507959 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.450992 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.515504 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 89567.880795 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80562.274762 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 87039.753759 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 103084.160313 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 109500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83683.315247 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 86487.549365 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 131961.518447 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 99951.316455 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 935.618564 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 936.397915 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 935.806405 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1900.814761 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 999.967969 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1315.789954 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92568.699232 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82292.930640 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 88196.730149 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89567.880795 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80562.274762 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 90207.338002 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 103084.160313 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 109500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83683.315247 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 82748.751222 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 131961.518447 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 98770.559325 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89567.880795 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80562.274762 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 90207.338002 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 103084.160313 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 109500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83683.315247 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 82748.751222 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 131961.518447 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 98770.559325 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2513,186 +2512,186 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 104097 # number of writebacks -system.l2c.writebacks::total 104097 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 162 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 101714 # number of writebacks +system.l2c.writebacks::total 101714 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 3 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 3 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 3 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 23847 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8693 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2289 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1041 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 178984 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8970 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2734 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11704 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 618 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1189 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1807 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11575 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8676 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 20251 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 162 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 22826 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8447 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 134637 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 21 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 3297 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1023 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6207 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 176610 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 9362 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2973 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12335 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 691 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1280 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1971 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11331 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8391 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 19722 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 23847 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20268 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2289 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9717 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 199235 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 162 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 22826 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19778 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134637 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 21 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 3297 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9414 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6207 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 196332 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 23847 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20268 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2289 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9717 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 199235 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1445321741 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 589131498 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 810750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 143882249 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 72327750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15392098420 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 91762404 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 27532715 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 119295119 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6310115 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11917186 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 18227301 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 807808323 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 530171012 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1337979335 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1445321741 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1396939821 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 810750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 143882249 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 602498762 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16730077755 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1445321741 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1396939821 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 810750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 143882249 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 602498762 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16730077755 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 163590000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5355654498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6093250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 257169500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5782507248 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4096891000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 150604000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4247495000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 163590000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9452545498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6093250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 407773500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10030002248 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.286105 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.123929 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.500587 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.806014 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813158 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.871062 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850353 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750795 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.866906 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.796500 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.442523 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.527868 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.520232 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.442523 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.527868 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.520232 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67770.792362 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69479.106628 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 85997.063536 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10229.922408 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.488296 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10192.679340 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10210.542071 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.864592 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10087.050913 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69789.055983 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61107.769940 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 66069.790875 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68923.417259 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62004.606566 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68923.417259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62004.606566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 22826 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19778 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134637 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 21 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 3297 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9414 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6207 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 196332 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 11628250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 70000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1553014454 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 629441200 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12219469940 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 2036500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 234611993 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 75645237 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 743074583 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15468992157 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 166983326 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 52806462 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 219789788 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 12384188 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22755279 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 35139467 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 908785069 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 585566519 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1494351588 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 11628250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 70000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1553014454 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1538226269 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12219469940 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 2036500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 234611993 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 661211756 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 743074583 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16963343745 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 11628250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 70000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1553014454 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1538226269 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12219469940 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 2036500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 234611993 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 661211756 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 743074583 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16963343745 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 205849250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3714789750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6630000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1920029500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5847298500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2763619000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1533180000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4296799000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 205849250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6478408750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6630000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3453209500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10144097500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.264448 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013889 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.322346 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.281304 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.639132 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.157925 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.121079 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.450992 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.496925 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.749800 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795558 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.760340 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.808187 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.891365 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.860323 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.737215 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.832110 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.774809 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.264448 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013889 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.322346 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.435658 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.639132 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.157925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.507959 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.450992 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.515497 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.264448 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013889 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.322346 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.435658 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.639132 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.157925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.507959 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.450992 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.515497 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74516.538416 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73944.513196 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 87588.427365 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17836.287759 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17762.012109 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17818.385732 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17922.124457 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.561719 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17828.243024 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80203.430324 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69785.069598 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 75770.793429 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77008.278146 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68037.082888 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77774.611639 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90758.632025 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96976.190476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71159.233546 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70237.067771 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119715.576446 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86401.318914 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2707,57 +2706,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 217279 # Transaction distribution -system.membus.trans_dist::ReadResp 217279 # Transaction distribution -system.membus.trans_dist::WriteReq 30939 # Transaction distribution -system.membus.trans_dist::WriteResp 30939 # Transaction distribution -system.membus.trans_dist::Writeback 140271 # Transaction distribution +system.membus.trans_dist::ReadReq 215369 # Transaction distribution +system.membus.trans_dist::ReadResp 215369 # Transaction distribution +system.membus.trans_dist::WriteReq 31074 # Transaction distribution +system.membus.trans_dist::WriteResp 31074 # Transaction distribution +system.membus.trans_dist::Writeback 137904 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 75080 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40217 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13603 # Transaction distribution -system.membus.trans_dist::ReadExReq 40948 # Transaction distribution -system.membus.trans_dist::ReadExResp 20159 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 77019 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40910 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14411 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.membus.trans_dist::ReadExReq 39992 # Transaction distribution +system.membus.trans_dist::ReadExResp 19617 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13590 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 668031 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 789629 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108880 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 898509 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663493 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 785643 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 894551 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27180 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19605228 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19796474 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24430906 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123136 # Total snoops (count) -system.membus.snoop_fanout::samples 511969 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28392 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19286572 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19478976 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24114432 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124537 # Total snoops (count) +system.membus.snoop_fanout::samples 508980 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 511969 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 508980 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 511969 # Request fanout histogram -system.membus.reqLayer0.occupancy 88887000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 508980 # Request fanout histogram +system.membus.reqLayer0.occupancy 88720999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11855500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12492999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1869891749 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2005520473 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38480431 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1167594605 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1174957130 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37546467 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2790,44 +2790,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 516876 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 516861 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30939 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30939 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 234152 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 78584 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40535 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 119119 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 13 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51536 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51536 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1131248 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 290761 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1422009 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34509719 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5415139 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39924858 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 285546 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 919868 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.039644 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.195121 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 518257 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 518242 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31074 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31074 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 232242 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36265 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80802 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41230 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 122032 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51798 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51798 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1084621 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339731 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1424352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34113464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5575752 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39689216 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 290726 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 922102 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.039605 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.195030 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 883401 96.04% 96.04% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36467 3.96% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 885582 96.04% 96.04% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36520 3.96% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 919868 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1489301846 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 922102 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 794355306 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1891845782 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 645358377 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 683518313 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 260405210 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 6a8c865e1..6dd28da03 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852858 # Number of seconds simulated -sim_ticks 2852857543000 # Number of ticks simulated -final_tick 2852857543000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.853442 # Number of seconds simulated +sim_ticks 2853442108500 # Number of ticks simulated +final_tick 2853442108500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109881 # Simulator instruction rate (inst/s) -host_op_rate 132861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2793727953 # Simulator tick rate (ticks/s) -host_mem_usage 608784 # Number of bytes of host memory used -host_seconds 1021.17 # Real time elapsed on the host -sim_insts 112207125 # Number of instructions simulated -sim_ops 135672670 # Number of ops (including micro ops) simulated +host_inst_rate 171765 # Simulator instruction rate (inst/s) +host_op_rate 207684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4374009836 # Simulator tick rate (ticks/s) +host_mem_usage 619996 # Number of bytes of host memory used +host_seconds 652.36 # Real time elapsed on the host +sim_insts 112053421 # Number of instructions simulated +sim_ops 135485276 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7296 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1662912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9175012 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1671680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9169380 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10847140 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1662912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1662912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7962752 # Number of bytes written to this memory +system.physmem.bytes_read::total 10849380 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1671680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1671680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7972992 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7980276 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7990516 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 114 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 25983 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143791 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170006 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124418 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170041 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124578 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128799 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128959 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2557 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 582893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3216078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3802202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 582893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 582893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2791150 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2797292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2791150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 585847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3213445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3802208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 585847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 585847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2794166 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2800308 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2794166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2557 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 582893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3222220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6599494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170006 # Number of read requests accepted -system.physmem.writeReqs 165023 # Number of write requests accepted -system.physmem.readBursts 170006 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165023 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10873728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 10175104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10847140 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10298612 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6006 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10656 # Per bank write bursts -system.physmem.perBankRdBursts::1 10651 # Per bank write bursts -system.physmem.perBankRdBursts::2 10704 # Per bank write bursts -system.physmem.perBankRdBursts::3 10614 # Per bank write bursts -system.physmem.perBankRdBursts::4 13356 # Per bank write bursts -system.physmem.perBankRdBursts::5 10666 # Per bank write bursts -system.physmem.perBankRdBursts::6 11042 # Per bank write bursts -system.physmem.perBankRdBursts::7 10972 # Per bank write bursts -system.physmem.perBankRdBursts::8 10208 # Per bank write bursts -system.physmem.perBankRdBursts::9 10672 # Per bank write bursts -system.physmem.perBankRdBursts::10 10509 # Per bank write bursts -system.physmem.perBankRdBursts::11 9657 # Per bank write bursts -system.physmem.perBankRdBursts::12 10109 # Per bank write bursts -system.physmem.perBankRdBursts::13 10747 # Per bank write bursts -system.physmem.perBankRdBursts::14 9757 # Per bank write bursts -system.physmem.perBankRdBursts::15 9582 # Per bank write bursts -system.physmem.perBankWrBursts::0 10072 # Per bank write bursts -system.physmem.perBankWrBursts::1 10092 # Per bank write bursts -system.physmem.perBankWrBursts::2 10491 # Per bank write bursts -system.physmem.perBankWrBursts::3 10304 # Per bank write bursts -system.physmem.perBankWrBursts::4 9538 # Per bank write bursts -system.physmem.perBankWrBursts::5 9899 # Per bank write bursts -system.physmem.perBankWrBursts::6 10133 # Per bank write bursts -system.physmem.perBankWrBursts::7 10134 # Per bank write bursts -system.physmem.perBankWrBursts::8 10091 # Per bank write bursts -system.physmem.perBankWrBursts::9 10380 # Per bank write bursts -system.physmem.perBankWrBursts::10 10169 # Per bank write bursts -system.physmem.perBankWrBursts::11 9697 # Per bank write bursts -system.physmem.perBankWrBursts::12 9799 # Per bank write bursts -system.physmem.perBankWrBursts::13 10201 # Per bank write bursts -system.physmem.perBankWrBursts::14 9040 # Per bank write bursts -system.physmem.perBankWrBursts::15 8946 # Per bank write bursts +system.physmem.bw_total::cpu.inst 585847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3219587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6602516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170041 # Number of read requests accepted +system.physmem.writeReqs 165183 # Number of write requests accepted +system.physmem.readBursts 170041 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165183 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10875008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 9072064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10849380 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10308852 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23407 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4604 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10431 # Per bank write bursts +system.physmem.perBankRdBursts::1 10779 # Per bank write bursts +system.physmem.perBankRdBursts::2 11040 # Per bank write bursts +system.physmem.perBankRdBursts::3 10735 # Per bank write bursts +system.physmem.perBankRdBursts::4 13061 # Per bank write bursts +system.physmem.perBankRdBursts::5 10390 # Per bank write bursts +system.physmem.perBankRdBursts::6 11080 # Per bank write bursts +system.physmem.perBankRdBursts::7 11267 # Per bank write bursts +system.physmem.perBankRdBursts::8 10153 # Per bank write bursts +system.physmem.perBankRdBursts::9 10232 # Per bank write bursts +system.physmem.perBankRdBursts::10 10264 # Per bank write bursts +system.physmem.perBankRdBursts::11 9394 # Per bank write bursts +system.physmem.perBankRdBursts::12 10277 # Per bank write bursts +system.physmem.perBankRdBursts::13 10799 # Per bank write bursts +system.physmem.perBankRdBursts::14 10090 # Per bank write bursts +system.physmem.perBankRdBursts::15 9930 # Per bank write bursts +system.physmem.perBankWrBursts::0 8676 # Per bank write bursts +system.physmem.perBankWrBursts::1 9067 # Per bank write bursts +system.physmem.perBankWrBursts::2 9547 # Per bank write bursts +system.physmem.perBankWrBursts::3 9319 # Per bank write bursts +system.physmem.perBankWrBursts::4 8434 # Per bank write bursts +system.physmem.perBankWrBursts::5 8678 # Per bank write bursts +system.physmem.perBankWrBursts::6 9214 # Per bank write bursts +system.physmem.perBankWrBursts::7 9423 # Per bank write bursts +system.physmem.perBankWrBursts::8 8918 # Per bank write bursts +system.physmem.perBankWrBursts::9 8886 # Per bank write bursts +system.physmem.perBankWrBursts::10 8752 # Per bank write bursts +system.physmem.perBankWrBursts::11 8449 # Per bank write bursts +system.physmem.perBankWrBursts::12 8824 # Per bank write bursts +system.physmem.perBankWrBursts::13 8894 # Per bank write bursts +system.physmem.perBankWrBursts::14 8297 # Per bank write bursts +system.physmem.perBankWrBursts::15 8373 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2852857119000 # Total gap between requests +system.physmem.numWrRetry 40 # Number of times write queue was full causing retry +system.physmem.totGap 2853441702500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169451 # Read request sizes (log2) +system.physmem.readPktSize::6 169486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160642 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160802 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,177 +159,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.308059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.690406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.894179 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22562 35.83% 35.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14454 22.96% 58.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6551 10.40% 69.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3518 5.59% 74.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2542 4.04% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1533 2.43% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1128 1.79% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1127 1.79% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9547 15.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62962 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6648 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.554603 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.154464 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6646 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6648 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6648 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.914862 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.938842 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.611148 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5537 83.29% 83.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 45 0.68% 83.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 19 0.29% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 242 3.64% 87.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 123 1.85% 89.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 0.80% 90.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 26 0.39% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 33 0.50% 91.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 114 1.71% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.29% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.21% 93.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.17% 93.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 33 0.50% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 20 0.30% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.15% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 22 0.33% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 60 0.90% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 16 0.24% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.11% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 13 0.20% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 84 1.26% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.08% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 9 0.14% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.14% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.23% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.05% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 10 0.15% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 37 0.56% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 8 0.12% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.14% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 5 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 4 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6648 # Writes before turning the bus around for reads -system.physmem.totQLat 1659710000 # Total ticks spent queuing -system.physmem.totMemAccLat 4845372500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849510000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9768.63 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 100 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.802648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.147121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.470119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22296 36.08% 36.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14465 23.41% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6637 10.74% 70.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3539 5.73% 75.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2616 4.23% 80.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1600 2.59% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1149 1.86% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1212 1.96% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8279 13.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.927818 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 584.509202 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5873 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.134684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.418054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 43.798135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5542 94.36% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 90 1.53% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.29% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 15 0.26% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 16 0.27% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 28 0.48% 97.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 28 0.48% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.22% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 10 0.17% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 8 0.14% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 17 0.29% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 16 0.27% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 10 0.17% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.09% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.12% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.09% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 11 0.19% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 8 0.14% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads +system.physmem.totQLat 1685079736 # Total ticks spent queuing +system.physmem.totMemAccLat 4871117236 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849610000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9916.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28518.63 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28666.78 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.33 # Average write queue length when enqueuing -system.physmem.readRowHits 140084 # Number of row buffer hits during reads -system.physmem.writeRowHits 125841 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes -system.physmem.avgGap 8515254.26 # Average gap between requests -system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 246909600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134722500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 691555800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 522696240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83503223595 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638462219000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909895676495 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.469106 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725585905000 # Time in different power states -system.physmem_0.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 140217 # Number of row buffer hits during reads +system.physmem.writeRowHits 109661 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.35 # Row buffer hit rate for writes +system.physmem.avgGap 8512044.79 # Average gap between requests +system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 242267760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132189750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 692507400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 468860400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83617160895 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638712655250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1910238133215 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.452112 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726011845150 # Time in different power states +system.physmem_0.memoryStateTime::REF 95282460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32002250000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32147776350 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 229083120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 124995750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 633664200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 507533040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82044200295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639742072250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909615898415 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.371033 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727729306000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem_1.actEnergy 224857080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122689875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 632876400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 449634240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82395435150 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639784344500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909982329005 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.362464 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727805815350 # Time in different power states +system.physmem_1.memoryStateTime::REF 95282460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29860939000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30353736650 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -349,15 +334,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31058702 # Number of BP lookups -system.cpu.branchPred.condPredicted 16880390 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2530392 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18557624 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13376459 # Number of BTB hits +system.cpu.branchPred.lookups 31053109 # Number of BP lookups +system.cpu.branchPred.condPredicted 16852863 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2525514 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18620216 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13364906 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.080666 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7810096 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1523796 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.776321 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7853668 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1516989 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -388,57 +373,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66845 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66845 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43967 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22878 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66845 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66845 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66845 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7791 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10107.303299 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7513.505454 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7923.201613 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7786 99.94% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7791 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 234495500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 234495500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 234495500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6429 82.52% 82.52% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1362 17.48% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7791 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66845 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 65844 # Table walker walks requested +system.cpu.dtb.walker.walksShort 65844 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43330 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22514 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 65844 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 65844 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 65844 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7786 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11086.116106 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8821.657087 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7338.018596 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 78.00% 78.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1707 21.92% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7786 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6400 82.20% 82.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1386 17.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7786 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65844 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66845 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7791 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65844 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7786 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7791 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74636 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7786 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 73630 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24793006 # DTB read hits -system.cpu.dtb.read_misses 59858 # DTB read misses -system.cpu.dtb.write_hits 19468400 # DTB write hits -system.cpu.dtb.write_misses 6987 # DTB write misses +system.cpu.dtb.read_hits 24757406 # DTB read hits +system.cpu.dtb.read_misses 59085 # DTB read misses +system.cpu.dtb.write_hits 19449348 # DTB write hits +system.cpu.dtb.write_misses 6759 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 757 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24852864 # DTB read accesses -system.cpu.dtb.write_accesses 19475387 # DTB write accesses +system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24816491 # DTB read accesses +system.cpu.dtb.write_accesses 19456107 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44261406 # DTB hits -system.cpu.dtb.misses 66845 # DTB misses -system.cpu.dtb.accesses 44328251 # DTB accesses +system.cpu.dtb.hits 44206754 # DTB hits +system.cpu.dtb.misses 65844 # DTB misses +system.cpu.dtb.accesses 44272598 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,37 +454,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5440 # Table walker walks requested -system.cpu.itb.walker.walksShort 5440 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 316 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5124 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5440 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5440 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5440 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3188 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10236.198243 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7641.069075 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7067.497935 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1310 41.09% 41.09% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1157 36.29% 77.38% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 720 22.58% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3188 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 234126500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 234126500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 234126500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2879 90.31% 90.31% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.69% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3188 # Table walker page sizes translated +system.cpu.itb.walker.walks 5446 # Table walker walks requested +system.cpu.itb.walker.walksShort 5446 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5122 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5446 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5446 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5446 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11253.454774 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8989.562910 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7050.042435 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1281 40.23% 40.23% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1185 37.22% 77.45% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 717 22.52% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2875 90.30% 90.30% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.70% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5440 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5440 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5446 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5446 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3188 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3188 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8628 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57692911 # ITB inst hits -system.cpu.itb.inst_misses 5440 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8630 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57726188 # ITB inst hits +system.cpu.itb.inst_misses 5446 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -507,119 +493,119 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2976 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8450 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57698351 # ITB inst accesses -system.cpu.itb.hits 57692911 # DTB hits -system.cpu.itb.misses 5440 # DTB misses -system.cpu.itb.accesses 57698351 # DTB accesses -system.cpu.numCycles 314937774 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57731634 # ITB inst accesses +system.cpu.itb.hits 57726188 # DTB hits +system.cpu.itb.misses 5446 # DTB misses +system.cpu.itb.accesses 57731634 # DTB accesses +system.cpu.numCycles 317415724 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112207125 # Number of instructions committed -system.cpu.committedOps 135672670 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7783589 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112053421 # Number of instructions committed +system.cpu.committedOps 135485276 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7764036 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390825701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.806754 # CPI: cycles per instruction -system.cpu.ipc 0.356283 # IPC: instructions per cycle +system.cpu.quiesceCycles 5389516808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.832718 # CPI: cycles per instruction +system.cpu.ipc 0.353018 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 228221487 # Number of cycles that the object actually ticked -system.cpu.idleCycles 86716287 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 841983 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.953279 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42762284 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842495 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.756721 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.953279 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999909 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy +system.cpu.tickCycles 228406815 # Number of cycles that the object actually ticked +system.cpu.idleCycles 89008909 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842109 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.947879 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42706608 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 842621 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.683057 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.947879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176413277 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176413277 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23536274 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23536274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18304900 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18304900 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457909 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457909 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460268 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41841174 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41841174 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41841174 # number of overall hits -system.cpu.dcache.overall_hits::total 41841174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 583393 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 583393 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 541748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 541748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8195 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8195 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176191359 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176191359 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23499832 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23499832 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18286134 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18286134 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457571 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457571 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460116 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460116 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41785966 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41785966 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41785966 # number of overall hits +system.cpu.dcache.overall_hits::total 41785966 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 583874 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 583874 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 541283 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 541283 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8366 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8366 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1125141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1125141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1125141 # number of overall misses -system.cpu.dcache.overall_misses::total 1125141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8651014339 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8651014339 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21393186307 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21393186307 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116036500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 116036500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30044200646 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30044200646 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30044200646 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30044200646 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24119667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24119667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18846648 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18846648 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466104 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466104 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460270 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460270 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42966315 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42966315 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42966315 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42966315 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024187 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024187 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028745 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028745 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017582 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017582 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 1125157 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1125157 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1125157 # number of overall misses +system.cpu.dcache.overall_misses::total 1125157 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8774452459 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8774452459 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 23299729316 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 23299729316 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 120081750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 120081750 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 165500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 32074181775 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 32074181775 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 32074181775 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 32074181775 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24083706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24083706 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18827417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18827417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465937 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 465937 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460118 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460118 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42911123 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42911123 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42911123 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42911123 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024244 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.024244 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.028750 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028750 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017955 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017955 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026187 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026187 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026187 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026187 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14828.793522 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14828.793522 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39489.183729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39489.183729 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14159.426480 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.426480 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26702.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26702.609403 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.026221 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.026221 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026221 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026221 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15027.989702 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15027.989702 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43045.374261 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43045.374261 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14353.544107 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14353.544107 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82750 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82750 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28506.405573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28506.405573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,70 +614,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 698310 # number of writebacks -system.cpu.dcache.writebacks::total 698310 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45149 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45149 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242834 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 242834 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 287983 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 287983 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 287983 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 287983 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538244 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 538244 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298914 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 298914 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8195 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8195 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 697919 # number of writebacks +system.cpu.dcache.writebacks::total 697919 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45195 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 45195 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242825 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 242825 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 288020 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 288020 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 288020 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 288020 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538679 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 538679 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298458 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298458 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8366 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8366 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 837158 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 837158 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 837158 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 837158 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6893184142 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6893184142 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11166823654 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11166823654 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99620500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99620500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18060007796 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18060007796 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18060007796 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18060007796 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790998000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790998000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4439562500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439562500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10230560500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230560500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022316 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022316 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015860 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015860 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017582 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017582 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 837137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 837137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 837137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 837137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7251218502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7251218502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12288582898 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12288582898 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 107501250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 107501250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19539801400 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19539801400 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19539801400 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19539801400 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836783750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836783750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510033500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510033500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346817250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346817250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017955 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017955 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.019484 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019484 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12806.801640 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12806.801640 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37357.981406 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37357.981406 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12156.253813 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.253813 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.019509 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019509 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13461.112280 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13461.112280 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41173.575170 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41173.575170 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12849.778867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12849.778867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -699,58 +685,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2900110 # number of replacements -system.cpu.icache.tags.tagsinuse 511.424371 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54783568 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2900622 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.886835 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15309705250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.424371 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998876 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998876 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2898605 # number of replacements +system.cpu.icache.tags.tagsinuse 511.397830 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54818221 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2899117 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.908592 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15715014250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.397830 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998824 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998824 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60584835 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60584835 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54783568 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54783568 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54783568 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54783568 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54783568 # number of overall hits -system.cpu.icache.overall_hits::total 54783568 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2900634 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2900634 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2900634 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2900634 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2900634 # number of overall misses -system.cpu.icache.overall_misses::total 2900634 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 39169046291 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 39169046291 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 39169046291 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 39169046291 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 39169046291 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 39169046291 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57684202 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57684202 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57684202 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57684202 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57684202 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57684202 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050285 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050285 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050285 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050285 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050285 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050285 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13503.615517 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13503.615517 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13503.615517 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13503.615517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13503.615517 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13503.615517 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60616478 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60616478 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54818221 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54818221 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54818221 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54818221 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54818221 # number of overall hits +system.cpu.icache.overall_hits::total 54818221 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2899129 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2899129 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2899129 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2899129 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2899129 # number of overall misses +system.cpu.icache.overall_misses::total 2899129 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 39309012875 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 39309012875 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39309012875 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39309012875 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39309012875 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39309012875 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57717350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57717350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57717350 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57717350 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57717350 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57717350 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050230 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050230 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050230 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050230 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050230 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050230 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13558.904373 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13558.904373 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13558.904373 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13558.904373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13558.904373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13558.904373 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,196 +745,196 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2900634 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2900634 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2900634 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2900634 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2900634 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2900634 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33358375709 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33358375709 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33358375709 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33358375709 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33358375709 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33358375709 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 222066250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 222066250 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 222066250 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 222066250 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050285 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050285 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050285 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050285 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11500.373956 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11500.373956 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11500.373956 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11500.373956 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2899129 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2899129 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2899129 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2899129 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2899129 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2899129 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 34950907125 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 34950907125 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34950907125 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34950907125 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34950907125 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34950907125 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050230 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050230 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050230 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12055.657794 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12055.657794 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12055.657794 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12055.657794 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.657794 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.657794 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96921 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65071.012008 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4047776 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162169 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.960233 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 96782 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65059.413288 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4045474 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 162031 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.967284 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 47498.508165 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 71.489031 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000365 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 12194.784847 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5306.229599 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.724770 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 47373.506796 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.256900 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12244.945403 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5373.703806 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.722862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001026 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186078 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.080967 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992905 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 37 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65211 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2285 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6934 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55872 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000565 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995041 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 36621683 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 36621683 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71038 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4429 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 2877594 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 532037 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3485098 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 698310 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 698310 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 164919 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 164919 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 71038 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 4429 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 2877594 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 696956 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3650017 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 71038 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 4429 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 2877594 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 696956 # number of overall hits -system.cpu.l2cache.overall_hits::total 3650017 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 128 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186843 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.081996 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992728 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65218 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2276 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6932 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55893 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000473 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995148 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 36598730 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 36598730 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69951 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4476 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 2876131 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 532779 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 3483337 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 697919 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 697919 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 49 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 49 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 164415 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 164415 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 69951 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 4476 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2876131 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 697194 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 3647752 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 69951 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 4476 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 2876131 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 697194 # number of overall hits +system.cpu.l2cache.overall_hits::total 3647752 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 114 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 1 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 23013 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 14397 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 37539 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2779 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2779 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 22980 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 14261 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 37356 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2807 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2807 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 131168 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 131168 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 128 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131192 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131192 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 114 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 1 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 23013 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 145565 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 168707 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 128 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 22980 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 145453 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 168548 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 114 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 1 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 23013 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 145565 # number of overall misses -system.cpu.l2cache.overall_misses::total 168707 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 10214250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 74500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1672158250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1100939750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2783386750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 790966 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 790966 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9154216683 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9154216683 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 10214250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 74500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1672158250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10255156433 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11937603433 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 10214250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 74500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1672158250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10255156433 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11937603433 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 71166 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4430 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 2900607 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 546434 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 3522637 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 698310 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 698310 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2832 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2832 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 22980 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 145453 # number of overall misses +system.cpu.l2cache.overall_misses::total 168548 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 9734000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 82500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1838541652 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1191731612 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3040089764 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 1092965 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 1092965 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 160500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10173645453 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10173645453 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 9734000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 82500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1838541652 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11365377065 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13213735217 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 9734000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 82500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1838541652 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11365377065 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13213735217 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 70065 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 4477 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 2899111 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 547040 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 3520693 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 697919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 697919 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2856 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2856 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296087 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296087 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 71166 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 4430 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 2900607 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 842521 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 3818724 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 71166 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 4430 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 2900607 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 842521 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 3818724 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001799 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000226 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007934 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026347 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.010657 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.981285 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.981285 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 295607 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295607 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 70065 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 4477 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 2899111 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 842647 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 3816300 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 70065 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 4477 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 2899111 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 842647 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 3816300 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001627 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000223 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.007927 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026069 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.010610 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.982843 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.982843 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443005 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.443005 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001799 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000226 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007934 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.172773 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.044179 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001799 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000226 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007934 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.172773 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.044179 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79798.828125 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72661.463086 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76470.080572 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74146.534271 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 284.622526 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 284.622526 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69790.014966 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69790.014966 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79798.828125 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72661.463086 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70450.701975 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70759.384216 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79798.828125 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74500 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72661.463086 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70450.701975 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70759.384216 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.443805 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.443805 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001627 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000223 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.007927 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.172614 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.044165 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001627 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000223 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.007927 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.172614 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.044165 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85385.964912 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80006.164143 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83565.781642 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81381.565585 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 389.371215 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 389.371215 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 80250 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 80250 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77547.757889 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77547.757889 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85385.964912 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80006.164143 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78137.797536 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78397.460765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85385.964912 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80006.164143 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78137.797536 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78397.460765 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -957,109 +943,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 88228 # number of writebacks -system.cpu.l2cache.writebacks::total 88228 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 20 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 142 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 88388 # number of writebacks +system.cpu.l2cache.writebacks::total 88388 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 140 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 162 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 20 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 142 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 140 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 162 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 20 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 142 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 140 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 162 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 128 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 114 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 1 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22993 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14255 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 37377 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2779 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2779 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 22958 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14121 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 37194 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2807 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2807 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131168 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 131168 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 128 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131192 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131192 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 114 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 1 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 22993 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 145423 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 168545 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 128 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 22958 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 145313 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 168386 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 114 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 1 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 22993 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 145423 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 168545 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8641250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1382505500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 913321500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2304530750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27979779 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27979779 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7500556317 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7500556317 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8641250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1382505500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8413877817 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9805087067 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8641250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 62500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1382505500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8413877817 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9805087067 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 159586250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385715000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545301250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107025000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107025000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 159586250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9492740000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652326250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026087 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010611 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.981285 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981285 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 22958 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 145313 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 168386 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 8305000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 70000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1550026348 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1005062888 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2563464236 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 49859307 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 49859307 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 136000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 136000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8531883047 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8531883047 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 8305000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 70000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1550026348 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9536945935 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11095347283 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 8305000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 70000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1550026348 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9536945935 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11095347283 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 191729750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5400527000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5592256750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151319000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151319000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 191729750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551846000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9743575750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010564 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982843 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982843 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443005 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443005 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044136 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007927 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172605 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044136 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60127.234376 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64070.256051 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61656.386280 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10068.290392 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10068.290392 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57182.821397 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443805 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443805 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172448 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044123 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172448 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044123 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67515.739524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71175.050492 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68921.445287 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17762.489134 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17762.489134 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 68000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68000 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65033.561856 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65033.561856 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1069,61 +1055,59 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3581727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3581627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 698310 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2832 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3579627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3579531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 697919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2856 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296087 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296087 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5807240 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506645 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160889 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8489768 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185830784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98804957 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284938125 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 61311 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4581044 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.007958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.088854 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295607 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804583 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506486 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15045 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8484537 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185746048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98788181 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 280260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284832397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61029 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4577967 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4544586 99.20% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36458 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4541479 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36488 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4581044 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3015323412 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4577967 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3013390750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 202500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4360848041 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4358889625 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1341145704 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1341438850 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10564000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10568000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89727250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88362250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1144,11 +1128,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1169,11 +1153,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1213,23 +1197,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347055145 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198914708 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36809505 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.033413 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.032937 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270192614000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.033413 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064588 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064588 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270823051000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.032937 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064559 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064559 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1243,14 +1227,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 27950377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 27950377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9592588263 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9592588263 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 27950377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 27950377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 27950377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 27950377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29244877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29244877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652334326 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6652334326 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29244877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29244877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29244877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29244877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1267,19 +1251,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119446.055556 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264813.059381 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264813.059381 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119446.055556 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119446.055556 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55542 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124978.106838 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124978.106838 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183644.388417 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183644.388417 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124978.106838 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22952 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7161 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.756179 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.565217 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1293,14 +1277,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15781377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15781377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7708930273 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7708930273 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15781377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15781377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15781377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15781377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16937877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16937877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768676336 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768676336 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16937877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16937877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16937877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16937877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1309,66 +1293,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212812.783597 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212812.783597 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72384.089744 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72384.089744 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131644.112633 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131644.112633 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71749 # Transaction distribution -system.membus.trans_dist::ReadResp 71749 # Transaction distribution -system.membus.trans_dist::WriteReq 27607 # Transaction distribution -system.membus.trans_dist::WriteResp 27607 # Transaction distribution -system.membus.trans_dist::Writeback 124418 # Transaction distribution +system.membus.trans_dist::ReadReq 71726 # Transaction distribution +system.membus.trans_dist::ReadResp 71726 # Transaction distribution +system.membus.trans_dist::WriteReq 27583 # Transaction distribution +system.membus.trans_dist::WriteResp 27583 # Transaction distribution +system.membus.trans_dist::Writeback 124578 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution -system.membus.trans_dist::ReadExReq 129351 # Transaction distribution -system.membus.trans_dist::ReadExResp 129351 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution +system.membus.trans_dist::ReadExReq 129395 # Transaction distribution +system.membus.trans_dist::ReadExResp 129395 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446451 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554083 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554255 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662970 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 663142 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16510296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16674077 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16522776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16686485 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21309533 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 332202 # Request fanout histogram +system.membus.pkt_size::total 21321941 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 504 # Total snoops (count) +system.membus.snoop_fanout::samples 332271 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332271 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332202 # Request fanout histogram -system.membus.reqLayer0.occupancy 87413000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332271 # Request fanout histogram +system.membus.reqLayer0.occupancy 90362500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1704000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1674431500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1690391904 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1022735199 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 997821410 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37468495 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index c276b537b..b7b8c766f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827025 # Number of seconds simulated -sim_ticks 2827025397500 # Number of ticks simulated -final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827616 # Number of seconds simulated +sim_ticks 2827616186000 # Number of ticks simulated +final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71679 # Simulator instruction rate (inst/s) -host_op_rate 86943 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1789973688 # Simulator tick rate (ticks/s) -host_mem_usage 620632 # Number of bytes of host memory used -host_seconds 1579.37 # Real time elapsed on the host -sim_insts 113206948 # Number of instructions simulated -sim_ops 137314363 # Number of ops (including micro ops) simulated +host_inst_rate 69501 # Simulator instruction rate (inst/s) +host_op_rate 84304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1736810486 # Simulator tick rate (ticks/s) +host_mem_usage 620504 # Number of bytes of host memory used +host_seconds 1628.05 # Real time elapsed on the host +sim_insts 113151083 # Number of instructions simulated +sim_ops 137250963 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory +system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171932 # Number of read requests accepted -system.physmem.writeReqs 167449 # Number of write requests accepted -system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11320 # Per bank write bursts -system.physmem.perBankRdBursts::1 10283 # Per bank write bursts -system.physmem.perBankRdBursts::2 11137 # Per bank write bursts -system.physmem.perBankRdBursts::3 11363 # Per bank write bursts -system.physmem.perBankRdBursts::4 13028 # Per bank write bursts -system.physmem.perBankRdBursts::5 10237 # Per bank write bursts -system.physmem.perBankRdBursts::6 10954 # Per bank write bursts -system.physmem.perBankRdBursts::7 11381 # Per bank write bursts -system.physmem.perBankRdBursts::8 10407 # Per bank write bursts -system.physmem.perBankRdBursts::9 11232 # Per bank write bursts -system.physmem.perBankRdBursts::10 10729 # Per bank write bursts -system.physmem.perBankRdBursts::11 9386 # Per bank write bursts -system.physmem.perBankRdBursts::12 9853 # Per bank write bursts -system.physmem.perBankRdBursts::13 10909 # Per bank write bursts -system.physmem.perBankRdBursts::14 9951 # Per bank write bursts -system.physmem.perBankRdBursts::15 9636 # Per bank write bursts -system.physmem.perBankWrBursts::0 10810 # Per bank write bursts -system.physmem.perBankWrBursts::1 10132 # Per bank write bursts -system.physmem.perBankWrBursts::2 10502 # Per bank write bursts -system.physmem.perBankWrBursts::3 10558 # Per bank write bursts -system.physmem.perBankWrBursts::4 9654 # Per bank write bursts -system.physmem.perBankWrBursts::5 9978 # Per bank write bursts -system.physmem.perBankWrBursts::6 10358 # Per bank write bursts -system.physmem.perBankWrBursts::7 10535 # Per bank write bursts -system.physmem.perBankWrBursts::8 10309 # Per bank write bursts -system.physmem.perBankWrBursts::9 10935 # Per bank write bursts -system.physmem.perBankWrBursts::10 10009 # Per bank write bursts -system.physmem.perBankWrBursts::11 9154 # Per bank write bursts -system.physmem.perBankWrBursts::12 9556 # Per bank write bursts -system.physmem.perBankWrBursts::13 10555 # Per bank write bursts -system.physmem.perBankWrBursts::14 9521 # Per bank write bursts -system.physmem.perBankWrBursts::15 9009 # Per bank write bursts +system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176173 # Number of read requests accepted +system.physmem.writeReqs 171661 # Number of write requests accepted +system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11334 # Per bank write bursts +system.physmem.perBankRdBursts::1 10890 # Per bank write bursts +system.physmem.perBankRdBursts::2 10732 # Per bank write bursts +system.physmem.perBankRdBursts::3 10393 # Per bank write bursts +system.physmem.perBankRdBursts::4 14045 # Per bank write bursts +system.physmem.perBankRdBursts::5 11531 # Per bank write bursts +system.physmem.perBankRdBursts::6 11498 # Per bank write bursts +system.physmem.perBankRdBursts::7 11674 # Per bank write bursts +system.physmem.perBankRdBursts::8 10645 # Per bank write bursts +system.physmem.perBankRdBursts::9 10993 # Per bank write bursts +system.physmem.perBankRdBursts::10 10307 # Per bank write bursts +system.physmem.perBankRdBursts::11 9597 # Per bank write bursts +system.physmem.perBankRdBursts::12 9956 # Per bank write bursts +system.physmem.perBankRdBursts::13 10908 # Per bank write bursts +system.physmem.perBankRdBursts::14 10689 # Per bank write bursts +system.physmem.perBankRdBursts::15 10844 # Per bank write bursts +system.physmem.perBankWrBursts::0 9257 # Per bank write bursts +system.physmem.perBankWrBursts::1 9346 # Per bank write bursts +system.physmem.perBankWrBursts::2 9336 # Per bank write bursts +system.physmem.perBankWrBursts::3 8962 # Per bank write bursts +system.physmem.perBankWrBursts::4 9705 # Per bank write bursts +system.physmem.perBankWrBursts::5 9746 # Per bank write bursts +system.physmem.perBankWrBursts::6 9125 # Per bank write bursts +system.physmem.perBankWrBursts::7 9630 # Per bank write bursts +system.physmem.perBankWrBursts::8 9307 # Per bank write bursts +system.physmem.perBankWrBursts::9 9634 # Per bank write bursts +system.physmem.perBankWrBursts::10 8942 # Per bank write bursts +system.physmem.perBankWrBursts::11 8449 # Per bank write bursts +system.physmem.perBankWrBursts::12 8881 # Per bank write bursts +system.physmem.perBankWrBursts::13 9361 # Per bank write bursts +system.physmem.perBankWrBursts::14 9018 # Per bank write bursts +system.physmem.perBankWrBursts::15 9072 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2827025186500 # Total gap between requests +system.physmem.numWrRetry 58 # Number of times write queue was full causing retry +system.physmem.totGap 2827615975000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2993 # Read request sizes (log2) +system.physmem.readPktSize::4 2994 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168384 # Read request sizes (log2) +system.physmem.readPktSize::6 172624 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 163068 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167280 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,175 +159,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads -system.physmem.totQLat 2011805750 # Total ticks spent queuing -system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads +system.physmem.totQLat 2104910750 # Total ticks spent queuing +system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing -system.physmem.readRowHits 141825 # Number of row buffer hits during reads -system.physmem.writeRowHits 127038 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes -system.physmem.avgGap 8329945.36 # Average gap between requests -system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.379373 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states -system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing +system.physmem.readRowHits 145058 # Number of row buffer hits during reads +system.physmem.writeRowHits 112529 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes +system.physmem.avgGap 8129210.99 # Average gap between requests +system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.422846 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states +system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.289511 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states -system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.324331 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states +system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -347,15 +333,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46965884 # Number of BP lookups -system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits +system.cpu.branchPred.lookups 46937284 # Number of BP lookups +system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -386,45 +372,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 9687 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9687 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9687 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9687 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9687 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 207947000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 207947000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 207947000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6190 82.28% 82.28% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1333 17.72% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7523 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9687 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 9923 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9923 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9923 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9923 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9923 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 230116500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 230116500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 230116500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 6339 81.70% 81.70% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1420 18.30% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7759 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9923 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9687 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7523 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7759 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7523 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17210 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7759 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17682 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24601959 # DTB read hits -system.cpu.checker.dtb.read_misses 8249 # DTB read misses -system.cpu.checker.dtb.write_hits 19645805 # DTB write hits -system.cpu.checker.dtb.write_misses 1438 # DTB write misses +system.cpu.checker.dtb.read_hits 24588859 # DTB read hits +system.cpu.checker.dtb.read_misses 8478 # DTB read misses +system.cpu.checker.dtb.write_hits 19638229 # DTB write hits +system.cpu.checker.dtb.write_misses 1445 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 4297 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 4321 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1738 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24610208 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19647243 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24597337 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19639674 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44247764 # DTB hits -system.cpu.checker.dtb.misses 9687 # DTB misses -system.cpu.checker.dtb.accesses 44257451 # DTB accesses +system.cpu.checker.dtb.hits 44227088 # DTB hits +system.cpu.checker.dtb.misses 9923 # DTB misses +system.cpu.checker.dtb.accesses 44237011 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -459,9 +445,9 @@ system.cpu.checker.itb.walker.walksShort 4826 # Ta system.cpu.checker.itb.walker.walkWaitTime::samples 4826 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::0 4826 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::total 4826 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 207571000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 207571000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 207571000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::samples 229704000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 229704000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 229704000 # Table walker pending requests distribution system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.24% 88.24% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::1M 373 11.76% 100.00% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::total 3171 # Table walker page sizes translated @@ -472,7 +458,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 7997 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115911347 # ITB inst hits +system.cpu.checker.itb.inst_hits 115853330 # ITB inst hits system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -489,11 +475,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115916173 # ITB inst accesses -system.cpu.checker.itb.hits 115911347 # DTB hits +system.cpu.checker.itb.inst_accesses 115858156 # ITB inst accesses +system.cpu.checker.itb.hits 115853330 # DTB hits system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115916173 # DTB accesses -system.cpu.checker.numCycles 139170806 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115858156 # DTB accesses +system.cpu.checker.numCycles 139105254 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -525,81 +511,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 69937 # Table walker walks requested -system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 72371 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25472400 # DTB read hits -system.cpu.dtb.read_misses 60528 # DTB read misses -system.cpu.dtb.write_hits 19920178 # DTB write hits -system.cpu.dtb.write_misses 9409 # DTB write misses +system.cpu.dtb.read_hits 25461870 # DTB read hits +system.cpu.dtb.read_misses 62291 # DTB read misses +system.cpu.dtb.write_hits 19915387 # DTB write hits +system.cpu.dtb.write_misses 10080 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25532928 # DTB read accesses -system.cpu.dtb.write_accesses 19929587 # DTB write accesses +system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25524161 # DTB read accesses +system.cpu.dtb.write_accesses 19925467 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45392578 # DTB hits -system.cpu.dtb.misses 69937 # DTB misses -system.cpu.dtb.accesses 45462515 # DTB accesses +system.cpu.dtb.hits 45377257 # DTB hits +system.cpu.dtb.misses 72371 # DTB misses +system.cpu.dtb.accesses 45449628 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -629,55 +618,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11957 # Table walker walks requested -system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 11974 # Table walker walks requested +system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66242388 # ITB inst hits -system.cpu.itb.inst_misses 11957 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66270436 # ITB inst hits +system.cpu.itb.inst_misses 11974 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -686,98 +676,98 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66254345 # ITB inst accesses -system.cpu.itb.hits 66242388 # DTB hits -system.cpu.itb.misses 11957 # DTB misses -system.cpu.itb.accesses 66254345 # DTB accesses -system.cpu.numCycles 260505842 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66282410 # ITB inst accesses +system.cpu.itb.hits 66270436 # DTB hits +system.cpu.itb.misses 11974 # DTB misses +system.cpu.itb.accesses 66282410 # DTB accesses +system.cpu.numCycles 263104506 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6274201 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -785,44 +775,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -846,101 +836,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued -system.cpu.iq.rate 0.550386 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued +system.cpu.iq.rate 0.544758 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151939321 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13215 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200965 # number of nop insts executed -system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed -system.cpu.iew.exec_branches 26544582 # Number of branches executed -system.cpu.iew.exec_stores 20883032 # Number of stores executed -system.cpu.iew.exec_rate 0.546767 # Inst execution rate -system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63301991 # num instructions producing a value -system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value +system.cpu.iew.exec_nop 201053 # number of nop insts executed +system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed +system.cpu.iew.exec_branches 26530134 # Number of branches executed +system.cpu.iew.exec_stores 20877849 # Number of stores executed +system.cpu.iew.exec_rate 0.541163 # Inst execution rate +system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63271750 # num instructions producing a value +system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back +system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113361853 # Number of instructions committed -system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113305988 # Number of instructions committed +system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45532382 # Number of memory references committed -system.cpu.commit.loads 24928817 # Number of loads committed -system.cpu.commit.membars 814713 # Number of memory barriers committed -system.cpu.commit.branches 26060941 # Number of branches committed +system.cpu.commit.refs 45511652 # Number of memory references committed +system.cpu.commit.loads 24916104 # Number of loads committed +system.cpu.commit.membars 814017 # Number of memory barriers committed +system.cpu.commit.branches 26045610 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120284813 # Number of committed integer instructions. -system.cpu.commit.function_calls 4896517 # Number of function calls committed. +system.cpu.commit.int_insts 120229462 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892502 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -964,214 +954,214 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction -system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction +system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373323554 # The number of ROB reads -system.cpu.rob.rob_writes 293054802 # The number of ROB writes -system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113206948 # Number of Instructions Simulated -system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155872747 # number of integer regfile reads -system.cpu.int_regfile_writes 88664447 # number of integer regfile writes -system.cpu.fp_regfile_reads 9607 # number of floating regfile reads +system.cpu.rob.rob_reads 375672050 # The number of ROB reads +system.cpu.rob.rob_writes 292972268 # The number of ROB writes +system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113151083 # Number of Instructions Simulated +system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads +system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155826637 # number of integer regfile reads +system.cpu.int_regfile_writes 88633022 # number of integer regfile writes +system.cpu.fp_regfile_reads 9606 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503168369 # number of cc regfile reads -system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes -system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837844 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502981884 # number of cc regfile reads +system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes +system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads +system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes +system.cpu.dcache.tags.replacements 839617 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15587007 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346674 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346674 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441974 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441974 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460321 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460321 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38917554 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38917554 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39264228 # number of overall hits -system.cpu.dcache.overall_hits::total 39264228 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700623 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700623 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3575875 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3575875 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177079 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177079 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26763 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26763 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4276498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4276498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4453577 # number of overall misses -system.cpu.dcache.overall_misses::total 4453577 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9909110648 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9909110648 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134775393563 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134775393563 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 355748499 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 355748499 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 176500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 176500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144684504211 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144684504211 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144684504211 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144684504211 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24031170 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24031170 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19162882 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19162882 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523753 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523753 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468737 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468737 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460325 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460325 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43194052 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43194052 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43717805 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43717805 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029155 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029155 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186604 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186604 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338096 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338096 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057096 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057096 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099007 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099007 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101871 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 44125 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 44125 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33832.473255 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32487.257818 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 491325 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15561026 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 345829 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 345829 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441066 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 459481 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 459481 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38877113 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38877113 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39222942 # number of overall hits +system.cpu.dcache.overall_hits::total 39222942 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 705718 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 705718 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3595150 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3595150 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177438 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177438 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26862 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26862 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses +system.cpu.dcache.overall_misses::total 4478306 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 459486 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 459486 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43177981 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43177981 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43701248 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43701248 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029378 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029378 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.187676 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.187676 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339096 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339096 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057406 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057406 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6982 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.370238 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695426 # number of writebacks -system.cpu.dcache.writebacks::total 695426 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286545 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 286545 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3276416 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3276416 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18452 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18452 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3562961 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3562961 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3562961 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3562961 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414078 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414078 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299459 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299459 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119308 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119308 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713537 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 713537 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 832845 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832845 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5351526415 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5351526415 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11825722463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11825722463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1475435001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1475435001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109426500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109426500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17177248878 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17177248878 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18652683879 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227794 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227794 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017731 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017731 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016519 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016519 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019050 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019050 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42125 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks +system.cpu.dcache.writebacks::total 696320 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18482 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18482 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3585952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3585952 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3585952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3585952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300275 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300275 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119609 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119609 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1179,265 +1169,265 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1894041 # number of replacements -system.cpu.icache.tags.tagsinuse 511.373863 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64258114 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894553 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.917296 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.373863 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1892540 # number of replacements +system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998723 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998723 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68134254 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68134254 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64258114 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64258114 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64258114 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64258114 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64258114 # number of overall hits -system.cpu.icache.overall_hits::total 64258114 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981572 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981572 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981572 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981572 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981572 # number of overall misses -system.cpu.icache.overall_misses::total 1981572 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26765848354 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26765848354 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26765848354 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26765848354 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26765848354 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26765848354 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66239686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66239686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66239686 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66239686 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66239686 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66239686 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029915 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029915 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029915 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029915 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029915 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029915 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.381187 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13507.381187 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13507.381187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13507.381187 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2017 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68160699 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68160699 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64285030 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64285030 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64285030 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64285030 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64285030 # number of overall hits +system.cpu.icache.overall_hits::total 64285030 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1982600 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1982600 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1982600 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1982600 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1982600 # number of overall misses +system.cpu.icache.overall_misses::total 1982600 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26922947970 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26922947970 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26922947970 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26922947970 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26922947970 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26922947970 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66267630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66267630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66267630 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66267630 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66267630 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66267630 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029918 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029918 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029918 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029918 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029918 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029918 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13579.616650 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13579.616650 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2392 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 103 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.582524 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.136000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87002 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 87002 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 87002 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 87002 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 87002 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 87002 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22163460869 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22163460869 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22163460869 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22163460869 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22163460869 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22163460869 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.412235 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.412235 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89529 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 89529 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 89529 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 89529 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028567 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98730 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65075.133005 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3019277 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163872 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.424606 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 103160 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49633.609196 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.158546 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798547 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10197.951777 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5229.614939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.757349 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000170 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155608 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.079798 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992968 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2965 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6995 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54988 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.993790 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28438035 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28438035 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53702 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11727 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1874573 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 527970 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2467972 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 695426 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 695426 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 32 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 159827 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 159827 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53702 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 11727 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1874573 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 687797 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2627799 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 53702 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 11727 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1874573 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 687797 # number of overall hits -system.cpu.l2cache.overall_hits::total 2627799 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 20 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.153913 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.087223 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992906 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6837 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55246 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 28477722 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 28477722 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56030 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12587 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1873051 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 528182 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2469850 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 696320 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 696320 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 157101 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 157101 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 56030 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 12587 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1873051 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 685283 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2626951 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 56030 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 12587 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1873051 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 685283 # number of overall hits +system.cpu.l2cache.overall_hits::total 2626951 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 19971 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 13600 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33598 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2743 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2743 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 19985 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 14326 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 34339 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2720 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2720 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 136984 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 136984 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 20 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 140540 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 140540 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19971 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 150584 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 170582 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 20 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 19985 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 154866 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 174879 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19971 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 150584 # number of overall misses -system.cpu.l2cache.overall_misses::total 170582 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1944750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1503081000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1083875750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2589438250 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 580975 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 580975 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9863483701 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9863483701 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1944750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1503081000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10947359451 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12452921951 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1944750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1503081000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10947359451 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12452921951 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53722 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11734 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894544 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 541570 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2501570 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 695426 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 695426 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2775 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2775 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296811 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296811 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53722 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 11734 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1894544 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 838381 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2798381 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53722 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 11734 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1894544 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 838381 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2798381 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000372 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000597 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010541 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025112 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013431 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988468 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988468 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461519 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461519 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000372 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000597 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010541 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.179613 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060957 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000372 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000597 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010541 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.179613 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060957 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97237.500000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76678.571429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75263.181613 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79696.746324 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77071.202155 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 211.802771 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 211.802771 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72004.640695 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72004.640695 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97237.500000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76678.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75263.181613 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72699.353524 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73002.555668 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97237.500000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76678.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75263.181613 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72699.353524 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73002.555668 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 19985 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 154866 # number of overall misses +system.cpu.l2cache.overall_misses::total 174879 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1759750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 542508 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2504189 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 696320 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 696320 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 297641 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 297641 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 12594 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1893036 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 840149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2801830 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 12594 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1893036 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 840149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2801830 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010557 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026407 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013713 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986938 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986938 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.472180 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.472180 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010557 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.184332 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062416 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010557 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.184332 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062416 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83797.619048 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 112821.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81954.603453 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85682.936619 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83517.458284 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1446,109 +1436,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 90654 # number of writebacks -system.cpu.l2cache.writebacks::total 90654 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 94866 # number of writebacks +system.cpu.l2cache.writebacks::total 94866 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 134 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 134 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 20 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 134 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19946 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33461 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2743 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2743 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14214 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34205 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2720 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2720 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136984 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 136984 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 20 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140540 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 140540 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19946 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 150472 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 170445 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 20 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19946 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 150472 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 170445 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1696750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1250973750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908888250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2162010000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27698243 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27698243 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8149358299 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8149358299 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1696750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1250973750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9058246549 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10311368299 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1696750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1250973750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9058246549 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10311368299 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157876500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387443500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545320000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107345000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107345000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157876500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494788500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652665000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024905 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013376 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988468 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988468 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461519 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461519 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62718.026171 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67384.953292 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64612.832850 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10097.791834 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10097.791834 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1558,65 +1548,61 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450497 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98357729 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219918257 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65703 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3562118 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9.010231 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 62589 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.010244 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 3525674 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 36444 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3526784 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36501 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1637,11 +1623,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1662,11 +1648,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1706,52 +1692,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 327996 # Number of tag accesses -system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses -system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.tags.tag_accesses 328113 # Number of tag accesses +system.iocache.tags.data_accesses 328113 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses +system.iocache.ReadReq_misses::total 233 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses -system.iocache.demand_misses::total 220 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 220 # number of overall misses -system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses +system.iocache.demand_misses::total 233 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 233 # number of overall misses +system.iocache.overall_misses::total 233 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1760,40 +1746,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1802,66 +1788,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67820 # Transaction distribution -system.membus.trans_dist::ReadResp 67819 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 126844 # Transaction distribution +system.membus.trans_dist::ReadReq 68566 # Transaction distribution +system.membus.trans_dist::ReadResp 68565 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::Writeback 131056 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution -system.membus.trans_dist::ReadExReq 135185 # Transaction distribution -system.membus.trans_dist::ReadExResp 135185 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution +system.membus.trans_dist::ReadExReq 138681 # Transaction distribution +system.membus.trans_dist::ReadExResp 138681 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 484 # Total snoops (count) -system.membus.snoop_fanout::samples 336478 # Request fanout histogram +system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 497 # Total snoops (count) +system.membus.snoop_fanout::samples 345038 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 336478 # Request fanout histogram -system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 345038 # Request fanout histogram +system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1895,6 +1881,6 @@ system.realview.ethernet.coalescedTotal nan # av system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 069845b38..3cbfaeabe 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.825254 # Number of seconds simulated -sim_ticks 2825254262000 # Number of ticks simulated -final_tick 2825254262000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.625396 # Number of seconds simulated +sim_ticks 2625395606000 # Number of ticks simulated +final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94727 # Simulator instruction rate (inst/s) -host_op_rate 114921 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2228089891 # Simulator tick rate (ticks/s) -host_mem_usage 647304 # Number of bytes of host memory used -host_seconds 1268.02 # Real time elapsed on the host -sim_insts 120114928 # Number of instructions simulated -sim_ops 145721614 # Number of ops (including micro ops) simulated +host_inst_rate 95828 # Simulator instruction rate (inst/s) +host_op_rate 116265 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2090645655 # Simulator tick rate (ticks/s) +host_mem_usage 649348 # Number of bytes of host memory used +host_seconds 1255.78 # Real time elapsed on the host +sim_insts 120339436 # Number of instructions simulated +sim_ops 146004136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1295328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1287356 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8203456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1180896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1238652 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8338496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 192592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 613216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 685312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 327120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 750304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 683328 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12280396 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1295328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 192592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1487920 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8689216 # Number of bytes written to this memory +system.physmem.bytes_read::total 12522572 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1180896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 327120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1508016 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8921792 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8706960 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22485 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20640 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 128179 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8939536 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 20697 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130289 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3076 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9605 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 10708 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5178 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11747 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 10677 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 194742 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135769 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198526 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 139403 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 140205 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 458482 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 455660 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2903617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 68168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 217048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 242566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4346652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 458482 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 68168 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 526650 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3075552 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6266 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3081832 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3075552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 458482 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 461927 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2903617 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 68168 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 217062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 242566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7428484 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 194742 # Number of read requests accepted -system.physmem.writeReqs 176429 # Number of write requests accepted -system.physmem.readBursts 194742 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 176429 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12454272 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue -system.physmem.bytesWritten 10909824 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12280396 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11025296 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5937 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13544 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12112 # Per bank write bursts -system.physmem.perBankRdBursts::1 11748 # Per bank write bursts -system.physmem.perBankRdBursts::2 12331 # Per bank write bursts -system.physmem.perBankRdBursts::3 12396 # Per bank write bursts -system.physmem.perBankRdBursts::4 14329 # Per bank write bursts -system.physmem.perBankRdBursts::5 12174 # Per bank write bursts -system.physmem.perBankRdBursts::6 12464 # Per bank write bursts -system.physmem.perBankRdBursts::7 12653 # Per bank write bursts -system.physmem.perBankRdBursts::8 12280 # Per bank write bursts -system.physmem.perBankRdBursts::9 12648 # Per bank write bursts -system.physmem.perBankRdBursts::10 12320 # Per bank write bursts -system.physmem.perBankRdBursts::11 11195 # Per bank write bursts -system.physmem.perBankRdBursts::12 11560 # Per bank write bursts -system.physmem.perBankRdBursts::13 11958 # Per bank write bursts -system.physmem.perBankRdBursts::14 11562 # Per bank write bursts -system.physmem.perBankRdBursts::15 10868 # Per bank write bursts -system.physmem.perBankWrBursts::0 10717 # Per bank write bursts -system.physmem.perBankWrBursts::1 10772 # Per bank write bursts -system.physmem.perBankWrBursts::2 11107 # Per bank write bursts -system.physmem.perBankWrBursts::3 11182 # Per bank write bursts -system.physmem.perBankWrBursts::4 10467 # Per bank write bursts -system.physmem.perBankWrBursts::5 10805 # Per bank write bursts -system.physmem.perBankWrBursts::6 10968 # Per bank write bursts -system.physmem.perBankWrBursts::7 10867 # Per bank write bursts -system.physmem.perBankWrBursts::8 10652 # Per bank write bursts -system.physmem.perBankWrBursts::9 11077 # Per bank write bursts -system.physmem.perBankWrBursts::10 11118 # Per bank write bursts -system.physmem.perBankWrBursts::11 10634 # Per bank write bursts -system.physmem.perBankWrBursts::12 10720 # Per bank write bursts -system.physmem.perBankWrBursts::13 10162 # Per bank write bursts -system.physmem.perBankWrBursts::14 9784 # Per bank write bursts -system.physmem.perBankWrBursts::15 9434 # Per bank write bursts +system.physmem.num_writes::total 143839 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 683 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 449797 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 471796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3176091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 124598 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 285787 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 260276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4769785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 449797 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 124598 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 574396 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3398266 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6743 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3405024 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3398266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 683 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 449797 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 478540 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3176091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 124598 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 285802 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 260276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8174809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198527 # Number of read requests accepted +system.physmem.writeReqs 180063 # Number of write requests accepted +system.physmem.readBursts 198527 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 180063 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12696000 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9728 # Total number of bytes read from write queue +system.physmem.bytesWritten 10018560 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12522636 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11257872 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 152 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23492 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14407 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12827 # Per bank write bursts +system.physmem.perBankRdBursts::1 12491 # Per bank write bursts +system.physmem.perBankRdBursts::2 12947 # Per bank write bursts +system.physmem.perBankRdBursts::3 12890 # Per bank write bursts +system.physmem.perBankRdBursts::4 14947 # Per bank write bursts +system.physmem.perBankRdBursts::5 12185 # Per bank write bursts +system.physmem.perBankRdBursts::6 12844 # Per bank write bursts +system.physmem.perBankRdBursts::7 12385 # Per bank write bursts +system.physmem.perBankRdBursts::8 12025 # Per bank write bursts +system.physmem.perBankRdBursts::9 12120 # Per bank write bursts +system.physmem.perBankRdBursts::10 11888 # Per bank write bursts +system.physmem.perBankRdBursts::11 11181 # Per bank write bursts +system.physmem.perBankRdBursts::12 11694 # Per bank write bursts +system.physmem.perBankRdBursts::13 12452 # Per bank write bursts +system.physmem.perBankRdBursts::14 11831 # Per bank write bursts +system.physmem.perBankRdBursts::15 11668 # Per bank write bursts +system.physmem.perBankWrBursts::0 10196 # Per bank write bursts +system.physmem.perBankWrBursts::1 10156 # Per bank write bursts +system.physmem.perBankWrBursts::2 10450 # Per bank write bursts +system.physmem.perBankWrBursts::3 10103 # Per bank write bursts +system.physmem.perBankWrBursts::4 9839 # Per bank write bursts +system.physmem.perBankWrBursts::5 9619 # Per bank write bursts +system.physmem.perBankWrBursts::6 10216 # Per bank write bursts +system.physmem.perBankWrBursts::7 9774 # Per bank write bursts +system.physmem.perBankWrBursts::8 9494 # Per bank write bursts +system.physmem.perBankWrBursts::9 9611 # Per bank write bursts +system.physmem.perBankWrBursts::10 9445 # Per bank write bursts +system.physmem.perBankWrBursts::11 9199 # Per bank write bursts +system.physmem.perBankWrBursts::12 9616 # Per bank write bursts +system.physmem.perBankWrBursts::13 9900 # Per bank write bursts +system.physmem.perBankWrBursts::14 9667 # Per bank write bursts +system.physmem.perBankWrBursts::15 9255 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2825253981000 # Total gap between requests +system.physmem.numWrRetry 63 # Number of times write queue was full causing retry +system.physmem.totGap 2625395343000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3083 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 191072 # Read request sizes (log2) +system.physmem.readPktSize::6 194857 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 171993 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 63499 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 64318 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 19752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8456 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7342 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4663 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 932 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 716 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 246 # What read queue length does an incoming req see +system.physmem.writePktSize::6 175627 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 71603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16635 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12571 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4946 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1315 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 955 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 264 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,160 +188,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10091 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11401 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11573 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 9000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 89336 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 261.529865 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.433799 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.548299 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46507 52.06% 52.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17145 19.19% 71.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5910 6.62% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3229 3.61% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2663 2.98% 84.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1401 1.57% 86.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 977 1.09% 87.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1056 1.18% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10448 11.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89336 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7194 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.049903 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 528.366464 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7192 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7194 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7194 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.695580 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.063476 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.872294 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 6078 84.49% 84.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 276 3.84% 88.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 196 2.72% 91.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 78 1.08% 92.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 140 1.95% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 36 0.50% 94.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 37 0.51% 95.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 44 0.61% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 68 0.95% 96.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 17 0.24% 96.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 97 1.35% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 14 0.19% 98.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 17 0.24% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 12 0.17% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 42 0.58% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.06% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 10 0.14% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 3 0.04% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 8 0.11% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.06% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 2 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-343 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7194 # Writes before turning the bus around for reads -system.physmem.totQLat 6681295250 # Total ticks spent queuing -system.physmem.totMemAccLat 10330007750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 972990000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34333.83 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2364 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9026 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9626 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8927 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1572 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1763 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 446 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 224 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 91717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 247.658515 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 138.206739 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 311.047088 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48645 53.04% 53.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18050 19.68% 72.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5879 6.41% 79.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3418 3.73% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2896 3.16% 86.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1497 1.63% 87.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 939 1.02% 88.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1042 1.14% 89.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9351 10.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91717 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6649 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.834862 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 569.193500 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6647 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6649 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6649 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.543390 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.659302 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 38.965105 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6283 94.50% 94.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 92 1.38% 95.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 34 0.51% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 28 0.42% 96.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 36 0.54% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 35 0.53% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.20% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.26% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 4 0.06% 98.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 17 0.26% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 15 0.23% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.18% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 5 0.08% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.08% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 1 0.02% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.03% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.08% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 4 0.06% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 13 0.20% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.05% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6649 # Writes before turning the bus around for reads +system.physmem.totQLat 7005041065 # Total ticks spent queuing +system.physmem.totMemAccLat 10724572315 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 991875000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35312.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 53083.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.86 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.35 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.90 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54062.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.84 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.77 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 4.29 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.38 # Average write queue length when enqueuing -system.physmem.readRowHits 162654 # Number of row buffer hits during reads -system.physmem.writeRowHits 113073 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.32 # Row buffer hit rate for writes -system.physmem.avgGap 7611731.47 # Average gap between requests -system.physmem.pageHitRate 75.52 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 347571000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 189646875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 781614600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 563014800 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79272493785 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625612031750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891297877370 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.427007 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704246406250 # Time in different power states -system.physmem_0.memoryStateTime::REF 94341260000 # Time in different power states +system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.13 # Average write queue length when enqueuing +system.physmem.readRowHits 165504 # Number of row buffer hits during reads +system.physmem.writeRowHits 97693 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.40 # Row buffer hit rate for writes +system.physmem.avgGap 6934666.38 # Average gap between requests +system.physmem.pageHitRate 74.15 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 361050480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 197001750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 807424800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 520687440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 75248496990 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1509227374500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1757839822440 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.553437 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2510629171267 # Time in different power states +system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 26661192500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27094642483 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 327809160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 178864125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 736242000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 541604880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184531504560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 78684430770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626127876500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891128331995 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.366996 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705112983500 # Time in different power states -system.physmem_1.memoryStateTime::REF 94341260000 # Time in different power states +system.physmem_1.actEnergy 332330040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 181330875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 739892400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 493691760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74790166545 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1509629418750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1757644616850 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.479084 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2511304272827 # Time in different power states +system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 25799982000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 26423733173 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -352,30 +353,30 @@ system.realview.nvmem.bytes_inst_read::total 320 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 45 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 68 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 113 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 45 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 68 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 113 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 49 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 73 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 122 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 49 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 73 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 122 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 49 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 73 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 122 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 23750953 # Number of BP lookups -system.cpu0.branchPred.condPredicted 15527618 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 965372 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 14472059 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10661692 # Number of BTB hits +system.cpu0.branchPred.lookups 51768532 # Number of BP lookups +system.cpu0.branchPred.condPredicted 23412360 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 919881 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 31255966 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 23302169 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.670872 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3843618 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 32002 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 74.552708 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15318582 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29481 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -406,87 +407,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 61986 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 61986 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26264 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18370 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 17352 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44634 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 336.413945 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2220.174334 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 43963 98.50% 98.50% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 507 1.14% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 73 0.16% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 64 0.14% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 21 0.05% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44634 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 13427 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 7972.648842 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 6416.497879 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 8239.915942 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 13383 99.67% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 25 0.19% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 6 0.04% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.07% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 13427 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 89356407948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.591290 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.497127 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 36606156956 40.97% 40.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 52714291992 58.99% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2 18812000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::3 8121500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4 2346000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::5 1919500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6 1535000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::7 979500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8 384000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::9 515500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10 241000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::11 224500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12 422000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::13 109500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14 86500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::15 262500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 89356407948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4894 78.56% 78.56% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1336 21.44% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6230 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61986 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 62660 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 62660 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24194 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18908 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 19558 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 43102 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 433.564568 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2585.553866 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-4095 41662 96.66% 96.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::4096-8191 436 1.01% 97.67% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-12287 432 1.00% 98.67% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::12288-16383 320 0.74% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-20479 76 0.18% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::20480-24575 60 0.14% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-28671 79 0.18% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::28672-32767 9 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-36863 4 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-45055 16 0.04% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::45056-49151 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-53247 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 43102 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 15681 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9053.791276 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 7430.926564 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8773.860990 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14744 94.02% 94.02% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 873 5.57% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 41 0.26% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 10 0.06% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::212992-229375 7 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 15681 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 91363987860 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.449877 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.503999 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 91318747860 99.95% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 34013000 0.04% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 5422000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 3241000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1011500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 587500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 452000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 12000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 91363987860 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5167 76.75% 76.75% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1565 23.25% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6732 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62660 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61986 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6230 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62660 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6732 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6230 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 68216 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6732 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 69392 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17554590 # DTB read hits -system.cpu0.dtb.read_misses 54209 # DTB read misses -system.cpu0.dtb.write_hits 14392399 # DTB write hits -system.cpu0.dtb.write_misses 7777 # DTB write misses +system.cpu0.dtb.read_hits 22710900 # DTB read hits +system.cpu0.dtb.read_misses 53664 # DTB read misses +system.cpu0.dtb.write_hits 16914206 # DTB write hits +system.cpu0.dtb.write_misses 8996 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3403 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 317 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2330 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3521 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 84 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1885 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 789 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17608799 # DTB read accesses -system.cpu0.dtb.write_accesses 14400176 # DTB write accesses +system.cpu0.dtb.perms_faults 828 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 22764564 # DTB read accesses +system.cpu0.dtb.write_accesses 16923202 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31946989 # DTB hits -system.cpu0.dtb.misses 61986 # DTB misses -system.cpu0.dtb.accesses 32008975 # DTB accesses +system.cpu0.dtb.hits 39625106 # DTB hits +system.cpu0.dtb.misses 62660 # DTB misses +system.cpu0.dtb.accesses 39687766 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -516,62 +516,59 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 10002 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10002 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3947 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 65 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9937 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 314.380598 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 1718.762352 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-2047 9514 95.74% 95.74% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::2048-4095 89 0.90% 96.64% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-6143 92 0.93% 97.56% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::6144-8191 156 1.57% 99.13% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-10239 23 0.23% 99.37% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::10240-12287 21 0.21% 99.58% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-14335 10 0.10% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::14336-16383 9 0.09% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-18431 7 0.07% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::18432-20479 4 0.04% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-22527 2 0.02% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::22528-24575 4 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-26623 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::26624-28671 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9937 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2600 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9117.887308 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 7551.234816 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5655.414847 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1525 58.65% 58.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 976 37.54% 96.19% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 32 1.23% 97.42% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 60 2.31% 99.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 5 0.19% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2600 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 20627596212 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.981751 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.134001 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 376836000 1.83% 1.83% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 20250383712 98.17% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 360000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 16500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 20627596212 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2218 87.50% 87.50% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 317 12.50% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2535 # Table walker page sizes translated +system.cpu0.itb.walker.walks 9923 # Table walker walks requested +system.cpu0.itb.walker.walksShort 9923 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3743 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6075 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 105 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9818 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 399.113872 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2107.706971 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9439 96.14% 96.14% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 239 2.43% 98.57% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 79 0.80% 99.38% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 28 0.29% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 10 0.10% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 11 0.11% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 5 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9818 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2687 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 10340.528470 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8874.826622 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6037.575177 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 928 34.54% 34.54% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1618 60.22% 94.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 45 1.67% 96.43% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.16% 99.59% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2687 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 18349502828 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.974755 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.157116 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 463854500 2.53% 2.53% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 17885129828 97.47% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 423500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 95000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 18349502828 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2262 87.61% 87.61% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 12.39% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2582 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10002 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10002 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9923 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2535 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2535 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 12537 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 37321844 # ITB inst hits -system.cpu0.itb.inst_misses 10002 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2582 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 12505 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 70918524 # ITB inst hits +system.cpu0.itb.inst_misses 9923 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -580,500 +577,500 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2308 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1915 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 37331846 # ITB inst accesses -system.cpu0.itb.hits 37321844 # DTB hits -system.cpu0.itb.misses 10002 # DTB misses -system.cpu0.itb.accesses 37331846 # DTB accesses -system.cpu0.numCycles 127490392 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70928447 # ITB inst accesses +system.cpu0.itb.hits 70918524 # DTB hits +system.cpu0.itb.misses 9923 # DTB misses +system.cpu0.itb.accesses 70928447 # DTB accesses +system.cpu0.numCycles 192710246 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 18416586 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 111347815 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 23750953 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 14505310 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 103542853 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2791794 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 127823 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 53549 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 359263 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 418714 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 68477 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 37322509 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 269100 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3836 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 124383162 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.079346 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.261981 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 19172907 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 190300440 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 51768532 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 38620751 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 166603353 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5605830 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 133760 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 54794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 348448 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 420234 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 74628 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 70919147 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 257234 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4157 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 189611039 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.227807 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.311092 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 62596919 50.33% 50.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 21226112 17.07% 67.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8654044 6.96% 74.35% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 31906087 25.65% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 87830492 46.32% 46.32% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 29214542 15.41% 61.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14106780 7.44% 69.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 58459225 30.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 124383162 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.186296 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.873382 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 19346102 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58140113 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 40971754 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4869688 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1055505 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3027271 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 344448 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 109400605 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3934770 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1055505 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 25005985 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11977086 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 36202111 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 40046327 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10096148 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 104386948 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1045357 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1411792 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 159433 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 59086 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 5966912 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 108436619 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 476371377 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 119317721 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9226 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 97033193 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11403415 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1211111 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1071444 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 12097609 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 18549268 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 15931724 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1681801 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2123013 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 101474466 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1673346 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 99505309 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 475979 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8870309 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 22101778 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 120255 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 124383162 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.799990 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.034146 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 189611039 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.268634 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.987495 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 24427882 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 101305691 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 56642715 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4754811 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2479940 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 2942193 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 327073 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 148781526 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3762312 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2479940 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 32842566 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11912016 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 79322122 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 52855770 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10198625 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 132285921 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1008096 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1377906 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 148604 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 51873 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6170558 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 135790293 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 611071310 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 146878490 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9376 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 124889963 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10900327 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2656202 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2518524 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22032615 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 23644678 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 18416726 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1638849 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2450280 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 129422072 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1660998 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 127592349 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 453825 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8506052 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21267672 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 117222 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 189611039 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.672916 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.964306 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 68905319 55.40% 55.40% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 22874220 18.39% 73.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 22288669 17.92% 91.71% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 9206102 7.40% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1108815 0.89% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 115784330 61.06% 61.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 32509497 17.15% 78.21% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 29946391 15.79% 94.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10293248 5.43% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1077539 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 124383162 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 189611039 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 9283826 40.69% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 70 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5520798 24.20% 64.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8011764 35.11% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10302435 44.02% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 127 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 44.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5400760 23.08% 67.10% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 7700326 32.90% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2266 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 65682798 66.01% 66.01% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 92825 0.09% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.10% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8012 0.01% 66.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 18253823 18.34% 84.46% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 15465584 15.54% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 86139109 67.51% 67.51% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 105637 0.08% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 7185 0.01% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.60% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 23381898 18.33% 85.93% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 17956248 14.07% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 99505309 # Type of FU issued -system.cpu0.iq.rate 0.780493 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 22816458 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.229299 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 346654844 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 112025701 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 97442801 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 31372 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11049 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9514 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 122299120 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 20381 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 360751 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 127592349 # Type of FU issued +system.cpu0.iq.rate 0.662094 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 23403648 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.183425 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 468620138 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 139596675 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 124128658 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 33072 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11274 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 150972031 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21694 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 349342 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1973339 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2498 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18704 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1001610 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1883137 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2543 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18891 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 974261 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 104951 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 329906 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 112825 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 327783 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1055505 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1579113 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 185823 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 103314574 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2479940 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1553148 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 173644 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 131254258 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 18549268 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 15931724 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 862014 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 26297 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 136520 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18704 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 287589 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 395520 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 683109 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 98423737 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 17803606 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1019712 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 23644678 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 18416726 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 851019 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 275684 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 650411 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 166762 # number of nop insts executed -system.cpu0.iew.exec_refs 33081779 # number of memory reference insts executed -system.cpu0.iew.exec_branches 16674739 # Number of branches executed -system.cpu0.iew.exec_stores 15278173 # Number of stores executed -system.cpu0.iew.exec_rate 0.772009 # Inst execution rate -system.cpu0.iew.wb_sent 97898733 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 97452315 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 50771632 # num instructions producing a value -system.cpu0.iew.wb_consumers 83764488 # num instructions consuming a value +system.cpu0.iew.exec_nop 171188 # number of nop insts executed +system.cpu0.iew.exec_refs 40733276 # number of memory reference insts executed +system.cpu0.iew.exec_branches 24565455 # Number of branches executed +system.cpu0.iew.exec_stores 17777509 # Number of stores executed +system.cpu0.iew.exec_rate 0.656753 # Inst execution rate +system.cpu0.iew.wb_sent 126045909 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 124138382 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 63204033 # num instructions producing a value +system.cpu0.iew.wb_consumers 102166760 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.764389 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.606124 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.644171 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618636 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 8390139 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1553091 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 624980 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 122653513 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.765118 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.477688 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9496881 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1543776 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 596906 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 186488308 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.647310 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.345681 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 78804860 64.25% 64.25% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 24438835 19.93% 84.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 8183554 6.67% 90.85% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3164514 2.58% 93.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3412948 2.78% 96.21% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1509244 1.23% 97.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1121963 0.91% 98.36% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 525683 0.43% 98.78% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1491912 1.22% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 128655160 68.99% 68.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 31929494 17.12% 86.11% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12238036 6.56% 92.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3079239 1.65% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4650991 2.49% 96.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2566190 1.38% 98.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1394957 0.75% 98.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 526048 0.28% 99.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1448193 0.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 122653513 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 78072085 # Number of instructions committed -system.cpu0.commit.committedOps 93844352 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186488308 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 99634335 # Number of instructions committed +system.cpu0.commit.committedOps 120715819 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 31506042 # Number of memory references committed -system.cpu0.commit.loads 16575928 # Number of loads committed -system.cpu0.commit.membars 642248 # Number of memory barriers committed -system.cpu0.commit.branches 16047033 # Number of branches committed -system.cpu0.commit.fp_insts 9500 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 80932371 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1914804 # Number of function calls committed. +system.cpu0.commit.refs 39204006 # Number of memory references committed +system.cpu0.commit.loads 21761541 # Number of loads committed +system.cpu0.commit.membars 628761 # Number of memory barriers committed +system.cpu0.commit.branches 23967170 # Number of branches committed +system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 105564175 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4749359 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 62239958 66.32% 66.32% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 90340 0.10% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.42% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8012 0.01% 66.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 16575928 17.66% 84.09% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 14930114 15.91% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 81401150 67.43% 67.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 103478 0.09% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 7185 0.01% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 21761541 18.03% 85.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 17442465 14.45% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 93844352 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1491912 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 120715819 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1448193 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 219244998 # The number of ROB reads -system.cpu0.rob.rob_writes 206197797 # The number of ROB writes -system.cpu0.timesIdled 126478 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3107230 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5523018391 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 77956509 # Number of Instructions Simulated -system.cpu0.committedOps 93728776 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.635404 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.635404 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.611470 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.611470 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 109237443 # number of integer regfile reads -system.cpu0.int_regfile_writes 59093647 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8049 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2136 # number of floating regfile writes -system.cpu0.cc_regfile_reads 346833598 # number of cc regfile reads -system.cpu0.cc_regfile_writes 40564465 # number of cc regfile writes -system.cpu0.misc_regfile_reads 243214174 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1207250 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 702516 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.143728 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 28480758 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 703028 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.511556 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 256726000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.143728 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970984 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.970984 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 292184577 # The number of ROB reads +system.cpu0.rob.rob_writes 263546817 # The number of ROB writes +system.cpu0.timesIdled 122559 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3099207 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5058081346 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 99512641 # Number of Instructions Simulated +system.cpu0.committedOps 120594125 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.936540 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.936540 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.516385 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.516385 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 137143613 # number of integer regfile reads +system.cpu0.int_regfile_writes 78685231 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8206 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes +system.cpu0.cc_regfile_reads 446712527 # number of cc regfile reads +system.cpu0.cc_regfile_writes 47224279 # number of cc regfile writes +system.cpu0.misc_regfile_reads 373664445 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1193481 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 673244 # number of replacements +system.cpu0.dcache.tags.tagsinuse 484.859625 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 36215686 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 673756 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 53.751931 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 278115000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.859625 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946991 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.946991 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 14 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 62650967 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 62650967 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15440226 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15440226 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 11830536 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 11830536 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 306667 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 306667 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 359893 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 359893 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 358331 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 358331 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 27270762 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 27270762 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 27577429 # number of overall hits -system.cpu0.dcache.overall_hits::total 27577429 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 630655 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 630655 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1827082 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1827082 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147933 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147933 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25364 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25364 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20059 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20059 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2457737 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2457737 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2605670 # number of overall misses -system.cpu0.dcache.overall_misses::total 2605670 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8272706723 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8272706723 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25439418868 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 25439418868 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 389472743 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 389472743 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444610334 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 444610334 # number of StoreCondReq miss cycles +system.cpu0.dcache.tags.tag_accesses 77975696 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 77975696 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 20636575 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 20636575 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14390339 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14390339 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296451 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 296451 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354772 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 354772 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351523 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 351523 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 35026914 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 35026914 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35323365 # number of overall hits +system.cpu0.dcache.overall_hits::total 35323365 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 606585 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 606585 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1800589 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1800589 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141770 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141770 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24267 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 24267 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21226 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21226 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2407174 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2407174 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2548944 # number of overall misses +system.cpu0.dcache.overall_misses::total 2548944 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8152337496 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8152337496 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26333386263 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 26333386263 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385690944 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 385690944 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485736540 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 485736540 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 421500 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 421500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 33712125591 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 33712125591 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 33712125591 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 33712125591 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16070881 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16070881 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13657618 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13657618 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 454600 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 454600 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 385257 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 385257 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 378390 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 378390 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 29728499 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 29728499 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30183099 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30183099 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039242 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039242 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.133778 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.133778 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.325414 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.325414 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065837 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065837 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053011 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053011 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082673 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.082673 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086329 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086329 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13117.642329 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13117.642329 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13923.523338 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 13923.523338 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15355.336027 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15355.336027 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22165.129568 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22165.129568 # average StoreCondReq miss latency +system.cpu0.dcache.demand_miss_latency::cpu0.data 34485723759 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34485723759 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34485723759 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34485723759 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 21243160 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 21243160 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16190928 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16190928 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 438221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379039 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 379039 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372749 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 372749 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 37434088 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 37434088 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 37872309 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 37872309 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028554 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028554 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111210 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.111210 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323513 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323513 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064022 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064022 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056944 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056944 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.064304 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.064304 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067304 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.067304 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13439.728144 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13439.728144 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14624.873451 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14624.873451 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15893.639263 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15893.639263 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22884.035617 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22884.035617 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13716.734374 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13716.734374 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12937.987386 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 12937.987386 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 953 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3495034 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 56 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 184351 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.017857 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 18.958584 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14326.228083 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14326.228083 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13529.416009 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13529.416009 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 842 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3715311 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 190617 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.541667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 19.490974 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 508420 # number of writebacks -system.cpu0.dcache.writebacks::total 508420 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 245938 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 245938 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1508738 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1508738 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18883 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18883 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1754676 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1754676 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1754676 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1754676 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 384717 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 384717 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 318344 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 318344 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102343 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102343 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6481 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6481 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20059 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20059 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 703061 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 703061 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 805404 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 805404 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4089649462 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4089649462 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4952590494 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4952590494 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1562592504 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1562592504 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 94643501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 94643501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403849666 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403849666 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 399500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 399500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9042239956 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9042239956 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10604832460 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10604832460 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4215061000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4215061000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3183836000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3183836000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7398897000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7398897000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023939 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023939 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023309 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023309 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225128 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225128 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016823 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016823 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053011 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053011 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026684 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026684 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10630.280081 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10630.280081 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15557.354604 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15557.354604 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15268.191317 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15268.191317 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14603.224965 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14603.224965 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20133.090682 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20133.090682 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 491598 # number of writebacks +system.cpu0.dcache.writebacks::total 491598 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 240080 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 240080 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1488537 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1488537 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18067 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18067 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1728617 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1728617 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1728617 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1728617 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366505 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366505 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312052 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312052 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98413 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 98413 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6200 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6200 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21226 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21226 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 678557 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 678557 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 776970 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 776970 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4125978302 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4125978302 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5242118761 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5242118761 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570027702 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570027702 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 93210251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93210251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452955960 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452955960 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 405000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 405000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9368097063 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9368097063 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10938124765 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10938124765 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5613897000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5613897000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4260937012 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4260937012 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9874834012 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9874834012 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017253 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019273 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019273 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224574 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224574 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016357 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056944 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056944 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018127 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018127 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020516 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020516 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11257.631689 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11257.631689 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16798.862885 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16798.862885 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15953.458405 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.458405 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15033.911452 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15033.911452 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21339.675869 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21339.675869 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12861.245263 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12861.245263 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13167.096836 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13167.096836 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13805.910282 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13805.910282 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14077.924199 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14077.924199 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1081,429 +1078,437 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1252930 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.771234 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36023030 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1253442 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.739287 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6360261750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.771234 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999553 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999553 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1204763 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.748349 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 69666497 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1205275 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 57.801329 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6415532250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748349 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999508 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999508 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 75891509 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 75891509 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 36023030 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 36023030 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 36023030 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 36023030 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 36023030 # number of overall hits -system.cpu0.icache.overall_hits::total 36023030 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1295987 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1295987 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1295987 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1295987 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1295987 # number of overall misses -system.cpu0.icache.overall_misses::total 1295987 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12767063333 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12767063333 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12767063333 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12767063333 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12767063333 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12767063333 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 37319017 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 37319017 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 37319017 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 37319017 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 37319017 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 37319017 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034727 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034727 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034727 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034727 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034727 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034727 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9851.227931 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9851.227931 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9851.227931 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9851.227931 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9851.227931 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1314207 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 320 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 107284 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.249795 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 143036633 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 143036633 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 69666497 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 69666497 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 69666497 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 69666497 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 69666497 # number of overall hits +system.cpu0.icache.overall_hits::total 69666497 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1249171 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1249171 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1249171 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1249171 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1249171 # number of overall misses +system.cpu0.icache.overall_misses::total 1249171 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12316352733 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12316352733 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12316352733 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12316352733 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12316352733 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12316352733 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 70915668 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 70915668 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 70915668 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 70915668 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 70915668 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 70915668 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017615 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.017615 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017615 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.017615 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017615 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.017615 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9859.621087 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9859.621087 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9859.621087 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9859.621087 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9859.621087 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9859.621087 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1363430 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 975 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 105819 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.884548 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 88.636364 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 42511 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 42511 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 42511 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 42511 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 42511 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 42511 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1253476 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1253476 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1253476 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1253476 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1253476 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1253476 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10355026178 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10355026178 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10355026178 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10355026178 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10355026178 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10355026178 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243898498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 243898498 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 243898498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 243898498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033588 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033588 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033588 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033588 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8261.048618 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8261.048618 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8261.048618 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8261.048618 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43872 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 43872 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 43872 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 43872 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 43872 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 43872 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1205299 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1205299 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1205299 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1205299 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1205299 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1205299 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10580120186 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 10580120186 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10580120186 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 10580120186 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10580120186 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 10580120186 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265434748 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265434748 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265434748 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 265434748 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.016996 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.016996 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.016996 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.016996 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8778.004616 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8778.004616 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8778.004616 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8778.004616 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1786740 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1791804 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 4513 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1762691 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1767870 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 4580 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 232652 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 271541 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16114.824240 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2179855 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 287784 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.574622 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7401.476938 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.779155 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.071208 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5022.663817 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1991.190162 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1686.642960 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.451750 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000780 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.306559 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.121533 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.102945 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983571 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1106 # Occupied blocks per task id +system.cpu0.l2cache.prefetcher.pfSpanPage 220490 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 265715 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16040.758095 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2094535 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 281946 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.428852 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2609861933500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 9327.683600 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 17.267794 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.026625 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4039.749605 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1610.171801 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1044.858671 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.569317 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001054 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000063 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.246567 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.098277 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063773 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.979050 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1077 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15123 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 20 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 467 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 462 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 483 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4242 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5796 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4505 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.067505 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15140 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 37 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 322 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 401 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 317 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4738 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7052 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2870 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.065735 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923035 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 43185169 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 43185169 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 51927 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11921 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1199916 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 396490 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1660254 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 508419 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 508419 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28435 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28435 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1750 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1750 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 214572 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 214572 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 51927 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11921 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1199916 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 611062 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1874826 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 51927 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11921 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1199916 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 611062 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1874826 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 385 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 135 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 53537 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 96948 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 151005 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26067 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26067 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18308 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18308 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 49454 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 49454 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 385 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 135 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 53537 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 146402 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 200459 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 385 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 135 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 53537 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 146402 # number of overall misses -system.cpu0.l2cache.overall_misses::total 200459 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10304000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3078250 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2513333739 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2834189427 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 5360905416 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 466106536 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 466106536 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 359161772 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 359161772 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 388500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 388500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2526024290 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2526024290 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10304000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3078250 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2513333739 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5360213717 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7886929706 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10304000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3078250 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2513333739 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5360213717 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7886929706 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 52312 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12056 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1253453 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 493438 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1811259 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 508419 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 508419 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54502 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 54502 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20058 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20058 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 264026 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 264026 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 52312 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12056 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1253453 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 757464 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2075285 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 52312 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12056 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1253453 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 757464 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2075285 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007360 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.011198 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042712 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.196475 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.083370 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.478276 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.478276 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.912753 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.912753 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.924072 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 41668980 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 41668980 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 50191 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11923 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1155240 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 372543 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1589897 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 491596 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 491596 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28444 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28444 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1603 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1603 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210600 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 210600 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 50191 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11923 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1155240 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 583143 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1800497 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 50191 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11923 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1155240 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 583143 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1800497 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 425 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 170 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 50043 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 98477 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 149115 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27382 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27382 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19621 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19621 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45870 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 45870 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 425 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 170 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 50043 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 144347 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 194985 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 425 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 170 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 50043 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 144347 # number of overall misses +system.cpu0.l2cache.overall_misses::total 194985 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11462248 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4075246 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2454493202 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2862988088 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 5333018784 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502169231 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 502169231 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396029410 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396029410 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 393499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 393499 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2652639758 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2652639758 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11462248 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4075246 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2454493202 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5515627846 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7985658542 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11462248 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4075246 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2454493202 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5515627846 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7985658542 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50616 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12093 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1205283 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 471020 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1739012 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 491597 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 491597 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55826 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55826 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21224 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 21224 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256470 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 256470 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50616 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12093 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1205283 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 727490 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1995482 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50616 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12093 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1205283 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 727490 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1995482 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.014058 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.041520 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.209072 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.085747 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000002 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000002 # miss rate for Writeback accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.490488 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.490488 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924472 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924472 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.187307 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.187307 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007360 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.011198 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042712 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.193279 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.096593 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007360 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.011198 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042712 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.193279 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.096593 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26763.636364 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22801.851852 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46945.733586 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29234.119600 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35501.509328 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17881.096252 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17881.096252 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19617.750273 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19617.750273 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 388500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 388500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51078.260404 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51078.260404 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26763.636364 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22801.851852 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46945.733586 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36612.981496 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 39344.353239 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26763.636364 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22801.851852 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46945.733586 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36612.981496 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 39344.353239 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 65 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.178851 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.178851 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.014058 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041520 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198418 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.097713 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008397 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.014058 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041520 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198418 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.097713 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 23972.035294 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49047.683033 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29072.657453 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35764.468927 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18339.391973 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18339.391973 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20183.956475 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20183.956475 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 196749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 196749.500000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57829.512928 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57829.512928 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 23972.035294 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49047.683033 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38210.893514 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 40955.245491 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26969.995294 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 23972.035294 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49047.683033 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38210.893514 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 40955.245491 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 152 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 16.250000 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 30.400000 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 194082 # number of writebacks -system.cpu0.l2cache.writebacks::total 194082 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits +system.cpu0.l2cache.writebacks::writebacks 193170 # number of writebacks +system.cpu0.l2cache.writebacks::total 193170 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 32 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 822 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 857 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 7903 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 7903 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 27 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 699 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 728 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6075 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 6075 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 32 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 8725 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 8760 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 27 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6774 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6803 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 32 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 8725 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 8760 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 383 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 134 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 53505 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 96126 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 150148 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 239164 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 239164 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26067 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26067 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18308 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18308 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 41551 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 41551 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 383 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 134 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 53505 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137677 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 191699 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 383 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 134 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 53505 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137677 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 239164 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 430863 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2127750 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2131132759 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2116031933 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4256879942 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 14990297637 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 14990297637 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 447102942 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 447102942 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 245146796 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 245146796 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 311500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 311500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1512200931 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1512200931 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2127750 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2131132759 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3628232864 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 5769080873 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 7587500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2127750 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2131132759 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3628232864 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 14990297637 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 20759378510 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 218480000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4052038481 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4270518481 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3037285940 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3037285940 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 218480000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 7089324421 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7307804421 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.194809 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.082897 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 27 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6774 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6803 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 424 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 169 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 50016 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97778 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 148387 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232167 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 232167 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27382 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27382 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19621 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19621 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 39795 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 39795 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 424 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 169 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 50016 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137573 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 188182 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 424 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 169 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 50016 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137573 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232167 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 420349 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2961750 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2122401548 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2188318454 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4322363002 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15144909271 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15144909271 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 533487187 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 533487187 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 293580560 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 293580560 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 321999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 321999 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1622773486 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1622773486 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2961750 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2122401548 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3811091940 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5945136488 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8681250 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2961750 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2122401548 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3811091940 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15144909271 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21090045759 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 241524750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5378380500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5619905250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4060847435 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4060847435 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 241524750 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9439227935 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9680752685 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.207588 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.085328 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.478276 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.478276 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.912753 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.912753 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.490488 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.490488 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924472 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924472 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157375 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157375 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181760 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.092372 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007321 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.011115 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042686 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181760 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155164 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155164 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094304 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207616 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22013.107099 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28351.226403 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 62677.901511 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17152.067442 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17152.067442 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13390.146166 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13390.146166 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36393.851676 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36393.851676 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30094.475574 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 19810.704961 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15878.731343 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39830.534698 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26353.224315 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 62677.901511 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 48180.926443 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210650 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22380.478778 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29128.987054 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65232.824954 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19483.134431 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19483.134431 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14962.568676 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.568676 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 160999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 160999.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40778.326071 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40778.326071 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31592.482214 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50172.703537 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1513,68 +1518,65 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1959682 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1897898 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19079 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19079 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 508419 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 329547 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 131 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88597 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42717 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112274 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 292255 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 279169 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2512932 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2353027 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27983 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 115316 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 5009258 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80268960 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 85221321 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48224 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 209248 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 165747753 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 677561 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3234113 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.173543 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.378716 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1908189 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1835262 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26172 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26172 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 491597 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 299764 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 91875 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43573 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 284602 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 270315 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2416584 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2311982 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27986 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112626 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4869178 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77186016 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82205272 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48372 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202464 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 159642124 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 659500 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3123483 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.174208 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.379288 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2672856 82.65% 82.65% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 561257 17.35% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 2579348 82.58% 82.58% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 544135 17.42% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3234113 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1876283497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 3123483 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1823730646 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 114853000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 112580498 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1888093495 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1815085939 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1210751284 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1180413157 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15934735 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15906731 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63036190 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 62058933 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 34134097 # Number of BP lookups -system.cpu1.branchPred.condPredicted 11727075 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 316019 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 18898892 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 15069568 # Number of BTB hits +system.cpu1.branchPred.lookups 6179090 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3881916 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 362855 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3346788 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2458848 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.737839 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12517859 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7561 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.468890 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 1048082 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 10606 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1604,91 +1606,91 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 23600 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 23600 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8914 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6871 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 7815 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 15785 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 672.093760 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3265.172364 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 14984 94.93% 94.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 394 2.50% 97.42% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 71 0.45% 97.87% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 205 1.30% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 14 0.09% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.19% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 46 0.29% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 19 0.12% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.10% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::45056-49151 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-53247 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 15785 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5984 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 7948.780916 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 6651.023666 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 5565.886785 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 4665 77.96% 77.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 897 14.99% 92.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 299 5.00% 97.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 93 1.55% 99.50% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 7 0.12% 99.62% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 21 0.35% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 2 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5984 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 71907287764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.149161 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.363512 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 61231753172 85.15% 85.15% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 10656881592 14.82% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 10600500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 3048000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1243000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 909500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 707500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 390500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 165000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 220500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 87000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 114500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 127500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 62500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 410000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 567000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 71907287764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2101 76.21% 76.21% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 656 23.79% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2757 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23600 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 24514 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 24514 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11457 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6002 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7055 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 17459 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 393.464689 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 2513.400268 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 16937 97.01% 97.01% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 156 0.89% 97.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 187 1.07% 98.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 85 0.49% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 23 0.13% 99.59% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 6 0.03% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 44 0.25% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 3 0.02% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 17459 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5476 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9377.190285 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8039.034346 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5934.391980 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2488 45.43% 45.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2481 45.31% 90.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 381 6.96% 97.70% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 96 1.75% 99.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 6 0.11% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 20 0.37% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5476 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 69614954880 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.366193 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.484439 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 44157971700 63.43% 63.43% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 25439149180 36.54% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 11249000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 3199000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 940000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 768000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 744500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 290500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 107000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 122500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 85500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 64000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 71500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 26500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 31000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 135000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 69614954880 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1964 73.78% 73.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 698 26.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2662 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24514 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23600 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2757 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24514 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2662 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2757 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 26357 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2662 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 27176 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10322903 # DTB read hits -system.cpu1.dtb.read_misses 19223 # DTB read misses -system.cpu1.dtb.write_hits 6788033 # DTB write hits -system.cpu1.dtb.write_misses 4377 # DTB write misses +system.cpu1.dtb.read_hits 5241297 # DTB read hits +system.cpu1.dtb.read_misses 21288 # DTB read misses +system.cpu1.dtb.write_hits 4318497 # DTB write hits +system.cpu1.dtb.write_misses 3226 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2089 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 54 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 72 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 621 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 398 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10342126 # DTB read accesses -system.cpu1.dtb.write_accesses 6792410 # DTB write accesses +system.cpu1.dtb.perms_faults 379 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5262585 # DTB read accesses +system.cpu1.dtb.write_accesses 4321723 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 17110936 # DTB hits -system.cpu1.dtb.misses 23600 # DTB misses -system.cpu1.dtb.accesses 17134536 # DTB accesses +system.cpu1.dtb.hits 9559794 # DTB hits +system.cpu1.dtb.misses 24514 # DTB misses +system.cpu1.dtb.accesses 9584308 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1718,65 +1720,67 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 7135 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7135 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4170 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2894 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 71 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 7064 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 161.877123 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1382.094776 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 6918 97.93% 97.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 45 0.64% 98.57% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 37 0.52% 99.09% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 22 0.31% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 14 0.20% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 9 0.13% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 3 0.04% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.03% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 1 0.01% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.06% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 6863 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6863 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4096 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2697 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 70 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6793 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 193.655233 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1558.039702 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-2047 6647 97.85% 97.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::2048-4095 36 0.53% 98.38% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 98.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::6144-8191 24 0.35% 99.15% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-10239 16 0.24% 99.38% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::10240-12287 12 0.18% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-14335 8 0.12% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.07% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-18431 3 0.04% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.04% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.06% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walkWaitTime::26624-28671 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-30719 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 7064 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1280 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9064.455469 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 7676.805908 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5570.114480 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 198 15.47% 15.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 721 56.33% 71.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 25 1.95% 73.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 272 21.25% 95.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 5 0.39% 95.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 10 0.78% 96.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.64% 97.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.48% 99.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.08% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.47% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1280 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16042620916 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.990716 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.095951 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 149006264 0.93% 0.93% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 15893540152 99.07% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 74500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16042620916 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1033 85.44% 85.44% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 176 14.56% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1209 # Table walker page sizes translated +system.cpu1.itb.walker.walkWaitTime::30720-32767 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6793 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1235 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 10095.547368 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8796.441001 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5908.625766 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 181 14.66% 14.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.17% 28.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 552 44.70% 73.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 256 20.73% 94.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.57% 94.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 7 0.57% 95.38% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.27% 97.65% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 18 1.46% 99.11% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.24% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.40% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.16% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1235 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 18043801328 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.988843 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.105174 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 201557764 1.12% 1.12% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 17842013064 98.88% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 213500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 17000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 18043801328 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7135 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7135 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6863 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6863 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1209 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1209 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 8344 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 43998995 # ITB inst hits -system.cpu1.itb.inst_misses 7135 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 8028 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 10532607 # ITB inst hits +system.cpu1.itb.inst_misses 6863 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1785,499 +1789,499 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1239 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1195 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 569 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 44006130 # ITB inst accesses -system.cpu1.itb.hits 43998995 # DTB hits -system.cpu1.itb.misses 7135 # DTB misses -system.cpu1.itb.accesses 44006130 # DTB accesses -system.cpu1.numCycles 106356723 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10539470 # ITB inst accesses +system.cpu1.itb.hits 10532607 # DTB hits +system.cpu1.itb.misses 6863 # DTB misses +system.cpu1.itb.accesses 10539470 # DTB accesses +system.cpu1.numCycles 43132973 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 10248604 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 110247468 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 34134097 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 27587427 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 92894950 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3804096 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 79886 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 35043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 199386 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 306315 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 18555 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 43998345 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 120822 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2367 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 105684787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.292794 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.339203 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9545781 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 31669827 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 6179090 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 3506930 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 31408441 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 995212 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 85708 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 38872 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 217286 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 331419 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 27804 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10531999 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 133008 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2352 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 42152917 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.913975 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.225517 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 48118877 45.53% 45.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 14213464 13.45% 58.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 7642144 7.23% 66.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 35710302 33.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 24362526 57.80% 57.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 6315176 14.98% 72.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2214119 5.25% 78.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 9261096 21.97% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 105684787 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.320940 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.036582 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 13299736 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 62299682 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 27136759 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1184524 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1764086 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 778297 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 140897 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69265057 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1207807 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1764086 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 17799261 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2243721 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 57294733 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 23798018 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2784968 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 56317455 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 239325 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 267963 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 37417 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15706 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1709289 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 56195584 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 266063253 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 60158486 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1810 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 53296548 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2899036 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1893782 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1819648 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13269922 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 10622155 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7171113 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 643276 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 895479 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 55388735 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 607798 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 55019063 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 118019 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2383882 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 6031867 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 50125 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 105684787 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.520596 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.855641 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 42152917 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.143257 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.734237 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8274124 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 20645023 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11553748 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1337865 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 342157 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 880050 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 158552 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 30233981 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1392367 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 342157 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 10058392 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2609511 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14923378 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11073163 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3146316 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 28748329 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 284293 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 329352 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 50565 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 19779 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1931384 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 29150261 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 132893523 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 32973401 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1672 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 25705063 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 3445198 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 453540 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375844 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3445196 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 5586646 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 4747027 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 699100 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 721726 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 27759685 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 627473 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 27258527 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 145234 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2799528 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 6943190 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 53970 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 42152917 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.646658 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.966330 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 71804994 67.94% 67.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16804413 15.90% 83.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 13307202 12.59% 96.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3472478 3.29% 99.72% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 295688 0.28% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 26379254 62.58% 62.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7348926 17.43% 80.01% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 5684884 13.49% 93.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2419597 5.74% 99.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 320238 0.76% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 18 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 105684787 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 42152917 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3013223 44.49% 44.49% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 670 0.01% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1729221 25.53% 70.03% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 2029703 29.97% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2004888 32.52% 32.52% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 611 0.01% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.53% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1891782 30.69% 63.22% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 2267092 36.78% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 73 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37421348 68.02% 68.02% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 46238 0.08% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3333 0.01% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 10544210 19.16% 87.27% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7003861 12.73% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 17154225 62.93% 62.93% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 35391 0.13% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4079 0.01% 63.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 5491685 20.15% 83.22% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 4573079 16.78% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 55019063 # Type of FU issued -system.cpu1.iq.rate 0.517307 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 6772817 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.123099 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 222607082 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58388753 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53008185 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6667 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2258 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1929 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 61787450 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4357 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 94839 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 27258527 # Type of FU issued +system.cpu1.iq.rate 0.631965 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6164373 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226145 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 102973934 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 31195241 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 26623969 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5644 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2049 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 33419259 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3574 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 107638 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 509093 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 756 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10627 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 368944 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 606025 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 849 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10642 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 402770 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 52621 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 79740 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 45923 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 97906 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1764086 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 541667 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 103172 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 56056220 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 342157 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 666539 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 117242 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 28442190 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 10622155 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7171113 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 314475 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 9900 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 85548 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10627 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 58910 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 131027 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 189937 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 54736921 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 10438101 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 258564 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 5586646 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 4747027 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 329140 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 12736 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 94970 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10642 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 72014 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 152187 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 224201 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 26920844 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 5360548 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 313188 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 59687 # number of nop insts executed -system.cpu1.iew.exec_refs 17373742 # number of memory reference insts executed -system.cpu1.iew.exec_branches 11974777 # Number of branches executed -system.cpu1.iew.exec_stores 6935641 # Number of stores executed -system.cpu1.iew.exec_rate 0.514654 # Inst execution rate -system.cpu1.iew.wb_sent 54589285 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53010114 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 25746768 # num instructions producing a value -system.cpu1.iew.wb_consumers 39490922 # num instructions consuming a value +system.cpu1.iew.exec_nop 55032 # number of nop insts executed +system.cpu1.iew.exec_refs 9857010 # number of memory reference insts executed +system.cpu1.iew.exec_branches 4125375 # Number of branches executed +system.cpu1.iew.exec_stores 4496462 # Number of stores executed +system.cpu1.iew.exec_rate 0.624136 # Inst execution rate +system.cpu1.iew.wb_sent 26746276 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 26625754 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 13483465 # num instructions producing a value +system.cpu1.iew.wb_consumers 21315020 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.498418 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.651967 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.617295 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.632580 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 3744166 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 557673 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 178057 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 103735818 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.501583 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.163784 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2680688 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 573503 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 207406 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 41589167 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.611775 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.358099 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 77652029 74.86% 74.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 14577800 14.05% 88.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6160967 5.94% 94.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 757264 0.73% 95.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 2015553 1.94% 97.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1576437 1.52% 99.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 460071 0.44% 99.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 129756 0.13% 99.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 405941 0.39% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 29454101 70.82% 70.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7064012 16.99% 87.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2119517 5.10% 92.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 873586 2.10% 95.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 770133 1.85% 96.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 442153 1.06% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 274514 0.66% 98.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 148169 0.36% 98.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 442982 1.07% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 103735818 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 42197750 # Number of instructions committed -system.cpu1.commit.committedOps 52032169 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 41589167 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 20860008 # Number of instructions committed +system.cpu1.commit.committedOps 25443224 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16915231 # Number of memory references committed -system.cpu1.commit.loads 10113062 # Number of loads committed -system.cpu1.commit.membars 214317 # Number of memory barriers committed -system.cpu1.commit.branches 11798243 # Number of branches committed -system.cpu1.commit.fp_insts 1928 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 46741115 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3380053 # Number of function calls committed. +system.cpu1.commit.refs 9324878 # Number of memory references committed +system.cpu1.commit.loads 4980621 # Number of loads committed +system.cpu1.commit.membars 230323 # Number of memory barriers committed +system.cpu1.commit.branches 3917567 # Number of branches committed +system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 22363157 # Number of committed integer instructions. +system.cpu1.commit.function_calls 552505 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 35068266 67.40% 67.40% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 45339 0.09% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.48% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3333 0.01% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.49% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 10113062 19.44% 86.93% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 6802169 13.07% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 16079933 63.20% 63.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 34334 0.13% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.33% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4079 0.02% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 4980621 19.58% 82.93% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 4344257 17.07% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 52032169 # Class of committed instruction -system.cpu1.commit.bw_lim_events 405941 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 25443224 # Class of committed instruction +system.cpu1.commit.bw_lim_events 442982 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 139039973 # The number of ROB reads -system.cpu1.rob.rob_writes 113498046 # The number of ROB writes -system.cpu1.timesIdled 59982 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 671936 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5543606797 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 42158419 # Number of Instructions Simulated -system.cpu1.committedOps 51992838 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.522787 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.522787 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.396387 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.396387 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 57596911 # number of integer regfile reads -system.cpu1.int_regfile_writes 36337307 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1495 # number of floating regfile reads -system.cpu1.fp_regfile_writes 580 # number of floating regfile writes -system.cpu1.cc_regfile_reads 194912842 # number of cc regfile reads -system.cpu1.cc_regfile_writes 16071052 # number of cc regfile writes -system.cpu1.misc_regfile_reads 208513912 # number of misc regfile reads -system.cpu1.misc_regfile_writes 404751 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 201045 # number of replacements -system.cpu1.dcache.tags.tagsinuse 470.607708 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 16083620 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 201364 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 79.873364 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 93308892000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 470.607708 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.919156 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.919156 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 304 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 15 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.623047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 33778764 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 33778764 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9715738 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9715738 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6106545 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6106545 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50809 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50809 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81509 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81509 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 73252 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 73252 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 15822283 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 15822283 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 15873092 # number of overall hits -system.cpu1.dcache.overall_hits::total 15873092 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 224637 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 224637 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 441375 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 441375 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 31038 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 31038 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18294 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18294 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 666012 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 666012 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 697050 # number of overall misses -system.cpu1.dcache.overall_misses::total 697050 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3524459329 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3524459329 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10055246312 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10055246312 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 359810249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 359810249 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545166265 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 545166265 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 431000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 431000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13579705641 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13579705641 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13579705641 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13579705641 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9940375 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9940375 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6547920 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6547920 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81847 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 81847 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 99803 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 99803 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 96921 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 96921 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16488295 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16488295 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16570142 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16570142 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022598 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.022598 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.067407 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.067407 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379220 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379220 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.183301 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.183301 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.244209 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.244209 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040393 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040393 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.042067 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.042067 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15689.576201 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15689.576201 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22781.639903 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22781.639903 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19668.210834 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19668.210834 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23032.923444 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23032.923444 # average StoreCondReq miss latency +system.cpu1.rob.rob_reads 68115809 # The number of ROB reads +system.cpu1.rob.rob_writes 56808236 # The number of ROB writes +system.cpu1.timesIdled 67589 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 980056 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5207108948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 20826795 # Number of Instructions Simulated +system.cpu1.committedOps 25410011 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.071033 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.071033 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.482851 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.482851 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 30054591 # number of integer regfile reads +system.cpu1.int_regfile_writes 16942565 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1393 # number of floating regfile reads +system.cpu1.fp_regfile_writes 518 # number of floating regfile writes +system.cpu1.cc_regfile_reads 96178951 # number of cc regfile reads +system.cpu1.cc_regfile_writes 9490884 # number of cc regfile writes +system.cpu1.misc_regfile_reads 81077063 # number of misc regfile reads +system.cpu1.misc_regfile_writes 422777 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 228827 # number of replacements +system.cpu1.dcache.tags.tagsinuse 478.548130 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8439386 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 229141 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.830537 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 103436351500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.548130 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934664 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.934664 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18658844 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18658844 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4567362 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4567362 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3580643 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3580643 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63652 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 63652 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87547 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 87547 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79571 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79571 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8148005 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8148005 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8211657 # number of overall hits +system.cpu1.dcache.overall_hits::total 8211657 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 253908 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 253908 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 480072 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 480072 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 36130 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 36130 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19184 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 19184 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23489 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23489 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 733980 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 733980 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 770110 # number of overall misses +system.cpu1.dcache.overall_misses::total 770110 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4026677920 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4026677920 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11127636122 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11127636122 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 374723986 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 374723986 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 547048827 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 547048827 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1003000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1003000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15154314042 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15154314042 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15154314042 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15154314042 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4821270 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4821270 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4060715 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4060715 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99782 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 99782 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106731 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 106731 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 103060 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 103060 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8881985 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8881985 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8981767 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8981767 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.052664 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.052664 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118224 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.118224 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.362089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.362089 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.179742 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.179742 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227916 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227916 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.082637 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.082637 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.085741 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.085741 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15858.806812 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15858.806812 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23179.098389 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23179.098389 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19533.151897 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19533.151897 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23289.574993 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23289.574993 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20389.581030 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20389.581030 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19481.680856 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19481.680856 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1443381 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 46 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 45166 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.391304 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 31.957247 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20646.766999 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20646.766999 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19678.116168 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19678.116168 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1600979 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 33 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 49143 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.363636 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 32.577966 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 125175 # number of writebacks -system.cpu1.dcache.writebacks::total 125175 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 81304 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 81304 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 345063 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 345063 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13214 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13214 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 426367 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 426367 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 426367 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 426367 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 143333 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 143333 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 96312 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 96312 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29478 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29478 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5080 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5080 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 239645 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 239645 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 269123 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 269123 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1836231651 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1836231651 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2306828153 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2306828153 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 473894752 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 473894752 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 85053999 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85053999 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 496613735 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 496613735 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 413000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 413000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4143059804 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4143059804 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4616954556 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4616954556 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298741750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298741750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826982999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826982999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125724749 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125724749 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014419 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014419 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014709 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014709 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.360160 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.360160 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050900 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050900 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.244209 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.244209 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014534 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014534 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016241 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016241 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12810.948288 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12810.948288 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23951.617171 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23951.617171 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16076.217925 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16076.217925 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16742.913189 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16742.913189 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 20981.610334 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20981.610334 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 137785 # number of writebacks +system.cpu1.dcache.writebacks::total 137785 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 90105 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 90105 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375217 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 375217 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13775 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13775 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 465322 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 465322 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 465322 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 465322 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163803 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 163803 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104855 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 104855 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32523 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 32523 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5409 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5409 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23489 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23489 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 268658 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 268658 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 301181 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 301181 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2171865461 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2171865461 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2612489394 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2612489394 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 519825898 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 519825898 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 98469253 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 98469253 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 510672173 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 510672173 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 974500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 974500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4784354855 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4784354855 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5304180753 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5304180753 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 979094500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 979094500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848774501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848774501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827869001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827869001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033975 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033975 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025822 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025822 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.325941 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.325941 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050679 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050679 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227916 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227916 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030248 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030248 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033532 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033532 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13259.009060 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13259.009060 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24915.258157 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24915.258157 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15983.331734 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15983.331734 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18204.705676 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18204.705676 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21740.907361 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21740.907361 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17288.321492 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17288.321492 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17155.555475 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17155.555475 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17808.346876 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17808.346876 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17611.272799 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17611.272799 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2285,425 +2289,415 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 614958 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.494107 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 43363824 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 615470 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 70.456438 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 78768329500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.494107 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975574 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975574 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 667401 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.527528 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 9840970 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 667913 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 14.733910 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 78865217000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.527528 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973687 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973687 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 493 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 18 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 88611673 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 88611673 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 43363824 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 43363824 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 43363824 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 43363824 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 43363824 # number of overall hits -system.cpu1.icache.overall_hits::total 43363824 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 634277 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 634277 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 634277 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 634277 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 634277 # number of overall misses -system.cpu1.icache.overall_misses::total 634277 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5597748699 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5597748699 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5597748699 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5597748699 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5597748699 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5597748699 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 43998101 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 43998101 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 43998101 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 43998101 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 43998101 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 43998101 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014416 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014416 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014416 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014416 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014416 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014416 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8825.400730 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8825.400730 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8825.400730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8825.400730 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8825.400730 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 423261 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 12 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 39865 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 21731377 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21731377 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 9840970 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9840970 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9840970 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9840970 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9840970 # number of overall hits +system.cpu1.icache.overall_hits::total 9840970 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 690756 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 690756 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 690756 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 690756 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 690756 # number of overall misses +system.cpu1.icache.overall_misses::total 690756 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6328356335 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6328356335 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6328356335 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6328356335 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6328356335 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6328356335 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10531726 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10531726 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10531726 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10531726 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10531726 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10531726 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065588 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.065588 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065588 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.065588 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065588 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.065588 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9161.493110 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9161.493110 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9161.493110 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9161.493110 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9161.493110 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 590927 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 49303 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 10.617359 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 12 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.985620 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 18806 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 18806 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 18806 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 18806 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 18806 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 18806 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615471 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 615471 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 615471 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 615471 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 615471 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 615471 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4523939883 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4523939883 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4523939883 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4523939883 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4523939883 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4523939883 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8397000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8397000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8397000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013989 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.013989 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013989 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.013989 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7350.370502 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7350.370502 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7350.370502 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7350.370502 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22831 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 22831 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 22831 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 22831 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 22831 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 22831 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 667925 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 667925 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 667925 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 667925 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 667925 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 667925 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5443930957 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5443930957 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5443930957 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5443930957 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5443930957 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5443930957 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8774500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8774500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8774500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8774500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063420 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.063420 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063420 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.063420 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8150.512343 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 229039 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 229849 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 714 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 270002 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 271052 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 936 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59807 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 55576 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15296.446244 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 851759 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 70922 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 12.009799 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 67932 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 66588 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15581.068012 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 931760 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 81198 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.475159 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8246.965221 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 13.312576 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 3.835357 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3924.928701 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2437.613409 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 669.790981 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.503355 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000813 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000234 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.239559 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.148780 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.040881 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.933621 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 766 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14561 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 628 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 120 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 6676.895279 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 16.747734 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.010823 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4682.837977 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2664.181165 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.395034 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.407525 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001022 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.285818 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.162609 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093896 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.950993 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1283 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13300 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 13 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 906 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 364 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 646 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 10959 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2956 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.046753 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001160 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.888733 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 17259149 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 17259149 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 17267 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7675 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 597307 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 107002 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 729251 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 125175 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 125175 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1610 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1610 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1001 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1001 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 32136 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 32136 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 17267 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7675 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 597307 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 139138 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 761387 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 17267 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7675 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 597307 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 139138 # number of overall hits -system.cpu1.l2cache.overall_hits::total 761387 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 431 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 284 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 18163 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 70870 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 89748 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28235 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28235 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22667 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22667 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35014 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35014 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 431 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 284 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 18163 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 105884 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 124762 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 431 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 284 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 18163 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 105884 # number of overall misses -system.cpu1.l2cache.overall_misses::total 124762 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 8966500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5677500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 626896483 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1561730924 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 2203271407 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 530022874 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 530022874 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 442433542 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 442433542 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 404000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 404000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1382751233 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1382751233 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 8966500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5677500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 626896483 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2944482157 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3586022640 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 8966500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5677500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 626896483 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2944482157 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3586022640 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17698 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7959 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 615470 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 177872 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 818999 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 125175 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 125175 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29845 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29845 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23668 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23668 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 67150 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 67150 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 17698 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7959 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 615470 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 245022 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 886149 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 17698 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7959 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 615470 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 245022 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 886149 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.024353 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035683 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.029511 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.398433 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.109583 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.946055 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.946055 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.957707 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.957707 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.521430 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.521430 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024353 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035683 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.029511 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.432141 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.140791 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.024353 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035683 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.029511 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.432141 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.140791 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 20803.944316 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19991.197183 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34515.029621 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 22036.558826 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 24549.532101 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18771.838994 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18771.838994 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19518.839811 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19518.839811 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 404000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 404000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39491.381533 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39491.381533 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 20803.944316 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19991.197183 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34515.029621 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27808.565572 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 28742.907616 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 20803.944316 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19991.197183 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34515.029621 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27808.565572 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 28742.907616 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 471 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8616 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4213 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078308 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001648 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811768 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 18862163 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 18862163 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19502 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7394 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 645640 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 128208 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 800744 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 137784 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 137784 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2324 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2324 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1121 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1121 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38121 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 38121 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19502 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7394 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 645640 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 166329 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 838865 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19502 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7394 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 645640 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 166329 # number of overall hits +system.cpu1.l2cache.overall_hits::total 838865 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 440 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 275 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73501 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 96483 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29168 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29168 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22368 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22368 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35878 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 35878 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 440 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 275 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 22267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 109379 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 132361 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 440 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 275 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 22267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 109379 # number of overall misses +system.cpu1.l2cache.overall_misses::total 132361 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9737996 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5511500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 907046728 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1743519842 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 2665816066 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 555344240 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 555344240 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449490983 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449490983 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 955500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 955500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1553872219 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1553872219 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9737996 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5511500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 907046728 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3297392061 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4219688285 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9737996 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5511500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 907046728 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3297392061 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4219688285 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19942 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7669 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 667907 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201709 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 897227 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 137784 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 137784 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31492 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 31492 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23489 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23489 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73999 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 73999 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19942 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7669 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 667907 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 275708 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 971226 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19942 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7669 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 667907 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 275708 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 971226 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.035859 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.033338 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.364391 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.107535 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.926203 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.926203 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.952276 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.952276 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484844 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484844 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.035859 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.033338 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.396720 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.136282 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022064 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.035859 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.033338 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.396720 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.136282 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20041.818182 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 40735.021691 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23721.035659 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27629.904398 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19039.503566 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19039.503566 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20095.269269 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20095.269269 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43309.889598 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43309.889598 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20041.818182 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40735.021691 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 30146.482058 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31880.148118 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22131.809091 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20041.818182 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40735.021691 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 30146.482058 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31880.148118 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 235 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 23.666667 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 26.111111 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 33017 # number of writebacks -system.cpu1.l2cache.writebacks::total 33017 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 39082 # number of writebacks +system.cpu1.l2cache.writebacks::total 39082 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 83 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 925 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 925 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 18 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 149 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 181 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 867 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 867 # number of ReadExReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1008 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 1028 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 1016 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 1048 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1008 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 1028 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 430 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 271 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 18157 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 70787 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 89645 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 28351 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 28351 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28235 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28235 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22667 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22667 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34089 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34089 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 430 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 271 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 18157 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104876 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 123734 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 430 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 271 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 18157 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104876 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 28351 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 152085 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3621000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 498710017 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1063464434 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1571728951 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1791435833 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1791435833 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 410729057 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 410729057 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 308678233 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308678233 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 341000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 341000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1031751458 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1031751458 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3621000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 498710017 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2095215892 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2603480409 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 5933500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3621000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 498710017 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2095215892 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1791435833 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4394916242 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7547000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182265750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189812750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737917999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737917999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7547000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3920183749 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927730749 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.397966 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.109457 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 1016 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 1048 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 439 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 262 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22249 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 73352 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 96302 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 37405 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 37405 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29168 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29168 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22368 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22368 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35011 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 35011 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 439 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 262 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22249 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108363 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 131313 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 439 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 262 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22249 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108363 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 37405 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 168718 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3646000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 759958022 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1259838411 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 2030303933 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1619373742 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1619373742 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484903709 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484903709 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 334604857 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 334604857 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 832000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 832000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1217604967 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1217604967 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3646000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 759958022 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2477443378 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3247908900 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6861500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3646000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 759958022 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2477443378 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1619373742 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4867282642 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7975000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 934007000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 941982000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 811858998 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 811858998 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7975000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1745865998 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1753840998 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.363653 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.107333 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946055 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946055 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.957707 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.957707 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.507655 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.507655 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.139631 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.024297 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034050 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.029501 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.428027 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926203 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926203 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952276 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952276 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.473128 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.473128 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135203 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022014 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033312 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.171625 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15023.442638 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17532.812215 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 63187.747628 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14546.805631 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14546.805631 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13617.957074 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13617.957074 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 341000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 341000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30266.404353 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30266.404353 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21040.945973 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13798.837209 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13361.623616 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27466.542766 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19978.030169 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63187.747628 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28897.762712 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.173717 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 17175.242815 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21082.676715 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43292.975324 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16624.510045 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16624.510045 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.086955 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.086955 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34777.783182 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34777.783182 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24734.100203 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13916.030534 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22862.447311 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43292.975324 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28848.626951 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2713,70 +2707,68 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1181364 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 879041 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11863 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11863 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 125175 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 39550 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 75362 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41966 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86419 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 89279 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 71717 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1231143 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 850974 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17917 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 40354 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2140388 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 39391696 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 26549567 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 31836 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70792 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 66043891 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 585425 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1574316 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.319194 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.466164 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1243272 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 949021 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 4907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4907 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 137784 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 47376 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75841 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43101 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89718 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 96830 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 79934 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1336034 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 901614 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17159 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 43403 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2298210 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42747664 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29480945 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 79768 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 72339053 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 592219 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1674781 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.301785 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.459032 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1071804 68.08% 68.08% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 502512 31.92% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 1169358 69.82% 69.82% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 505423 30.18% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1574316 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 680504524 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1674781 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 730243456 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 81017999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87400998 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 924938756 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1002964345 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 418581676 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 454923751 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 10092231 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9604282 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 22735342 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 23499938 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31021 # Transaction distribution -system.iobus.trans_dist::ReadResp 31021 # Transaction distribution -system.iobus.trans_dist::WriteReq 59439 # Transaction distribution -system.iobus.trans_dist::WriteResp 23215 # Transaction distribution +system.iobus.trans_dist::ReadReq 31011 # Transaction distribution +system.iobus.trans_dist::ReadResp 31011 # Transaction distribution +system.iobus.trans_dist::WriteReq 59421 # Transaction distribution +system.iobus.trans_dist::WriteResp 23197 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2792,16 +2784,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180920 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71598 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180864 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 448 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2817,11 +2809,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162793 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484096 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40134000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484041 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40089000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2831,7 +2823,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 505000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2861,23 +2853,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347085145 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198996708 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84753000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36840554 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36791507 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.558041 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.446927 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254609644000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.558041 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909878 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909878 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 254830116000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.446927 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.902933 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.902933 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2891,14 +2883,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31425377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31425377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9633411214 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9633411214 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31425377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31425377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31425377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31425377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32290377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32290377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6656632824 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6656632824 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32290377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32290377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32290377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32290377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -2915,19 +2907,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124703.876984 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124703.876984 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265940.018054 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265940.018054 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124703.876984 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124703.876984 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124703.876984 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56535 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128136.416667 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128136.416667 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183763.052783 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183763.052783 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128136.416667 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128136.416667 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128136.416667 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 23055 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7211 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3532 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.840105 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.527463 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2941,14 +2933,14 @@ system.iocache.demand_mshr_misses::realview.ide 252 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18320377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18320377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7749655322 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7749655322 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18320377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18320377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18320377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18320377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19155377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19155377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772970838 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772970838 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19155377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19155377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19155377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19155377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2957,521 +2949,518 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72699.908730 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72699.908730 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213937.039587 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213937.039587 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72699.908730 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72699.908730 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76013.400794 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76013.400794 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131762.666685 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131762.666685 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76013.400794 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76013.400794 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 131156 # number of replacements -system.l2c.tags.tagsinuse 63989.320892 # Cycle average of tags in use -system.l2c.tags.total_refs 352673 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195503 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.803926 # Average number of references to valid blocks. +system.l2c.tags.replacements 136223 # number of replacements +system.l2c.tags.tagsinuse 64041.513044 # Cycle average of tags in use +system.l2c.tags.total_refs 356136 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200557 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.775735 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 11841.549695 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.064672 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.035376 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7520.794001 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2869.625937 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 37329.338161 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.624339 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1925.336025 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 701.530072 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1779.513002 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.180688 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000215 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.114758 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043787 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.569600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000071 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12781.567033 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 15.527645 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.082100 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5930.123644 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1752.659752 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33401.860992 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.992291 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903251 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3387.143441 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1822.858320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4939.794575 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.195031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000237 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000017 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.090487 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.026743 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.509672 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000122 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029378 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010704 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027153 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976400 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31812 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32516 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6391 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25201 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.051684 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.027815 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.075375 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977196 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 31391 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32916 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 116 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6119 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 25156 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 25 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 410 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6149 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 25933 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.485413 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.496155 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5013444 # Number of tag accesses -system.l2c.tags.data_accesses 5013444 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 174 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 66 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 34010 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 46649 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 75 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 15163 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 9968 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4879 # number of ReadReq hits -system.l2c.ReadReq_hits::total 156615 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 227099 # number of Writeback hits -system.l2c.Writeback_hits::total 227099 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2891 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 673 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3564 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 168 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 175 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 343 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3845 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1635 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5480 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 174 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 66 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 34010 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 50494 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 75 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 15163 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11603 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 4879 # number of demand (read+write) hits -system.l2c.demand_hits::total 162095 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 174 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 66 # number of overall hits -system.l2c.overall_hits::cpu0.inst 34010 # number of overall hits -system.l2c.overall_hits::cpu0.data 50494 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45581 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 75 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits -system.l2c.overall_hits::cpu1.inst 15163 # number of overall hits -system.l2c.overall_hits::cpu1.data 11603 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 4879 # number of overall hits -system.l2c.overall_hits::total 162095 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 25 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 19495 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 9130 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 128336 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 5 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 474 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4913 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27508 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.478989 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.502258 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5099427 # Number of tag accesses +system.l2c.tags.data_accesses 5099427 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 187 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 89 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 32294 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 45191 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 42802 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 60 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 34 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 17148 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11819 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7598 # number of ReadReq hits +system.l2c.ReadReq_hits::total 157222 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 232253 # number of Writeback hits +system.l2c.Writeback_hits::total 232253 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2477 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 788 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3265 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 249 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 61 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 310 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3656 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1776 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5432 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 187 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 32294 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 48847 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 42802 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 60 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 34 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 17148 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13595 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 7598 # number of demand (read+write) hits +system.l2c.demand_hits::total 162654 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 187 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits +system.l2c.overall_hits::cpu0.inst 32294 # number of overall hits +system.l2c.overall_hits::cpu0.data 48847 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 42802 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 60 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 34 # number of overall hits +system.l2c.overall_hits::cpu1.inst 17148 # number of overall hits +system.l2c.overall_hits::cpu1.data 13595 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 7598 # number of overall hits +system.l2c.overall_hits::total 162654 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 28 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 17722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8264 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130446 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2993 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1306 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 10708 # number of ReadReq misses -system.l2c.ReadReq_misses::total 172002 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8592 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2954 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11546 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 671 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1237 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1908 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11187 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8302 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19489 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 19495 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20317 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 128336 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 5 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu1.inst 5101 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2487 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 10677 # number of ReadReq misses +system.l2c.ReadReq_misses::total 174741 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8406 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3815 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12221 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 945 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1142 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2087 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11293 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9270 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 20563 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 28 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17722 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19557 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 130446 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2993 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9608 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 10708 # number of demand (read+write) misses -system.l2c.demand_misses::total 191491 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 19495 # number of overall misses -system.l2c.overall_misses::cpu0.data 20317 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 128336 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 5 # number of overall misses +system.l2c.demand_misses::cpu1.inst 5101 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 11757 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 10677 # number of demand (read+write) misses +system.l2c.demand_misses::total 195304 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 28 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17722 # number of overall misses +system.l2c.overall_misses::cpu0.data 19557 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 130446 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2993 # number of overall misses -system.l2c.overall_misses::cpu1.data 9608 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 10708 # number of overall misses -system.l2c.overall_misses::total 191491 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2355750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 238250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1465167233 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 772533245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14046141125 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 402500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 234350497 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 111853999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1655983955 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18289101054 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 5093287 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2228405 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 7321692 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 941966 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 816465 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1758431 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 983356186 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 627855471 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1611211657 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2355750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 238250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1465167233 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1755889431 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14046141125 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 402500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 234350497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 739709470 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1655983955 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 19900312711 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2355750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 238250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1465167233 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1755889431 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14046141125 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 402500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 234350497 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 739709470 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1655983955 # number of overall miss cycles -system.l2c.overall_miss_latency::total 19900312711 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 199 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 69 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 53505 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 55779 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 173917 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 80 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 51 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 18156 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11274 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 15587 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 328617 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 227099 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 227099 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 11483 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3627 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 15110 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 839 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1412 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2251 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15032 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 9937 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24969 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 199 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 69 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 53505 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 70811 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173917 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 80 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 51 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 18156 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 21211 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 15587 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 353586 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 199 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 69 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 53505 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 70811 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173917 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 80 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 51 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 18156 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 21211 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 15587 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 353586 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.125628 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.043478 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.364358 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.163682 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.737915 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019608 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.164849 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.115842 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.686983 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.523412 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.748237 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.814447 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.764130 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.799762 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.876062 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.847623 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.744212 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.835463 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.780528 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.125628 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.043478 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.364358 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.286919 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.737915 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.164849 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.452973 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.686983 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.541568 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.125628 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.043478 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.364358 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.286919 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.737915 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.062500 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.164849 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.452973 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.686983 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.541568 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 94230 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79416.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75156.051962 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 84614.813253 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 109448.176077 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78299.531240 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 85646.247320 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 154649.230015 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 106330.746468 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 592.794111 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 754.368653 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 634.132340 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1403.824143 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 660.036378 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 921.609539 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87901.688210 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75627.014093 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 82672.874801 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 94230 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79416.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 75156.051962 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 86424.640990 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 109448.176077 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 78299.531240 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 76988.912365 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 154649.230015 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 103922.966150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 94230 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79416.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 75156.051962 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 86424.640990 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 109448.176077 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78299.531240 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 76988.912365 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 154649.230015 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 103922.966150 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.overall_misses::cpu1.inst 5101 # number of overall misses +system.l2c.overall_misses::cpu1.data 11757 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 10677 # number of overall misses +system.l2c.overall_misses::total 195304 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2541750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 428750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1457831781 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 749814704 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 937500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 83000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 434889757 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 222071664 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 18802084724 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 7178272 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2845410 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 10023682 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1135970 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 748476 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1884446 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1078166540 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 778316723 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1856483263 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2541750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 428750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1457831781 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1827981244 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 937500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 83000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 434889757 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1000388387 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20658567987 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2541750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 428750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1457831781 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1827981244 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14466749329 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 937500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 83000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 434889757 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1000388387 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1466736489 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20658567987 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 215 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 94 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 50016 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 53455 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 173248 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 70 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 35 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 22249 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 14306 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 18275 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 331963 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 232253 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 232253 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10883 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4603 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 15486 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1194 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1203 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2397 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 14949 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 11046 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25995 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 215 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 94 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 50016 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 68404 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173248 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 70 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 35 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 22249 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25352 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 18275 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 357958 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 215 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 94 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 50016 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 68404 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173248 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 70 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 35 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 22249 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25352 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 18275 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 357958 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.053191 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.354327 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.154597 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.028571 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.229269 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.173843 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.526387 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.772397 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.828807 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.789164 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.791457 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.949293 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.870672 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.755435 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.839218 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.791037 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.053191 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.354327 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.285904 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.028571 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.229269 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.463750 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.545606 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.130233 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.053191 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.354327 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.285904 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.752944 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.142857 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.028571 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.229269 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.463750 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.584241 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.545606 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82261.131983 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 90732.660213 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 93750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 83000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85255.784552 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 89292.989144 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 107599.731740 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 853.946229 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 745.847969 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 820.201457 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1202.084656 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 655.408056 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 902.944897 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 95472.110157 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83960.811543 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90282.705004 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82261.131983 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 93469.409623 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 93750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 85255.784552 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 85088.746024 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 105776.471485 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90776.785714 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82261.131983 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 93469.409623 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110902.207266 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 93750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 83000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 85255.784552 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 85088.746024 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 137373.465299 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 105776.471485 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 1085 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 10 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 108.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 99563 # number of writebacks -system.l2c.writebacks::total 99563 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 9 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 19493 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 9129 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 128336 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 5 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 103197 # number of writebacks +system.l2c.writebacks::total 103197 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 16 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 12 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 16 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 16 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 28 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 28 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 17706 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8264 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2987 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1306 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 10708 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 171993 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8592 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2954 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11546 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 671 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1237 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1908 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11187 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8302 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19489 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 19493 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20316 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128336 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 5 # number of demand (read+write) MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 5089 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 2487 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 174713 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8406 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3815 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12221 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 945 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1142 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 2087 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11293 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9270 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 20563 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 28 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17706 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19557 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2987 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9608 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10708 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 191482 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 19493 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20316 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128336 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 5 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 5089 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 11757 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 195276 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 28 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17706 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19557 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130446 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2987 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9608 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10708 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 191482 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2044750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 201250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1220263233 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 659205995 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12472170125 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 340000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 196513747 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 95618499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1525698955 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 16172119054 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 86672539 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 29737438 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 116409977 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6840149 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12430724 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 19270873 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 844195812 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 523093527 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1367289339 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2044750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 201250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1220263233 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1503401807 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12472170125 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 340000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 196513747 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 618712026 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1525698955 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17539408393 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2044750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 201250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1220263233 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1503401807 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12472170125 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 340000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 196513747 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 618712026 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1525698955 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17539408393 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 158845000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3685006498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5557500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1920304250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5769713248 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2711627000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1536025000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4247652000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 158845000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6396633498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5557500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3456329250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10017365248 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163664 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.115842 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.523384 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.748237 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.814447 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.764130 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.799762 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.876062 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.847623 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.744212 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.835463 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.780528 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.286905 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.452973 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.541543 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.125628 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.043478 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.364321 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.286905 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737915 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.062500 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.164519 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.452973 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.686983 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.541543 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 72210.099135 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 73214.777182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 94027.774700 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10087.586010 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10066.837508 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10082.277585 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10193.962742 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10049.089733 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10100.038260 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75462.216144 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63008.133823 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 70156.977731 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 74000.876501 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 64395.506453 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 91598.209717 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 81790 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67083.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62600.073514 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 74000.876501 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 97183.721832 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65789.670907 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 64395.506453 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 142482.158666 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 91598.209717 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu1.inst 5089 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 11757 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10677 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 195276 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 365750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1235097219 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 646670292 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 812500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 70500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 370572993 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 190918836 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 16645401734 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 149850873 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 67813301 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 217664174 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16896440 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20270643 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 37167083 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 939052460 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 662623777 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1601676237 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 365750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1235097219 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1585722752 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 812500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 70500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 370572993 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 853542613 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 18247077971 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2189250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 365750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1235097219 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1585722752 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12862638093 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 812500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 70500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 370572993 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 853542613 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1336066301 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 18247077971 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 181479250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4804405000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5954500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 824214500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5816053250 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3576332065 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 720875502 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4297207567 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 181479250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8380737065 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5954500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1545090002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10113260817 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.154597 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.173843 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.526303 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.772397 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.828807 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.789164 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.791457 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.949293 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.870672 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.755435 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.839218 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.791037 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.545528 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.130233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.053191 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354007 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.285904 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.752944 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.142857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.028571 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.228729 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.463750 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.584241 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.545528 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78251.487415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76766.721351 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 95272.828776 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17826.656317 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17775.439318 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17810.668030 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17879.830688 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17750.125219 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17808.856253 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83153.498627 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71480.450593 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 77891.175266 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78187.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 73150 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69755.857845 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81082.106254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98605.078676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 81250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72818.430536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 72598.674237 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125134.991196 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 93442.501746 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3486,57 +3475,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 210212 # Transaction distribution -system.membus.trans_dist::ReadResp 210211 # Transaction distribution -system.membus.trans_dist::WriteReq 30942 # Transaction distribution -system.membus.trans_dist::WriteResp 30942 # Transaction distribution -system.membus.trans_dist::Writeback 135769 # Transaction distribution +system.membus.trans_dist::ReadReq 213069 # Transaction distribution +system.membus.trans_dist::ReadResp 213068 # Transaction distribution +system.membus.trans_dist::WriteReq 31079 # Transaction distribution +system.membus.trans_dist::WriteResp 31079 # Transaction distribution +system.membus.trans_dist::Writeback 139403 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76140 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40614 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13546 # Transaction distribution -system.membus.trans_dist::ReadExReq 39344 # Transaction distribution -system.membus.trans_dist::ReadExResp 19397 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107968 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 77234 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41651 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14409 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.membus.trans_dist::ReadExReq 40484 # Transaction distribution +system.membus.trans_dist::ReadExResp 20462 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13598 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 770072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14202 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 662750 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 784904 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 878993 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 893825 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27196 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18669148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18859512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19143964 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19335481 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23495992 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123727 # Total snoops (count) -system.membus.snoop_fanout::samples 500337 # Request fanout histogram +system.membus.pkt_size::total 23971961 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125081 # Total snoops (count) +system.membus.snoop_fanout::samples 510035 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 500337 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 510035 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 500337 # Request fanout histogram -system.membus.reqLayer0.occupancy 81279500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 510035 # Request fanout histogram +system.membus.reqLayer0.occupancy 81680000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 26000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 28500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11516000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11944988 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1822464250 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1904793274 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38546446 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1164089698 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1154561869 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37506493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3569,48 +3559,48 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 489006 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 488990 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30942 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30942 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 227099 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79612 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40957 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 120569 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 20 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 20 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50358 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50358 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1016462 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 341372 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1357834 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31696041 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5742799 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37438840 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 287500 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 885309 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.041201 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.198756 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 494432 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 494416 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31079 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31079 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 232253 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80398 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41961 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 122359 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50963 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50963 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1036150 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339974 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1376124 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31294456 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6755201 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38049657 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 290334 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 898197 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.040648 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.197474 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 848833 95.88% 95.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36476 4.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 861687 95.94% 95.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36510 4.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 885309 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1431615961 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1066500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 898197 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 772973190 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1714942226 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 674969400 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 636594669 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 265283017 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1858 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 2070 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2748 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index 8914a4f8a..e4b623d06 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827025 # Number of seconds simulated -sim_ticks 2827025397500 # Number of ticks simulated -final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827616 # Number of seconds simulated +sim_ticks 2827616186000 # Number of ticks simulated +final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 96738 # Simulator instruction rate (inst/s) -host_op_rate 117339 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2415768223 # Simulator tick rate (ticks/s) -host_mem_usage 619580 # Number of bytes of host memory used -host_seconds 1170.24 # Real time elapsed on the host -sim_insts 113206948 # Number of instructions simulated -sim_ops 137314363 # Number of ops (including micro ops) simulated +host_inst_rate 99248 # Simulator instruction rate (inst/s) +host_op_rate 120386 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2480177298 # Simulator tick rate (ticks/s) +host_mem_usage 619560 # Number of bytes of host memory used +host_seconds 1140.09 # Real time elapsed on the host +sim_insts 113151083 # Number of instructions simulated +sim_ops 137250963 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory +system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171932 # Number of read requests accepted -system.physmem.writeReqs 167449 # Number of write requests accepted -system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11320 # Per bank write bursts -system.physmem.perBankRdBursts::1 10283 # Per bank write bursts -system.physmem.perBankRdBursts::2 11137 # Per bank write bursts -system.physmem.perBankRdBursts::3 11363 # Per bank write bursts -system.physmem.perBankRdBursts::4 13028 # Per bank write bursts -system.physmem.perBankRdBursts::5 10237 # Per bank write bursts -system.physmem.perBankRdBursts::6 10954 # Per bank write bursts -system.physmem.perBankRdBursts::7 11381 # Per bank write bursts -system.physmem.perBankRdBursts::8 10407 # Per bank write bursts -system.physmem.perBankRdBursts::9 11232 # Per bank write bursts -system.physmem.perBankRdBursts::10 10729 # Per bank write bursts -system.physmem.perBankRdBursts::11 9386 # Per bank write bursts -system.physmem.perBankRdBursts::12 9853 # Per bank write bursts -system.physmem.perBankRdBursts::13 10909 # Per bank write bursts -system.physmem.perBankRdBursts::14 9951 # Per bank write bursts -system.physmem.perBankRdBursts::15 9636 # Per bank write bursts -system.physmem.perBankWrBursts::0 10810 # Per bank write bursts -system.physmem.perBankWrBursts::1 10132 # Per bank write bursts -system.physmem.perBankWrBursts::2 10502 # Per bank write bursts -system.physmem.perBankWrBursts::3 10558 # Per bank write bursts -system.physmem.perBankWrBursts::4 9654 # Per bank write bursts -system.physmem.perBankWrBursts::5 9978 # Per bank write bursts -system.physmem.perBankWrBursts::6 10358 # Per bank write bursts -system.physmem.perBankWrBursts::7 10535 # Per bank write bursts -system.physmem.perBankWrBursts::8 10309 # Per bank write bursts -system.physmem.perBankWrBursts::9 10935 # Per bank write bursts -system.physmem.perBankWrBursts::10 10009 # Per bank write bursts -system.physmem.perBankWrBursts::11 9154 # Per bank write bursts -system.physmem.perBankWrBursts::12 9556 # Per bank write bursts -system.physmem.perBankWrBursts::13 10555 # Per bank write bursts -system.physmem.perBankWrBursts::14 9521 # Per bank write bursts -system.physmem.perBankWrBursts::15 9009 # Per bank write bursts +system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176173 # Number of read requests accepted +system.physmem.writeReqs 171661 # Number of write requests accepted +system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11334 # Per bank write bursts +system.physmem.perBankRdBursts::1 10890 # Per bank write bursts +system.physmem.perBankRdBursts::2 10732 # Per bank write bursts +system.physmem.perBankRdBursts::3 10393 # Per bank write bursts +system.physmem.perBankRdBursts::4 14045 # Per bank write bursts +system.physmem.perBankRdBursts::5 11531 # Per bank write bursts +system.physmem.perBankRdBursts::6 11498 # Per bank write bursts +system.physmem.perBankRdBursts::7 11674 # Per bank write bursts +system.physmem.perBankRdBursts::8 10645 # Per bank write bursts +system.physmem.perBankRdBursts::9 10993 # Per bank write bursts +system.physmem.perBankRdBursts::10 10307 # Per bank write bursts +system.physmem.perBankRdBursts::11 9597 # Per bank write bursts +system.physmem.perBankRdBursts::12 9956 # Per bank write bursts +system.physmem.perBankRdBursts::13 10908 # Per bank write bursts +system.physmem.perBankRdBursts::14 10689 # Per bank write bursts +system.physmem.perBankRdBursts::15 10844 # Per bank write bursts +system.physmem.perBankWrBursts::0 9257 # Per bank write bursts +system.physmem.perBankWrBursts::1 9346 # Per bank write bursts +system.physmem.perBankWrBursts::2 9336 # Per bank write bursts +system.physmem.perBankWrBursts::3 8962 # Per bank write bursts +system.physmem.perBankWrBursts::4 9705 # Per bank write bursts +system.physmem.perBankWrBursts::5 9746 # Per bank write bursts +system.physmem.perBankWrBursts::6 9125 # Per bank write bursts +system.physmem.perBankWrBursts::7 9630 # Per bank write bursts +system.physmem.perBankWrBursts::8 9307 # Per bank write bursts +system.physmem.perBankWrBursts::9 9634 # Per bank write bursts +system.physmem.perBankWrBursts::10 8942 # Per bank write bursts +system.physmem.perBankWrBursts::11 8449 # Per bank write bursts +system.physmem.perBankWrBursts::12 8881 # Per bank write bursts +system.physmem.perBankWrBursts::13 9361 # Per bank write bursts +system.physmem.perBankWrBursts::14 9018 # Per bank write bursts +system.physmem.perBankWrBursts::15 9072 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2827025186500 # Total gap between requests +system.physmem.numWrRetry 58 # Number of times write queue was full causing retry +system.physmem.totGap 2827615975000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2993 # Read request sizes (log2) +system.physmem.readPktSize::4 2994 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168384 # Read request sizes (log2) +system.physmem.readPktSize::6 172624 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 163068 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167280 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,175 +159,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads -system.physmem.totQLat 2011805750 # Total ticks spent queuing -system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads +system.physmem.totQLat 2104910750 # Total ticks spent queuing +system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing -system.physmem.readRowHits 141825 # Number of row buffer hits during reads -system.physmem.writeRowHits 127038 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes -system.physmem.avgGap 8329945.36 # Average gap between requests -system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.379373 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states -system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing +system.physmem.readRowHits 145058 # Number of row buffer hits during reads +system.physmem.writeRowHits 112529 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes +system.physmem.avgGap 8129210.99 # Average gap between requests +system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.422846 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states +system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.289511 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states -system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.324331 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states +system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -347,15 +333,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46965884 # Number of BP lookups -system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits +system.cpu.branchPred.lookups 46937284 # Number of BP lookups +system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -386,81 +372,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 69937 # Table walker walks requested -system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 72371 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25472400 # DTB read hits -system.cpu.dtb.read_misses 60528 # DTB read misses -system.cpu.dtb.write_hits 19920178 # DTB write hits -system.cpu.dtb.write_misses 9409 # DTB write misses +system.cpu.dtb.read_hits 25461870 # DTB read hits +system.cpu.dtb.read_misses 62291 # DTB read misses +system.cpu.dtb.write_hits 19915387 # DTB write hits +system.cpu.dtb.write_misses 10080 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25532928 # DTB read accesses -system.cpu.dtb.write_accesses 19929587 # DTB write accesses +system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25524161 # DTB read accesses +system.cpu.dtb.write_accesses 19925467 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45392578 # DTB hits -system.cpu.dtb.misses 69937 # DTB misses -system.cpu.dtb.accesses 45462515 # DTB accesses +system.cpu.dtb.hits 45377257 # DTB hits +system.cpu.dtb.misses 72371 # DTB misses +system.cpu.dtb.accesses 45449628 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -490,55 +479,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11957 # Table walker walks requested -system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 11974 # Table walker walks requested +system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66242388 # ITB inst hits -system.cpu.itb.inst_misses 11957 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66270436 # ITB inst hits +system.cpu.itb.inst_misses 11974 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -547,98 +537,98 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66254345 # ITB inst accesses -system.cpu.itb.hits 66242388 # DTB hits -system.cpu.itb.misses 11957 # DTB misses -system.cpu.itb.accesses 66254345 # DTB accesses -system.cpu.numCycles 260505842 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66282410 # ITB inst accesses +system.cpu.itb.hits 66270436 # DTB hits +system.cpu.itb.misses 11974 # DTB misses +system.cpu.itb.accesses 66282410 # DTB accesses +system.cpu.numCycles 263104506 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6274201 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -646,44 +636,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -707,101 +697,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued -system.cpu.iq.rate 0.550386 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued +system.cpu.iq.rate 0.544758 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151939321 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13215 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200965 # number of nop insts executed -system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed -system.cpu.iew.exec_branches 26544582 # Number of branches executed -system.cpu.iew.exec_stores 20883032 # Number of stores executed -system.cpu.iew.exec_rate 0.546767 # Inst execution rate -system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63301991 # num instructions producing a value -system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value +system.cpu.iew.exec_nop 201053 # number of nop insts executed +system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed +system.cpu.iew.exec_branches 26530134 # Number of branches executed +system.cpu.iew.exec_stores 20877849 # Number of stores executed +system.cpu.iew.exec_rate 0.541163 # Inst execution rate +system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63271750 # num instructions producing a value +system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back +system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113361853 # Number of instructions committed -system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113305988 # Number of instructions committed +system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45532382 # Number of memory references committed -system.cpu.commit.loads 24928817 # Number of loads committed -system.cpu.commit.membars 814713 # Number of memory barriers committed -system.cpu.commit.branches 26060941 # Number of branches committed +system.cpu.commit.refs 45511652 # Number of memory references committed +system.cpu.commit.loads 24916104 # Number of loads committed +system.cpu.commit.membars 814017 # Number of memory barriers committed +system.cpu.commit.branches 26045610 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120284813 # Number of committed integer instructions. -system.cpu.commit.function_calls 4896517 # Number of function calls committed. +system.cpu.commit.int_insts 120229462 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892502 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -825,214 +815,214 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction -system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction +system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373323554 # The number of ROB reads -system.cpu.rob.rob_writes 293054802 # The number of ROB writes -system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113206948 # Number of Instructions Simulated -system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155872747 # number of integer regfile reads -system.cpu.int_regfile_writes 88664446 # number of integer regfile writes -system.cpu.fp_regfile_reads 9607 # number of floating regfile reads +system.cpu.rob.rob_reads 375672050 # The number of ROB reads +system.cpu.rob.rob_writes 292972268 # The number of ROB writes +system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113151083 # Number of Instructions Simulated +system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads +system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155826637 # number of integer regfile reads +system.cpu.int_regfile_writes 88633021 # number of integer regfile writes +system.cpu.fp_regfile_reads 9606 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503168366 # number of cc regfile reads -system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes -system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837844 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads +system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes +system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads +system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes +system.cpu.dcache.tags.replacements 839617 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15587007 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 346674 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 346674 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441974 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441974 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460321 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460321 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38917554 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38917554 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39264228 # number of overall hits -system.cpu.dcache.overall_hits::total 39264228 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 700623 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 700623 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3575875 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3575875 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177079 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177079 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26763 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26763 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4276498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4276498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4453577 # number of overall misses -system.cpu.dcache.overall_misses::total 4453577 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9909110648 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9909110648 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 134775393563 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 134775393563 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 355748499 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 355748499 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 176500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 176500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 144684504211 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 144684504211 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 144684504211 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 144684504211 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24031170 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24031170 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19162882 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19162882 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523753 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523753 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468737 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468737 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460325 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460325 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43194052 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43194052 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43717805 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43717805 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029155 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029155 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186604 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.186604 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338096 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.338096 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057096 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057096 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099007 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099007 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101871 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 44125 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 44125 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33832.473255 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32487.257818 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 491325 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15561026 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 345829 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 345829 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441066 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441066 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 459481 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 459481 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38877113 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38877113 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39222942 # number of overall hits +system.cpu.dcache.overall_hits::total 39222942 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 705718 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 705718 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3595150 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3595150 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177438 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177438 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26862 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26862 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses +system.cpu.dcache.overall_misses::total 4478306 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 459486 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 459486 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43177981 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43177981 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43701248 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43701248 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029378 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029378 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.187676 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.187676 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339096 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339096 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057406 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057406 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6982 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 70.370238 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 695426 # number of writebacks -system.cpu.dcache.writebacks::total 695426 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286545 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 286545 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3276416 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3276416 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18452 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18452 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3562961 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3562961 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3562961 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3562961 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414078 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414078 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299459 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299459 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119308 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119308 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8311 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 713537 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 713537 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 832845 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 832845 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5351526415 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5351526415 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11825722463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11825722463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1475435001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1475435001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109426500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109426500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17177248878 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17177248878 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18652683879 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227794 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227794 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017731 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017731 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016519 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016519 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019050 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019050 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42125 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks +system.cpu.dcache.writebacks::total 696320 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18482 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18482 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3585952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3585952 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3585952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3585952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300275 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300275 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119609 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119609 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1040,265 +1030,265 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1894041 # number of replacements -system.cpu.icache.tags.tagsinuse 511.373863 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64258114 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1894553 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.917296 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.373863 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1892540 # number of replacements +system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998723 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998723 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68134254 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68134254 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64258114 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64258114 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64258114 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64258114 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64258114 # number of overall hits -system.cpu.icache.overall_hits::total 64258114 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1981572 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1981572 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1981572 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1981572 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1981572 # number of overall misses -system.cpu.icache.overall_misses::total 1981572 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26765848354 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26765848354 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26765848354 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26765848354 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26765848354 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26765848354 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66239686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66239686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66239686 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66239686 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66239686 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66239686 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029915 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029915 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029915 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029915 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029915 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029915 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13507.381187 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13507.381187 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13507.381187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13507.381187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13507.381187 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2017 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68160699 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68160699 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64285030 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64285030 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64285030 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64285030 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64285030 # number of overall hits +system.cpu.icache.overall_hits::total 64285030 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1982600 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1982600 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1982600 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1982600 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1982600 # number of overall misses +system.cpu.icache.overall_misses::total 1982600 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26922947970 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26922947970 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26922947970 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26922947970 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26922947970 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26922947970 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66267630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66267630 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66267630 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66267630 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66267630 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66267630 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029918 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029918 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029918 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029918 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029918 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029918 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13579.616650 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13579.616650 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2392 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 103 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.582524 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.136000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87002 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 87002 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 87002 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 87002 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 87002 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 87002 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1894570 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1894570 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1894570 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1894570 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1894570 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22163460869 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22163460869 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22163460869 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22163460869 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22163460869 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22163460869 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 202549500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 202549500 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 202549500 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 202549500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028602 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028602 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028602 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.412235 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11698.412235 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.412235 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11698.412235 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89529 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 89529 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 89529 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 89529 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028567 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98730 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65075.133005 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3019277 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 163872 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 18.424606 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 103160 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49633.609196 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.158546 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.798547 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10197.951777 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5229.614939 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.757349 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000170 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155608 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.079798 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992968 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65129 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2965 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6995 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54988 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000198 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.993790 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28438035 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28438035 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53702 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 11727 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1874573 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 527970 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2467972 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 695426 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 695426 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 32 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 32 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 2 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 159827 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 159827 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 53702 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 11727 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1874573 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 687797 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2627799 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 53702 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 11727 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1874573 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 687797 # number of overall hits -system.cpu.l2cache.overall_hits::total 2627799 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 20 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.153913 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.087223 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992906 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6837 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55246 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 28477722 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 28477722 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56030 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12587 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1873051 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 528182 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2469850 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 696320 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 696320 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 157101 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 157101 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 56030 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 12587 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1873051 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 685283 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2626951 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 56030 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 12587 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1873051 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 685283 # number of overall hits +system.cpu.l2cache.overall_hits::total 2626951 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 19971 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 13600 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33598 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2743 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2743 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 19985 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 14326 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 34339 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2720 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2720 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 136984 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 136984 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 20 # number of demand (read+write) misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 140540 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 140540 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19971 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 150584 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 170582 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 20 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 19985 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 154866 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 174879 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19971 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 150584 # number of overall misses -system.cpu.l2cache.overall_misses::total 170582 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1944750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 536750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1503081000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1083875750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2589438250 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 580975 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 580975 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9863483701 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9863483701 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1944750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 536750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1503081000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10947359451 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12452921951 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1944750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 536750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1503081000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10947359451 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12452921951 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 53722 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 11734 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1894544 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 541570 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2501570 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 695426 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 695426 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2775 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2775 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296811 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296811 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 53722 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 11734 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1894544 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 838381 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2798381 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 53722 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 11734 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1894544 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 838381 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2798381 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000372 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000597 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010541 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025112 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013431 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988468 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988468 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.461519 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.461519 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000372 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000597 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010541 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.179613 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.060957 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000372 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000597 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010541 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.179613 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.060957 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 97237.500000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 76678.571429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75263.181613 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79696.746324 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77071.202155 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 211.802771 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 211.802771 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72004.640695 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72004.640695 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 97237.500000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 76678.571429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75263.181613 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72699.353524 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73002.555668 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 97237.500000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 76678.571429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75263.181613 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72699.353524 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73002.555668 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 19985 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 154866 # number of overall misses +system.cpu.l2cache.overall_misses::total 174879 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1759750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197750141 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11197750141 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12425243891 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14065656141 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12425243891 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14065656141 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 542508 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2504189 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 696320 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 696320 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 297641 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 297641 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56051 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 12594 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1893036 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 840149 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2801830 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56051 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 12594 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1893036 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 840149 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2801830 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010557 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026407 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013713 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986938 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986938 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.472180 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.472180 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010557 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.184332 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062416 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010557 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.184332 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062416 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83797.619048 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 112821.428571 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81954.603453 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85682.936619 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83517.458284 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.605529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.605529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80430.790095 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.225866 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80430.790095 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1307,109 +1297,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 90654 # number of writebacks -system.cpu.l2cache.writebacks::total 90654 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 94866 # number of writebacks +system.cpu.l2cache.writebacks::total 94866 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 134 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 134 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 137 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 20 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 134 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19946 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 13488 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 33461 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2743 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2743 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19963 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14214 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 34205 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2720 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2720 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 136984 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 136984 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 20 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140540 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 140540 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19946 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 150472 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 170445 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 20 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19946 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 150472 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 170445 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1696750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 451250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1250973750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 908888250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2162010000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27698243 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27698243 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8149358299 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8149358299 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1696750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 451250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1250973750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9058246549 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10311368299 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1696750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 451250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1250973750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9058246549 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10311368299 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 157876500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5387443500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545320000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4107345000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107345000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 157876500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9494788500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652665000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.024905 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013376 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.988468 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.988468 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.461519 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.461519 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.060908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000372 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000597 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010528 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.179479 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.060908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62718.026171 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67384.953292 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64612.832850 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10097.791834 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10097.791834 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59491.315037 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59491.315037 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 84837.500000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62718.026171 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60198.884503 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60496.748505 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1419,61 +1409,59 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6450497 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98357729 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 219918257 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 65703 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3562118 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.010231 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 62589 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010244 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3525674 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36444 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3526784 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36501 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1494,11 +1482,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1519,11 +1507,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1563,52 +1551,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 327996 # Number of tag accesses -system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses -system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.tags.tag_accesses 328113 # Number of tag accesses +system.iocache.tags.data_accesses 328113 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses +system.iocache.ReadReq_misses::total 233 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses -system.iocache.demand_misses::total 220 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 220 # number of overall misses -system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses +system.iocache.demand_misses::total 233 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 233 # number of overall misses +system.iocache.overall_misses::total 233 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1617,40 +1605,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1659,66 +1647,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67820 # Transaction distribution -system.membus.trans_dist::ReadResp 67819 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 126844 # Transaction distribution +system.membus.trans_dist::ReadReq 68566 # Transaction distribution +system.membus.trans_dist::ReadResp 68565 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::Writeback 131056 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution -system.membus.trans_dist::ReadExReq 135185 # Transaction distribution -system.membus.trans_dist::ReadExResp 135185 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution +system.membus.trans_dist::ReadExReq 138681 # Transaction distribution +system.membus.trans_dist::ReadExResp 138681 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 484 # Total snoops (count) -system.membus.snoop_fanout::samples 336478 # Request fanout histogram +system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 497 # Total snoops (count) +system.membus.snoop_fanout::samples 345038 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 336478 # Request fanout histogram -system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 345038 # Request fanout histogram +system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1752,6 +1740,6 @@ system.realview.ethernet.coalescedTotal nan # av system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index da0ad220f..2b4d78664 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,153 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.818071 # Number of seconds simulated -sim_ticks 2818071194500 # Number of ticks simulated -final_tick 2818071194500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.817778 # Number of seconds simulated +sim_ticks 2817777605000 # Number of ticks simulated +final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 294940 # Simulator instruction rate (inst/s) -host_op_rate 358127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6587540433 # Simulator tick rate (ticks/s) -host_mem_usage 622484 # Number of bytes of host memory used -host_seconds 427.79 # Real time elapsed on the host -sim_insts 126171688 # Number of instructions simulated -sim_ops 153202470 # Number of ops (including micro ops) simulated +host_inst_rate 297325 # Simulator instruction rate (inst/s) +host_op_rate 361032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6636656496 # Simulator tick rate (ticks/s) +host_mem_usage 622556 # Number of bytes of host memory used +host_seconds 424.58 # Real time elapsed on the host +sim_insts 126237777 # Number of instructions simulated +sim_ops 153286368 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 666276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4385696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 655396 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4517280 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 127360 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1038980 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 6016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 505600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 4227776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 125824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1063044 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 5888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 519744 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 4071296 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10959048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 666276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 127360 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 505600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1299236 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8262336 # Number of bytes written to this memory +system.physmem.bytes_read::total 10959816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 655396 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 125824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 519744 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1300964 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8260864 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8279860 # Number of bytes written to this memory +system.physmem.bytes_written::total 8278388 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 18864 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 69045 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 18694 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 71101 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16235 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 94 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 7900 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 66059 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1966 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16611 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 92 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 8121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 63614 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180208 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 129099 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180220 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129076 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133480 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133457 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 236430 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1556276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 232593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1603136 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 368685 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 2135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 179413 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 1500237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 44654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 377263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 2090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 184452 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 1444861 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3888847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 236430 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 179413 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 461037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2931912 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3889525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 232593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 44654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 184452 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 461699 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2931695 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2938130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2931912 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2937914 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2931695 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 236430 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1562491 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 232593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1609352 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 368688 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 2135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 179413 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1500237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 44654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 377266 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 2090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 184452 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1444861 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6826977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 92280 # Number of read requests accepted -system.physmem.writeReqs 90311 # Number of write requests accepted -system.physmem.readBursts 92280 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 90311 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5901184 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4736 # Total number of bytes read from write queue -system.physmem.bytesWritten 5694528 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5905860 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 5779784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 74 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1313 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2491 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 6033 # Per bank write bursts -system.physmem.perBankRdBursts::1 5793 # Per bank write bursts -system.physmem.perBankRdBursts::2 5545 # Per bank write bursts -system.physmem.perBankRdBursts::3 6032 # Per bank write bursts -system.physmem.perBankRdBursts::4 5564 # Per bank write bursts -system.physmem.perBankRdBursts::5 5452 # Per bank write bursts -system.physmem.perBankRdBursts::6 6124 # Per bank write bursts -system.physmem.perBankRdBursts::7 6804 # Per bank write bursts -system.physmem.perBankRdBursts::8 6414 # Per bank write bursts -system.physmem.perBankRdBursts::9 6339 # Per bank write bursts -system.physmem.perBankRdBursts::10 5684 # Per bank write bursts -system.physmem.perBankRdBursts::11 5101 # Per bank write bursts -system.physmem.perBankRdBursts::12 5267 # Per bank write bursts -system.physmem.perBankRdBursts::13 5451 # Per bank write bursts -system.physmem.perBankRdBursts::14 5288 # Per bank write bursts -system.physmem.perBankRdBursts::15 5315 # Per bank write bursts -system.physmem.perBankWrBursts::0 5413 # Per bank write bursts -system.physmem.perBankWrBursts::1 4989 # Per bank write bursts -system.physmem.perBankWrBursts::2 5365 # Per bank write bursts -system.physmem.perBankWrBursts::3 5927 # Per bank write bursts -system.physmem.perBankWrBursts::4 5380 # Per bank write bursts -system.physmem.perBankWrBursts::5 5714 # Per bank write bursts -system.physmem.perBankWrBursts::6 5766 # Per bank write bursts -system.physmem.perBankWrBursts::7 6373 # Per bank write bursts -system.physmem.perBankWrBursts::8 6011 # Per bank write bursts -system.physmem.perBankWrBursts::9 5951 # Per bank write bursts -system.physmem.perBankWrBursts::10 5678 # Per bank write bursts -system.physmem.perBankWrBursts::11 4910 # Per bank write bursts -system.physmem.perBankWrBursts::12 5493 # Per bank write bursts -system.physmem.perBankWrBursts::13 5839 # Per bank write bursts -system.physmem.perBankWrBursts::14 5189 # Per bank write bursts -system.physmem.perBankWrBursts::15 4979 # Per bank write bursts +system.physmem.bw_total::total 6827439 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 90406 # Number of read requests accepted +system.physmem.writeReqs 90720 # Number of write requests accepted +system.physmem.readBursts 90406 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 90720 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5783616 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2368 # Total number of bytes read from write queue +system.physmem.bytesWritten 4983552 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5785924 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 5805960 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 37 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 12831 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2411 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5941 # Per bank write bursts +system.physmem.perBankRdBursts::1 5711 # Per bank write bursts +system.physmem.perBankRdBursts::2 5475 # Per bank write bursts +system.physmem.perBankRdBursts::3 5399 # Per bank write bursts +system.physmem.perBankRdBursts::4 5366 # Per bank write bursts +system.physmem.perBankRdBursts::5 5838 # Per bank write bursts +system.physmem.perBankRdBursts::6 6281 # Per bank write bursts +system.physmem.perBankRdBursts::7 6483 # Per bank write bursts +system.physmem.perBankRdBursts::8 6268 # Per bank write bursts +system.physmem.perBankRdBursts::9 6346 # Per bank write bursts +system.physmem.perBankRdBursts::10 5330 # Per bank write bursts +system.physmem.perBankRdBursts::11 5015 # Per bank write bursts +system.physmem.perBankRdBursts::12 5399 # Per bank write bursts +system.physmem.perBankRdBursts::13 5276 # Per bank write bursts +system.physmem.perBankRdBursts::14 4950 # Per bank write bursts +system.physmem.perBankRdBursts::15 5291 # Per bank write bursts +system.physmem.perBankWrBursts::0 4893 # Per bank write bursts +system.physmem.perBankWrBursts::1 4429 # Per bank write bursts +system.physmem.perBankWrBursts::2 4791 # Per bank write bursts +system.physmem.perBankWrBursts::3 4794 # Per bank write bursts +system.physmem.perBankWrBursts::4 4700 # Per bank write bursts +system.physmem.perBankWrBursts::5 5367 # Per bank write bursts +system.physmem.perBankWrBursts::6 5289 # Per bank write bursts +system.physmem.perBankWrBursts::7 5346 # Per bank write bursts +system.physmem.perBankWrBursts::8 5326 # Per bank write bursts +system.physmem.perBankWrBursts::9 5240 # Per bank write bursts +system.physmem.perBankWrBursts::10 4672 # Per bank write bursts +system.physmem.perBankWrBursts::11 4285 # Per bank write bursts +system.physmem.perBankWrBursts::12 5029 # Per bank write bursts +system.physmem.perBankWrBursts::13 5084 # Per bank write bursts +system.physmem.perBankWrBursts::14 4218 # Per bank write bursts +system.physmem.perBankWrBursts::15 4405 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2816505052000 # Total gap between requests +system.physmem.numWrRetry 38 # Number of times write queue was full causing retry +system.physmem.totGap 2816211460500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 1 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 92279 # Read request sizes (log2) +system.physmem.readPktSize::6 90405 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 90309 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60465 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 28317 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2940 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see +system.physmem.writePktSize::6 90718 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 59525 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27440 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2853 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 545 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -175,194 +175,174 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 54 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 52 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3728 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 3952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3603 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 243 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 48 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 33947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.579050 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.896082 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 361.051588 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12589 37.08% 37.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7648 22.53% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3047 8.98% 68.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1722 5.07% 73.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1227 3.61% 77.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 803 2.37% 79.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 549 1.62% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 558 1.64% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5804 17.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 33947 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3440 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 26.800581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 525.347088 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 3439 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3440 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3440 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.865407 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.895854 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 25.306431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 5 0.15% 0.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 1 0.03% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 3 0.09% 0.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 4 0.12% 0.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 2693 78.28% 78.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 34 0.99% 79.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 21 0.61% 80.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 172 5.00% 85.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 62 1.80% 87.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 30 0.87% 87.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 17 0.49% 88.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 16 0.47% 88.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 84 2.44% 91.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 11 0.32% 91.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.41% 92.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.29% 92.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 20 0.58% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 6 0.17% 93.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.17% 93.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 25 0.73% 94.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 46 1.34% 95.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.12% 95.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.12% 95.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 9 0.26% 95.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 47 1.37% 97.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.09% 97.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 6 0.17% 97.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.06% 97.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 16 0.47% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 1 0.03% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 7 0.20% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.06% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 22 0.64% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.09% 99.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.06% 99.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.17% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.09% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.09% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.03% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.09% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.12% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 2 0.06% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.09% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3440 # Writes before turning the bus around for reads -system.physmem.totQLat 1163516500 # Total ticks spent queuing -system.physmem.totMemAccLat 2892379000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 461030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12618.66 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 3919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3722 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 3652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3857 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 777 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 667 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1866 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1082 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 208 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 105 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 33321 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 323.130758 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 184.789706 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.993140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12624 37.89% 37.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 7779 23.35% 61.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3018 9.06% 70.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1714 5.14% 75.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1413 4.24% 79.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 752 2.26% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 537 1.61% 83.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 554 1.66% 85.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4930 14.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 33321 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2995 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.170618 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 514.809638 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 2993 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::27648-28671 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 2995 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2995 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.999332 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.796866 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 47.448084 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 17 0.57% 0.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 2784 92.95% 93.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 41 1.37% 94.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 11 0.37% 95.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 6 0.20% 95.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 14 0.47% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 11 0.37% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 12 0.40% 96.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 7 0.23% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 11 0.37% 97.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 7 0.23% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 15 0.50% 98.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 14 0.47% 98.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 4 0.13% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 1 0.03% 98.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.07% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 4 0.13% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.10% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.10% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 6 0.20% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.03% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.20% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 5 0.17% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.03% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.07% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.10% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2995 # Writes before turning the bus around for reads +system.physmem.totQLat 1193098984 # Total ticks spent queuing +system.physmem.totMemAccLat 2887517734 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 451845000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13202.53 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31368.66 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.09 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.02 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.05 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31952.53 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.05 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.77 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.05 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 6.25 # Average write queue length when enqueuing -system.physmem.readRowHits 76428 # Number of row buffer hits during reads -system.physmem.writeRowHits 70807 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.56 # Row buffer hit rate for writes -system.physmem.avgGap 15425212.92 # Average gap between requests -system.physmem.pageHitRate 81.25 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 134288280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 73012500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 369306600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 291126960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 68919855390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1612195386000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1860855224610 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.510956 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2632883157750 # Time in different power states -system.physmem_0.memoryStateTime::REF 91447980000 # Time in different power states +system.physmem.avgWrQLen 4.64 # Average write queue length when enqueuing +system.physmem.readRowHits 74590 # Number of row buffer hits during reads +system.physmem.writeRowHits 60325 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.45 # Row buffer hit rate for writes +system.physmem.avgGap 15548355.62 # Average gap between requests +system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 130667040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 71094375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 362653200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 256666320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 68967490005 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1611945575250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1860586561230 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.497599 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2632498894488 # Time in different power states +system.physmem_0.memoryStateTime::REF 91437840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14405588500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14475823012 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 122351040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 66577500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 349884600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 285444000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 178872248880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 68134185630 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1610493455250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1858324146900 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.557325 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2634053636000 # Time in different power states -system.physmem_1.memoryStateTime::REF 91447980000 # Time in different power states +system.physmem_1.actEnergy 121239720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 65934000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 342209400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 247918320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 178852415040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 68215091715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1611413256750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1859258064945 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.496864 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2633620948492 # Time in different power states +system.physmem_1.memoryStateTime::REF 91437840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 13230281250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 13360607258 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -412,48 +392,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5757 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5757 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5757 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5757 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5757 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.475514 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 87128456868 52.45% 52.45% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 78993152250 47.55% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 166121609118 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3229 67.67% 67.67% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1543 32.33% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4772 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5757 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 5755 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5755 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5755 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5755 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5755 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.475663 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 87076283368 52.43% 52.43% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 78993148500 47.57% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 166069431868 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3189 67.65% 67.65% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1525 32.35% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4714 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5755 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5757 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4772 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5755 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4714 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4772 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10529 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4714 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10469 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14474153 # DTB read hits -system.cpu0.dtb.read_misses 4865 # DTB read misses -system.cpu0.dtb.write_hits 11054581 # DTB write hits -system.cpu0.dtb.write_misses 892 # DTB write misses -system.cpu0.dtb.flush_tlb 188 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 14452204 # DTB read hits +system.cpu0.dtb.read_misses 4833 # DTB read misses +system.cpu0.dtb.write_hits 11089888 # DTB write hits +system.cpu0.dtb.write_misses 922 # DTB write misses +system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3207 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3319 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 943 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 937 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 195 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14479018 # DTB read accesses -system.cpu0.dtb.write_accesses 11055473 # DTB write accesses +system.cpu0.dtb.perms_faults 217 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14457037 # DTB read accesses +system.cpu0.dtb.write_accesses 11090810 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 25528734 # DTB hits -system.cpu0.dtb.misses 5757 # DTB misses -system.cpu0.dtb.accesses 25534491 # DTB accesses +system.cpu0.dtb.hits 25542092 # DTB hits +system.cpu0.dtb.misses 5755 # DTB misses +system.cpu0.dtb.accesses 25547847 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,387 +463,387 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2755 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2755 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2755 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2755 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2755 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 166121609118 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.475515 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.499400 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 87128348368 52.45% 52.45% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 78993260750 47.55% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 166121609118 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1528 75.53% 75.53% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 495 24.47% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2023 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2817 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2817 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2817 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2817 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2817 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 166069431868 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.475664 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.499407 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 87076165368 52.43% 52.43% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 78993266500 47.57% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 166069431868 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1542 75.55% 75.55% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 499 24.45% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2041 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2755 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2755 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2817 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2817 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2023 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2023 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4778 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 67991390 # ITB inst hits -system.cpu0.itb.inst_misses 2755 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2041 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2041 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4858 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 67891248 # ITB inst hits +system.cpu0.itb.inst_misses 2817 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 188 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 401 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 445 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1966 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2012 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 67994145 # ITB inst accesses -system.cpu0.itb.hits 67991390 # DTB hits -system.cpu0.itb.misses 2755 # DTB misses -system.cpu0.itb.accesses 67994145 # DTB accesses -system.cpu0.numCycles 82552372 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 67894065 # ITB inst accesses +system.cpu0.itb.hits 67891248 # DTB hits +system.cpu0.itb.misses 2817 # DTB misses +system.cpu0.itb.accesses 67894065 # DTB accesses +system.cpu0.numCycles 82517225 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 66182532 # Number of instructions committed -system.cpu0.committedOps 80633643 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 70853114 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5470 # Number of float alu accesses -system.cpu0.num_func_calls 7266071 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 8791663 # number of instructions that are conditional controls -system.cpu0.num_int_insts 70853114 # number of integer instructions -system.cpu0.num_fp_insts 5470 # number of float instructions -system.cpu0.num_int_register_reads 131368884 # number of times the integer registers were read -system.cpu0.num_int_register_writes 49289864 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4246 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 245759484 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 29458192 # number of times the CC registers were written -system.cpu0.num_mem_refs 26200850 # number of memory refs -system.cpu0.num_load_insts 14651277 # Number of load instructions -system.cpu0.num_store_insts 11549573 # Number of store instructions -system.cpu0.num_idle_cycles 77943726.541103 # Number of idle cycles -system.cpu0.num_busy_cycles 4608645.458897 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055827 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944173 # Percentage of idle cycles -system.cpu0.Branches 16455843 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 55777669 67.99% 67.99% # Class of executed instruction -system.cpu0.op_class::IntMult 58831 0.07% 68.06% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4520 0.01% 68.06% # Class of executed instruction +system.cpu0.committedInsts 66111161 # Number of instructions committed +system.cpu0.committedOps 80627134 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 70885778 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5615 # Number of float alu accesses +system.cpu0.num_func_calls 7285085 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 8754092 # number of instructions that are conditional controls +system.cpu0.num_int_insts 70885778 # number of integer instructions +system.cpu0.num_fp_insts 5615 # number of float instructions +system.cpu0.num_int_register_reads 131498293 # number of times the integer registers were read +system.cpu0.num_int_register_writes 49310474 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4327 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1292 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 245812611 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 29370316 # number of times the CC registers were written +system.cpu0.num_mem_refs 26208491 # number of memory refs +system.cpu0.num_load_insts 14628012 # Number of load instructions +system.cpu0.num_store_insts 11580479 # Number of store instructions +system.cpu0.num_idle_cycles 77919171.769514 # Number of idle cycles +system.cpu0.num_busy_cycles 4598053.230486 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055722 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944278 # Percentage of idle cycles +system.cpu0.Branches 16437108 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2194 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 55772206 67.98% 67.98% # Class of executed instruction +system.cpu0.op_class::IntMult 58001 0.07% 68.05% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4497 0.01% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.06% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::MemRead 14651277 17.86% 85.92% # Class of executed instruction -system.cpu0.op_class::MemWrite 11549573 14.08% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 14628012 17.83% 85.89% # Class of executed instruction +system.cpu0.op_class::MemWrite 11580479 14.11% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 82044063 # Class of executed instruction +system.cpu0.op_class::total 82045389 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3055 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 833838 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 46974042 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 834350 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.300164 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 3057 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 831864 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.997018 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 47054976 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 832376 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.530914 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.894462 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.632625 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.469713 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949013 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032486 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018496 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.861119 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.669659 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.466239 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948947 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032558 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018489 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 301 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 198459549 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 198459549 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 13785736 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 4396523 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 8506631 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 26688890 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10662175 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 3165503 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 5162158 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18989836 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190654 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60573 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130462 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 381689 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235825 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80326 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 134935 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 451086 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 237211 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82830 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 139650 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459691 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 24447911 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 7562026 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 13668789 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 45678726 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 24638565 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 7622599 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 13799251 # number of overall hits -system.cpu0.dcache.overall_hits::total 46060415 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 191504 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 58959 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 314968 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 565431 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 143878 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 35403 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 1532172 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1711453 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54012 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 21177 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 65552 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 140741 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4456 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3300 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9701 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17457 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 198551178 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 198551178 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 13770345 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 4433242 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 8498402 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 26701989 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10695058 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 3174725 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 5187481 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 19057264 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 188196 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 61394 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 132351 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 381941 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 234602 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80377 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 136196 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 451175 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236074 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 82808 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140857 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459739 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 24465403 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 7607967 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 13685883 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 45759253 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 24653599 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 7669361 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 13818234 # number of overall hits +system.cpu0.dcache.overall_hits::total 46141194 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 187937 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 59498 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 318451 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 565886 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 147418 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 35026 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 1470502 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1652946 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54526 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20446 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 66281 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141253 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4541 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3227 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9714 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 17482 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 3 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu2.data 16 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 335382 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94362 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 1847140 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2276884 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389394 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 115539 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1912692 # number of overall misses -system.cpu0.dcache.overall_misses::total 2417625 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 898816250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5241989350 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6140805600 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1325719411 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70529735198 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71855454609 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46466000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132057494 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 178523494 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 259504 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 259504 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2224535661 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 75771724548 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 77996260209 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2224535661 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 75771724548 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 77996260209 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 13977240 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 4455482 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 8821599 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 27254321 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 10806053 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 3200906 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 6694330 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 20701289 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 244666 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 81750 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 196014 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 522430 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 240281 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83626 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 144636 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 468543 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 237213 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82830 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 139666 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459709 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 24783293 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 7656388 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 15515929 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 47955610 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 25027959 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 7738138 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 15711943 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 48478040 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013701 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013233 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035704 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020746 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013315 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.011060 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228876 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.082674 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.220758 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.259046 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334425 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269397 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018545 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039461 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.067072 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037258 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000115 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000039 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013533 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012325 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.119048 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.047479 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015558 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014931 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121735 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.049871 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15244.767550 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16642.926742 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10860.397820 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37446.527441 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46032.518019 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41985.058666 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14080.606061 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13612.771261 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10226.470413 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16219 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14416.888889 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23574.486138 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41021.105356 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34255.702183 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19253.547815 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39615.225320 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32261.521207 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 372760 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 22765 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 24978 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 525 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.923533 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 43.361905 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_misses::total 19 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 335355 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 94524 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 1788953 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2218832 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389881 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 114970 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1855234 # number of overall misses +system.cpu0.dcache.overall_misses::total 2360085 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 914696992 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4873257385 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5787954377 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1450684328 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 71024926938 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 72475611266 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 43850500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 129200998 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 173051498 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 333505 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 333505 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 2365381320 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 75898184323 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 78263565643 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 2365381320 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 75898184323 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 78263565643 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 13958282 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 4492740 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 8816853 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 27267875 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 10842476 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 3209751 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 6657983 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 20710210 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 242722 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 81840 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 198632 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 523194 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239143 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83604 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 145910 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 468657 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236077 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 82808 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 140873 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 459758 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 24800758 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 7702491 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 15474836 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 47978085 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 25043480 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 7784331 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 15673468 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 48501279 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013464 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013243 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.036118 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.020753 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013596 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010912 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220863 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.079813 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224644 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249829 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.333687 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269982 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018989 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.038599 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066575 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037302 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000013 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000114 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000041 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013522 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012272 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115604 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.046247 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015568 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014769 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118368 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.048660 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15373.575448 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15303.005439 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10228.127886 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 41417.356478 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48299.782617 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43846.327264 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13588.627208 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13300.493926 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9898.838691 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 20844.062500 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 17552.894737 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25024.134823 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 42426.035968 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35272.416137 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20573.900322 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 40910.302594 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33161.333445 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 378962 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 29004 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19067 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 710 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.875282 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 40.850704 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 692729 # number of writebacks -system.cpu0.dcache.writebacks::total 692729 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 123 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 154842 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 154965 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1412163 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1412163 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1954 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6831 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8785 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 123 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 1567005 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1567128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 123 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 1567005 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1567128 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 58836 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 160126 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 218962 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 35403 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 120009 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 155412 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 20795 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43908 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 64703 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1346 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2870 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4216 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 690587 # number of writebacks +system.cpu0.dcache.writebacks::total 690587 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 87 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 157237 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 157324 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1353907 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1353907 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1937 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6801 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8738 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 87 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 1511144 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1511231 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 87 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 1511144 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1511231 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 59411 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 161214 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 220625 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 35026 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 116595 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 151621 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 20077 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 44216 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 64293 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1290 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2913 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4203 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 16 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 94239 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 280135 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 374374 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 115034 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 324043 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 439077 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 777918000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2124515706 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2902433706 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1248908571 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5424851729 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6673760300 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 265951000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 654196260 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 920147260 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21422750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35664251 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57087001 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 227496 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 227496 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2026826571 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7549367435 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9576194006 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2292777571 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8203563695 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10496341266 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1019447000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1696986500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2716433500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 779587000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1319132500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2098719500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1799034000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3016119000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4815153000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013205 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018152 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008034 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011060 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017927 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.254373 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224004 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.123850 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016095 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019843 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008998 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000115 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94437 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 277809 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 372246 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 114514 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 322025 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 436539 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 823130250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2155055358 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2978185608 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1391922672 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5640631884 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7032554556 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 264066008 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 576983002 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 841049010 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19999250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 37322251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57321501 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 309495 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 309495 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2215052922 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7795687242 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10010740164 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2479118930 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8372670244 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10851789174 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1043159500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1692820000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2735979500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 803109000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1311241000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2114350000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1846268500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3004061000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4850329500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013224 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018285 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008091 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010912 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017512 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007321 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.245320 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.222603 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122886 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.015430 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019964 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.008968 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000114 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000035 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012309 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018055 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.007807 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014866 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020624 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.009057 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13221.802978 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13267.774790 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13255.421973 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35276.913567 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45203.707464 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 42942.374463 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12789.180091 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14899.249795 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14221.091140 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15915.861813 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12426.568293 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13540.560009 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14218.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14218.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21507.301340 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26949.033270 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25579.217590 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 19931.303536 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25316.281157 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23905.468212 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012261 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017952 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.007759 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014711 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020546 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.009001 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13854.845904 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13367.668800 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13498.858280 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 39739.698281 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 48377.991200 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46382.457285 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13152.662649 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13049.190384 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13081.502030 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15503.294574 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12812.307243 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13638.234832 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 19343.437500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19343.437500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23455.350361 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 28061.319979 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 26892.807885 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -874,142 +854,142 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1797406 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.544833 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 100910374 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1797917 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.126269 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 10928216250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.581873 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.468426 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.494533 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932777 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.041931 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.024403 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999111 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1799096 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.534039 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 100909280 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1799607 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 56.072954 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 10982089250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.173904 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.006307 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 13.353828 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.931980 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.041028 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.026082 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999090 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 230 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 104556280 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 104556280 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 67125667 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 21618827 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 12165880 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 100910374 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 67125667 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 21618827 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 12165880 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 100910374 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 67125667 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 21618827 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 12165880 # number of overall hits -system.cpu0.icache.overall_hits::total 100910374 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 867746 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 249012 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 731202 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1847960 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 867746 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 249012 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 731202 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1847960 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 867746 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 249012 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 731202 # number of overall misses -system.cpu0.icache.overall_misses::total 1847960 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3371834500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10026972776 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13398807276 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 3371834500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 10026972776 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13398807276 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 3371834500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 10026972776 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13398807276 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 67993413 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 21867839 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 12897082 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 102758334 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 67993413 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 21867839 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 12897082 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 102758334 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 67993413 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 21867839 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 12897082 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 102758334 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012762 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011387 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.056695 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017984 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012762 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011387 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.056695 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017984 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012762 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011387 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.056695 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017984 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13540.851445 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13712.999658 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7250.593777 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13540.851445 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13712.999658 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7250.593777 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13540.851445 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13712.999658 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7250.593777 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 6029 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 104560332 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 104560332 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 67029897 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 21781554 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 12097829 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 100909280 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 67029897 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 21781554 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 12097829 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 100909280 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 67029897 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 21781554 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 12097829 # number of overall hits +system.cpu0.icache.overall_hits::total 100909280 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 863392 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 250227 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 737787 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1851406 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 863392 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 250227 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 737787 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1851406 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 863392 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 250227 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 737787 # number of overall misses +system.cpu0.icache.overall_misses::total 1851406 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3390224750 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10026619709 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13416844459 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 3390224750 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 10026619709 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13416844459 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 3390224750 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 10026619709 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13416844459 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 67893289 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 22031781 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 12835616 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 102760686 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 67893289 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 22031781 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 12835616 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 102760686 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 67893289 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 22031781 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 12835616 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 102760686 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012717 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011358 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.057480 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.018017 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012717 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011358 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.057480 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.018017 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012717 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011358 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.057480 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.018017 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13548.596874 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13590.127922 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7246.840757 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13548.596874 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13590.127922 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7246.840757 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13548.596874 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13590.127922 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7246.840757 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 7212 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 382 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 416 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.782723 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.336538 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50013 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 50013 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 50013 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 50013 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 50013 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 50013 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 249012 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 681189 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 930201 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 249012 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 681189 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 930201 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 249012 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 681189 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 930201 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2873083500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8182514470 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11055597970 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2873083500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8182514470 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11055597970 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2873083500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8182514470 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11055597970 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009052 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009052 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011387 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.052817 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009052 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11885.171022 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11885.171022 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11537.931907 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12012.105994 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11885.171022 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 51759 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 51759 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 51759 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 51759 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 51759 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 51759 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250227 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 686028 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 936255 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 250227 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 686028 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 936255 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 250227 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 686028 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 936255 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 3014176750 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8498569729 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11512746479 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 3014176750 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8498569729 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11512746479 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 3014176750 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8498569729 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11512746479 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009111 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009111 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011358 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053447 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009111 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12296.592786 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12045.769441 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12388.079975 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12296.592786 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1040,56 +1020,56 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1854 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1854 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 620 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1234 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1854 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1854 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1854 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1496 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9777.746658 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7722.280706 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6250.292235 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 511 34.16% 34.16% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 754 50.40% 84.56% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 230 15.37% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::73728-81919 1 0.07% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1496 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1000015000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000015000 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1000015000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 885 59.16% 59.16% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 611 40.84% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1496 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1854 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 1874 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1874 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 637 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1237 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1874 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1874 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1874 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1601 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12056.839475 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10248.777265 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6448.828751 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 390 24.36% 24.36% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 856 53.47% 77.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 354 22.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1601 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1000015500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000015500 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1000015500 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 972 60.71% 60.71% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 629 39.29% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1601 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1874 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1854 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1496 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1874 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1601 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1496 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3350 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1601 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3475 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4626652 # DTB read hits -system.cpu1.dtb.read_misses 1593 # DTB read misses -system.cpu1.dtb.write_hits 3288334 # DTB write hits -system.cpu1.dtb.write_misses 261 # DTB write misses -system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 4664064 # DTB read hits +system.cpu1.dtb.read_misses 1628 # DTB read misses +system.cpu1.dtb.write_hits 3297220 # DTB write hits +system.cpu1.dtb.write_misses 246 # DTB write misses +system.cpu1.dtb.flush_tlb 168 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1268 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1307 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 232 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 257 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 69 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4628245 # DTB read accesses -system.cpu1.dtb.write_accesses 3288595 # DTB write accesses +system.cpu1.dtb.perms_faults 60 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4665692 # DTB read accesses +system.cpu1.dtb.write_accesses 3297466 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7914986 # DTB hits -system.cpu1.dtb.misses 1854 # DTB misses -system.cpu1.dtb.accesses 7916840 # DTB accesses +system.cpu1.dtb.hits 7961284 # DTB hits +system.cpu1.dtb.misses 1874 # DTB misses +system.cpu1.dtb.accesses 7963158 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1119,129 +1099,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 832 # Table walker walks requested -system.cpu1.itb.walker.walksShort 832 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 221 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 611 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 832 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 832 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 832 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 612 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10456.699346 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8281.924765 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6395.528631 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::2048-4095 192 31.37% 31.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 1 0.16% 31.54% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 290 47.39% 78.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 12 1.96% 80.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-22527 105 17.16% 98.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 12 1.96% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 612 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 876 # Table walker walks requested +system.cpu1.itb.walker.walksShort 876 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 230 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 646 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 876 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 876 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 876 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 692 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12877.167630 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11119.022104 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6272.001420 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::2048-4095 140 20.23% 20.23% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 230 33.24% 53.47% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 143 20.66% 74.13% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-22527 156 22.54% 96.68% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 23 3.32% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 692 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 391 63.89% 63.89% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 221 36.11% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 612 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 462 66.76% 66.76% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 230 33.24% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 692 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 832 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 832 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 876 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 876 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 612 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 612 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1444 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 21867839 # ITB inst hits -system.cpu1.itb.inst_misses 832 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 692 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 692 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1568 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 22031781 # ITB inst hits +system.cpu1.itb.inst_misses 876 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 147 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 168 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 112 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 672 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 752 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 21868671 # ITB inst accesses -system.cpu1.itb.hits 21867839 # DTB hits -system.cpu1.itb.misses 832 # DTB misses -system.cpu1.itb.accesses 21868671 # DTB accesses -system.cpu1.numCycles 158011786 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 22032657 # ITB inst accesses +system.cpu1.itb.hits 22031781 # DTB hits +system.cpu1.itb.misses 876 # DTB misses +system.cpu1.itb.accesses 22032657 # DTB accesses +system.cpu1.numCycles 158012603 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 21167008 # Number of instructions committed -system.cpu1.committedOps 25384727 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 22581810 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1738 # Number of float alu accesses -system.cpu1.num_func_calls 2402385 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2688390 # number of instructions that are conditional controls -system.cpu1.num_int_insts 22581810 # number of integer instructions -system.cpu1.num_fp_insts 1738 # number of float instructions -system.cpu1.num_int_register_reads 41656503 # number of times the integer registers were read -system.cpu1.num_int_register_writes 15851657 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1290 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 92262793 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 9324878 # number of times the CC registers were written -system.cpu1.num_mem_refs 8128633 # number of memory refs -system.cpu1.num_load_insts 4673659 # Number of load instructions -system.cpu1.num_store_insts 3454974 # Number of store instructions -system.cpu1.num_idle_cycles 151523982.353984 # Number of idle cycles -system.cpu1.num_busy_cycles 6487803.646016 # Number of busy cycles -system.cpu1.not_idle_fraction 0.041059 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.958941 # Percentage of idle cycles -system.cpu1.Branches 5241513 # Number of branches fetched -system.cpu1.op_class::No_OpClass 34 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 17951469 68.78% 68.78% # Class of executed instruction -system.cpu1.op_class::IntMult 18860 0.07% 68.85% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.85% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 1172 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.86% # Class of executed instruction -system.cpu1.op_class::MemRead 4673659 17.91% 86.76% # Class of executed instruction -system.cpu1.op_class::MemWrite 3454974 13.24% 100.00% # Class of executed instruction +system.cpu1.committedInsts 21317281 # Number of instructions committed +system.cpu1.committedOps 25549926 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 22701009 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1608 # Number of float alu accesses +system.cpu1.num_func_calls 2410952 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2737582 # number of instructions that are conditional controls +system.cpu1.num_int_insts 22701009 # number of integer instructions +system.cpu1.num_fp_insts 1608 # number of float instructions +system.cpu1.num_int_register_reads 41843043 # number of times the integer registers were read +system.cpu1.num_int_register_writes 15920660 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1288 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 320 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 92840963 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 9448697 # number of times the CC registers were written +system.cpu1.num_mem_refs 8172131 # number of memory refs +system.cpu1.num_load_insts 4710232 # Number of load instructions +system.cpu1.num_store_insts 3461899 # Number of store instructions +system.cpu1.num_idle_cycles 151539718.287508 # Number of idle cycles +system.cpu1.num_busy_cycles 6472884.712492 # Number of busy cycles +system.cpu1.not_idle_fraction 0.040964 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.959036 # Percentage of idle cycles +system.cpu1.Branches 5298424 # Number of branches fetched +system.cpu1.op_class::No_OpClass 41 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 18071289 68.81% 68.81% # Class of executed instruction +system.cpu1.op_class::IntMult 19339 0.07% 68.88% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 1186 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.88% # Class of executed instruction +system.cpu1.op_class::MemRead 4710232 17.93% 86.82% # Class of executed instruction +system.cpu1.op_class::MemWrite 3461899 13.18% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 26100168 # Class of executed instruction +system.cpu1.op_class::total 26263986 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 17449157 # Number of BP lookups -system.cpu2.branchPred.condPredicted 9464735 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 398390 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 10718645 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 8165775 # Number of BTB hits +system.cpu2.branchPred.lookups 17390044 # Number of BP lookups +system.cpu2.branchPred.condPredicted 9451928 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 400737 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 10830418 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 8125283 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 76.182904 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 4093661 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 20704 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 75.022802 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 4068079 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21097 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1271,92 +1250,88 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 43517 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 43517 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13970 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11118 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 18429 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 25088 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 493.961256 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 3141.545513 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-8191 24512 97.70% 97.70% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::8192-16383 373 1.49% 99.19% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::16384-24575 135 0.54% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::24576-32767 33 0.13% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::32768-40959 15 0.06% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::40960-49151 7 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::49152-57343 6 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 25088 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 9234 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 11931.507147 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 9422.312939 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 7440.393288 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 2697 29.21% 29.21% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 4034 43.69% 72.89% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2262 24.50% 97.39% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::24576-32767 120 1.30% 98.69% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::32768-40959 50 0.54% 99.23% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::40960-49151 64 0.69% 99.92% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::49152-57343 4 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::73728-81919 2 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 9234 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 52111304876 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.433489 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.514696 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-1 52056176876 99.89% 99.89% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::2-3 40469500 0.08% 99.97% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-5 8303000 0.02% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::6-7 2155500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-9 1410500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::10-11 753500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-13 454000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::14-15 1056000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-17 83500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::18-19 122000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-21 61500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::22-23 86000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-25 164500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::26-27 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::28-29 4500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 52111304876 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 2902 72.88% 72.88% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 1080 27.12% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 3982 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43517 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walks 43271 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 43271 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 13795 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 11030 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 18446 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 24825 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 526.888218 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 3382.784717 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-16383 24602 99.10% 99.10% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::16384-32767 180 0.73% 99.83% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::32768-49151 23 0.09% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::49152-65535 14 0.06% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-81919 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::98304-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 24825 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 9018 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12445.276336 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10074.043051 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 7598.717395 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 2712 30.07% 30.07% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 3866 42.87% 72.94% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 2205 24.45% 97.39% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::24576-32767 103 1.14% 98.54% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::32768-40959 58 0.64% 99.18% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::40960-49151 71 0.79% 99.97% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 9018 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 60407494468 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.614556 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.505382 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-1 60349981968 99.90% 99.90% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::2-3 42488500 0.07% 99.98% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-5 7802000 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::6-7 2924500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-9 1368500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-13 331000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::14-15 1040000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-17 124500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::18-19 121000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-21 186000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::22-23 81500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-25 109000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::26-27 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::28-29 5500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::30-31 75000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 60407494468 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 2796 73.35% 73.35% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 1016 26.65% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 3812 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 43271 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43517 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3982 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 43271 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 3812 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3982 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 47499 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 3812 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 47083 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 9677625 # DTB read hits -system.cpu2.dtb.read_misses 37716 # DTB read misses -system.cpu2.dtb.write_hits 7160348 # DTB write hits -system.cpu2.dtb.write_misses 5801 # DTB write misses -system.cpu2.dtb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA +system.cpu2.dtb.read_hits 9630626 # DTB read hits +system.cpu2.dtb.read_misses 37535 # DTB read misses +system.cpu2.dtb.write_hits 7130235 # DTB write hits +system.cpu2.dtb.write_misses 5736 # DTB write misses +system.cpu2.dtb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2469 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 945 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 520 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 952 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 418 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 9715341 # DTB read accesses -system.cpu2.dtb.write_accesses 7166149 # DTB write accesses +system.cpu2.dtb.perms_faults 414 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 9668161 # DTB read accesses +system.cpu2.dtb.write_accesses 7135971 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 16837973 # DTB hits -system.cpu2.dtb.misses 43517 # DTB misses -system.cpu2.dtb.accesses 16881490 # DTB accesses +system.cpu2.dtb.hits 16760861 # DTB hits +system.cpu2.dtb.misses 43271 # DTB misses +system.cpu2.dtb.accesses 16804132 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1386,387 +1361,396 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 6476 # Table walker walks requested -system.cpu2.itb.walker.walksShort 6476 # Table walker walks initiated with short descriptors -system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2218 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4151 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 107 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 6369 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1246.035484 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 5374.992147 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-8191 6033 94.72% 94.72% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::8192-16383 153 2.40% 97.13% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::16384-24575 113 1.77% 98.90% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::24576-32767 28 0.44% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-40959 19 0.30% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::40960-49151 8 0.13% 99.76% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::49152-57343 9 0.14% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::57344-65535 3 0.05% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::73728-81919 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 6369 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 1962 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12125.644750 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 9197.080965 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 8421.034460 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-8191 606 30.89% 30.89% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::8192-16383 818 41.69% 72.58% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::16384-24575 463 23.60% 96.18% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::24576-32767 28 1.43% 97.60% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-40959 29 1.48% 99.08% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::40960-49151 11 0.56% 99.64% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::49152-57343 5 0.25% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::57344-65535 1 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::73728-81919 1 0.05% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 1962 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 4866645120 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.377306 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.486503 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 3033838520 62.34% 62.34% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 1830102100 37.61% 99.94% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 2122000 0.04% 99.99% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 461500 0.01% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 121000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 4866645120 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 1443 77.79% 77.79% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 412 22.21% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 1855 # Table walker page sizes translated +system.cpu2.itb.walker.walks 6235 # Table walker walks requested +system.cpu2.itb.walker.walksShort 6235 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walksShortTerminationLevel::Level1 2044 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 4088 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 6132 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1114.562948 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 4869.153513 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-8191 5831 95.09% 95.09% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::8192-16383 152 2.48% 97.57% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::16384-24575 99 1.61% 99.18% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::24576-32767 29 0.47% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-40959 9 0.15% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::40960-49151 4 0.07% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::49152-57343 3 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::57344-65535 1 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-73727 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::90112-98303 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::106496-114687 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 6132 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 1857 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12539.311255 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 10038.361952 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 8040.211817 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-4095 547 29.46% 29.46% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-8191 43 2.32% 31.77% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::8192-12287 410 22.08% 53.85% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-16383 373 20.09% 73.94% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::16384-20479 9 0.48% 74.42% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::20480-24575 413 22.24% 96.66% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::24576-28671 14 0.75% 97.42% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::28672-32767 13 0.70% 98.12% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-36863 11 0.59% 98.71% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::36864-40959 8 0.43% 99.14% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::40960-45055 10 0.54% 99.68% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::45056-49151 1 0.05% 99.73% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::49152-53247 1 0.05% 99.78% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::53248-57343 2 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::57344-61439 1 0.05% 99.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::61440-65535 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 1857 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 13162833212 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.828087 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.377922 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 2265327000 17.21% 17.21% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 10895443212 82.77% 99.98% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 1802500 0.01% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 162000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 51500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::5 47000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 13162833212 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 1358 77.42% 77.42% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 396 22.58% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 1754 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6476 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6476 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 6235 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 6235 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1855 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1855 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 8331 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 12898498 # ITB inst hits -system.cpu2.itb.inst_misses 6476 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 1754 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 1754 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 7989 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 12837123 # ITB inst hits +system.cpu2.itb.inst_misses 6235 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 182 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb 179 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 360 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1789 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1683 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1015 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1125 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 12904974 # ITB inst accesses -system.cpu2.itb.hits 12898498 # DTB hits -system.cpu2.itb.misses 6476 # DTB misses -system.cpu2.itb.accesses 12904974 # DTB accesses -system.cpu2.numCycles 69896550 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 12843358 # ITB inst accesses +system.cpu2.itb.hits 12837123 # DTB hits +system.cpu2.itb.misses 6235 # DTB misses +system.cpu2.itb.accesses 12843358 # DTB accesses +system.cpu2.numCycles 69616646 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 26772867 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 69167442 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 17449157 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 12259436 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 39647350 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2075847 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 94572 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 925 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 261 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 361977 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 99094 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 575 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 12897087 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 269205 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2824 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 68015518 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.222532 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.345771 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 26594039 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 69071466 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 17390044 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12193362 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 39655163 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2070826 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 93322 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 918 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 302 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 323029 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 106475 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 727 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 12835626 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 269064 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2716 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 67809362 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.223662 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.348600 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49396866 72.63% 72.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 2407853 3.54% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 1558370 2.29% 78.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 4909650 7.22% 85.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 1103212 1.62% 87.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 700919 1.03% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 3889597 5.72% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 749830 1.10% 95.15% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3299221 4.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 49260090 72.64% 72.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 2390617 3.53% 76.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 1561768 2.30% 78.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 4865604 7.18% 85.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 1097205 1.62% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 701816 1.03% 88.30% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 3870082 5.71% 94.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 751059 1.11% 95.12% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3311121 4.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 68015518 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.249643 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.989569 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 18660323 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 36954486 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 10395816 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 1074729 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 929937 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 1306815 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 109505 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 59278443 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 354551 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 929937 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 19281301 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 4387069 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 27167714 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 10836297 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 5412952 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 56807794 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2395 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 934627 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 156415 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 3819110 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 58701003 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 260943920 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 63689416 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 4317 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 48649356 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10051631 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 957722 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 893887 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 6244990 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 10262812 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 7930622 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 1370921 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 1928187 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 54587761 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 670112 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 51973443 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 68390 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7260181 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 18315253 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 68730 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 68015518 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.764141 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.466174 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 67809362 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.249797 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.992169 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 18546973 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36871218 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 10413141 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1051163 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 926599 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 1313756 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 110434 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 59271705 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 356279 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 926599 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 19159512 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 3828211 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 27033628 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 10840093 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 6021054 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 56800254 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 1622 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 892733 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 160451 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4475802 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 58727822 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 260839498 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 63695069 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 4195 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 48596346 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10131460 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 953771 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 889969 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 6004915 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 10275852 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 7909386 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1396867 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1932490 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 54546075 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 673336 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 51866821 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 68048 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7293157 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 18430167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68913 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 67809362 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.764892 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.469149 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 47556774 69.92% 69.92% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 6833375 10.05% 79.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 5102327 7.50% 87.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 4195165 6.17% 93.64% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 1616653 2.38% 96.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1064575 1.57% 97.58% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 1125788 1.66% 99.23% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 361184 0.53% 99.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 159677 0.23% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 47470041 70.01% 70.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 6738750 9.94% 79.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 5086869 7.50% 87.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 4143776 6.11% 93.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 1653610 2.44% 95.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1071590 1.58% 97.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 1124885 1.66% 99.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 357423 0.53% 99.76% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 162418 0.24% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 68015518 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 67809362 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 78584 9.71% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.71% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 374915 46.33% 56.04% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 355764 43.96% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 76711 9.73% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 2 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.73% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 365050 46.29% 56.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 346827 43.98% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 110 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 34433275 66.25% 66.25% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 39265 0.08% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 2873 0.01% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 9958899 19.16% 85.49% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 7539012 14.51% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 102 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 34390478 66.31% 66.31% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 39542 0.08% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 1 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.38% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 2888 0.01% 66.39% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.39% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 66.39% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.39% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 9917724 19.12% 85.51% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 7516080 14.49% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 51973443 # Type of FU issued -system.cpu2.iq.rate 0.743577 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 809264 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.015571 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 172830468 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 62550700 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 50376095 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 9590 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 5049 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 4207 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 52777410 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 5187 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 265138 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 51866821 # Type of FU issued +system.cpu2.iq.rate 0.745035 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 788590 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.015204 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 172390251 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 62545050 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 50322136 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 9391 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4963 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4144 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 52650258 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 5051 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 268895 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1600472 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1933 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 38461 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 793125 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1610409 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1859 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 38198 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 800698 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 131320 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 120276 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 130635 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 68542 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 929937 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 3246832 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 971285 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 55360766 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 91934 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 10262812 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 7930622 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 358706 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 34253 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 928134 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 38461 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 182765 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 162631 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 345396 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 51539725 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 9783295 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 390308 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 926599 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 3277236 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 403345 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 55328961 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 92252 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 10275852 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 7909386 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 360332 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 33301 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 361214 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 38198 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 183568 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 164696 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 348264 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 51429187 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 9738477 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 394455 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 102893 # number of nop insts executed -system.cpu2.iew.exec_refs 17248466 # number of memory reference insts executed -system.cpu2.iew.exec_branches 9490874 # Number of branches executed -system.cpu2.iew.exec_stores 7465171 # Number of stores executed -system.cpu2.iew.exec_rate 0.737372 # Inst execution rate -system.cpu2.iew.wb_sent 51085657 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 50380302 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 26454346 # num instructions producing a value -system.cpu2.iew.wb_consumers 45953910 # num instructions consuming a value +system.cpu2.iew.exec_nop 109550 # number of nop insts executed +system.cpu2.iew.exec_refs 17180160 # number of memory reference insts executed +system.cpu2.iew.exec_branches 9476518 # Number of branches executed +system.cpu2.iew.exec_stores 7441683 # Number of stores executed +system.cpu2.iew.exec_rate 0.738748 # Inst execution rate +system.cpu2.iew.wb_sent 51031347 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 50326280 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 26469079 # num instructions producing a value +system.cpu2.iew.wb_consumers 46041332 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.720784 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575671 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.722906 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.574898 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 8107084 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 601382 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 290377 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 66292417 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.712682 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.616986 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 8143906 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 604423 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 291897 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 66086949 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.713825 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.622364 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 48208105 72.72% 72.72% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 8091600 12.21% 84.93% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 3999207 6.03% 90.96% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 1724132 2.60% 93.56% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 877027 1.32% 94.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 615427 0.93% 95.81% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 1259890 1.90% 97.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 297840 0.45% 98.16% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1219189 1.84% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 48131767 72.83% 72.83% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 7989880 12.09% 84.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 3968576 6.01% 90.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 1690353 2.56% 93.48% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 906489 1.37% 94.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 608385 0.92% 95.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 1262051 1.91% 97.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 299318 0.45% 98.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1230130 1.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 66292417 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 38883433 # Number of instructions committed -system.cpu2.commit.committedOps 47245385 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 66086949 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 38874571 # Number of instructions committed +system.cpu2.commit.committedOps 47174544 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 15799837 # Number of memory references committed -system.cpu2.commit.loads 8662340 # Number of loads committed -system.cpu2.commit.membars 225899 # Number of memory barriers committed -system.cpu2.commit.branches 8915887 # Number of branches committed -system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 41357490 # Number of committed integer instructions. -system.cpu2.commit.function_calls 1642928 # Number of function calls committed. +system.cpu2.commit.refs 15774131 # Number of memory references committed +system.cpu2.commit.loads 8665443 # Number of loads committed +system.cpu2.commit.membars 227144 # Number of memory barriers committed +system.cpu2.commit.branches 8900555 # Number of branches committed +system.cpu2.commit.fp_insts 4112 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 41283041 # Number of committed integer instructions. +system.cpu2.commit.function_calls 1636102 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 31404754 66.47% 66.47% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 37921 0.08% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.55% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 2873 0.01% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 31359241 66.47% 66.47% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 38284 0.08% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 2888 0.01% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 8662340 18.33% 84.89% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 7137497 15.11% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 8665443 18.37% 84.93% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 7108688 15.07% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 47245385 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1219189 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 47174544 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1230130 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 113003070 # The number of ROB reads -system.cpu2.rob.rob_writes 112431430 # The number of ROB writes -system.cpu2.timesIdled 280451 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1881032 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 5250223632 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 38822148 # Number of Instructions Simulated -system.cpu2.committedOps 47184100 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.800430 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.800430 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.555423 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.555423 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 56420474 # number of integer regfile reads -system.cpu2.int_regfile_writes 31939226 # number of integer regfile writes -system.cpu2.fp_regfile_reads 15888 # number of floating regfile reads -system.cpu2.fp_regfile_writes 13694 # number of floating regfile writes -system.cpu2.cc_regfile_reads 182315650 # number of cc regfile reads -system.cpu2.cc_regfile_writes 19227541 # number of cc regfile writes -system.cpu2.misc_regfile_reads 124375401 # number of misc regfile reads -system.cpu2.misc_regfile_writes 481787 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30188 # Transaction distribution -system.iobus.trans_dist::ReadResp 30188 # Transaction distribution -system.iobus.trans_dist::WriteReq 59019 # Transaction distribution -system.iobus.trans_dist::WriteResp 22795 # Transaction distribution +system.cpu2.rob.rob_reads 112818862 # The number of ROB reads +system.cpu2.rob.rob_writes 112362949 # The number of ROB writes +system.cpu2.timesIdled 279332 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1807284 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 5249914577 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 38809335 # Number of Instructions Simulated +system.cpu2.committedOps 47109308 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.793812 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.793812 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.557472 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.557472 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 56301107 # number of integer regfile reads +system.cpu2.int_regfile_writes 31916155 # number of integer regfile writes +system.cpu2.fp_regfile_reads 15723 # number of floating regfile reads +system.cpu2.fp_regfile_writes 13758 # number of floating regfile writes +system.cpu2.cc_regfile_reads 181999487 # number of cc regfile reads +system.cpu2.cc_regfile_writes 19225356 # number of cc regfile writes +system.cpu2.misc_regfile_reads 123907195 # number of misc regfile reads +system.cpu2.misc_regfile_writes 485009 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30180 # Transaction distribution +system.iobus.trans_dist::ReadResp 30180 # Transaction distribution +system.iobus.trans_dist::WriteReq 59003 # Transaction distribution +system.iobus.trans_dist::WriteResp 22779 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54126 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1787,11 +1771,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105414 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178366 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67843 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1812,10 +1796,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159071 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480319 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 18225000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) @@ -1838,29 +1822,29 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 2807000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 2714000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 15727000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 15729000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 217868633 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 124959118 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 39885000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39808000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 22990014 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 23061006 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36442 # number of replacements -system.iocache.tags.tagsinuse 0.993331 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.992064 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 245002453509 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.993331 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062083 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062083 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 244950709509 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.992064 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062004 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062004 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1874,14 +1858,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 14419928 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 14419928 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6024842691 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6024842691 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 14419928 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 14419928 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 14419928 # number of overall miss cycles -system.iocache.overall_miss_latency::total 14419928 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 14858930 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 14858930 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 4185043182 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 4185043182 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 14858930 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 14858930 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 14858930 # number of overall miss cycles +system.iocache.overall_miss_latency::total 14858930 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1898,347 +1882,347 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 57221.936508 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 57221.936508 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 166321.849906 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 166321.849906 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 57221.936508 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 57221.936508 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 57221.936508 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34568 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 58964.007937 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 58964.007937 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 115532.331659 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 115532.331659 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 58964.007937 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 58964.007937 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 58964.007937 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 14316 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4486 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2165 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.705751 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.612471 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 127 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 127 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22736 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 22736 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 127 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 127 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 127 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 127 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 7815928 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 7815928 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4842542719 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4842542719 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 7815928 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 7815928 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 7815928 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 7815928 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.503968 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.627650 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.627650 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.503968 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.503968 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.503968 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61542.740157 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 61542.740157 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212990.091441 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212990.091441 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 61542.740157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 61542.740157 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 22752 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 22752 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 8240930 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 8240930 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 3001927194 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 3001927194 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 8240930 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 8240930 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 8240930 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 8240930 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.628092 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.628092 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 65927.440000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 65927.440000 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131941.244462 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131941.244462 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 65927.440000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 65927.440000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 65927.440000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 65927.440000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 100812 # number of replacements -system.l2c.tags.tagsinuse 65118.584894 # Cycle average of tags in use -system.l2c.tags.total_refs 2893892 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166052 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.427625 # Average number of references to valid blocks. +system.l2c.tags.replacements 100862 # number of replacements +system.l2c.tags.tagsinuse 65121.580421 # Cycle average of tags in use +system.l2c.tags.total_refs 2889469 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166056 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 17.400570 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49801.969845 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939327 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 49829.873035 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939329 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5299.216432 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2852.911552 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969199 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1106.770268 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 948.162110 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 57.070020 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3510.700878 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1538.875168 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.759918 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5354.052994 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2949.398573 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969230 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1018.817810 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 810.859726 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 62.513746 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 3585.332677 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1507.823205 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.760344 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.080860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043532 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.081696 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.045004 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.016888 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.014468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000871 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.053569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.023481 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993631 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 49 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65191 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 49 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu1.inst 0.015546 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012373 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000954 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.054708 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.023008 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993676 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65144 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3289 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7961 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53600 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000748 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994736 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 27438611 # Number of tag accesses -system.l2c.tags.data_accesses 27438611 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5008 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2568 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 857894 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 243025 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1381 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 686 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 247021 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 78422 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 27314 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 6601 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 673200 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 202331 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2345451 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 692729 # number of Writeback hits -system.l2c.Writeback_hits::total 692729 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 9 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 31 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 45 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 12 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 80142 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 20956 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 56564 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 157662 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5008 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 2568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 857894 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 323167 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 1381 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 686 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 247021 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 99378 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 27314 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 6601 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 673200 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 258895 # number of demand (read+write) hits -system.l2c.demand_hits::total 2503113 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5008 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 2568 # number of overall hits -system.l2c.overall_hits::cpu0.inst 857894 # number of overall hits -system.l2c.overall_hits::cpu0.data 323167 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 1381 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 686 # number of overall hits -system.l2c.overall_hits::cpu1.inst 247021 # number of overall hits -system.l2c.overall_hits::cpu1.data 99378 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 27314 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 6601 # number of overall hits -system.l2c.overall_hits::cpu2.inst 673200 # number of overall hits -system.l2c.overall_hits::cpu2.data 258895 # number of overall hits -system.l2c.overall_hits::total 2503113 # number of overall hits +system.l2c.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2979 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8228 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53568 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994019 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 27412273 # Number of tag accesses +system.l2c.tags.data_accesses 27412273 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4625 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2417 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 853709 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 239887 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1714 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 910 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 248258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 78311 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 26936 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 6133 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 677801 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 203846 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2344547 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 690587 # number of Writeback hits +system.l2c.Writeback_hits::total 690587 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 33 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 81710 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 20207 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 55512 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 157429 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 4625 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 2417 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 853709 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 321597 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 1714 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 910 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 248258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 98518 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 26936 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 6133 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 677801 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 259358 # number of demand (read+write) hits +system.l2c.demand_hits::total 2501976 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4625 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 2417 # number of overall hits +system.l2c.overall_hits::cpu0.inst 853709 # number of overall hits +system.l2c.overall_hits::cpu0.data 321597 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 1714 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 910 # number of overall hits +system.l2c.overall_hits::cpu1.inst 248258 # number of overall hits +system.l2c.overall_hits::cpu1.data 98518 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 26936 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 6133 # number of overall hits +system.l2c.overall_hits::cpu2.inst 677801 # number of overall hits +system.l2c.overall_hits::cpu2.data 259358 # number of overall hits +system.l2c.overall_hits::total 2501976 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 9847 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6947 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 9677 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7117 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1990 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2555 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 94 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 7907 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 4559 # number of ReadReq misses -system.l2c.ReadReq_misses::total 33905 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1226 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 430 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 1061 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2717 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 4 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 6 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 62501 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 14012 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 62367 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 138880 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 1966 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2467 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 92 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 8131 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 4488 # number of ReadReq misses +system.l2c.ReadReq_misses::total 33944 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1342 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 299 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 1074 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2715 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 3 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu2.data 6 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 9 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 64356 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14516 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 59985 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 138857 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 9847 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69448 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 9677 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 71473 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1990 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16567 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 94 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 7907 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 66926 # number of demand (read+write) misses -system.l2c.demand_misses::total 172785 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1966 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16983 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 92 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 8131 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 64473 # number of demand (read+write) misses +system.l2c.demand_misses::total 172801 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 9847 # number of overall misses -system.l2c.overall_misses::cpu0.data 69448 # number of overall misses +system.l2c.overall_misses::cpu0.inst 9677 # number of overall misses +system.l2c.overall_misses::cpu0.data 71473 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1990 # number of overall misses -system.l2c.overall_misses::cpu1.data 16567 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 94 # number of overall misses -system.l2c.overall_misses::cpu2.inst 7907 # number of overall misses -system.l2c.overall_misses::cpu2.data 66926 # number of overall misses -system.l2c.overall_misses::total 172785 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 145472000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 191058000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7840000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 604236250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 365385246 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1314065996 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 22999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 279988 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 302987 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu2.data 46998 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 46998 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 984500010 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 4647758244 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 5632258254 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 145472000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1175558010 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 7840000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 604236250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 5013143490 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6946324250 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 145472000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1175558010 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 7840000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 604236250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 5013143490 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6946324250 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 5012 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 2569 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 867741 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 249972 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 1382 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 686 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 249011 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 80977 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 27408 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 6601 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 681107 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 206890 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2379356 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 692729 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 692729 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1235 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 435 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1092 # number of UpgradeReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.inst 1966 # number of overall misses +system.l2c.overall_misses::cpu1.data 16983 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 92 # number of overall misses +system.l2c.overall_misses::cpu2.inst 8131 # number of overall misses +system.l2c.overall_misses::cpu2.data 64473 # number of overall misses +system.l2c.overall_misses::total 172801 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 82500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 157235750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 203986258 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7890000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 682853750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 390763250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1442811508 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 93497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 280991 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 374488 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu2.data 63499 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 63499 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1135317971 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 4897657997 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6032975968 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 82500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 157235750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1339304229 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 7890000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 682853750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 5288421247 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 7475787476 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 82500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 157235750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1339304229 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 7890000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 682853750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 5288421247 # number of overall miss cycles +system.l2c.overall_miss_latency::total 7475787476 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4629 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 2418 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 863386 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 247004 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 1715 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 910 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 250224 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 80778 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 27028 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 6133 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 685932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 208334 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2378491 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 690587 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 690587 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 303 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1107 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2762 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 3 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu2.data 16 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 142643 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 34968 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 118931 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296542 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5012 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2569 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 867741 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392615 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 1382 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 686 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 249011 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 115945 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 27408 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 6601 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 681107 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 325821 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2675898 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 5012 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2569 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 867741 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392615 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 1382 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 686 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 249011 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 115945 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 27408 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 6601 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 681107 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 325821 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2675898 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000798 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000389 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.011348 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.027791 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.007992 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.031552 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003430 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.011609 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.022036 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.014250 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992713 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.988506 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.971612 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.983707 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_accesses::total 19 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 146066 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 34723 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 115497 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296286 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 4629 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 2418 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 863386 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 393070 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 1715 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 910 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 250224 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 115501 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 27028 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 6133 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 685932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 323831 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2674777 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4629 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 2418 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 863386 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 393070 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 1715 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 910 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 250224 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 115501 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 27028 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 6133 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 685932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 323831 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2674777 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000414 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.011208 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.028813 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000583 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007857 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030540 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003404 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.011854 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.021542 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.014271 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992604 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.986799 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.970190 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.982983 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.438164 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.400709 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.524396 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.468332 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000798 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000389 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.011348 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.176886 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.007992 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.142887 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003430 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.011609 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.205407 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.064571 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000798 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000389 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.011348 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.176886 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000724 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.007992 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.142887 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003430 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.011609 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.205407 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.064571 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73101.507538 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 74778.082192 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 83404.255319 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76417.889212 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 80145.919281 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 38757.292317 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 53.486047 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 263.890669 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 111.515274 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 11749.500000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 7833 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70261.205395 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74522.716244 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 40554.854940 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 73101.507538 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 70957.808294 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 83404.255319 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 76417.889212 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 74905.768909 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 40202.125474 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 73101.507538 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 70957.808294 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 83404.255319 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 76417.889212 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 74905.768909 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 40202.125474 # average overall miss latency +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.375000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.473684 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.440595 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.418051 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.519364 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.468659 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000414 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.011208 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.181833 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000583 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007857 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.147038 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003404 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.011854 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.199095 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.064604 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000864 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000414 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.011208 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.181833 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000583 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007857 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.147038 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003404 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.011854 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.199095 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.064604 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 79977.492370 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 82685.957844 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85760.869565 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 83981.521338 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 87068.460339 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 42505.641881 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 312.698997 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 261.630354 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 137.932965 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu2.data 10583.166667 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 7055.444444 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 78211.488771 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81648.045295 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 43447.402493 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 79977.492370 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 78861.463169 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85760.869565 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 83981.521338 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 82025.363284 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 43262.408643 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 79977.492370 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 78861.463169 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85760.869565 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 83981.521338 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 82025.363284 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 43262.408643 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2247,142 +2231,142 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 92909 # number of writebacks -system.l2c.writebacks::total 92909 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.inst 4 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 92886 # number of writebacks +system.l2c.writebacks::total 92886 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu2.data 44 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 4 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu2.data 44 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 4 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu2.data 44 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 48 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 51 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1990 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 2555 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 94 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 7903 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 4515 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 17058 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 430 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 1061 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1491 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 4 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 14012 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 62367 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 76379 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1966 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 2467 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 92 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 8124 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 4444 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 17094 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 299 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 1074 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1373 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 6 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 6 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14516 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 59985 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 74501 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1990 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 16567 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 94 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 7903 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 66882 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 93437 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1966 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 16983 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 92 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 8124 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 64429 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 91595 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1990 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 16567 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 94 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 7903 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 66882 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 93437 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 120319500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 159125500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 6677500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 504714500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 306175246 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1097074746 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4300430 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10613561 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14913991 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 40004 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 40004 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 805305490 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3877303256 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4682608746 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 120319500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 964430990 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 6677500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 504714500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 4183478502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5779683492 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 120319500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 964430990 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 6677500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 504714500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 4183478502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5779683492 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 944099500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1583789000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 2527888500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 725229500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1236940000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1962169500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1669329000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2820729000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4490058000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007992 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.031552 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003430 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011603 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021823 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.007169 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.988506 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.971612 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.539826 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.222222 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.400709 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.524396 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.257566 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007992 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.142887 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003430 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011603 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.205272 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.034918 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000724 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007992 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.142887 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003430 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011603 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.205272 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.034918 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60462.060302 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62280.039139 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63863.659370 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67812.900554 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 64314.383046 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10003.356268 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.676727 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57472.558521 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62169.148043 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61307.541942 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60462.060302 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58213.978994 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63863.659370 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62550.140576 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61856.475401 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60462.060302 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58213.978994 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 71037.234043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63863.659370 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62550.140576 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61856.475401 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu1.inst 1966 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 16983 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 92 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 8124 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 64429 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 91595 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 132598250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 173127242 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 6735500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 580526000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 331871000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1224927992 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5327299 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 19051574 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 24378873 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 109005 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 109005 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 953509029 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4148606003 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5102115032 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 70000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 132598250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1126636271 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 6735500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 580526000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 4480477003 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6327043024 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 70000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 132598250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1126636271 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 6735500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 580526000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 4480477003 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6327043024 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 960816500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1572406000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 2533222500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 743288000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1223622500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1966910500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1704104500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2796028500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4500133000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000583 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030540 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003404 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011844 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021331 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.007187 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.986799 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.970190 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.497104 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.375000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.315789 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.418051 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.519364 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.251450 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000583 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007857 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.147038 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003404 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.198959 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.034244 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007857 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.147038 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003404 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.198959 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.034244 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67445.701933 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70177.236319 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 74678.442844 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 71658.359190 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17817.053512 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17738.895717 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17755.916242 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 18167.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 18167.500000 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65686.761436 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69160.723564 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 68483.846284 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67445.701933 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66339.060884 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67445.701933 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66339.060884 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 73211.956522 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2393,55 +2377,55 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74222 # Transaction distribution -system.membus.trans_dist::ReadResp 74221 # Transaction distribution -system.membus.trans_dist::WriteReq 27571 # Transaction distribution -system.membus.trans_dist::WriteResp 27571 # Transaction distribution -system.membus.trans_dist::Writeback 129099 # Transaction distribution +system.membus.trans_dist::ReadReq 74250 # Transaction distribution +system.membus.trans_dist::ReadResp 74249 # Transaction distribution +system.membus.trans_dist::WriteReq 27555 # Transaction distribution +system.membus.trans_dist::WriteResp 27555 # Transaction distribution +system.membus.trans_dist::Writeback 129076 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4550 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 6 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4556 # Transaction distribution -system.membus.trans_dist::ReadExReq 137047 # Transaction distribution -system.membus.trans_dist::ReadExResp 137047 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 4552 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4561 # Transaction distribution +system.membus.trans_dist::ReadExReq 137020 # Transaction distribution +system.membus.trans_dist::ReadExResp 137020 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105414 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 579034 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109015 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 109015 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 688049 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471581 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 578995 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109017 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 109017 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 688012 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159071 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16929468 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17092587 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4642496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21735083 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 289 # Total snoops (count) -system.membus.snoop_fanout::samples 341035 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16928828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17091899 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4642624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4642624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21734523 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 283 # Total snoops (count) +system.membus.snoop_fanout::samples 341064 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 341035 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 341064 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 341035 # Request fanout histogram -system.membus.reqLayer0.occupancy 40827000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 341064 # Request fanout histogram +system.membus.reqLayer0.occupancy 45631500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 469500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 463000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 937138500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 565034415 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 904275509 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 525270598 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 23892986 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 23441994 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2474,54 +2458,52 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2442249 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2442245 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 692729 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 22736 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2441800 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2441792 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27555 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27555 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 690587 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 22777 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2762 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296542 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296542 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3613854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484499 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29280 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87986 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6215619 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115099320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97925875 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49208 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154964 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 213229367 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 51973 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3430536 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.010633 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.102566 # Request fanout histogram +system.toL2Bus.trans_dist::SCUpgradeReq 19 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2781 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3617238 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2478347 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29055 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6212277 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115207096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97661699 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 48712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154828 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 213072335 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 51752 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3427725 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.010649 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.102642 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3394060 98.94% 98.94% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36476 1.06% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3391224 98.94% 98.94% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36501 1.06% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3430536 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2377189197 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 558000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3427725 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1275217471 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 177000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 4188720502 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2021336108 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 12001413 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1406471499 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 694961258 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 11749485 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 39606873 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 39124219 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index 355e87caf..ec623239f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,140 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.814515 # Number of seconds simulated -sim_ticks 2814515403000 # Number of ticks simulated -final_tick 2814515403000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.804323 # Number of seconds simulated +sim_ticks 2804323403500 # Number of ticks simulated +final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109456 # Simulator instruction rate (inst/s) -host_op_rate 132849 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2632808896 # Simulator tick rate (ticks/s) -host_mem_usage 624704 # Number of bytes of host memory used -host_seconds 1069.02 # Real time elapsed on the host -sim_insts 117010217 # Number of instructions simulated -sim_ops 142017883 # Number of ops (including micro ops) simulated +host_inst_rate 111168 # Simulator instruction rate (inst/s) +host_op_rate 134929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2664755466 # Simulator tick rate (ticks/s) +host_mem_usage 625128 # Number of bytes of host memory used +host_seconds 1052.38 # Real time elapsed on the host +sim_insts 116990114 # Number of instructions simulated +sim_ops 141995948 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 4416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 4352 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 748224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5094496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 4096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 629568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4721220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 690752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4989088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 4032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 687552 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4838852 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11203044 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 748224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 629568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1377792 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8429952 # Number of bytes written to this memory +system.physmem.bytes_read::total 11215652 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 690752 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 687552 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1378304 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8426048 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8447476 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 69 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8443572 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 68 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 11691 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 80120 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 64 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9837 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 73770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 78473 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 63 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 10743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75608 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 175567 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131718 # Number of write requests responded to by this memory +system.physmem.num_reads::total 175764 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131657 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 136099 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 1569 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 136038 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1552 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 265845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1810079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 223686 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1677454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3980452 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 265845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 223686 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 489531 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2995170 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6223 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 246317 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1779070 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 245176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1725497 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3999415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 246317 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 245176 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 491493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3004663 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3001396 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2995170 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 1569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3010912 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3004663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1552 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 265845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1816303 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 223686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1677457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6981848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 175568 # Number of read requests accepted -system.physmem.writeReqs 172295 # Number of write requests accepted -system.physmem.readBursts 175568 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 172295 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11229120 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 10657088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11203108 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10764020 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5755 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4657 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11278 # Per bank write bursts -system.physmem.perBankRdBursts::1 11187 # Per bank write bursts -system.physmem.perBankRdBursts::2 11389 # Per bank write bursts -system.physmem.perBankRdBursts::3 10916 # Per bank write bursts -system.physmem.perBankRdBursts::4 11527 # Per bank write bursts -system.physmem.perBankRdBursts::5 11542 # Per bank write bursts -system.physmem.perBankRdBursts::6 11806 # Per bank write bursts -system.physmem.perBankRdBursts::7 11898 # Per bank write bursts -system.physmem.perBankRdBursts::8 10235 # Per bank write bursts -system.physmem.perBankRdBursts::9 10554 # Per bank write bursts -system.physmem.perBankRdBursts::10 10596 # Per bank write bursts -system.physmem.perBankRdBursts::11 9816 # Per bank write bursts -system.physmem.perBankRdBursts::12 10461 # Per bank write bursts -system.physmem.perBankRdBursts::13 11360 # Per bank write bursts -system.physmem.perBankRdBursts::14 10541 # Per bank write bursts -system.physmem.perBankRdBursts::15 10349 # Per bank write bursts -system.physmem.perBankWrBursts::0 10520 # Per bank write bursts -system.physmem.perBankWrBursts::1 10540 # Per bank write bursts -system.physmem.perBankWrBursts::2 10805 # Per bank write bursts -system.physmem.perBankWrBursts::3 10377 # Per bank write bursts -system.physmem.perBankWrBursts::4 10808 # Per bank write bursts -system.physmem.perBankWrBursts::5 10825 # Per bank write bursts -system.physmem.perBankWrBursts::6 10943 # Per bank write bursts -system.physmem.perBankWrBursts::7 10998 # Per bank write bursts -system.physmem.perBankWrBursts::8 9971 # Per bank write bursts -system.physmem.perBankWrBursts::9 10108 # Per bank write bursts -system.physmem.perBankWrBursts::10 9937 # Per bank write bursts -system.physmem.perBankWrBursts::11 9693 # Per bank write bursts -system.physmem.perBankWrBursts::12 10233 # Per bank write bursts -system.physmem.perBankWrBursts::13 10896 # Per bank write bursts -system.physmem.perBankWrBursts::14 10053 # Per bank write bursts -system.physmem.perBankWrBursts::15 9810 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 246317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1785316 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 245176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1725500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7010327 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 175765 # Number of read requests accepted +system.physmem.writeReqs 172232 # Number of write requests accepted +system.physmem.readBursts 175765 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 172232 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11239872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue +system.physmem.bytesWritten 9513088 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11215716 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10759988 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23563 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4633 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11568 # Per bank write bursts +system.physmem.perBankRdBursts::1 11615 # Per bank write bursts +system.physmem.perBankRdBursts::2 11475 # Per bank write bursts +system.physmem.perBankRdBursts::3 10984 # Per bank write bursts +system.physmem.perBankRdBursts::4 11566 # Per bank write bursts +system.physmem.perBankRdBursts::5 11265 # Per bank write bursts +system.physmem.perBankRdBursts::6 12051 # Per bank write bursts +system.physmem.perBankRdBursts::7 11828 # Per bank write bursts +system.physmem.perBankRdBursts::8 10136 # Per bank write bursts +system.physmem.perBankRdBursts::9 10546 # Per bank write bursts +system.physmem.perBankRdBursts::10 10466 # Per bank write bursts +system.physmem.perBankRdBursts::11 9460 # Per bank write bursts +system.physmem.perBankRdBursts::12 10169 # Per bank write bursts +system.physmem.perBankRdBursts::13 11261 # Per bank write bursts +system.physmem.perBankRdBursts::14 10850 # Per bank write bursts +system.physmem.perBankRdBursts::15 10383 # Per bank write bursts +system.physmem.perBankWrBursts::0 9594 # Per bank write bursts +system.physmem.perBankWrBursts::1 9874 # Per bank write bursts +system.physmem.perBankWrBursts::2 9855 # Per bank write bursts +system.physmem.perBankWrBursts::3 9284 # Per bank write bursts +system.physmem.perBankWrBursts::4 9607 # Per bank write bursts +system.physmem.perBankWrBursts::5 9407 # Per bank write bursts +system.physmem.perBankWrBursts::6 10082 # Per bank write bursts +system.physmem.perBankWrBursts::7 9751 # Per bank write bursts +system.physmem.perBankWrBursts::8 8758 # Per bank write bursts +system.physmem.perBankWrBursts::9 9037 # Per bank write bursts +system.physmem.perBankWrBursts::10 8724 # Per bank write bursts +system.physmem.perBankWrBursts::11 8208 # Per bank write bursts +system.physmem.perBankWrBursts::12 8857 # Per bank write bursts +system.physmem.perBankWrBursts::13 9711 # Per bank write bursts +system.physmem.perBankWrBursts::14 9203 # Per bank write bursts +system.physmem.perBankWrBursts::15 8690 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2814515217000 # Total gap between requests +system.physmem.numWrRetry 53 # Number of times write queue was full causing retry +system.physmem.totGap 2804323239500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 175013 # Read request sizes (log2) +system.physmem.readPktSize::6 175210 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 167914 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 104295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8447 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167851 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 103659 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61692 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 8548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1701 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1 # What read queue length does an incoming req see @@ -161,198 +161,173 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 101 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 89 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2228 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3809 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11398 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10784 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9993 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66987 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 326.722260 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.177109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 345.277059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24335 36.33% 36.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15823 23.62% 59.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6599 9.85% 69.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3701 5.52% 75.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2840 4.24% 79.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1617 2.41% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1134 1.69% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1090 1.63% 85.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9848 14.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66987 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.589488 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 462.801411 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7132 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.338052 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.587494 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 21.995044 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 12 0.17% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 6 0.08% 0.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 5 0.07% 0.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 6 0.08% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5911 82.85% 83.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 110 1.54% 84.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 53 0.74% 85.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 225 3.15% 88.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 144 2.02% 90.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.70% 91.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 36 0.50% 91.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 29 0.41% 92.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 105 1.47% 93.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.24% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.14% 94.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.20% 94.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 31 0.43% 94.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 18 0.25% 95.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.13% 95.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 33 0.46% 95.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 56 0.78% 96.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.20% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.08% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 11 0.15% 96.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 75 1.05% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 8 0.11% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 14 0.20% 98.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 98.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 17 0.24% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 5 0.07% 98.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 6 0.08% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.07% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 32 0.45% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.10% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.08% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 5 0.07% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 7 0.10% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.04% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7135 # Writes before turning the bus around for reads -system.physmem.totQLat 2670855500 # Total ticks spent queuing -system.physmem.totMemAccLat 5960636750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 877275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 15222.45 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::9 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 82 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1608 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7418 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1200 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1780 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1497 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1465 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 112 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 314.556969 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.654540 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 335.497717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24476 37.10% 37.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15740 23.86% 60.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6623 10.04% 71.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3719 5.64% 76.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2901 4.40% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1575 2.39% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1142 1.73% 85.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1107 1.68% 86.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8692 13.17% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65975 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6306 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.843324 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 438.660877 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6303 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-6143 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6306 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6306 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.571519 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.321112 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 39.451011 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 32 0.51% 0.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5917 93.83% 94.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 88 1.40% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 21 0.33% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 16 0.25% 96.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 33 0.52% 96.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 35 0.56% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 27 0.43% 97.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.21% 98.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.27% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 20 0.32% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 8 0.13% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.08% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.03% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 9 0.14% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.10% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 4 0.06% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 11 0.17% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 6 0.10% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6306 # Writes before turning the bus around for reads +system.physmem.totQLat 2686689750 # Total ticks spent queuing +system.physmem.totMemAccLat 5979621000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 878115000 # Total ticks spent in databus transfers +system.physmem.avgQLat 15298.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 33972.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.79 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.98 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.82 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 34048.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.84 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.20 # Average write queue length when enqueuing -system.physmem.readRowHits 145151 # Number of row buffer hits during reads -system.physmem.writeRowHits 129833 # Number of row buffer hits during writes +system.physmem.avgRdQLen 1.64 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.09 # Average write queue length when enqueuing +system.physmem.readRowHits 145297 # Number of row buffer hits during reads +system.physmem.writeRowHits 112992 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.73 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.96 # Row buffer hit rate for writes -system.physmem.avgGap 8090872.61 # Average gap between requests -system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 265386240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 144804000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 714027600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 556087680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 183830200320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 77881590900 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1620389778750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1883781875490 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.310395 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2695567326750 # Time in different power states -system.physmem_0.memoryStateTime::REF 93982720000 # Time in different power states +system.physmem.writeRowHitRate 76.00 # Row buffer hit rate for writes +system.physmem.avgGap 8058469.58 # Average gap between requests +system.physmem.pageHitRate 79.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 264138840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 144123375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 720337800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 501901920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 183164495280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 78122450385 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1614063177750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1876980625350 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.317704 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2685041541216 # Time in different power states +system.physmem_0.memoryStateTime::REF 93642380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 24965345250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 25639471784 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 241035480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 131517375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654513600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 522942480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 183830200320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 77208822180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1620979926750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1883568958185 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.234745 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2696551299250 # Time in different power states -system.physmem_1.memoryStateTime::REF 93982720000 # Time in different power states +system.physmem_1.actEnergy 234632160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 128023500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 649513800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 461298240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 183164495280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 76868306460 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1615163304000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1876669573440 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.206785 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2686874826210 # Time in different power states +system.physmem_1.memoryStateTime::REF 93642380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 23977600750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 23802212540 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 640 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory @@ -360,27 +335,27 @@ system.realview.nvmem.bytes_inst_read::cpu0.inst 640 system.realview.nvmem.bytes_inst_read::total 640 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 10 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 10 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 227 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 227 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 227 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 227 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 227 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 227 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 228 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 228 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 228 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 228 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 228 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 27466718 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14314218 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 559197 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 17107445 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 12928393 # Number of BTB hits +system.cpu0.branchPred.lookups 26894348 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13975310 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 545296 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 16832825 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 12628735 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 75.571735 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 6777363 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 30194 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 75.024454 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 6673545 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29900 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,96 +386,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 58720 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 58720 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 19962 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14154 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 24604 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 34116 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 475.187595 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3075.067201 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 33369 97.81% 97.81% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 426 1.25% 99.06% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 228 0.67% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 49 0.14% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 17 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 15 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 6 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 34116 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 12972 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12168.830173 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9642.893366 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7992.253434 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-8191 3564 27.47% 27.47% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::8192-16383 6077 46.85% 74.32% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2864 22.08% 96.40% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::24576-32767 230 1.77% 98.17% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-40959 90 0.69% 98.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::40960-49151 115 0.89% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-57343 10 0.08% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::57344-65535 3 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-73727 2 0.02% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::73728-81919 10 0.08% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-90111 4 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::90112-98303 2 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-106495 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 12972 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 78620736948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.741175 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.458010 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 78549397948 99.91% 99.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 52259000 0.07% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 9664500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 3325500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 2093000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1088000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 676500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1423500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 291000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 117500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-21 73500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::22-23 71500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-25 138500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::26-27 55500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-29 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::30-31 55500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 78620736948 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3790 68.96% 68.96% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1706 31.04% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 5496 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 58720 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 59638 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 59638 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 19278 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 14808 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 25552 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 34086 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 541.028575 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3545.315816 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-16383 33770 99.07% 99.07% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-32767 252 0.74% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-49151 35 0.10% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-65535 20 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-81919 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::98304-114687 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-147455 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 34086 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 11896 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11442.270763 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9167.474880 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7450.500727 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-8191 3982 33.47% 33.47% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::8192-16383 5461 45.91% 79.38% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-24575 2160 18.16% 97.54% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::24576-32767 140 1.18% 98.71% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-40959 47 0.40% 99.11% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::40960-49151 93 0.78% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-57343 3 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::57344-65535 3 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-73727 4 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-90111 1 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::90112-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::106496-114687 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 11896 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 76466975540 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.696036 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.478552 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 76445440540 99.97% 99.97% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 15483000 0.02% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 3531500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 1916000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 394500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 120500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 34000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 54000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 76466975540 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3544 69.19% 69.19% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1578 30.81% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5122 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 59638 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 58720 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5496 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 59638 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5122 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5496 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 64216 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5122 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 64760 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 14377700 # DTB read hits -system.cpu0.dtb.read_misses 50689 # DTB read misses -system.cpu0.dtb.write_hits 10391095 # DTB write hits -system.cpu0.dtb.write_misses 8031 # DTB write misses +system.cpu0.dtb.read_hits 13978309 # DTB read hits +system.cpu0.dtb.read_misses 51149 # DTB read misses +system.cpu0.dtb.write_hits 10338750 # DTB write hits +system.cpu0.dtb.write_misses 8489 # DTB write misses system.cpu0.dtb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 456 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3541 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1016 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1359 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3463 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 922 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1428 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 592 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 14428389 # DTB read accesses -system.cpu0.dtb.write_accesses 10399126 # DTB write accesses +system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 14029458 # DTB read accesses +system.cpu0.dtb.write_accesses 10347239 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 24768795 # DTB hits -system.cpu0.dtb.misses 58720 # DTB misses -system.cpu0.dtb.accesses 24827515 # DTB accesses +system.cpu0.dtb.hits 24317059 # DTB hits +system.cpu0.dtb.misses 59638 # DTB misses +system.cpu0.dtb.accesses 24376697 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -530,636 +493,640 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 8876 # Table walker walks requested -system.cpu0.itb.walker.walksShort 8876 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3394 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5333 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 149 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 8727 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1034.949009 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 4440.773831 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-8191 8334 95.50% 95.50% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-16383 202 2.31% 97.81% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-24575 114 1.31% 99.12% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-32767 44 0.50% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-40959 18 0.21% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-49151 9 0.10% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::49152-57343 3 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::57344-65535 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 8727 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2584 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12070.828560 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9384.773588 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 7691.454372 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 754 29.18% 29.18% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1107 42.84% 72.02% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 648 25.08% 97.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 49 1.90% 98.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 17 0.66% 99.65% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 4 0.15% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-57343 3 0.12% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 8503 # Table walker walks requested +system.cpu0.itb.walker.walksShort 8503 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3306 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5069 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 128 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 8375 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1173.014925 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 5467.905811 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-8191 7973 95.20% 95.20% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-16383 197 2.35% 97.55% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-24575 109 1.30% 98.85% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-32767 49 0.59% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-40959 12 0.14% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-49151 14 0.17% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::49152-57343 5 0.06% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::57344-65535 7 0.08% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-73727 2 0.02% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::73728-81919 4 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::90112-98303 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-106495 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 8375 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2444 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12500.308511 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 9992.698413 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 7939.202624 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 801 32.77% 32.77% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 949 38.83% 71.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 632 25.86% 97.46% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 25 1.02% 98.49% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 24 0.98% 99.47% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 9 0.37% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 2 0.08% 99.92% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::73728-81919 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2584 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 31375770192 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.875900 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.330034 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3896845928 12.42% 12.42% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 27476174764 87.57% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 2435000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 275000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 39500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 31375770192 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1855 76.18% 76.18% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 580 23.82% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2435 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::65536-73727 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2444 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 29185295284 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.914937 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.279656 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 2486739500 8.52% 8.52% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 26695454284 91.47% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 2358500 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 523000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 145500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 74500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 29185295284 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1760 75.99% 75.99% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 556 24.01% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2316 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8876 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8876 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 8503 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 8503 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2435 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2435 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 11311 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 20634228 # ITB inst hits -system.cpu0.itb.inst_misses 8876 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2316 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2316 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 10819 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 20234859 # ITB inst hits +system.cpu0.itb.inst_misses 8503 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 181 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 478 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 456 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2373 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2268 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1477 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1416 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 20643104 # ITB inst accesses -system.cpu0.itb.hits 20634228 # DTB hits -system.cpu0.itb.misses 8876 # DTB misses -system.cpu0.itb.accesses 20643104 # DTB accesses -system.cpu0.numCycles 108167671 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 20243362 # ITB inst accesses +system.cpu0.itb.hits 20234859 # DTB hits +system.cpu0.itb.misses 8503 # DTB misses +system.cpu0.itb.accesses 20243362 # DTB accesses +system.cpu0.numCycles 106376136 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 40851007 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 106236775 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 27466718 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 19705756 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 62062972 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3267693 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 153669 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 7048 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 432 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 489783 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 144519 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 202 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 20632894 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 382391 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3679 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 105343442 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.211364 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.309053 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 39965142 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 103919162 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 26894348 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 19302280 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 61475471 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3204102 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 133084 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 4359 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 386 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 482542 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 142714 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 389 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 20233629 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 371892 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3629 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 103806101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.204244 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.303663 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 76103279 72.24% 72.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 3910098 3.71% 75.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 2412212 2.29% 78.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 8199484 7.78% 86.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1671331 1.59% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 1069053 1.01% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 6251821 5.93% 94.56% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 1074556 1.02% 95.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4651608 4.42% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 75119256 72.36% 72.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 3853264 3.71% 76.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 2394905 2.31% 78.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 8055629 7.76% 86.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1633408 1.57% 87.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 1025690 0.99% 88.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 6108914 5.88% 94.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 1037923 1.00% 95.59% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4577112 4.41% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 105343442 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.253927 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.982149 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 28225112 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 58231710 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 15904811 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 1498973 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1482577 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1930879 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 153387 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 88028064 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 497001 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1482577 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 29091969 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 7814173 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 44573853 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 16523893 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 5856699 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 84168015 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2790 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 1211369 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 234681 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 3674238 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 86834114 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 387462225 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 93765985 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 6215 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 72808994 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14025104 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1551576 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1456348 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 8924255 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 15135142 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 11528605 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1955130 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2746979 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 80972727 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1061733 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 77600115 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 93477 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10225467 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 25113988 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 116264 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 105343442 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.736639 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.430545 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 103806101 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.252823 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.976903 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 27584011 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 57734540 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 15584006 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 1449686 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1453608 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1869283 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 150514 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 86108463 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 484067 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1453608 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 28423517 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 6508141 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 43695790 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 16185317 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 7539460 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 82326363 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 3052 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 1072870 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 278724 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 5472953 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 84763927 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 379438570 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 91864230 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 6406 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 71037693 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13726234 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1533064 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1439152 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 8446360 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 14835811 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 11457004 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1997727 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2772041 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 79153572 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1058697 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 75784801 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 96696 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10015024 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 24599963 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 115562 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 103806101 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.730061 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.422275 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 74430085 70.65% 70.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 10248464 9.73% 80.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 7900647 7.50% 87.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 6607763 6.27% 94.16% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2341378 2.22% 96.38% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1506364 1.43% 97.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 1572871 1.49% 99.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 494450 0.47% 99.77% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 241420 0.23% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 73542195 70.85% 70.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 10050115 9.68% 80.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 7748986 7.46% 87.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 6432670 6.20% 94.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2352911 2.27% 96.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1476701 1.42% 97.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 1498599 1.44% 99.32% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 479431 0.46% 99.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 224493 0.22% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 105343442 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 103806101 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 114775 10.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 10.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 538516 46.90% 56.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 494955 43.11% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 98458 8.93% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 1 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 516893 46.87% 55.80% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 487368 44.20% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 2213 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 51768146 66.71% 66.71% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 57542 0.07% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 2 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 1 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 4481 0.01% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 14787493 19.06% 85.85% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 10980227 14.15% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2186 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 50425393 66.54% 66.54% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 57237 0.08% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 4320 0.01% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.62% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 14387296 18.98% 85.61% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 10908366 14.39% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 77600115 # Type of FU issued -system.cpu0.iq.rate 0.717406 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1148249 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.014797 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 261771758 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 92305365 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 75123288 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 13640 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 7254 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5910 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 78738792 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 7359 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 349889 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 75784801 # Type of FU issued +system.cpu0.iq.rate 0.712423 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1102720 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.014551 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 256560915 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 90272679 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 73457837 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 14204 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 7628 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 6340 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 76877738 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 7597 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 359549 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2246274 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2500 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 53675 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1142950 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2204717 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2719 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 54058 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1152347 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 210780 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 206750 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 205467 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 94593 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1482577 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 5380945 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 2158862 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 82157406 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 132522 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 15135142 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 11528605 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 554173 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44324 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2102450 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 53675 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 259338 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 224546 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 483884 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 76981591 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 14546003 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 559940 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1453608 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 5664191 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 635354 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 80356167 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 128884 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 14835811 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 11457004 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 551529 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 43992 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 579512 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 54058 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 250397 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 220538 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 470935 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 75169409 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 14142783 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 555867 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 122946 # number of nop insts executed -system.cpu0.iew.exec_refs 25419191 # number of memory reference insts executed -system.cpu0.iew.exec_branches 14512373 # Number of branches executed -system.cpu0.iew.exec_stores 10873188 # Number of stores executed -system.cpu0.iew.exec_rate 0.711688 # Inst execution rate -system.cpu0.iew.wb_sent 76311316 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 75129198 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 39246313 # num instructions producing a value -system.cpu0.iew.wb_consumers 68010606 # num instructions consuming a value +system.cpu0.iew.exec_nop 143898 # number of nop insts executed +system.cpu0.iew.exec_refs 24942986 # number of memory reference insts executed +system.cpu0.iew.exec_branches 14187310 # Number of branches executed +system.cpu0.iew.exec_stores 10800203 # Number of stores executed +system.cpu0.iew.exec_rate 0.706638 # Inst execution rate +system.cpu0.iew.wb_sent 74627910 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 73464177 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 38231116 # num instructions producing a value +system.cpu0.iew.wb_consumers 66477839 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.694562 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.577062 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.690608 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575096 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 11503261 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 945469 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 407891 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 102758261 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.686747 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.577053 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 11279021 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 943135 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 396816 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 101272480 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.681216 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.570732 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 75291319 73.27% 73.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 12321005 11.99% 85.26% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 6288153 6.12% 91.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 2655881 2.58% 93.96% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1298740 1.26% 95.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 839233 0.82% 96.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1891164 1.84% 97.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 416236 0.41% 98.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1756530 1.71% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 74367990 73.43% 73.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 12119249 11.97% 85.40% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 6128079 6.05% 91.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 2581969 2.55% 94.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1298466 1.28% 95.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 821679 0.81% 96.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1839446 1.82% 97.91% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 396658 0.39% 98.30% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1718944 1.70% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 102758261 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 58183568 # Number of instructions committed -system.cpu0.commit.committedOps 70568955 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 101272480 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 56718354 # Number of instructions committed +system.cpu0.commit.committedOps 68988407 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 23274523 # Number of memory references committed -system.cpu0.commit.loads 12888868 # Number of loads committed -system.cpu0.commit.membars 375842 # Number of memory barriers committed -system.cpu0.commit.branches 13706650 # Number of branches committed -system.cpu0.commit.fp_insts 5838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 61788721 # Number of committed integer instructions. -system.cpu0.commit.function_calls 2663542 # Number of function calls committed. +system.cpu0.commit.refs 22935751 # Number of memory references committed +system.cpu0.commit.loads 12631094 # Number of loads committed +system.cpu0.commit.membars 378784 # Number of memory barriers committed +system.cpu0.commit.branches 13402892 # Number of branches committed +system.cpu0.commit.fp_insts 6286 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 60396974 # Number of committed integer instructions. +system.cpu0.commit.function_calls 2623511 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 47234123 66.93% 66.93% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 55828 0.08% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 4481 0.01% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.02% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 12888868 18.26% 85.28% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 10385655 14.72% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 45992810 66.67% 66.67% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 55529 0.08% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 4317 0.01% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.75% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 12631094 18.31% 85.06% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 10304657 14.94% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 70568955 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1756530 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 68988407 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1718944 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 170410924 # The number of ROB reads -system.cpu0.rob.rob_writes 166734025 # The number of ROB writes -system.cpu0.timesIdled 403289 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 2824229 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2462180705 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 58113002 # Number of Instructions Simulated -system.cpu0.committedOps 70498389 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.861333 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.861333 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.537249 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.537249 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 83710036 # number of integer regfile reads -system.cpu0.int_regfile_writes 47877732 # number of integer regfile writes -system.cpu0.fp_regfile_reads 16593 # number of floating regfile reads -system.cpu0.fp_regfile_writes 13071 # number of floating regfile writes -system.cpu0.cc_regfile_reads 272135235 # number of cc regfile reads -system.cpu0.cc_regfile_writes 28380305 # number of cc regfile writes -system.cpu0.misc_regfile_reads 192072102 # number of misc regfile reads -system.cpu0.misc_regfile_writes 725098 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 853107 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.984634 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 42535549 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 853619 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.829665 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 91705250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 327.353563 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 184.631071 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.639362 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.360608 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 167372763 # The number of ROB reads +system.cpu0.rob.rob_writes 163072923 # The number of ROB writes +system.cpu0.timesIdled 393865 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 2570035 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2956119679 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 56633353 # Number of Instructions Simulated +system.cpu0.committedOps 68903406 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.878330 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.878330 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.532388 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.532388 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 81817364 # number of integer regfile reads +system.cpu0.int_regfile_writes 46775146 # number of integer regfile writes +system.cpu0.fp_regfile_reads 16878 # number of floating regfile reads +system.cpu0.fp_regfile_writes 13235 # number of floating regfile writes +system.cpu0.cc_regfile_reads 265909763 # number of cc regfile reads +system.cpu0.cc_regfile_writes 27649979 # number of cc regfile writes +system.cpu0.misc_regfile_reads 189136920 # number of misc regfile reads +system.cpu0.misc_regfile_writes 724107 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 853909 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.982202 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42514992 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 854421 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 49.758833 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 105520250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 184.898512 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 327.083689 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.361130 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.638835 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999965 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 188 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 189955198 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 189955198 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 12681674 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 12667533 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25349207 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 7766233 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 8148068 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15914301 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181732 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 180331 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 362063 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209455 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 237675 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 447130 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 215313 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 244405 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 459718 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20447907 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20815601 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41263508 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20629639 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 20995932 # number of overall hits -system.cpu0.dcache.overall_hits::total 41625571 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 429725 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 402525 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 832250 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1921923 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1778424 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 3700347 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 98138 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 84449 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 182587 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13508 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14201 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 27709 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 30 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 48 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 78 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2351648 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 2180949 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4532597 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2449786 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 2265398 # number of overall misses -system.cpu0.dcache.overall_misses::total 4715184 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7060794359 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6694788448 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13755582807 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 83430874942 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 75332466558 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 158763341500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 183117244 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 210458494 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 393575738 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 643510 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 802514 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 1446024 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 90491669301 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 82027255006 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 172518924307 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 90491669301 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 82027255006 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 172518924307 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 13111399 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 13070058 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26181457 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9688156 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9926492 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19614648 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 279870 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 264780 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 544650 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 222963 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 251876 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 474839 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 215343 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 244453 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 459796 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 22799555 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 22996550 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 45796105 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 23079425 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 23261330 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 46340755 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032775 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030797 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.031788 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.198379 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.179159 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.188652 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.350656 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.318940 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.335237 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060584 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056381 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058355 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000139 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000196 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000170 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.103144 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.094838 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.098973 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.106146 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.097389 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.101750 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16430.960170 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16631.981735 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 16528.186010 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43410.102768 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 42359.114901 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 42904.987424 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13556.206988 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14819.977044 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14203.895413 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21450.333333 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 16719.041667 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18538.769231 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 38480.108120 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 37610.808417 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 38061.827316 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36938.601699 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 36208.761112 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36587.951670 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1102752 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 157342 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 69674 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 2409 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.827310 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 65.314238 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 189859724 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 189859724 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 12422539 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 12908546 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 25331085 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 7676552 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 8235772 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15912324 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 178433 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 183837 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 362270 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 209755 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 237006 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 446761 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216045 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 243370 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 459415 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 20099091 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 21144318 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41243409 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 20277524 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 21328155 # number of overall hits +system.cpu0.dcache.overall_hits::total 41605679 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 408353 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 423480 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 831833 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1950457 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1746190 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 3696647 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 84124 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 98955 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 183079 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13813 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 14039 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 27852 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 34 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 55 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2358810 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 2169670 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4528480 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2442934 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 2268625 # number of overall misses +system.cpu0.dcache.overall_misses::total 4711559 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6108609853 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 6466487368 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 12575097221 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 85969014596 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 79541032692 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 165510047288 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 182474999 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 208223500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 390698499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 466006 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 533501 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 999507 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 92077624449 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 86007520060 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 178085144509 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 92077624449 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 86007520060 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 178085144509 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 12830892 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 13332026 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 26162918 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9627009 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9981962 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19608971 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 262557 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 282792 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 545349 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 223568 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 251045 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 474613 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216066 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 243404 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 459470 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 22457901 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 23313988 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 45771889 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 22720458 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 23596780 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 46317238 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.031826 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031764 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.031794 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.202603 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.174935 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.188518 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.320403 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.349921 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.335710 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061784 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.055922 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000097 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000140 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000120 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.105033 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.093063 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.098936 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.107521 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.096141 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.101724 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14959.140383 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15269.876660 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15117.333913 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44076.344465 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 45551.190129 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44773.019249 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13210.381452 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14831.790014 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14027.664046 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22190.761905 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 15691.205882 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 18172.854545 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39035.625781 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 39640.830200 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 39325.589273 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37691.408957 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 37911.739516 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37797.498558 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1124276 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 180492 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 53485 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 2944 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.020398 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 61.308424 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 703765 # number of writebacks -system.cpu0.dcache.writebacks::total 703765 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 215820 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 190387 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 406207 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1767730 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1633312 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3401042 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9415 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8962 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18377 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1983550 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1823699 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 3807249 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1983550 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1823699 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 3807249 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 213905 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 212138 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 426043 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 154193 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 145112 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 299305 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 64082 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 57716 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 121798 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4093 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5239 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9332 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 30 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 48 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 78 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 368098 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 357250 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 725348 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 432180 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 414966 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 847146 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2879120711 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2930558911 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5809679622 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6700541283 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6184063438 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 12884604721 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 975154510 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 900261506 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1875416016 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 47931501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80133502 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 128065003 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 583490 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 706486 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 1289976 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9579661994 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9114622349 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 18694284343 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10554816504 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10014883855 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 20569700359 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3162299001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2622267000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5784566001 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2409236377 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2026898500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4436134877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5571535378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4649165500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10220700878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016314 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016231 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016273 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015916 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014619 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015259 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228971 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.217977 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223626 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018357 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020800 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019653 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000139 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000196 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000170 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016145 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015535 # mshr miss rate for demand accesses +system.cpu0.dcache.writebacks::writebacks 704443 # number of writebacks +system.cpu0.dcache.writebacks::total 704443 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 195410 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 211050 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 406460 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1794100 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1602957 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3397057 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 9538 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8888 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18426 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1989510 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1814007 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 3803517 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1989510 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1814007 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 3803517 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 212943 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 212430 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 425373 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 156357 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 143233 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 299590 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 58111 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64761 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 122872 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4275 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 5151 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9426 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 34 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 55 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369300 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 355663 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 724963 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 427411 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 420424 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 847835 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2911652660 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2946522646 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5858175306 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7110951020 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6670158760 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 13781109780 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 777722500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 894500250 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1672222750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 53569251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82009500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 135578751 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 434494 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 482499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 916993 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10022603680 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9616681406 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 19639285086 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10800326180 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10511181656 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 21311507836 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3107181500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2733312000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5840493500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2374455377 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2136736500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4511191877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5481636877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 4870048500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10351685377 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015934 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016241 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015278 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.221327 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.229006 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225309 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.019122 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020518 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019860 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000097 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000140 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000120 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016444 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.015255 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.015839 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018726 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017839 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018281 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13459.810248 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13814.398698 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13636.369151 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 43455.547807 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42615.796337 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43048.411223 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15217.292063 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15598.127140 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15397.757073 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11710.603714 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15295.572056 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13723.210780 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19449.666667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14718.458333 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16538.153846 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26024.759694 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 25513.288591 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25772.848816 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24422.269665 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24134.227515 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24281.175097 # average overall mshr miss latency +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018812 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.017817 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018305 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13673.389874 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13870.558047 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13771.855068 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 45478.942548 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 46568.589361 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 45999.899129 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13383.395571 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13812.329180 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13609.469611 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12530.818947 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15921.083285 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14383.487269 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20690.190476 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 14191.147059 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 16672.600000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 27139.462984 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 27038.745683 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 27090.051611 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25269.181607 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25001.383499 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25136.386014 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1170,150 +1137,150 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1946899 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.580862 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 39112552 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1947411 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 20.084385 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9482142250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 275.928996 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 235.651865 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.538924 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.460258 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1944350 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.567211 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 39122099 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1944862 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 20.115617 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9678062250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 228.929190 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 282.638021 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.447127 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.552027 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999155 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 150 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 43147534 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 43147534 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 19581661 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 19530891 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 39112552 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 19581661 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 19530891 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 39112552 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 19581661 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 19530891 # number of overall hits -system.cpu0.icache.overall_hits::total 39112552 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1050570 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 1036904 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2087474 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1050570 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 1036904 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2087474 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1050570 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 1036904 # number of overall misses -system.cpu0.icache.overall_misses::total 2087474 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14373129884 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14097990125 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 28471120009 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 14373129884 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 14097990125 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 28471120009 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 14373129884 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 14097990125 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 28471120009 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 20632231 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 20567795 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 41200026 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 20632231 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 20567795 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 41200026 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 20632231 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 20567795 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 41200026 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050919 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050414 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050667 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050919 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.050414 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050667 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050919 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.050414 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050667 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13681.268153 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13596.234680 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13639.029760 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13681.268153 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13596.234680 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13639.029760 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13681.268153 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13596.234680 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13639.029760 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8502 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 43155983 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 43155983 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 19191895 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 19930204 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 39122099 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 19191895 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 19930204 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 39122099 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 19191895 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 19930204 # number of overall hits +system.cpu0.icache.overall_hits::total 39122099 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1041065 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 1047869 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2088934 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1041065 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 1047869 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2088934 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1041065 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 1047869 # number of overall misses +system.cpu0.icache.overall_misses::total 2088934 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14016266373 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14162864905 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28179131278 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14016266373 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 14162864905 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28179131278 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14016266373 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 14162864905 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28179131278 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 20232960 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 20978073 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 41211033 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 20232960 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 20978073 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 41211033 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 20232960 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 20978073 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 41211033 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051454 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.049951 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050689 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051454 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.049951 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050689 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051454 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.049951 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050689 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13463.392173 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13515.873554 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.718334 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13515.873554 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13489.718334 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.873554 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13489.718334 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 10636 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 563 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 597 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.101243 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.815745 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 70345 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 69620 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 139965 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 70345 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 69620 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 139965 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 70345 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 69620 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 139965 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 980225 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 967284 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1947509 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 980225 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 967284 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1947509 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 980225 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 967284 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1947509 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11736390069 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11515392307 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 23251782376 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11736390069 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 11515392307 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 23251782376 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11736390069 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 11515392307 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 23251782376 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 49454750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 49454750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 49454750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 49454750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047509 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.047029 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047270 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047509 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.047029 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.047270 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047509 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.047029 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.047270 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11973.159294 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11904.872103 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11939.242579 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11973.159294 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11904.872103 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11939.242579 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11973.159294 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11904.872103 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11939.242579 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 71345 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 72638 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 143983 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 71345 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 72638 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 143983 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 71345 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 72638 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 143983 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 969720 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 975231 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1944951 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 969720 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 975231 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1944951 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 969720 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 975231 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1944951 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11896534814 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 12012710558 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 23909245372 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11896534814 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12012710558 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 23909245372 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11896534814 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 12012710558 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 23909245372 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52863250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52863250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52863250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 52863250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.047928 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.047195 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.047928 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.047195 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.047928 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.047195 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.980837 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.980837 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12292.980837 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 27252662 # Number of BP lookups -system.cpu1.branchPred.condPredicted 14161158 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 545075 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 17238794 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 12795126 # Number of BTB hits +system.cpu1.branchPred.lookups 27831531 # Number of BP lookups +system.cpu1.branchPred.condPredicted 14488346 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 557776 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 17618092 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 13095982 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 74.222860 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 6755804 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 29339 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 74.332578 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 6872630 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 30030 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1343,94 +1310,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 58706 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 58706 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19477 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 14176 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 25053 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 33653 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 557.840311 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3475.112155 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-8191 32827 97.55% 97.55% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-16383 501 1.49% 99.03% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-24575 206 0.61% 99.65% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-32767 52 0.15% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-40959 23 0.07% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-49151 18 0.05% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-57343 14 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::57344-65535 2 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-73727 2 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::81920-90111 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::90112-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-106495 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::122880-131071 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 33653 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 11554 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10457.034101 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8151.140813 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7042.402736 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 4078 35.30% 35.30% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5524 47.81% 83.11% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1648 14.26% 97.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 166 1.44% 98.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 76 0.66% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 59 0.51% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::73728-81919 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 11554 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 82024244244 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.681515 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.487291 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 81955384244 99.92% 99.92% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 50513000 0.06% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 9145000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 3183000 0.00% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 1958500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 1084000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 660000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 995500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 376500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 124000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-21 98500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::22-23 69500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-25 91500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::26-27 76000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-29 274000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::30-31 211000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 82024244244 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3372 68.52% 68.52% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1549 31.48% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 4921 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58706 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 58148 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 58148 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 20423 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 13441 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 24284 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 33864 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 507.057642 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3287.460249 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-16383 33558 99.10% 99.10% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-32767 245 0.72% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-49151 40 0.12% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-65535 17 0.05% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::81920-98303 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::98304-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-147455 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 33864 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 11833 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12004.944308 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9742.881321 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7470.572043 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 3519 29.74% 29.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 5647 47.72% 77.46% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 2322 19.62% 97.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 174 1.47% 98.55% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 60 0.51% 99.06% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 104 0.88% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 1 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 3 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 11833 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 89903617428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.686126 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.480378 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 89833985928 99.92% 99.92% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 50516000 0.06% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 9974500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 3130500 0.00% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 1885500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 1212500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 715000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 1356000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 345000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 227000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-21 44000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::22-23 32500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-25 52500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::26-27 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-29 23000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::30-31 95000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 89903617428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3585 68.60% 68.60% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1641 31.40% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5226 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 58148 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58706 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 4921 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 58148 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5226 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 4921 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 63627 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5226 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 63374 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 14299827 # DTB read hits -system.cpu1.dtb.read_misses 48713 # DTB read misses -system.cpu1.dtb.write_hits 10649623 # DTB write hits -system.cpu1.dtb.write_misses 9993 # DTB write misses -system.cpu1.dtb.flush_tlb 175 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 14522718 # DTB read hits +system.cpu1.dtb.read_misses 49745 # DTB read misses +system.cpu1.dtb.write_hits 10695995 # DTB write hits +system.cpu1.dtb.write_misses 8403 # DTB write misses +system.cpu1.dtb.flush_tlb 177 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 461 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 3345 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 749 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1307 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 3436 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 922 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 1213 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 516 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 14348540 # DTB read accesses -system.cpu1.dtb.write_accesses 10659616 # DTB write accesses +system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 14572463 # DTB read accesses +system.cpu1.dtb.write_accesses 10704398 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 24949450 # DTB hits -system.cpu1.dtb.misses 58706 # DTB misses -system.cpu1.dtb.accesses 25008156 # DTB accesses +system.cpu1.dtb.hits 25218713 # DTB hits +system.cpu1.dtb.misses 58148 # DTB misses +system.cpu1.dtb.accesses 25276861 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1460,392 +1421,389 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 7607 # Table walker walks requested -system.cpu1.itb.walker.walksShort 7607 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2551 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 4918 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 138 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 7469 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1253.983130 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 5505.331618 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-8191 7086 94.87% 94.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-16383 200 2.68% 97.55% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-24575 109 1.46% 99.01% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-32767 32 0.43% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-40959 14 0.19% 99.63% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::40960-49151 11 0.15% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::57344-65535 6 0.08% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-73727 6 0.08% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::81920-90111 3 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::106496-114687 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 7469 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2377 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11683.850652 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8982.900240 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 7620.243918 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 698 29.36% 29.36% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 50 2.10% 31.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 916 38.54% 70.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 82 3.45% 73.45% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 34 1.43% 74.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 536 22.55% 97.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 26 1.09% 98.53% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 4 0.17% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 7 0.29% 98.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 17 0.72% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 6 0.25% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2377 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 26182117896 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.680154 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.466824 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 8377919500 32.00% 32.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 17801455396 67.99% 99.99% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 2155000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 325500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 194500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 68000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 26182117896 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1688 75.39% 75.39% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 551 24.61% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2239 # Table walker page sizes translated +system.cpu1.itb.walker.walks 7828 # Table walker walks requested +system.cpu1.itb.walker.walksShort 7828 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2631 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 5055 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 142 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 7686 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1468.839448 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 6467.961047 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-8191 7241 94.21% 94.21% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-16383 210 2.73% 96.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-24575 113 1.47% 98.41% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-32767 52 0.68% 99.09% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-40959 17 0.22% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::40960-49151 18 0.23% 99.54% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-57343 9 0.12% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::57344-65535 10 0.13% 99.79% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-73727 7 0.09% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::73728-81919 6 0.08% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::81920-90111 3 0.04% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 7686 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2491 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12581.694099 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10170.903635 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 7854.515527 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 763 30.63% 30.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1045 41.95% 72.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 622 24.97% 97.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 29 1.16% 98.72% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 22 0.88% 99.60% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 6 0.24% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2491 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 25478819488 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.779989 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.414945 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 5610872428 22.02% 22.02% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 19864341560 77.96% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 2357000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 850000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 398500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 25478819488 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1770 75.35% 75.35% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 579 24.65% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2349 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7607 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7607 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 7828 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 7828 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2239 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2239 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 9846 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 20569517 # ITB inst hits -system.cpu1.itb.inst_misses 7607 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2349 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2349 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 10177 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 20979938 # ITB inst hits +system.cpu1.itb.inst_misses 7828 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 175 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 439 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 177 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 461 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2207 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2294 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1289 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1372 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 20577124 # ITB inst accesses -system.cpu1.itb.hits 20569517 # DTB hits -system.cpu1.itb.misses 7607 # DTB misses -system.cpu1.itb.accesses 20577124 # DTB accesses -system.cpu1.numCycles 107002102 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 20987766 # ITB inst accesses +system.cpu1.itb.hits 20979938 # DTB hits +system.cpu1.itb.misses 7828 # DTB misses +system.cpu1.itb.accesses 20987766 # DTB accesses +system.cpu1.numCycles 108755615 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 40500350 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 106310459 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 27252662 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 19550930 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 61683449 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3213099 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 111780 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 3981 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 436 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 347701 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 135656 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 234 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20567798 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 376508 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3292 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 104390100 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.225611 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.323253 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 40802320 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108613899 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 27831531 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 19968612 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 63156516 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3276855 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 120748 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 7463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 413 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 335058 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 133595 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 290 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 20978077 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 379105 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3473 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 106194794 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.229505 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.326126 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 75144035 71.98% 71.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 3907124 3.74% 75.73% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 2485008 2.38% 78.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 8099840 7.76% 85.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1578542 1.51% 87.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 1169165 1.12% 88.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 6151960 5.89% 94.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 1142182 1.09% 95.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4712244 4.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 76382369 71.93% 71.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 3967856 3.74% 75.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2509209 2.36% 78.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 8248224 7.77% 85.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1616537 1.52% 87.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 1210559 1.14% 88.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 6288171 5.92% 94.38% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 1186864 1.12% 95.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4785005 4.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 104390100 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.254693 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.993536 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27682693 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 57882458 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 15650277 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1716894 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1457466 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1955529 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 151159 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 88694873 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 489106 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1457466 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28625802 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 6604433 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 45361321 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 16416425 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 5924344 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 84834346 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 2307 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 1574765 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 278233 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 3285499 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 87641847 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 391276070 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 94803920 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 5749 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 73988395 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13653452 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1589936 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1488982 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 10049361 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 15102779 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 11808907 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 2150791 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 2768917 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 81595404 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1156818 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 78284353 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93210 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 9952134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 25073057 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 106330 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 104390100 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.749921 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.429238 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 106194794 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.255909 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.998697 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 27865394 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 59086639 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 16014101 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1741536 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1486862 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 2014125 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 153633 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 90617334 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 499096 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1486862 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 28829421 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 4993628 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 46364709 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 16784538 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7735362 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 86665296 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 1758 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1681489 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 204965 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 5046479 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 89687558 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 399294691 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 96716693 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 5355 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 75738735 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13948807 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1608168 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1506785 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 10100252 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 15391291 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 11882778 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2188376 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 2888870 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 83375619 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158159 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 79910900 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 92494 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10129412 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 25615832 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 107265 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 106194794 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.752494 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.434563 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 72870740 69.81% 69.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 10640655 10.19% 80.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 8029126 7.69% 87.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 6654786 6.37% 94.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 2478739 2.37% 96.44% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1537519 1.47% 97.91% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1459463 1.40% 99.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 490817 0.47% 99.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 228255 0.22% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 74167078 69.84% 69.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 10703730 10.08% 79.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 8178605 7.70% 87.62% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 6800959 6.40% 94.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 2513016 2.37% 96.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1570037 1.48% 97.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1528184 1.44% 99.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 489750 0.46% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 243435 0.23% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 104390100 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 106194794 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 100798 8.75% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 4 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.75% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 535574 46.51% 55.26% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 515204 44.74% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 110018 9.66% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 6 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 9.66% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 521312 45.77% 55.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 507746 44.58% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 124 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 52262651 66.76% 66.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59116 0.08% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4115 0.01% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 1 0.00% 66.84% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 14698419 18.78% 85.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 11259924 14.38% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 151 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 53586361 67.06% 67.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59349 0.07% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 2 0.00% 67.13% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4262 0.01% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.14% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 14931901 18.69% 85.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 11328871 14.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 78284353 # Type of FU issued -system.cpu1.iq.rate 0.731615 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 1151580 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.014710 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 262190696 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 92748647 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 75915598 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 12900 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 6883 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 5649 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 79428849 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 6960 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 366149 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 79910900 # Type of FU issued +system.cpu1.iq.rate 0.734775 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 1139082 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.014254 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 267236211 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 94707265 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 77543645 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 11959 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 6289 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 81043378 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 351971 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2166601 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2614 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 52391 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1139774 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2202451 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2360 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 51509 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1138977 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 191651 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 153600 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 192559 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 108870 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1457466 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 4280991 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 2091777 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 82896193 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 132170 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 15102779 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 11808907 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 583505 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 47325 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 2032029 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 52391 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 250395 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 218336 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 468731 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 77684491 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 14461832 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 541313 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1486862 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 4086013 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 663456 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 84657415 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 129656 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 15391291 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 11882778 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 585252 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 42277 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 608480 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 51509 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 260306 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 223242 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 483548 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 79294807 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 14687603 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 558095 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 143971 # number of nop insts executed -system.cpu1.iew.exec_refs 25613639 # number of memory reference insts executed -system.cpu1.iew.exec_branches 14454387 # Number of branches executed -system.cpu1.iew.exec_stores 11151807 # Number of stores executed -system.cpu1.iew.exec_rate 0.726009 # Inst execution rate -system.cpu1.iew.wb_sent 77065601 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 75921247 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 39733715 # num instructions producing a value -system.cpu1.iew.wb_consumers 69689049 # num instructions consuming a value +system.cpu1.iew.exec_nop 123637 # number of nop insts executed +system.cpu1.iew.exec_refs 25906138 # number of memory reference insts executed +system.cpu1.iew.exec_branches 14775343 # Number of branches executed +system.cpu1.iew.exec_stores 11218535 # Number of stores executed +system.cpu1.iew.exec_rate 0.729110 # Inst execution rate +system.cpu1.iew.wb_sent 78721985 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 77548836 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 40818570 # num instructions producing a value +system.cpu1.iew.wb_consumers 71550295 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.709530 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.570157 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.713056 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.570488 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 11280608 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 1050488 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 395955 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 101852201 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.703017 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.586598 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 11482053 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1050894 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 406174 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103612513 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.706116 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.593552 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 73888394 72.54% 72.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 12531229 12.30% 84.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6432271 6.32% 91.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 2665520 2.62% 93.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1405579 1.38% 95.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 922819 0.91% 96.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1826114 1.79% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 423793 0.42% 98.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1756482 1.72% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 75208985 72.59% 72.59% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 12628786 12.19% 84.78% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6551089 6.32% 91.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 2721278 2.63% 93.72% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1429301 1.38% 95.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 940289 0.91% 96.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1888025 1.82% 97.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 437231 0.42% 98.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1807529 1.74% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 101852201 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 58981554 # Number of instructions committed -system.cpu1.commit.committedOps 71603833 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103612513 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 60426665 # Number of instructions committed +system.cpu1.commit.committedOps 73162446 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 23605311 # Number of memory references committed -system.cpu1.commit.loads 12936178 # Number of loads committed -system.cpu1.commit.membars 439363 # Number of memory barriers committed -system.cpu1.commit.branches 13694258 # Number of branches committed -system.cpu1.commit.fp_insts 5590 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 62751370 # Number of committed integer instructions. -system.cpu1.commit.function_calls 2679190 # Number of function calls committed. +system.cpu1.commit.refs 23932641 # Number of memory references committed +system.cpu1.commit.loads 13188840 # Number of loads committed +system.cpu1.commit.membars 435550 # Number of memory barriers committed +system.cpu1.commit.branches 14000562 # Number of branches committed +system.cpu1.commit.fp_insts 5142 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 64124542 # Number of committed integer instructions. +system.cpu1.commit.function_calls 2721670 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 47937101 66.95% 66.95% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 57311 0.08% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4110 0.01% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.03% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 12936178 18.07% 85.10% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 10669133 14.90% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 49168040 67.20% 67.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 57503 0.08% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.28% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4262 0.01% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.29% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 13188840 18.03% 85.32% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 10743801 14.68% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 71603833 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1756482 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 73162446 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1807529 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 170496195 # The number of ROB reads -system.cpu1.rob.rob_writes 168311101 # The number of ROB writes -system.cpu1.timesIdled 389572 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2612002 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2951648369 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 58897215 # Number of Instructions Simulated -system.cpu1.committedOps 71519494 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.816760 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.816760 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.550430 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.550430 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 84567520 # number of integer regfile reads -system.cpu1.int_regfile_writes 48323955 # number of integer regfile writes -system.cpu1.fp_regfile_reads 16256 # number of floating regfile reads -system.cpu1.fp_regfile_writes 13038 # number of floating regfile writes -system.cpu1.cc_regfile_reads 274360839 # number of cc regfile reads -system.cpu1.cc_regfile_writes 28850413 # number of cc regfile writes -system.cpu1.misc_regfile_reads 191580382 # number of misc regfile reads -system.cpu1.misc_regfile_writes 795927 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 30210 # Transaction distribution -system.iobus.trans_dist::ReadResp 30210 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.cpu1.rob.rob_reads 173729023 # The number of ROB reads +system.cpu1.rob.rob_writes 171875858 # The number of ROB writes +system.cpu1.timesIdled 390006 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 2560821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2437360736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 60356761 # Number of Instructions Simulated +system.cpu1.committedOps 73092542 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.801880 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.801880 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.554976 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.554976 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 86251315 # number of integer regfile reads +system.cpu1.int_regfile_writes 49415173 # number of integer regfile writes +system.cpu1.fp_regfile_reads 15994 # number of floating regfile reads +system.cpu1.fp_regfile_writes 13022 # number of floating regfile writes +system.cpu1.cc_regfile_reads 279979129 # number of cc regfile reads +system.cpu1.cc_regfile_writes 29562027 # number of cc regfile writes +system.cpu1.misc_regfile_reads 195055078 # number of misc regfile reads +system.cpu1.misc_regfile_writes 795609 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 30198 # Transaction distribution +system.iobus.trans_dist::ReadResp 30198 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1866,11 +1824,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1891,11 +1849,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480349 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1935,46 +1893,46 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347059161 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198975032 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36834571 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36852019 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36411 # number of replacements -system.iocache.tags.tagsinuse 1.036460 # Cycle average of tags in use -system.iocache.tags.total_refs 28 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36427 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs 0.000769 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 234008190000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.036460 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064779 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064779 # Average percentage of cache occupancy +system.iocache.tags.replacements 36409 # number of replacements +system.iocache.tags.tagsinuse 0.981278 # Cycle average of tags in use +system.iocache.tags.total_refs 30 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 36425 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0.000824 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 234149213000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 0.981278 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.061330 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.061330 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328229 # Number of tag accesses -system.iocache.tags.data_accesses 328229 # Number of data accesses -system.iocache.WriteInvalidateReq_hits::realview.ide 27 # number of WriteInvalidateReq hits -system.iocache.WriteInvalidateReq_hits::total 27 # number of WriteInvalidateReq hits +system.iocache.tags.tag_accesses 328227 # Number of tag accesses +system.iocache.tags.data_accesses 328227 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 29 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 29 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses system.iocache.ReadReq_misses::total 249 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36197 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36197 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 36195 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 36195 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses system.iocache.demand_misses::total 249 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 249 # number of overall misses system.iocache.overall_misses::total 249 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29657377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29657377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617288213 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617288213 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29657377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29657377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29657377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29657377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 30962377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 30962377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6648903636 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6648903636 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 30962377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 30962377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 30962377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 30962377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1985,306 +1943,306 @@ system.iocache.overall_accesses::realview.ide 249 system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.999255 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.999255 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.999199 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.999199 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119105.931727 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119105.931727 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265692.963864 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265692.963864 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119105.931727 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119105.931727 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119105.931727 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119105.931727 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56457 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124346.895582 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124346.895582 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183696.743639 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183696.743639 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124346.895582 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124346.895582 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124346.895582 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124346.895582 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22802 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7214 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3472 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.826033 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.567396 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36162 # number of writebacks -system.iocache.writebacks::total 36162 # number of writebacks +system.iocache.writebacks::writebacks 36160 # number of writebacks +system.iocache.writebacks::total 36160 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 249 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36197 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36197 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36195 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 36195 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 249 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16708377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16708377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7734902355 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7734902355 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16708377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16708377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16708377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16708377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17850377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17850377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766725674 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766725674 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17850377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17850377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17850377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17850377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.999255 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999255 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.999199 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.999199 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67101.915663 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67101.915663 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213689.044810 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213689.044810 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67101.915663 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67101.915663 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67101.915663 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67101.915663 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 71688.261044 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 71688.261044 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131695.694820 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131695.694820 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 71688.261044 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 71688.261044 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 71688.261044 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 71688.261044 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104467 # number of replacements -system.l2c.tags.tagsinuse 65129.957708 # Cycle average of tags in use -system.l2c.tags.total_refs 3116952 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169707 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 18.366667 # Average number of references to valid blocks. +system.l2c.tags.replacements 104656 # number of replacements +system.l2c.tags.tagsinuse 65129.158587 # Cycle average of tags in use +system.l2c.tags.total_refs 3113742 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169901 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.326802 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48713.108693 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 48.622899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000234 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5546.203044 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2803.513756 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 43.406508 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4962.784204 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3012.318369 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.743303 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000742 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 48669.329761 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 43.033999 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000245 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4678.591805 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2387.812073 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.916630 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5867.753400 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3437.720673 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.742635 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000657 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.084628 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042778 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000662 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.075726 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.045964 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993804 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 90 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 90 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.071390 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.036435 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000685 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.089535 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.052455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993792 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 70 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65175 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 70 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9019 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 52534 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.001373 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.994110 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 29257096 # Number of tag accesses -system.l2c.tags.data_accesses 29257096 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 37572 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 9067 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 969052 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 275148 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 36337 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 7588 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 957278 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 266835 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2558877 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 703765 # number of Writeback hits -system.l2c.Writeback_hits::total 703765 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 49 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 106 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 34 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 52 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 78975 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 77026 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 156001 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 37572 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 9067 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 969052 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 354123 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 36337 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 7588 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 957278 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 343861 # number of demand (read+write) hits -system.l2c.demand_hits::total 2714878 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 37572 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 9067 # number of overall hits -system.l2c.overall_hits::cpu0.inst 969052 # number of overall hits -system.l2c.overall_hits::cpu0.data 354123 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 36337 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 7588 # number of overall hits -system.l2c.overall_hits::cpu1.inst 957278 # number of overall hits -system.l2c.overall_hits::cpu1.data 343861 # number of overall hits -system.l2c.overall_hits::total 2714878 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 69 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1024::1 366 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3243 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 9051 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52499 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.001068 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.994492 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 29235849 # Number of tag accesses +system.l2c.tags.data_accesses 29235849 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 36383 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 8250 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 959469 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 268247 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 36362 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7924 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 964356 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 274193 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2555184 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 704443 # number of Writeback hits +system.l2c.Writeback_hits::total 704443 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 48 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 87 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 82853 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 73309 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 156162 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 36383 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 8250 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 959469 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 351100 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 36362 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7924 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 964356 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 347502 # number of demand (read+write) hits +system.l2c.demand_hits::total 2711346 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 36383 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 8250 # number of overall hits +system.l2c.overall_hits::cpu0.inst 959469 # number of overall hits +system.l2c.overall_hits::cpu0.data 351100 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 36362 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7924 # number of overall hits +system.l2c.overall_hits::cpu1.inst 964356 # number of overall hits +system.l2c.overall_hits::cpu1.data 347502 # number of overall hits +system.l2c.overall_hits::total 2711346 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 68 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 11048 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6910 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 64 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9843 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 8238 # number of ReadReq misses -system.l2c.ReadReq_misses::total 36173 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1336 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1398 # number of UpgradeReq misses +system.l2c.ReadReq_misses::cpu0.inst 10143 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 7063 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 63 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 10750 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 8134 # number of ReadReq misses +system.l2c.ReadReq_misses::total 36222 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1453 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1281 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2734 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 12 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 14 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 26 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 73855 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 66651 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140506 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 69 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::cpu0.data 7 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 9 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 72022 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 68619 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140641 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 68 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 11048 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 80765 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 64 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9843 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 74889 # number of demand (read+write) misses -system.l2c.demand_misses::total 176679 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 69 # number of overall misses +system.l2c.demand_misses::cpu0.inst 10143 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 79085 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 63 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 10750 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 76753 # number of demand (read+write) misses +system.l2c.demand_misses::total 176863 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 68 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 11048 # number of overall misses -system.l2c.overall_misses::cpu0.data 80765 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 64 # number of overall misses -system.l2c.overall_misses::cpu1.inst 9843 # number of overall misses -system.l2c.overall_misses::cpu1.data 74889 # number of overall misses -system.l2c.overall_misses::total 176679 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 5336500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 838505750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 551999991 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5114500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 750478500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 687098992 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2838608733 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 370984 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 464480 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 835464 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 262495 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 139494 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 401989 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5637036528 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5153264325 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10790300853 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 5336500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 838505750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 6189036519 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 5114500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 750478500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5840363317 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 13628909586 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 5336500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 838505750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 6189036519 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 5114500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 750478500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 5840363317 # number of overall miss cycles -system.l2c.overall_miss_latency::total 13628909586 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 37641 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 9068 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 980100 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 282058 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 36401 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7588 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 967121 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 275073 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2595050 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 703765 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 703765 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1385 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1455 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2840 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 30 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 48 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 78 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 152830 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 143677 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296507 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 37641 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 9068 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 980100 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 434888 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 36401 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7588 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 967121 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 418750 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2891557 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 37641 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 9068 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 980100 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 434888 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 36401 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7588 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 967121 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 418750 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2891557 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001833 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000110 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.011272 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.024499 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001758 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010178 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.029948 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.013939 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.964621 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.960825 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.962676 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.400000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.291667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.333333 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.483249 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.463895 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.473871 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001833 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000110 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.011272 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.185714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001758 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010178 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.178839 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.061102 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001833 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000110 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.011272 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.185714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001758 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010178 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.178839 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.061102 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 77340.579710 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75896.610246 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 79884.224457 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79914.062500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76244.894849 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 83406.044185 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 78473.135571 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 277.682635 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 332.246066 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 305.583029 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 21874.583333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 9963.857143 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 15461.115385 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76325.726464 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77317.134402 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76796.014782 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 77340.579710 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 75896.610246 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 76630.180388 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79914.062500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76244.894849 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 77986.931552 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 77139.386039 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 77340.579710 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 75896.610246 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 76630.180388 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79914.062500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76244.894849 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 77986.931552 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 77139.386039 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 10143 # number of overall misses +system.l2c.overall_misses::cpu0.data 79085 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 63 # number of overall misses +system.l2c.overall_misses::cpu1.inst 10750 # number of overall misses +system.l2c.overall_misses::cpu1.data 76753 # number of overall misses +system.l2c.overall_misses::total 176863 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 5921750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 68750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 835233999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 610760750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 5497500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 894308500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 720028000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 3071819249 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 436986 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 406987 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 843973 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 141998 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 81000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 222998 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6026469540 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5704758320 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11731227860 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 5921750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 68750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 835233999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 6637230290 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 5497500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 894308500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6424786320 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 14803047109 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 5921750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 68750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 835233999 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 6637230290 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 5497500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 894308500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6424786320 # number of overall miss cycles +system.l2c.overall_miss_latency::total 14803047109 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 36451 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 8251 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 969612 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 275310 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 36425 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7924 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 975106 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 282327 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2591406 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 704443 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 704443 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1501 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1320 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2821 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 21 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 34 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 55 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 154875 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 141928 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 296803 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 36451 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 8251 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 969612 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 430185 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 36425 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7924 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 975106 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 424255 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2888209 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 36451 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 8251 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 969612 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 430185 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 36425 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7924 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 975106 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 424255 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2888209 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001866 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000121 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.010461 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.025655 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001730 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011024 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.028811 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.013978 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.968021 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.970455 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.969160 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.333333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.058824 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.163636 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.465033 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.483478 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.473853 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001866 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000121 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.010461 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.183840 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001730 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011024 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.180912 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.061236 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001866 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000121 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.010461 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.183840 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001730 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011024 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.180912 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.061236 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87084.558824 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 68750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82345.854185 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 86473.276228 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83191.488372 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 88520.776985 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 84805.346171 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 300.747419 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 317.710383 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 308.695318 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 20285.428571 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 40500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 24777.555556 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 83675.398351 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83136.716070 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 83412.574285 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87084.558824 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 68750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83191.488372 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 83697.817571 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87084.558824 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 68750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82345.854185 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 83925.273946 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87261.904762 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83191.488372 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83707.298998 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 83697.817571 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2293,166 +2251,166 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 95556 # number of writebacks -system.l2c.writebacks::total 95556 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 69 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 68 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 148 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 69 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 68 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 148 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 69 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 68 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 148 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 69 # number of ReadReq MSHR misses +system.l2c.writebacks::writebacks 95497 # number of writebacks +system.l2c.writebacks::total 95497 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 75 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 61 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 75 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 61 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 75 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 61 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 146 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 68 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 11041 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6841 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 64 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 9839 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 8170 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 36025 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1336 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1398 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 10139 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6988 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 63 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 10744 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 8073 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 36076 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1453 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1281 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 2734 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 12 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 14 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 26 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 73855 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 66651 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140506 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 69 # number of demand (read+write) MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 7 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 9 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 72022 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 68619 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140641 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 68 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 11041 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 80696 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 64 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 9839 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 74821 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 176531 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 69 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 10139 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 79010 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 63 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 10744 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 76692 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 176717 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 68 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 11041 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 80696 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 64 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 9839 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 74821 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 176531 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 4480000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 699224000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 462918491 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4323000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 626250000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 581032492 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 2378290483 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13361336 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14241398 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 27602734 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 221010 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 140014 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 361024 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4714978472 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4324409175 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 9039387647 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 4480000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 699224000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 5177896963 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4323000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 626250000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4905441667 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 11417678130 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 4480000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 699224000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 5177896963 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4323000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 626250000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4905441667 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 11417678130 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 35704750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2941058500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2438229500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5414992750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2208397500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1893885000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4102282500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 35704750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5149456000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4332114500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 9517275250 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001833 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000110 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.011265 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.024254 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001758 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010173 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.029701 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.013882 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.964621 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.960825 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.962676 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.291667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.483249 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.463895 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.473871 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001833 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000110 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.011265 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.185556 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001758 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010173 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.178677 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.061050 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001833 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000110 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.011265 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.185556 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001758 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010173 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.178677 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.061050 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63329.770854 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67668.248940 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63649.761155 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71117.808078 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 66017.778848 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10186.979971 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10096.098756 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18417.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 13885.538462 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63841.019186 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64881.384750 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 64334.531244 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63329.770854 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64165.472427 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63649.761155 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65562.364403 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 64678.034623 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64927.536232 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63329.770854 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64165.472427 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67546.875000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63649.761155 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65562.364403 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 64678.034623 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 10139 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 79010 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 63 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 10744 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 76692 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 176717 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 56250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 708062999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 518326750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 759667250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 614985750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2610872749 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 25946451 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 22749281 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 48695732 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 173506 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 86501 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 260007 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5129956460 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4854039180 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9983995640 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 56250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 708062999 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 5648283210 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 759667250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5469024930 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 12594868389 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 5068250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 56250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 708062999 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 5648283210 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 4705500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 759667250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5469024930 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 12594868389 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 41164749 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2875017500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2529278000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5445460249 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2162093500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1988256000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4150349500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 41164749 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5037111000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4517534000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 9595809749 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.025382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001730 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011018 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.028595 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013921 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.968021 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.970455 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.969160 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.058824 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.163636 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.465033 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.483478 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.473853 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.183665 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001730 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011018 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.180769 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.061186 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.183665 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001730 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011018 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.180769 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.061186 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74173.833715 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76178.093645 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.458837 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17857.158293 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17759.001561 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.167520 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24786.571429 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 43250.500000 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 28889.666667 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71227.631279 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70738.996196 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 70989.225333 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -2465,57 +2423,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68075 # Transaction distribution -system.membus.trans_dist::ReadResp 68074 # Transaction distribution -system.membus.trans_dist::WriteReq 27609 # Transaction distribution -system.membus.trans_dist::WriteResp 27609 # Transaction distribution -system.membus.trans_dist::Writeback 131718 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36196 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4633 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4659 # Transaction distribution -system.membus.trans_dist::ReadExReq 138608 # Transaction distribution -system.membus.trans_dist::ReadExResp 138608 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 68117 # Transaction distribution +system.membus.trans_dist::ReadResp 68116 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::Writeback 131657 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36194 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36194 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4626 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 9 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4635 # Transaction distribution +system.membus.trans_dist::ReadExReq 138750 # Transaction distribution +system.membus.trans_dist::ReadExResp 138750 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2076 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465023 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 572669 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108820 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681489 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465311 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 572879 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108814 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681693 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4152 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17335192 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17499181 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4631872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22131053 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 522 # Total snoops (count) -system.membus.snoop_fanout::samples 347455 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17344024 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17507929 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4631616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22139545 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 523 # Total snoops (count) +system.membus.snoop_fanout::samples 347614 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 347455 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 347614 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 347455 # Request fanout histogram -system.membus.reqLayer0.occupancy 81552000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 347614 # Request fanout histogram +system.membus.reqLayer0.occupancy 95655500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1698000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1658000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1759525499 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1732085345 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38509429 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1067095796 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1022748121 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37540981 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2548,57 +2506,55 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2659236 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2659139 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27609 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27609 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 703765 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36196 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2841 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 78 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2918 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296507 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296507 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3896051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2534528 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43103 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 170141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6643823 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124664384 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99866733 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 66624 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 296168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224893909 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 68735 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3666824 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.009939 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.099200 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2657013 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2656927 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 704443 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2822 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 55 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2876 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296803 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296803 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2536659 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169075 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6639094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124504512 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99962073 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 64700 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 291504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224822789 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 70210 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3665576 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.009952 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.099262 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3630378 99.01% 99.01% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36446 0.99% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3629096 99.00% 99.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36480 1.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3666824 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4674174231 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 688500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3665576 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2562503934 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 246000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 8773601584 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3912223359 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 26520841 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2923288858 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1353662761 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 26203715 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 96916821 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96601513 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3042 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt index 15d0bc0bd..7478799f2 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/stats.txt @@ -1,137 +1,137 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.904914 # Number of seconds simulated -sim_ticks 2904913754500 # Number of ticks simulated -final_tick 2904913754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903641 # Number of seconds simulated +sim_ticks 2903640922500 # Number of ticks simulated +final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 719084 # Simulator instruction rate (inst/s) -host_op_rate 866994 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 18567568294 # Simulator tick rate (ticks/s) -host_mem_usage 616260 # Number of bytes of host memory used -host_seconds 156.45 # Real time elapsed on the host -sim_insts 112501381 # Number of instructions simulated -sim_ops 135642071 # Number of ops (including micro ops) simulated +host_inst_rate 705602 # Simulator instruction rate (inst/s) +host_op_rate 850741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18218787173 # Simulator tick rate (ticks/s) +host_mem_usage 616688 # Number of bytes of host memory used +host_seconds 159.38 # Real time elapsed on the host +sim_insts 112456119 # Number of instructions simulated +sim_ops 135587804 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 553252 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4270880 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 635584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4758596 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 582564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3808480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 602944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5025476 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10219848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 553252 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 635584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1188836 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7620224 # Number of bytes written to this memory +system.physmem.bytes_read::total 10021000 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 582564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 602944 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1185508 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7434688 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 7637748 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 17098 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 67251 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 9931 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74354 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7452212 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 17556 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 60026 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 9421 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 78524 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168658 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 119066 # Number of write requests responded to by this memory +system.physmem.num_reads::total 165551 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 116167 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 123447 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190454 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1470226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 218796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1638120 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3518124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190454 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 218796 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 409250 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2623219 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 120548 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 66 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 44 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 200632 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1311622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 88 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 207651 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1730750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3451184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 200632 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 207651 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 408283 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2560471 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6032 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2629251 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2623219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1476256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 218796 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 1638122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6147376 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168658 # Number of read requests accepted -system.physmem.writeReqs 159671 # Number of write requests accepted -system.physmem.readBursts 168658 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 159671 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10788160 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5952 # Total number of bytes read from write queue -system.physmem.bytesWritten 9869632 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10219848 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9956084 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 93 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5450 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4495 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9771 # Per bank write bursts -system.physmem.perBankRdBursts::1 9508 # Per bank write bursts -system.physmem.perBankRdBursts::2 10210 # Per bank write bursts -system.physmem.perBankRdBursts::3 9949 # Per bank write bursts -system.physmem.perBankRdBursts::4 18798 # Per bank write bursts -system.physmem.perBankRdBursts::5 10140 # Per bank write bursts -system.physmem.perBankRdBursts::6 10351 # Per bank write bursts -system.physmem.perBankRdBursts::7 10416 # Per bank write bursts -system.physmem.perBankRdBursts::8 9932 # Per bank write bursts -system.physmem.perBankRdBursts::9 10416 # Per bank write bursts -system.physmem.perBankRdBursts::10 9794 # Per bank write bursts -system.physmem.perBankRdBursts::11 9556 # Per bank write bursts -system.physmem.perBankRdBursts::12 10053 # Per bank write bursts -system.physmem.perBankRdBursts::13 9934 # Per bank write bursts -system.physmem.perBankRdBursts::14 9961 # Per bank write bursts -system.physmem.perBankRdBursts::15 9776 # Per bank write bursts -system.physmem.perBankWrBursts::0 9468 # Per bank write bursts -system.physmem.perBankWrBursts::1 9241 # Per bank write bursts -system.physmem.perBankWrBursts::2 10223 # Per bank write bursts -system.physmem.perBankWrBursts::3 9791 # Per bank write bursts -system.physmem.perBankWrBursts::4 9126 # Per bank write bursts -system.physmem.perBankWrBursts::5 9458 # Per bank write bursts -system.physmem.perBankWrBursts::6 9597 # Per bank write bursts -system.physmem.perBankWrBursts::7 9810 # Per bank write bursts -system.physmem.perBankWrBursts::8 9882 # Per bank write bursts -system.physmem.perBankWrBursts::9 10274 # Per bank write bursts -system.physmem.perBankWrBursts::10 9701 # Per bank write bursts -system.physmem.perBankWrBursts::11 9802 # Per bank write bursts -system.physmem.perBankWrBursts::12 9921 # Per bank write bursts -system.physmem.perBankWrBursts::13 9488 # Per bank write bursts -system.physmem.perBankWrBursts::14 9342 # Per bank write bursts -system.physmem.perBankWrBursts::15 9089 # Per bank write bursts +system.physmem.bw_write::total 2566506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2560471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 66 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 200632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1317655 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 88 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 207651 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 1730753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6017690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 165551 # Number of read requests accepted +system.physmem.writeReqs 156772 # Number of write requests accepted +system.physmem.readBursts 165551 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 156772 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10588736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 8522624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10021000 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9770548 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23601 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4489 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9899 # Per bank write bursts +system.physmem.perBankRdBursts::1 9526 # Per bank write bursts +system.physmem.perBankRdBursts::2 9759 # Per bank write bursts +system.physmem.perBankRdBursts::3 9793 # Per bank write bursts +system.physmem.perBankRdBursts::4 18999 # Per bank write bursts +system.physmem.perBankRdBursts::5 10033 # Per bank write bursts +system.physmem.perBankRdBursts::6 10462 # Per bank write bursts +system.physmem.perBankRdBursts::7 10803 # Per bank write bursts +system.physmem.perBankRdBursts::8 9925 # Per bank write bursts +system.physmem.perBankRdBursts::9 10243 # Per bank write bursts +system.physmem.perBankRdBursts::10 9858 # Per bank write bursts +system.physmem.perBankRdBursts::11 9250 # Per bank write bursts +system.physmem.perBankRdBursts::12 9247 # Per bank write bursts +system.physmem.perBankRdBursts::13 9475 # Per bank write bursts +system.physmem.perBankRdBursts::14 9028 # Per bank write bursts +system.physmem.perBankRdBursts::15 9149 # Per bank write bursts +system.physmem.perBankWrBursts::0 8258 # Per bank write bursts +system.physmem.perBankWrBursts::1 8244 # Per bank write bursts +system.physmem.perBankWrBursts::2 8572 # Per bank write bursts +system.physmem.perBankWrBursts::3 8149 # Per bank write bursts +system.physmem.perBankWrBursts::4 8563 # Per bank write bursts +system.physmem.perBankWrBursts::5 8536 # Per bank write bursts +system.physmem.perBankWrBursts::6 8718 # Per bank write bursts +system.physmem.perBankWrBursts::7 9117 # Per bank write bursts +system.physmem.perBankWrBursts::8 8657 # Per bank write bursts +system.physmem.perBankWrBursts::9 8771 # Per bank write bursts +system.physmem.perBankWrBursts::10 8610 # Per bank write bursts +system.physmem.perBankWrBursts::11 7990 # Per bank write bursts +system.physmem.perBankWrBursts::12 7949 # Per bank write bursts +system.physmem.perBankWrBursts::13 7964 # Per bank write bursts +system.physmem.perBankWrBursts::14 7531 # Per bank write bursts +system.physmem.perBankWrBursts::15 7537 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2904913375000 # Total gap between requests +system.physmem.numWrRetry 32 # Number of times write queue was full causing retry +system.physmem.totGap 2903640597500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 159086 # Read request sizes (log2) +system.physmem.readPktSize::6 155979 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 155290 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167768 # What read queue length does an incoming req see +system.physmem.writePktSize::6 152391 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 164623 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 272 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -161,196 +161,183 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 200 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 172 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 163 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8604 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8946 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10874 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10170 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60740 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.100889 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 196.092266 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 354.277091 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21340 35.13% 35.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14718 24.23% 59.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5632 9.27% 68.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3268 5.38% 74.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2341 3.85% 77.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1599 2.63% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1029 1.69% 82.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1125 1.85% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9688 15.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60740 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.064066 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 545.583235 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6227 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::14 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5271 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5453 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7269 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6043 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1272 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2179 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1872 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1747 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 308 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57876 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 330.211072 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 191.290947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.940345 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 20714 35.79% 35.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14256 24.63% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5208 9.00% 69.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3123 5.40% 74.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2440 4.22% 79.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1489 2.57% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1071 1.85% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1111 1.92% 85.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8464 14.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57876 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5262 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 31.441087 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 579.786182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5260 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6228 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.761240 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.356568 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.463142 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 15 0.24% 0.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 11 0.18% 0.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.13% 0.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 13 0.21% 0.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4938 79.29% 80.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 76 1.22% 81.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 62 1.00% 82.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 242 3.89% 86.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 139 2.23% 88.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.80% 89.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.50% 89.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 38 0.61% 90.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 131 2.10% 92.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.37% 92.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 11 0.18% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 18 0.29% 93.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 33 0.53% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 12 0.19% 93.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 9 0.14% 94.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 29 0.47% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 74 1.19% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 10 0.16% 95.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.10% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 12 0.19% 96.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 105 1.69% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 8 0.13% 98.07% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 5 0.08% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 14 0.22% 98.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 5 0.08% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 10 0.16% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 36 0.58% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 5 0.08% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.05% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.02% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.08% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.05% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6228 # Writes before turning the bus around for reads -system.physmem.totQLat 1469432250 # Total ticks spent queuing -system.physmem.totMemAccLat 4630026000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 842825000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8717.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5262 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5262 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.307108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.699141 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 47.946490 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 45 0.86% 0.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4897 93.06% 93.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 79 1.50% 95.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 16 0.30% 95.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 14 0.27% 95.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 19 0.36% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 31 0.59% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 27 0.51% 97.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.25% 97.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 8 0.15% 97.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.06% 97.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 23 0.44% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 14 0.27% 98.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 10 0.19% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.06% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 4 0.08% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 8 0.15% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.08% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.06% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.10% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 8 0.15% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.06% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.06% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5262 # Writes before turning the bus around for reads +system.physmem.totQLat 1437662314 # Total ticks spent queuing +system.physmem.totMemAccLat 4539831064 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 827245000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8689.46 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27467.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.43 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27439.46 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.65 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.94 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.45 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.36 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.21 # Average write queue length when enqueuing -system.physmem.readRowHits 138952 # Number of row buffer hits during reads -system.physmem.writeRowHits 123085 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.43 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes -system.physmem.avgGap 8847568.67 # Average gap between requests -system.physmem.pageHitRate 81.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 232530480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 126876750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 695315400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 497106720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189734581920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86967425385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1666658766000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1944912602655 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.525949 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2772474399000 # Time in different power states -system.physmem_0.memoryStateTime::REF 97001320000 # Time in different power states +system.physmem.avgWrQLen 10.50 # Average write queue length when enqueuing +system.physmem.readRowHits 136363 # Number of row buffer hits during reads +system.physmem.writeRowHits 104375 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.42 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.38 # Row buffer hit rate for writes +system.physmem.avgGap 9008480.93 # Average gap between requests +system.physmem.pageHitRate 80.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 229453560 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 125197875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 696337200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 441657360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86953063950 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665909868500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1944007265085 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.506799 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2771232360210 # Time in different power states +system.physmem_0.memoryStateTime::REF 96958940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35434263500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35449523540 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 226663920 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123675750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 619483800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 502193520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189734581920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 86205812760 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1667326855500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1944739267170 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.466276 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2773597933750 # Time in different power states -system.physmem_1.memoryStateTime::REF 97001320000 # Time in different power states +system.physmem_1.actEnergy 208089000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 113540625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 594157200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 421258320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189651686640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 84877892595 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1667730194250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943596818630 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.365444 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2774279366726 # Time in different power states +system.physmem_1.memoryStateTime::REF 96958940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34314407250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32402517024 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -400,60 +387,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7245 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7245 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2256 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4989 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7245 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7245 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7245 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6163 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11073.588350 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8976.658748 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6262.578720 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-2047 6 0.10% 0.10% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::2048-4095 1618 26.25% 26.35% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::4096-6143 2 0.03% 26.38% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::10240-12287 3154 51.18% 77.56% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::12288-14335 39 0.63% 78.19% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::14336-16383 18 0.29% 78.48% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::20480-22527 1281 20.79% 99.27% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::22528-24575 45 0.73% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6163 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 809116500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 809116500 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 809116500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3931 63.78% 63.78% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 2232 36.22% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6163 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7245 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 6899 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 6899 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 2220 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 4679 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 6899 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 6899 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 6899 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 5841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12315.228557 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10506.489584 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6688.963614 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 4458 76.32% 76.32% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1381 23.64% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 5841 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 3645 62.40% 62.40% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 2196 37.60% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 5841 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 6899 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7245 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6163 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 6899 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 5841 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6163 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 13408 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 5841 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 12740 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12308192 # DTB read hits -system.cpu0.dtb.read_misses 6208 # DTB read misses -system.cpu0.dtb.write_hits 9797532 # DTB write hits -system.cpu0.dtb.write_misses 1037 # DTB write misses -system.cpu0.dtb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu0.dtb.read_hits 12462635 # DTB read hits +system.cpu0.dtb.read_misses 5988 # DTB read misses +system.cpu0.dtb.write_hits 9832923 # DTB write hits +system.cpu0.dtb.write_misses 911 # DTB write misses +system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 4666 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 4660 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 859 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 940 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 219 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12314400 # DTB read accesses -system.cpu0.dtb.write_accesses 9798569 # DTB write accesses +system.cpu0.dtb.perms_faults 240 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12468623 # DTB read accesses +system.cpu0.dtb.write_accesses 9833834 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 22105724 # DTB hits -system.cpu0.dtb.misses 7245 # DTB misses -system.cpu0.dtb.accesses 22112969 # DTB accesses +system.cpu0.dtb.hits 22295558 # DTB hits +system.cpu0.dtb.misses 6899 # DTB misses +system.cpu0.dtb.accesses 22302457 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,372 +466,364 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3600 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3600 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 840 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2760 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3600 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3600 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3600 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2772 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11755.230880 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 9457.284814 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6774.641568 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 701 25.29% 25.29% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1365 49.24% 74.53% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 705 25.43% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::73728-81919 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2772 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1932 69.70% 69.70% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 840 30.30% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2772 # Table walker page sizes translated +system.cpu0.itb.walker.walks 3577 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3577 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 835 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 2742 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3577 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3577 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3577 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2726 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12637.197359 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 10746.267304 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6704.748097 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 633 23.22% 23.22% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1408 51.65% 74.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 683 25.06% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2726 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1891 69.37% 69.37% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 835 30.63% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2726 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3600 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3600 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3577 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3577 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2772 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2772 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6372 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 58198432 # ITB inst hits -system.cpu0.itb.inst_misses 3600 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2726 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2726 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6303 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 58414032 # ITB inst hits +system.cpu0.itb.inst_misses 3577 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 2937 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 436 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb 2938 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 496 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2765 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2760 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 58202032 # ITB inst accesses -system.cpu0.itb.hits 58198432 # DTB hits -system.cpu0.itb.misses 3600 # DTB misses -system.cpu0.itb.accesses 58202032 # DTB accesses -system.cpu0.numCycles 2905779233 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 58417609 # ITB inst accesses +system.cpu0.itb.hits 58414032 # DTB hits +system.cpu0.itb.misses 3577 # DTB misses +system.cpu0.itb.accesses 58417609 # DTB accesses +system.cpu0.numCycles 2904051621 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 56657023 # Number of instructions committed -system.cpu0.committedOps 68159505 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 60230099 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 6043 # Number of float alu accesses -system.cpu0.num_func_calls 4917301 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7681441 # number of instructions that are conditional controls -system.cpu0.num_int_insts 60230099 # number of integer instructions -system.cpu0.num_fp_insts 6043 # number of float instructions -system.cpu0.num_int_register_reads 109460291 # number of times the integer registers were read -system.cpu0.num_int_register_writes 41577079 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4484 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1562 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 246097869 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 26230649 # number of times the CC registers were written -system.cpu0.num_mem_refs 22747427 # number of memory refs -system.cpu0.num_load_insts 12471045 # Number of load instructions -system.cpu0.num_store_insts 10276382 # Number of store instructions -system.cpu0.num_idle_cycles 2686979283.194706 # Number of idle cycles -system.cpu0.num_busy_cycles 218799949.805294 # Number of busy cycles -system.cpu0.not_idle_fraction 0.075298 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.924702 # Percentage of idle cycles -system.cpu0.Branches 13013493 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2203 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46896636 67.27% 67.28% # Class of executed instruction -system.cpu0.op_class::IntMult 58754 0.08% 67.36% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.36% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4258 0.01% 67.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.37% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.37% # Class of executed instruction -system.cpu0.op_class::MemRead 12471045 17.89% 85.26% # Class of executed instruction -system.cpu0.op_class::MemWrite 10276382 14.74% 100.00% # Class of executed instruction +system.cpu0.committedInsts 56844590 # Number of instructions committed +system.cpu0.committedOps 68476862 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 60556147 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5891 # Number of float alu accesses +system.cpu0.num_func_calls 5072041 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7664286 # number of instructions that are conditional controls +system.cpu0.num_int_insts 60556147 # number of integer instructions +system.cpu0.num_fp_insts 5891 # number of float instructions +system.cpu0.num_int_register_reads 110162183 # number of times the integer registers were read +system.cpu0.num_int_register_writes 41899351 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4609 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1284 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 247668564 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 26017746 # number of times the CC registers were written +system.cpu0.num_mem_refs 22952183 # number of memory refs +system.cpu0.num_load_insts 12628752 # Number of load instructions +system.cpu0.num_store_insts 10323431 # Number of store instructions +system.cpu0.num_idle_cycles 2690582406.498001 # Number of idle cycles +system.cpu0.num_busy_cycles 213469214.501999 # Number of busy cycles +system.cpu0.not_idle_fraction 0.073507 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.926493 # Percentage of idle cycles +system.cpu0.Branches 13135796 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2207 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 47055843 67.15% 67.15% # Class of executed instruction +system.cpu0.op_class::IntMult 59396 0.08% 67.24% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.24% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4431 0.01% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.25% # Class of executed instruction +system.cpu0.op_class::MemRead 12628752 18.02% 85.27% # Class of executed instruction +system.cpu0.op_class::MemWrite 10323431 14.73% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 69709278 # Class of executed instruction +system.cpu0.op_class::total 70074060 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 3038 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 822797 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.850764 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 43249693 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 823309 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 52.531544 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 320.252560 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 191.598204 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.625493 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.374215 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999709 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 3032 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 821716 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.827808 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 43234238 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 822228 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 52.581812 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1008982250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 377.484524 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 134.343284 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.737274 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.262389 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 177183348 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 177183348 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11600363 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 11519690 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23120053 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 9402507 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 9428435 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18830942 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 198621 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 193510 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 392131 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 227529 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 215892 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 443421 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 235788 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 224612 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460400 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 21002870 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 20948125 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 41950995 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 21201491 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 21141635 # number of overall hits -system.cpu0.dcache.overall_hits::total 42343126 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 199566 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 203021 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 402587 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 147875 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 150867 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 298742 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 56730 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 62226 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 118956 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11165 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 11603 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 22768 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 177115546 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 177115546 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 11742107 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 11368313 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23110420 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 9438605 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 9386535 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 18825140 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 200385 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 191808 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392193 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 230728 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 212742 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 443470 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 239351 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 220930 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 460281 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 21180712 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 20754848 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41935560 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 21381097 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 20946656 # number of overall hits +system.cpu0.dcache.overall_hits::total 42327753 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 202379 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 199779 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 402158 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 143306 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 155169 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 298475 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 60388 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 58192 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 118580 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 11633 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 10971 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 22604 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 347441 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 353888 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 701329 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 404171 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 416114 # number of overall misses -system.cpu0.dcache.overall_misses::total 820285 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2922711750 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 3005321250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5928033000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5690666011 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6074803686 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11765469697 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 136173000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 144644250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 280817250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 75500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 75500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 151000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 8613377761 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 9080124936 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 17693502697 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 8613377761 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 9080124936 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 17693502697 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11799929 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 11722711 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23522640 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 9550382 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 9579302 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 19129684 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 255351 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 255736 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511087 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 238694 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 227495 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 466189 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 235789 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 224613 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 460402 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 21350311 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 21302013 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 42652324 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 21605662 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 21557749 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 43163411 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016912 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017319 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.017115 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015484 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015749 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.222165 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.243321 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232751 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046775 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.051003 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048839 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 345685 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 354948 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 700633 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 406073 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 413140 # number of overall misses +system.cpu0.dcache.overall_misses::total 819213 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 2998718242 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2978169130 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5976887372 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5523492960 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6886936529 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 12410429489 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 144593750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 135344000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 279937750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 164000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8522211202 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 9865105659 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18387316861 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8522211202 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 9865105659 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18387316861 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 11944486 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 11568092 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23512578 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 9581911 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 9541704 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 19123615 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 260773 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 250000 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 510773 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 242361 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 223713 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 466074 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 239353 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 220930 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 460283 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 21526397 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 21109796 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42636193 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 21787170 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 21359796 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43146966 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016943 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.017270 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.017104 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014956 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.016262 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015608 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.231573 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.232768 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.232158 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.047999 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048499 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016273 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016613 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.016443 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018707 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019302 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14645.339136 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14803.006832 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14724.849536 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38482.948511 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40265.954026 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39383.379963 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12196.417376 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12466.107903 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12333.856729 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 75500 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 75500 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 75500 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24790.907697 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25658.188286 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 25228.534250 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 21311.221639 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 21821.243544 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21569.945442 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016059 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.016814 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016433 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018638 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.019342 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.018987 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14817.338963 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14907.318237 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14862.037736 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38543.347522 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 44383.456290 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41579.460554 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12429.618327 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12336.523562 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12384.434171 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 82000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 24653.112522 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27793.101127 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 26243.863565 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 20986.894480 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 23878.360021 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22445.098968 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 686778 # number of writebacks -system.cpu0.dcache.writebacks::total 686778 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 276 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 344 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 620 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7049 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7156 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14205 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 276 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 620 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 276 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 620 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 199290 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 202677 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 401967 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 147875 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 150867 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 298742 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 55842 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 60970 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 116812 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4116 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 4447 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8563 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 687030 # number of writebacks +system.cpu0.dcache.writebacks::total 687030 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 373 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 660 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 7066 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 7026 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14092 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 287 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 373 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 287 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 373 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 202092 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 199406 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 401498 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 143306 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 155169 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 298475 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 59468 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 57033 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 116501 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 4567 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 3945 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8512 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 2 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 347165 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 353544 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 700709 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 403007 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 414514 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 817521 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2517038250 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2591733500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5108771750 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5367510939 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 5742623268 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11110134207 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 678934750 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 762190250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1441125000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 48430250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 52495750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 100926000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 73500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 73500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 147000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7884549189 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 8334356768 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 16218905957 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8563483939 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 9096547018 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17660030957 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2685824500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3105604250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5791428750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2183466000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2246337500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4429803500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4869290500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5351941750 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10221232250 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016889 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017289 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017089 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.015484 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015749 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.218687 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.238410 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228556 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017244 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019548 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018368 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 345398 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 354575 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 699973 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 404866 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 411608 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 816474 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2687850000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2671783250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5359633250 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5284681040 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6621405971 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 11906087011 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 749127008 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 719245636 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1468372644 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 55884250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 49619250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 105503500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7972531040 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 9293189221 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 17265720261 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8721658048 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10012434857 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 18734092905 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2822172000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3011105500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5833277500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2259926000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2253271000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4513197000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5082098000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5264376500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10346474500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016919 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.017238 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017076 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014956 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016262 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015608 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228045 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.228132 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228088 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.018844 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.017634 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018263 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000008 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016597 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.016428 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018653 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019228 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12630.027849 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12787.506723 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12709.430749 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36297.622580 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38064.144366 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37189.729623 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12158.138140 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12501.070198 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12337.131459 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11766.338678 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11804.756015 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11786.289852 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 73500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 73500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22711.244477 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23573.746883 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23146.421634 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21248.970710 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21945.089956 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21601.929439 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016045 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.016797 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016417 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018583 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.019270 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018923 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13300.130634 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13398.710420 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13349.090780 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36876.900060 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 42672.221713 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39889.729495 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12597.144817 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12611.043361 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12603.948842 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12236.533830 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12577.756654 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12394.678102 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23082.157511 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 26209.375227 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24666.266072 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -859,79 +834,79 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699876 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.774945 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 113899876 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1700388 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 66.984639 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.439814 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.335131 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.819218 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.178389 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1701384 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 113852033 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1701896 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 66.897174 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 25697074250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 399.197143 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 111.536926 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.779682 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.217846 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997527 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 251 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 117300664 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 117300664 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 57350245 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 56549631 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 113899876 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 57350245 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 56549631 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 113899876 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 57350245 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 56549631 # number of overall hits -system.cpu0.icache.overall_hits::total 113899876 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 848187 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 852207 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1700394 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 848187 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 852207 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1700394 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 848187 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 852207 # number of overall misses -system.cpu0.icache.overall_misses::total 1700394 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11567227499 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11741384499 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 23308611998 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 11567227499 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 11741384499 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 23308611998 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 11567227499 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 11741384499 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 23308611998 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 58198432 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 57401838 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 115600270 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 58198432 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 57401838 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 115600270 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 58198432 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 57401838 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 115600270 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014574 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014846 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014709 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014574 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014846 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014709 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014574 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014846 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014709 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13637.591120 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13777.620342 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13707.771257 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13637.591120 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13777.620342 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13707.771257 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13637.591120 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13777.620342 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13707.771257 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 117255837 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 117255837 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 57557381 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 56294652 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 113852033 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 57557381 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 56294652 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 113852033 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 57557381 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 56294652 # number of overall hits +system.cpu0.icache.overall_hits::total 113852033 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 856651 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 845251 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1701902 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 856651 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 845251 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1701902 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 856651 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 845251 # number of overall misses +system.cpu0.icache.overall_misses::total 1701902 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11730914498 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11646451999 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 23377366497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 11730914498 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 11646451999 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 23377366497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 11730914498 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 11646451999 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 23377366497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 58414032 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 57139903 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 115553935 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 58414032 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 57139903 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 115553935 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 58414032 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 57139903 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 115553935 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014665 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014793 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014728 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014665 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014793 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014728 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014665 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014793 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014728 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.924945 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13778.690589 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13736.023870 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13736.023870 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.924945 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13778.690589 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13736.023870 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -940,46 +915,46 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 848187 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 852207 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1700394 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 848187 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 852207 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1700394 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 848187 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 852207 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1700394 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9867956501 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10033302501 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19901259002 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9867956501 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10033302501 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19901259002 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9867956501 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10033302501 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19901259002 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014709 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014709 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014574 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014846 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014709 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11703.910389 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11703.910389 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11634.175602 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11773.316226 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11703.910389 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 856651 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 845251 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1701902 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 856651 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 845251 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1701902 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10442855002 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10375133501 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 20817988503 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10442855002 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10375133501 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 20817988503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 677067750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014728 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014728 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014665 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014793 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014728 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.189928 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency @@ -1014,61 +989,60 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 6287 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 6287 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1877 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4409 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walks 6646 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 6646 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 1848 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4797 # Level at which table walker walks with short descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 6286 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 6286 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 6286 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5205 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 10664.029395 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8432.528945 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7016.441417 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 4168 80.08% 80.08% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 1031 19.81% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-81919 3 0.06% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-98303 2 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-180223 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5205 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 2238481496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.553158 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.497166 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1000247500 44.68% 44.68% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 1238233996 55.32% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 2238481496 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 3350 64.37% 64.37% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 1854 35.63% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 5204 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 6645 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 6645 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 6645 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5540 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12435.469314 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10508.495094 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6654.820556 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1371 24.75% 24.75% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2761 49.84% 74.58% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 1405 25.36% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::81920-90111 3 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5540 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -586099820 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 2.706592 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::gmean inf # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1000233500 -170.66% -170.66% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 -1586333320 270.66% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -586099820 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 3714 67.05% 67.05% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 1825 32.95% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 5539 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 6646 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6287 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5204 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 6646 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 5539 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5204 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 11491 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5539 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 12185 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12222323 # DTB read hits -system.cpu1.dtb.read_misses 5479 # DTB read misses -system.cpu1.dtb.write_hits 9816234 # DTB write hits -system.cpu1.dtb.write_misses 808 # DTB write misses -system.cpu1.dtb.flush_tlb 2935 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu1.dtb.read_hits 12057381 # DTB read hits +system.cpu1.dtb.read_misses 5757 # DTB read misses +system.cpu1.dtb.write_hits 9774636 # DTB write hits +system.cpu1.dtb.write_misses 889 # DTB write misses +system.cpu1.dtb.flush_tlb 2932 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 4100 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 4087 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 935 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1001 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 226 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12227802 # DTB read accesses -system.cpu1.dtb.write_accesses 9817042 # DTB write accesses +system.cpu1.dtb.perms_faults 205 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12063138 # DTB read accesses +system.cpu1.dtb.write_accesses 9775525 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 22038557 # DTB hits -system.cpu1.dtb.misses 6287 # DTB misses -system.cpu1.dtb.accesses 22044844 # DTB accesses +system.cpu1.dtb.hits 21832017 # DTB hits +system.cpu1.dtb.misses 6646 # DTB misses +system.cpu1.dtb.accesses 21838663 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1098,127 +1072,125 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3158 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3158 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 699 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2459 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 3158 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3158 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3158 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 2331 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 10972.758473 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8658.635701 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6654.132285 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::2048-4095 701 30.07% 30.07% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 5 0.21% 30.29% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 1063 45.60% 75.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 47 2.02% 77.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 1 0.04% 77.95% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-22527 442 18.96% 96.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 72 3.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 2331 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1000205500 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1000205500 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1000205500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1632 70.01% 70.01% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 699 29.99% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2331 # Table walker page sizes translated +system.cpu1.itb.walker.walks 3230 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3230 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 673 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2557 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 3230 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3230 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3230 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 2426 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12666.941467 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10866.952957 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6275.492791 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::2048-4095 541 22.30% 22.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 673 27.74% 50.04% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 619 25.52% 75.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-22527 528 21.76% 97.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 65 2.68% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 2426 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1000198000 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1000198000 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1000198000 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 1753 72.26% 72.26% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 673 27.74% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2426 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3158 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3158 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3230 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3230 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2331 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2331 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5489 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 57401838 # ITB inst hits -system.cpu1.itb.inst_misses 3158 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2426 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2426 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5656 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 57139903 # ITB inst hits +system.cpu1.itb.inst_misses 3230 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 2935 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 481 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb 2932 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 421 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2358 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2427 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 57404996 # ITB inst accesses -system.cpu1.itb.hits 57401838 # DTB hits -system.cpu1.itb.misses 3158 # DTB misses -system.cpu1.itb.accesses 57404996 # DTB accesses -system.cpu1.numCycles 2904048276 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 57143133 # ITB inst accesses +system.cpu1.itb.hits 57139903 # DTB hits +system.cpu1.itb.misses 3230 # DTB misses +system.cpu1.itb.accesses 57143133 # DTB accesses +system.cpu1.numCycles 2903230224 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 55844358 # Number of instructions committed -system.cpu1.committedOps 67482566 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 59712832 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5183 # Number of float alu accesses -system.cpu1.num_func_calls 4980648 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 7553958 # number of instructions that are conditional controls -system.cpu1.num_int_insts 59712832 # number of integer instructions -system.cpu1.num_fp_insts 5183 # number of float instructions -system.cpu1.num_int_register_reads 108693830 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41104260 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4030 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1154 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 243842957 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 25682716 # number of times the CC registers were written -system.cpu1.num_mem_refs 22677996 # number of memory refs -system.cpu1.num_load_insts 12382220 # Number of load instructions -system.cpu1.num_store_insts 10295776 # Number of store instructions -system.cpu1.num_idle_cycles 2693878470.584054 # Number of idle cycles -system.cpu1.num_busy_cycles 210169805.415946 # Number of busy cycles -system.cpu1.not_idle_fraction 0.072371 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.927629 # Percentage of idle cycles -system.cpu1.Branches 12913817 # Number of branches fetched -system.cpu1.op_class::No_OpClass 134 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 46316521 67.07% 67.07% # Class of executed instruction -system.cpu1.op_class::IntMult 55928 0.08% 67.15% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.15% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4215 0.01% 67.16% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 67.16% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.16% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.16% # Class of executed instruction -system.cpu1.op_class::MemRead 12382220 17.93% 85.09% # Class of executed instruction -system.cpu1.op_class::MemWrite 10295776 14.91% 100.00% # Class of executed instruction +system.cpu1.committedInsts 55611529 # Number of instructions committed +system.cpu1.committedOps 67110942 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 59336824 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 5270 # Number of float alu accesses +system.cpu1.num_func_calls 4819801 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 7566653 # number of instructions that are conditional controls +system.cpu1.num_int_insts 59336824 # number of integer instructions +system.cpu1.num_fp_insts 5270 # number of float instructions +system.cpu1.num_int_register_reads 107900734 # number of times the integer registers were read +system.cpu1.num_int_register_writes 40745080 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3840 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1432 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 242074272 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 25879956 # number of times the CC registers were written +system.cpu1.num_mem_refs 22456627 # number of memory refs +system.cpu1.num_load_insts 12214155 # Number of load instructions +system.cpu1.num_store_insts 10242472 # Number of store instructions +system.cpu1.num_idle_cycles 2696428184.778518 # Number of idle cycles +system.cpu1.num_busy_cycles 206802039.221482 # Number of busy cycles +system.cpu1.not_idle_fraction 0.071232 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.928768 # Percentage of idle cycles +system.cpu1.Branches 12781357 # Number of branches fetched +system.cpu1.op_class::No_OpClass 130 0.00% 0.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 46119057 67.20% 67.20% # Class of executed instruction +system.cpu1.op_class::IntMult 54779 0.08% 67.28% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4036 0.01% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.28% # Class of executed instruction +system.cpu1.op_class::MemRead 12214155 17.80% 85.08% # Class of executed instruction +system.cpu1.op_class::MemWrite 10242472 14.92% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69054794 # Class of executed instruction +system.cpu1.op_class::total 68634629 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1239,11 +1211,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1264,11 +1236,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1308,23 +1280,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347068533 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198848287 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36807005 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.084285 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.134606 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 309430209000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.084285 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.067768 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.067768 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 299121172000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.134606 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1338,14 +1310,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9589202651 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9589202651 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29267377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29267377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6633096905 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6633096905 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29267377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29267377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29267377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29267377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1362,19 +1334,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264719.596152 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264719.596152 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55434 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 125074.260684 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125074.260684 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183113.320036 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183113.320036 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125074.260684 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 125074.260684 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125074.260684 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22198 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7152 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3387 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.750839 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.553882 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1388,14 +1360,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7705544661 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7705544661 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16965377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16965377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4749438915 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4749438915 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16965377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16965377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16965377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16965377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1404,255 +1376,250 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212719.320368 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212719.320368 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72501.611111 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72501.611111 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131113.044252 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131113.044252 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72501.611111 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72501.611111 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 89554 # number of replacements -system.l2c.tags.tagsinuse 64927.556568 # Cycle average of tags in use -system.l2c.tags.total_refs 2767374 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 154795 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 17.877670 # Average number of references to valid blocks. +system.l2c.tags.replacements 86345 # number of replacements +system.l2c.tags.tagsinuse 64916.534496 # Cycle average of tags in use +system.l2c.tags.total_refs 2772933 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 151598 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 18.291356 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 50576.969864 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943928 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3885.587272 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2054.187516 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768426 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 5757.064003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2648.035097 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.771743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059289 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.031344 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000073 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.087846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.040406 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.990716 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 50295.187878 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.860187 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.965052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4502.634002 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2814.628972 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.894234 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 5158.115832 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2140.248339 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.767444 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.068705 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000029 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.078707 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.032658 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.990548 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65236 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65248 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 20 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6815 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 56246 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2139 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6724 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 56346 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.995422 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26304357 # Number of tag accesses -system.l2c.tags.data_accesses 26304357 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6457 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3455 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 840087 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 253709 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5233 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 2755 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 842268 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 261492 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2215456 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 686778 # number of Writeback hits -system.l2c.Writeback_hits::total 686778 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 84285 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 80755 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 165040 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6457 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3455 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 840087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 337994 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5233 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 2755 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 842268 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 342247 # number of demand (read+write) hits -system.l2c.demand_hits::total 2380496 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6457 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3455 # number of overall hits -system.l2c.overall_hits::cpu0.inst 840087 # number of overall hits -system.l2c.overall_hits::cpu0.data 337994 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5233 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 2755 # number of overall hits -system.l2c.overall_hits::cpu1.inst 842268 # number of overall hits -system.l2c.overall_hits::cpu1.data 342247 # number of overall hits -system.l2c.overall_hits::total 2380496 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 8081 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 5539 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 9933 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6602 # number of ReadReq misses -system.l2c.ReadReq_misses::total 30164 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 1351 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1370 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2721 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses +system.l2c.tags.occ_task_id_percent::1024 0.995605 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 26318997 # Number of tag accesses +system.l2c.tags.data_accesses 26318997 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6505 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3514 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 848098 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 260151 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3258 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 835810 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 254237 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2217790 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 687030 # number of Writeback hits +system.l2c.Writeback_hits::total 687030 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 16 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 87471 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 80339 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 167810 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6505 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3514 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 848098 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 347622 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6217 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3258 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 835810 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 334576 # number of demand (read+write) hits +system.l2c.demand_hits::total 2385600 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6505 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3514 # number of overall hits +system.l2c.overall_hits::cpu0.inst 848098 # number of overall hits +system.l2c.overall_hits::cpu0.data 347622 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6217 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3258 # number of overall hits +system.l2c.overall_hits::cpu1.inst 835810 # number of overall hits +system.l2c.overall_hits::cpu1.data 334576 # number of overall hits +system.l2c.overall_hits::total 2385600 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 8541 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5976 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 9421 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6147 # number of ReadReq misses +system.l2c.ReadReq_misses::total 30094 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1338 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1365 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2703 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 62227 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 68731 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130958 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8081 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 67766 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 7 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 9933 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 75333 # number of demand (read+write) misses -system.l2c.demand_misses::total 161122 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 8081 # number of overall misses -system.l2c.overall_misses::cpu0.data 67766 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 7 # number of overall misses -system.l2c.overall_misses::cpu1.inst 9933 # number of overall misses -system.l2c.overall_misses::cpu1.data 75333 # number of overall misses -system.l2c.overall_misses::total 161122 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 589837500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 423411750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 565750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 727930000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 495576749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2237471249 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 208991 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 255489 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 464480 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 72500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 72500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 145000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4319557815 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4724128661 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9043686476 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 589837500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 4742969565 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 565750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 727930000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 5219705410 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 11281157725 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 589837500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 4742969565 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 565750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 727930000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 5219705410 # number of overall miss cycles -system.l2c.overall_miss_latency::total 11281157725 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 6458 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3456 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 848168 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 259248 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5240 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 2755 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 852201 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 268094 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2245620 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 686778 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 686778 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 1363 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 1381 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2744 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses::cpu0.data 54481 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 73452 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 127933 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 8541 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 60457 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 9421 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 79599 # number of demand (read+write) misses +system.l2c.demand_misses::total 158027 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 8541 # number of overall misses +system.l2c.overall_misses::cpu0.data 60457 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu1.inst 9421 # number of overall misses +system.l2c.overall_misses::cpu1.data 79599 # number of overall misses +system.l2c.overall_misses::total 158027 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 261750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 166000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 681157002 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 494631258 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 330000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 753847500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 510531136 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2440924646 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 341989 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 434486 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 776475 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 159000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4180870378 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 5579789336 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9760659714 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 261750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 166000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 681157002 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 4675501636 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 330000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 753847500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 6090320472 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 12201584360 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 261750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 166000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 681157002 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 4675501636 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 330000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 753847500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 6090320472 # number of overall miss cycles +system.l2c.overall_miss_latency::total 12201584360 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 6508 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3516 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 856639 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 266127 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 6221 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 3258 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 845231 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 260384 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2247884 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 687030 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 687030 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1354 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 1378 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2732 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 146512 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 149486 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 295998 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 6458 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3456 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 848168 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 405760 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5240 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 2755 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 852201 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 417580 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2541618 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 6458 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3456 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 848168 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 405760 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5240 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 2755 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 852201 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 417580 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2541618 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000155 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000289 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.009528 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.021366 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.001336 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.011656 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024626 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.013432 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.991196 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992035 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991618 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 141952 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 153791 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295743 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 6508 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3516 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 856639 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 408079 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 6221 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 3258 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 845231 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 414175 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2543627 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 6508 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3516 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 856639 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 408079 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 6221 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 3258 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 845231 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 414175 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2543627 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000569 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.009970 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.022455 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.011146 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.023607 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.013388 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.988183 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.990566 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989385 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.424723 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.459782 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.442429 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000155 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000289 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.009528 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.167010 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.001336 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.011656 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.180404 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.063393 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000155 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000289 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.009528 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.167010 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.001336 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.011656 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.180404 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.063393 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 72990.657097 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 76441.911897 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80821.428571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73284.002819 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75064.639352 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 74176.874718 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 154.693560 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 186.488321 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 170.701948 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 72500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 72500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 72500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 69416.134716 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68733.594171 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69057.915332 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 72990.657097 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 69990.401750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80821.428571 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 73284.002819 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 69288.431497 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 70016.246850 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 72990.657097 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 69990.401750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80821.428571 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 73284.002819 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69288.431497 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 70016.246850 # average overall miss latency +system.l2c.ReadExReq_miss_rate::cpu0.data 0.383799 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.477609 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.432582 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000569 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.009970 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.148150 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.011146 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.192187 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.062127 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000461 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000569 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.009970 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.148150 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000643 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.011146 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.192187 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.062127 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 87250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 83000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 79751.434492 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 82769.621486 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80017.779429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 83053.706849 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 81110.010168 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 255.597160 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 318.304762 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 287.264151 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 79500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76739.971329 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75965.111039 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76295.089727 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 77335.984849 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 77212.023009 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 87250 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 83000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 79751.434492 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 77335.984849 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 80017.779429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76512.524931 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 77212.023009 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1661,151 +1628,147 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 82876 # number of writebacks -system.l2c.writebacks::total 82876 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 8081 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 5539 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 9933 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6602 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 30164 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 1351 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1370 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.writebacks::writebacks 79977 # number of writebacks +system.l2c.writebacks::total 79977 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 8541 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 5976 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 9421 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6147 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 30094 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 1338 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1365 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 2703 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 2 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 62227 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 68731 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 130958 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 8081 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 67766 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 7 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 9933 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 75333 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 161122 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 8081 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 67766 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 7 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 9933 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 75333 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 161122 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 487730500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 354370250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 478750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 602289500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 413151749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1858145749 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 13563351 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 13796370 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 27359721 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 60500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 60500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 121000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3523043185 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3843695339 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7366738524 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 487730500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 3877413435 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 478750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 602289500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 4256847088 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 9224884273 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 487730500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 3877413435 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 478750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 602289500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 4256847088 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 9224884273 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 474215000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2493378000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2892620500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5860213500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1997125000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2101188000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4098313000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 474215000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4490503000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4993808500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 9958526500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000155 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000289 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.021366 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001336 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011656 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024626 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.013432 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991196 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992035 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991618 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_misses::cpu0.data 54481 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 73452 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 127933 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 8541 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 60457 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 9421 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 79599 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 158027 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 3 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 8541 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 60457 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 9421 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 79599 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 158027 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 223750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 141000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 574142498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 419922242 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 635806000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 433639364 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 2064154854 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 23826338 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 24325865 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 48152203 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 135000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3498745622 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4660357664 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 8159103286 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 223750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 141000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 574142498 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 3918667864 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 280000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 635806000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 5093997028 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 10223258140 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 223750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 141000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 574142498 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 3918667864 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 280000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 635806000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 5093997028 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 10223258140 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 546237750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2603822250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2793047000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5943107000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2054472000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2099890500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4154362500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 546237750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4658294250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4892937500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10097469500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.022455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.023607 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.013388 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.988183 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.990566 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.989385 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.424723 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.459782 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.442429 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000155 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000289 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.167010 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001336 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011656 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.180404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.063393 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000155 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000289 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009528 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.167010 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001336 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011656 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.180404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.063393 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60355.215939 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63977.297346 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62579.786277 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 61601.437110 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10039.490007 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.343066 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10055.024256 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 60500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60500 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 60500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56615.989603 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55923.751131 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56252.680432 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60355.215939 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57217.681950 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56507.069783 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57254.032801 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60355.215939 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57217.681950 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68392.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60635.205879 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56507.069783 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57254.032801 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.383799 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.477609 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.432582 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.062127 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000461 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000569 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009970 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.148150 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000643 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011146 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.192187 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.062127 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70268.112784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70544.877827 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 68590.245697 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17807.427504 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17821.146520 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17814.355531 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 64219.555845 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63447.661929 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63776.377369 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74583.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67221.929282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64817.438245 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -1818,57 +1781,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70570 # Transaction distribution -system.membus.trans_dist::ReadResp 70570 # Transaction distribution -system.membus.trans_dist::WriteReq 27613 # Transaction distribution -system.membus.trans_dist::WriteResp 27613 # Transaction distribution -system.membus.trans_dist::Writeback 119066 # Transaction distribution +system.membus.trans_dist::ReadReq 70492 # Transaction distribution +system.membus.trans_dist::ReadResp 70492 # Transaction distribution +system.membus.trans_dist::WriteReq 27594 # Transaction distribution +system.membus.trans_dist::WriteResp 27594 # Transaction distribution +system.membus.trans_dist::Writeback 116167 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4495 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4489 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4497 # Transaction distribution -system.membus.trans_dist::ReadExReq 129184 # Transaction distribution -system.membus.trans_dist::ReadExResp 129184 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4491 # Transaction distribution +system.membus.trans_dist::ReadExReq 126147 # Transaction distribution +system.membus.trans_dist::ReadExResp 126147 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438193 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 545857 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 429068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 536678 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 654744 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 645565 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15540476 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 15703901 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15156092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 15319481 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20339357 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 319369 # Request fanout histogram +system.membus.snoop_fanout::samples 313389 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 319369 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 313389 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 319369 # Request fanout histogram -system.membus.reqLayer0.occupancy 87174000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 313389 # Request fanout histogram +system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1737000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1721500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1663053000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1641418005 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 960656101 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 947025657 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37465995 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1901,54 +1864,52 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2303048 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2303033 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 686778 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2744 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2303937 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2303837 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27594 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27594 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 687030 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36246 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2732 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2746 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 295998 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 295998 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3418807 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2456695 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18188 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34627 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5928317 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108859704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96844773 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24844 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46792 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205776113 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 53699 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3284622 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011100 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.104768 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 2734 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 295743 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 295743 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3421816 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2454612 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18880 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 35749 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5931057 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108955768 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96785921 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 52269 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3285526 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011103 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.104785 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3248164 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3249046 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36480 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3284622 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4418893499 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3285526 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 7666187498 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 3782041495 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11977000 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 2567253247 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1309775845 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 12106000 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 22953702 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 23020250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt index f7aa432dd..f6bd584fc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.355615 # Number of seconds simulated -sim_ticks 47355615197500 # Number of ticks simulated -final_tick 47355615197500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.357291 # Number of seconds simulated +sim_ticks 47357290872500 # Number of ticks simulated +final_tick 47357290872500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 119180 # Simulator instruction rate (inst/s) -host_op_rate 140167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6305360463 # Simulator tick rate (ticks/s) -host_mem_usage 747912 # Number of bytes of host memory used -host_seconds 7510.37 # Real time elapsed on the host -sim_insts 895084962 # Number of instructions simulated -sim_ops 1052703090 # Number of ops (including micro ops) simulated +host_inst_rate 179609 # Simulator instruction rate (inst/s) +host_op_rate 211253 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 9509351214 # Simulator tick rate (ticks/s) +host_mem_usage 764316 # Number of bytes of host memory used +host_seconds 4980.08 # Real time elapsed on the host +sim_insts 894465242 # Number of instructions simulated +sim_ops 1052057457 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 106496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 83264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 8104128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10821016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 17557952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 158592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 147776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3589696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 10178208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 16399360 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 427968 # Number of bytes read from this memory -system.physmem.bytes_read::total 67574456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 8104128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3589696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 11693824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 78266240 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 141696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 131328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 8696576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 13989464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 21378112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 133248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 113344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3297088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7559072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 13082368 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 433472 # Number of bytes read from this memory +system.physmem.bytes_read::total 68955768 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 8696576 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3297088 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11993664 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 79042240 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 78287056 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1664 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1301 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 126627 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 169100 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 274343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2478 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2309 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 56089 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 159049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 256240 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6687 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1055887 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1222910 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 79063056 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2214 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2052 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 135884 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 218607 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 334033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2082 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 51517 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 118125 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 204412 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6773 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1077470 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1235035 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1225513 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 1758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 171133 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 228505 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 370768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 75803 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 214931 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 346302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1426958 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 171133 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 75803 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 246936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1652734 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1237638 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 183638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 295403 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 451422 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2814 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 69622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 159618 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 276248 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1456075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 183638 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 69622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 253259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1669062 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1653174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1652734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2249 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 1758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 171133 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 228945 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 370768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 75803 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 214931 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 346302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3080131 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1055887 # Number of read requests accepted -system.physmem.writeReqs 1888199 # Number of write requests accepted -system.physmem.readBursts 1055887 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1888199 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 67557888 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue -system.physmem.bytesWritten 120408192 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 67574456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 120698960 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6789 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 114993 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 58784 # Per bank write bursts -system.physmem.perBankRdBursts::1 68771 # Per bank write bursts -system.physmem.perBankRdBursts::2 59130 # Per bank write bursts -system.physmem.perBankRdBursts::3 67531 # Per bank write bursts -system.physmem.perBankRdBursts::4 66855 # Per bank write bursts -system.physmem.perBankRdBursts::5 75133 # Per bank write bursts -system.physmem.perBankRdBursts::6 65903 # Per bank write bursts -system.physmem.perBankRdBursts::7 67407 # Per bank write bursts -system.physmem.perBankRdBursts::8 54196 # Per bank write bursts -system.physmem.perBankRdBursts::9 110706 # Per bank write bursts -system.physmem.perBankRdBursts::10 54461 # Per bank write bursts -system.physmem.perBankRdBursts::11 64104 # Per bank write bursts -system.physmem.perBankRdBursts::12 57097 # Per bank write bursts -system.physmem.perBankRdBursts::13 66166 # Per bank write bursts -system.physmem.perBankRdBursts::14 60751 # Per bank write bursts -system.physmem.perBankRdBursts::15 58597 # Per bank write bursts -system.physmem.perBankWrBursts::0 116651 # Per bank write bursts -system.physmem.perBankWrBursts::1 125865 # Per bank write bursts -system.physmem.perBankWrBursts::2 118664 # Per bank write bursts -system.physmem.perBankWrBursts::3 124773 # Per bank write bursts -system.physmem.perBankWrBursts::4 121001 # Per bank write bursts -system.physmem.perBankWrBursts::5 125597 # Per bank write bursts -system.physmem.perBankWrBursts::6 113710 # Per bank write bursts -system.physmem.perBankWrBursts::7 116980 # Per bank write bursts -system.physmem.perBankWrBursts::8 110183 # Per bank write bursts -system.physmem.perBankWrBursts::9 114411 # Per bank write bursts -system.physmem.perBankWrBursts::10 109841 # Per bank write bursts -system.physmem.perBankWrBursts::11 116847 # Per bank write bursts -system.physmem.perBankWrBursts::12 116927 # Per bank write bursts -system.physmem.perBankWrBursts::13 118874 # Per bank write bursts -system.physmem.perBankWrBursts::14 112844 # Per bank write bursts -system.physmem.perBankWrBursts::15 118210 # Per bank write bursts +system.physmem.bw_write::total 1669501 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1669062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2992 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 183638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 295842 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 451422 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2814 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2393 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 69622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 159618 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 276248 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3125576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1077470 # Number of read requests accepted +system.physmem.writeReqs 1907210 # Number of write requests accepted +system.physmem.readBursts 1077470 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1907210 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 68937984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20096 # Total number of bytes read from write queue +system.physmem.bytesWritten 118940800 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 68955768 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 121915664 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 314 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 48739 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 118611 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 58565 # Per bank write bursts +system.physmem.perBankRdBursts::1 71236 # Per bank write bursts +system.physmem.perBankRdBursts::2 60619 # Per bank write bursts +system.physmem.perBankRdBursts::3 68763 # Per bank write bursts +system.physmem.perBankRdBursts::4 63623 # Per bank write bursts +system.physmem.perBankRdBursts::5 74242 # Per bank write bursts +system.physmem.perBankRdBursts::6 69161 # Per bank write bursts +system.physmem.perBankRdBursts::7 67695 # Per bank write bursts +system.physmem.perBankRdBursts::8 61029 # Per bank write bursts +system.physmem.perBankRdBursts::9 112215 # Per bank write bursts +system.physmem.perBankRdBursts::10 55292 # Per bank write bursts +system.physmem.perBankRdBursts::11 71140 # Per bank write bursts +system.physmem.perBankRdBursts::12 63760 # Per bank write bursts +system.physmem.perBankRdBursts::13 63951 # Per bank write bursts +system.physmem.perBankRdBursts::14 57537 # Per bank write bursts +system.physmem.perBankRdBursts::15 58328 # Per bank write bursts +system.physmem.perBankWrBursts::0 113661 # Per bank write bursts +system.physmem.perBankWrBursts::1 123588 # Per bank write bursts +system.physmem.perBankWrBursts::2 119813 # Per bank write bursts +system.physmem.perBankWrBursts::3 126847 # Per bank write bursts +system.physmem.perBankWrBursts::4 114977 # Per bank write bursts +system.physmem.perBankWrBursts::5 123724 # Per bank write bursts +system.physmem.perBankWrBursts::6 117451 # Per bank write bursts +system.physmem.perBankWrBursts::7 117840 # Per bank write bursts +system.physmem.perBankWrBursts::8 112656 # Per bank write bursts +system.physmem.perBankWrBursts::9 114020 # Per bank write bursts +system.physmem.perBankWrBursts::10 109420 # Per bank write bursts +system.physmem.perBankWrBursts::11 118853 # Per bank write bursts +system.physmem.perBankWrBursts::12 108855 # Per bank write bursts +system.physmem.perBankWrBursts::13 111956 # Per bank write bursts +system.physmem.perBankWrBursts::14 111151 # Per bank write bursts +system.physmem.perBankWrBursts::15 113638 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 47355613259000 # Total gap between requests +system.physmem.numWrRetry 260 # Number of times write queue was full causing retry +system.physmem.totGap 47357288950000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1055845 # Read request sizes (log2) +system.physmem.readPktSize::6 1077428 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1885596 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 695873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 103690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 41556 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 38114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 34076 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 30233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 21396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 5411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3052 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2413 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1873 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 532 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 364 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 274 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1904607 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 705573 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 108235 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 48143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 42943 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 38392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 34676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 30928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26708 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 22131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 7359 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 2189 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1653 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 376 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,179 +188,169 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 41751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 61472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 87023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 107335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 120415 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 125723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 127870 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 127803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 120389 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 118443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 115533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 109052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 105629 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 105973 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 96497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 93321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 90489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 85925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 6797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 5240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 4118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2547 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 819 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 455 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1046123 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 179.678328 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 108.587927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 250.922876 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 666099 63.67% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 200536 19.17% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 50293 4.81% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 24222 2.32% 89.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 17786 1.70% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12328 1.18% 92.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8853 0.85% 93.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7558 0.72% 94.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 58448 5.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1046123 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79224 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 13.323930 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 140.057237 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 79222 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 44576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 64765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 92305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 104587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 111564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 110175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 106822 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 101643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 99926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 96867 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 96399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 113990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 101913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 97920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 100658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 96398 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 8098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 6069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4413 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 4155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 4227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 907 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 693 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 412 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 263 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 781 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 1066280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 176.199272 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 107.583604 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.477591 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 681708 63.93% 63.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 204893 19.22% 83.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51569 4.84% 87.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 24658 2.31% 90.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19159 1.80% 92.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12349 1.16% 93.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8689 0.81% 94.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7706 0.72% 94.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 55549 5.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1066280 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 82344 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.080819 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 137.450182 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 82341 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79224 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79224 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.747576 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.323530 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.901705 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 65925 83.21% 83.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 5556 7.01% 90.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 2071 2.61% 92.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 1166 1.47% 94.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1087 1.37% 95.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 456 0.58% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 393 0.50% 96.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 290 0.37% 97.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 329 0.42% 97.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 179 0.23% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 294 0.37% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 101 0.13% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 139 0.18% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 103 0.13% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 155 0.20% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 83 0.10% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 89 0.11% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 58 0.07% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 57 0.07% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 65 0.08% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 66 0.08% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 81 0.10% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 58 0.07% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 58 0.07% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 69 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 72 0.09% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 57 0.07% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 44 0.06% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 31 0.04% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 21 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 22 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 15 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 7 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::280-287 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-295 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::296-303 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-311 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::312-319 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-327 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::328-335 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-343 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::344-351 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-359 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::360-367 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-375 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::376-383 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-391 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::456-463 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-503 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79224 # Writes before turning the bus around for reads -system.physmem.totQLat 39480003252 # Total ticks spent queuing -system.physmem.totMemAccLat 59272353252 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5277960000 # Total ticks spent in databus transfers -system.physmem.avgQLat 37400.82 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 82344 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 82344 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 22.569343 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.983627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 21.346474 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 74619 90.62% 90.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 3701 4.49% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 1617 1.96% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 776 0.94% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 389 0.47% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 290 0.35% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 467 0.57% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 184 0.22% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 57 0.07% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 20 0.02% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 62 0.08% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 36 0.04% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.00% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 13 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 9 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 24 0.03% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 3 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 82344 # Writes before turning the bus around for reads +system.physmem.totQLat 41096385470 # Total ticks spent queuing +system.physmem.totMemAccLat 61293060470 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5385780000 # Total ticks spent in databus transfers +system.physmem.avgQLat 38152.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 56150.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.54 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.43 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.55 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 56902.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.46 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.51 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.46 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.57 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.00 # Average write queue length when enqueuing -system.physmem.readRowHits 797783 # Number of row buffer hits during reads -system.physmem.writeRowHits 1093063 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.10 # Row buffer hit rate for writes -system.physmem.avgGap 16084996.59 # Average gap between requests -system.physmem.pageHitRate 64.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4126437000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2251528125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4130209200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6241801680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1193820708150 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27366157608000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31669766818395 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.764772 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45525574397500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem.avgWrQLen 25.47 # Average write queue length when enqueuing +system.physmem.readRowHits 809420 # Number of row buffer hits during reads +system.physmem.writeRowHits 1059902 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.03 # Row buffer hit rate for writes +system.physmem.avgGap 15866789.39 # Average gap between requests +system.physmem.pageHitRate 63.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4185760320 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2283897000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4164435600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6207198480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1197399382470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27364022846250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31671411386760 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.775859 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45522011263316 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581363940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 248732168750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 253913912184 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3782252880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2063729250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4103353800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5949527760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3093038526240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1183965961905 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27374802122250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31667705474085 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.721243 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45539970549502 # Time in different power states -system.physmem_1.memoryStateTime::REF 1581308040000 # Time in different power states +system.physmem_1.actEnergy 3875316480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2114508000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4237256400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5835557520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093147866640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1190113153695 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27370414275000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31669737933735 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.740522 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45532636458203 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581363940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 234336016748 # Time in different power states +system.physmem_1.memoryStateTime::ACT 243288251797 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -394,15 +384,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 131272413 # Number of BP lookups -system.cpu0.branchPred.condPredicted 92904470 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 6038757 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 98925935 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 71271707 # Number of BTB hits +system.cpu0.branchPred.lookups 151571686 # Number of BP lookups +system.cpu0.branchPred.condPredicted 107212809 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6769997 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 114323741 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 82790418 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.045523 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15434878 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 1076370 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.417520 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17895403 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 1177591 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -433,67 +423,61 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 271399 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 271399 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8182 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72706 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 271399 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 271399 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 271399 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 80888 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 17168.766430 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15272.701717 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 12980.054286 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 77350 95.63% 95.63% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2802 3.46% 99.09% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 370 0.46% 99.55% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 250 0.31% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 18 0.02% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 21 0.03% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 10 0.01% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 23 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 80888 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 644436704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 644436704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 644436704 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 72706 89.88% 89.88% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 8182 10.12% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 80888 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 271399 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 310912 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 310912 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11841 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90150 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 310912 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 310912 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 310912 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 101991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 19193.830760 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17232.192163 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 15084.416179 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 100737 98.77% 98.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1058 1.04% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 37 0.04% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 76 0.07% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 58 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 6 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 101991 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 90150 88.39% 88.39% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11841 11.61% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 101991 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 310912 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 271399 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 80888 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 310912 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 101991 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 80888 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 352287 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 101991 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 412903 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83830376 # DTB read hits -system.cpu0.dtb.read_misses 224800 # DTB read misses -system.cpu0.dtb.write_hits 74836136 # DTB write hits -system.cpu0.dtb.write_misses 46599 # DTB write misses +system.cpu0.dtb.read_hits 98035121 # DTB read hits +system.cpu0.dtb.read_misses 261233 # DTB read misses +system.cpu0.dtb.write_hits 86222704 # DTB write hits +system.cpu0.dtb.write_misses 49679 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 31986 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 2076 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8713 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 42277 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 2349 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 10561 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10302 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 84055176 # DTB read accesses -system.cpu0.dtb.write_accesses 74882735 # DTB write accesses +system.cpu0.dtb.perms_faults 12531 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 98296354 # DTB read accesses +system.cpu0.dtb.write_accesses 86272383 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 158666512 # DTB hits -system.cpu0.dtb.misses 271399 # DTB misses -system.cpu0.dtb.accesses 158937911 # DTB accesses +system.cpu0.dtb.hits 184257825 # DTB hits +system.cpu0.dtb.misses 310912 # DTB misses +system.cpu0.dtb.accesses 184568737 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -523,185 +507,185 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 59516 # Table walker walks requested -system.cpu0.itb.walker.walksLong 59516 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 630 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 51758 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 59516 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 59516 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 59516 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 52388 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 19494.417176 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17354.171367 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 14602.329148 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 48500 92.58% 92.58% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 3085 5.89% 98.47% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 277 0.53% 99.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 436 0.83% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 18 0.03% 99.86% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 31 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 67664 # Table walker walks requested +system.cpu0.itb.walker.walksLong 67664 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 693 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59407 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 67664 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 67664 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 67664 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 60100 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 21688.993677 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 19128.313408 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 17789.670668 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 55182 91.82% 91.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 3533 5.88% 97.70% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 493 0.82% 98.52% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 740 1.23% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 21 0.03% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 25 0.04% 99.82% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 48 0.08% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 24 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 15 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 52388 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 643764704 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 643764704 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 643764704 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 51758 98.80% 98.80% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 630 1.20% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 52388 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 60100 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 59407 98.85% 98.85% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 693 1.15% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60100 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59516 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59516 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 67664 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 67664 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52388 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52388 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 111904 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 234493726 # ITB inst hits -system.cpu0.itb.inst_misses 59516 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60100 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 127764 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 272362835 # ITB inst hits +system.cpu0.itb.inst_misses 67664 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 22765 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 29878 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 197741 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 206888 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 234553242 # ITB inst accesses -system.cpu0.itb.hits 234493726 # DTB hits -system.cpu0.itb.misses 59516 # DTB misses -system.cpu0.itb.accesses 234553242 # DTB accesses -system.cpu0.numCycles 936626399 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 272430499 # ITB inst accesses +system.cpu0.itb.hits 272362835 # DTB hits +system.cpu0.itb.misses 67664 # DTB misses +system.cpu0.itb.accesses 272430499 # DTB accesses +system.cpu0.numCycles 1079786982 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 433367687 # Number of instructions committed -system.cpu0.committedOps 509515701 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 43981618 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 3754 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 93775213530 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.161274 # CPI: cycles per instruction -system.cpu0.ipc 0.462690 # IPC: instructions per cycle +system.cpu0.committedInsts 504924574 # Number of instructions committed +system.cpu0.committedOps 592395738 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 49310302 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 4906 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 93635655345 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.138511 # CPI: cycles per instruction +system.cpu0.ipc 0.467615 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 12643 # number of quiesce instructions executed -system.cpu0.tickCycles 703108983 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 233517416 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 5387052 # number of replacements -system.cpu0.dcache.tags.tagsinuse 501.034252 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 150576282 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5387564 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.948862 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 4951668000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 501.034252 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978583 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.978583 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 320066517 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 320066517 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77114778 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77114778 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 69351990 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 69351990 # number of WriteReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 251432 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 251432 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1745310 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1745310 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1668274 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1668274 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 146466768 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 146466768 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 146466768 # number of overall hits -system.cpu0.dcache.overall_hits::total 146466768 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3852692 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3852692 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 2255601 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2255601 # number of WriteReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766100 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 766100 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 104059 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 104059 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180014 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 180014 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 6108293 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 6108293 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 6108293 # number of overall misses -system.cpu0.dcache.overall_misses::total 6108293 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 54452724607 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 54452724607 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 41906959422 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 41906959422 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 27296991314 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27296991314 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 1502404735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 1502404735 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3769027814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 3769027814 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2840500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 96359684029 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 96359684029 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 96359684029 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 96359684029 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80967470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80967470 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 71607591 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 71607591 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1017532 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1017532 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1849369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1849369 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1848288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1848288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 152575061 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 152575061 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 152575061 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 152575061 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047583 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.047583 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.031499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.031499 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.752900 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.752900 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056267 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056267 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097395 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097395 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.040035 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.040035 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.040035 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.040035 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14133.682269 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14133.682269 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18579.065811 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18579.065811 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 35631.107315 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 35631.107315 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.008582 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14438.008582 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20937.414946 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 20937.414946 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13863 # number of quiesce instructions executed +system.cpu0.tickCycles 807512344 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 272274638 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 6269899 # number of replacements +system.cpu0.dcache.tags.tagsinuse 502.388707 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 174903450 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6270410 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.893463 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.388707 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.981228 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.981228 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 105 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 371740852 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 371740852 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 90280740 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 90280740 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80064017 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80064017 # number of WriteReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 281235 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 281235 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1931472 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1931472 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1872190 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1872190 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 170344757 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 170344757 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 170344757 # number of overall hits +system.cpu0.dcache.overall_hits::total 170344757 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 4509015 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 4509015 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 2541213 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2541213 # number of WriteReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 864871 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 864871 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 140737 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 140737 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 198480 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 198480 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 7050228 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7050228 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 7050228 # number of overall misses +system.cpu0.dcache.overall_misses::total 7050228 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 66986292890 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 66986292890 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 47882988891 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 47882988891 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 35264024894 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 35264024894 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2028925085 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2028925085 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4179395855 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4179395855 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2760500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 114869281781 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 114869281781 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 114869281781 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 114869281781 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 94789755 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 94789755 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82605230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82605230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1146106 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1146106 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2072209 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2072209 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2070670 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2070670 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 177394985 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 177394985 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 177394985 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 177394985 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.047569 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.047569 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030763 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030763 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.754617 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.754617 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.067916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.067916 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095853 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095853 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.039743 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.039743 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.039743 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.039743 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14856.081182 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14856.081182 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18842.571989 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18842.571989 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40773.739545 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 40773.739545 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14416.429830 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14416.429830 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21057.012571 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21057.012571 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15775.222968 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15775.222968 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15775.222968 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16292.988224 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16292.988224 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16292.988224 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -710,88 +694,88 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3733142 # number of writebacks -system.cpu0.dcache.writebacks::total 3733142 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 361487 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 361487 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 935411 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 935411 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 100 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 100 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 34 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.StoreCondReq_mshr_hits::total 67 # number of StoreCondReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1296898 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1296898 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1296898 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1296898 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3491205 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3491205 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1320190 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1320190 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 766000 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 766000 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104025 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104025 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 179947 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 179947 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4811395 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4811395 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4811395 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4811395 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 42113152704 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 42113152704 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22270249828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22270249828 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 25755951436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 25755951436 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1293404753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1293404753 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3399276642 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3399276642 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2291500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2291500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 64383402532 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 64383402532 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 64383402532 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 64383402532 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5824362996 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5824362996 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5586865743 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5586865743 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11411228739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11411228739 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043119 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018436 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.752802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.752802 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056249 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056249 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097359 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.031535 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.031535 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12062.641038 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12062.641038 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16868.973275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16868.973275 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33623.957488 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 33623.957488 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12433.595318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12433.595318 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18890.432416 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18890.432416 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 4374601 # number of writebacks +system.cpu0.dcache.writebacks::total 4374601 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 429861 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 429861 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1046667 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1046667 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 81 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 81 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 33 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 33 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::cpu0.data 55 # number of StoreCondReq MSHR hits +system.cpu0.dcache.StoreCondReq_mshr_hits::total 55 # number of StoreCondReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1476528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1476528 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1476528 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1476528 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 4079154 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 4079154 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1494546 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1494546 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 864790 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 864790 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140704 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140704 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 198425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 198425 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 5573700 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 5573700 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5573700 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5573700 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 53839740568 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 53839740568 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26185332493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26185332493 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 33958968357 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 33958968357 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1816137650 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1816137650 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3868892109 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3868892109 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2341500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 80025073061 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 80025073061 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 80025073061 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 80025073061 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5766564749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5766564749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5473208250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5473208250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11239772999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11239772999 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.043034 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.043034 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018093 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018093 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.754546 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.754546 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.067900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.067900 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095826 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.031420 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031420 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031420 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13198.751645 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13198.751645 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17520.593206 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17520.593206 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39268.456339 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39268.456339 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12907.505472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12907.505472 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19498.007353 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19498.007353 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13381.441875 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13381.441875 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14357.621160 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14357.621160 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -799,58 +783,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 9463678 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.932976 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 224826074 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 9464190 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 23.755448 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 21621868750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.932976 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999869 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 10307657 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.930132 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 261841431 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 10308169 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 25.401352 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 23262861250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930132 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 478044747 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 478044747 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 224826074 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 224826074 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 224826074 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 224826074 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 224826074 # number of overall hits -system.cpu0.icache.overall_hits::total 224826074 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 9464200 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 9464200 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 9464200 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 9464200 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 9464200 # number of overall misses -system.cpu0.icache.overall_misses::total 9464200 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93878607487 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 93878607487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 93878607487 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 93878607487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 93878607487 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 93878607487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 234290274 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 234290274 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 234290274 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 234290274 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 234290274 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 234290274 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040395 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.040395 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040395 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.040395 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040395 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.040395 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9919.338928 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9919.338928 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9919.338928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9919.338928 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9919.338928 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 554607398 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 554607398 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 261841431 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 261841431 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 261841431 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 261841431 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 261841431 # number of overall hits +system.cpu0.icache.overall_hits::total 261841431 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 10308179 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 10308179 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 10308179 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 10308179 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 10308179 # number of overall misses +system.cpu0.icache.overall_misses::total 10308179 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 103403812050 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 103403812050 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 103403812050 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 103403812050 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 103403812050 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 103403812050 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 272149610 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 272149610 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 272149610 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 272149610 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 272149610 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 272149610 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.037877 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.037877 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.037877 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.037877 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.037877 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.037877 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10031.239470 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10031.239470 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10031.239470 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10031.239470 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10031.239470 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -859,383 +842,384 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 9464200 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 9464200 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 9464200 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 9464200 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 9464200 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 9464200 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 79648587963 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 79648587963 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 79648587963 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 79648587963 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 79648587963 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 79648587963 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4713229500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4713229500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 4713229500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.040395 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.040395 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.040395 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.040395 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8415.776079 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8415.776079 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8415.776079 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 10308179 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 10308179 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 10308179 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 10308179 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 10308179 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 10308179 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 93061406416 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 93061406416 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 93061406416 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 93061406416 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 93061406416 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 93061406416 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.037877 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.037877 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.037877 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.037877 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9027.919133 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9027.919133 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9027.919133 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 11128158 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 11136239 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7035 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 12908052 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 12916183 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7100 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1270201 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2736028 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16197.540138 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 15248127 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2752162 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.540418 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5578143500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4129.920995 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 42.114006 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 24.266127 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6921.151423 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2517.491382 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2562.596205 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.252070 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002570 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001481 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.422434 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.153655 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.156408 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988619 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 2519 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 71 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13544 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 133 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 367 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1060 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 959 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 25 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1002 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 2423 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4868 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5129 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.153748 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004333 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.826660 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 319708402 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 319708402 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 463342 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 138212 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 8698965 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2911592 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 12212111 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3733141 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3733141 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 193768 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 193768 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 68627 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 68627 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33597 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 33597 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 855771 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 855771 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 463342 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 138212 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 8698965 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3767363 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 13067882 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 463342 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 138212 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 8698965 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3767363 # number of overall hits -system.cpu0.l2cache.overall_hits::total 13067882 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11843 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8238 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 765234 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 683379 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1468694 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570757 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 570757 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 126856 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 126856 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 146340 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 146340 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 10 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 10 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 270676 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 270676 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11843 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8238 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 765234 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 954055 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1739370 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11843 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8238 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 765234 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 954055 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1739370 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 383176229 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 279750987 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 22688045273 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 22235459859 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 45586432348 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 223595615 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 223595615 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2548596996 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2548596996 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 2948593769 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 2948593769 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2234000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2234000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12372799630 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 12372799630 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 383176229 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 279750987 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22688045273 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 34608259489 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 57959231978 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 383176229 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 279750987 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22688045273 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 34608259489 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 57959231978 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 475185 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 146450 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 9464199 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3594971 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 13680805 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3733141 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3733141 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 764525 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 764525 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 195483 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 195483 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 179937 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 179937 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 10 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1126447 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1126447 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 475185 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 146450 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 9464199 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 4721418 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 14807252 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 475185 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 146450 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 9464199 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 4721418 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 14807252 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056251 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.080856 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.190093 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.107354 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.746551 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.746551 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.648936 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.648936 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.813285 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.813285 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 1498641 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 3094586 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16261.036528 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 17187399 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 3110668 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 5.525308 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 6030.877634 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.708580 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.789449 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5140.303922 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 2691.250303 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 2256.106640 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.368096 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004072 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004626 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.313739 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.164261 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.137702 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.992495 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 2268 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13711 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 410 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 1208 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 648 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 19 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 19 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 35 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 978 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3981 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4660 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3950 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.138428 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.836853 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 360310183 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 360310183 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 541380 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 157488 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 9448425 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 3428429 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 13575722 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4374599 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4374599 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 237260 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 237260 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 76611 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 76611 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 40970 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 40970 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1008686 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 1008686 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 541380 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 157488 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 9448425 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 4437115 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 14584408 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 541380 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 157488 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 9448425 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 4437115 # number of overall hits +system.cpu0.l2cache.overall_hits::total 14584408 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11963 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8535 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 859753 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 791034 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1671285 # number of ReadReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 626077 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 626077 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 129747 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 129747 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 157450 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 157450 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 281357 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 281357 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11963 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8535 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 859753 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1072391 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1952642 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11963 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8535 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 859753 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1072391 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1952642 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 444201231 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 355740746 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 26443287117 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 29025017983 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 56268247077 # number of ReadReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 235084146 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 235084146 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2906366764 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2906366764 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3310532200 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3310532200 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2287498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2287498 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14147306643 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 14147306643 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 444201231 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 355740746 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 26443287117 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 43172324626 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 70415553720 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 444201231 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 355740746 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 26443287117 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 43172324626 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 70415553720 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 553343 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 166023 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 10308178 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4219463 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 15247007 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4374599 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4374599 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 863337 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 863337 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 206358 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 206358 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 198420 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 198420 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1290043 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1290043 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 553343 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 166023 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 10308178 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5509506 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 16537050 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 553343 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 166023 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 10308178 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5509506 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 16537050 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021620 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.051409 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.083405 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.187473 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.109614 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.725183 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.725183 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.628747 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.628747 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.793519 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.793519 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.240292 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.240292 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056251 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.080856 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.202070 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.117467 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.024923 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056251 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.080856 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.202070 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.117467 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33958.604880 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29648.506565 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 32537.522896 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 31038.754395 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 391.752734 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 391.752734 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20090.472630 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20090.472630 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20148.925577 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20148.925577 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 223400 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 223400 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45710.737672 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45710.737672 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33958.604880 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29648.506565 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 36274.910240 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 33321.968286 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32354.659208 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33958.604880 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29648.506565 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 36274.910240 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 33321.968286 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 82 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.218099 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.218099 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021620 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.051409 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.083405 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.194644 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.118077 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021620 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.051409 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.083405 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.194644 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.118077 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37131.257293 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41680.228002 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30756.841927 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 36692.503714 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33667.655174 # average ReadReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 375.487593 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 375.487593 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22400.261771 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22400.261771 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 21025.926961 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 21025.926961 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 457499.600000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 457499.600000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50282.405069 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50282.405069 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37131.257293 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41680.228002 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30756.841927 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 40258.007225 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 36061.681414 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37131.257293 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41680.228002 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30756.841927 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 40258.007225 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 36061.681414 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 82 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1399370 # number of writebacks -system.cpu0.l2cache.writebacks::total 1399370 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3395 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 3404 # number of ReadReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 156 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 156 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 9658 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 9658 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 13053 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 13062 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 13053 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 13062 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11843 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8237 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 765226 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 679984 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1465290 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 1036981 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 570601 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570601 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 126856 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 126856 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 146340 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 146340 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 10 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 10 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 261018 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 261018 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11843 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8237 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 765226 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 941002 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1726308 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11843 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8237 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 765226 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 941002 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 1036981 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2763289 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 221721501 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 17303340727 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 17052440522 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 34877337999 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 47311809533 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 20034543782 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 20034543782 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2151275072 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2151275072 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 1993779824 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 1993779824 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1835000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1835000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9532664011 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9532664011 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 221721501 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 17303340727 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 26585104533 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 44410002010 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 299835249 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 221721501 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 17303340727 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 26585104533 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 47311809533 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 91721811543 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4113621500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5558383242 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9672004742 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5338553005 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5338553005 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4113621500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10896936247 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15010557747 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.189149 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.107106 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.writebacks::writebacks 1572908 # number of writebacks +system.cpu0.l2cache.writebacks::total 1572908 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 4 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 11 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 3791 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 3806 # number of ReadReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 19 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 19 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 10276 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 10276 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 11 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 14067 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 14082 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 4 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 11 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 14067 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 14082 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 11963 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8531 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 859742 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 787243 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 1667479 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 1152806 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 1152806 # number of HardPFReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 626058 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 626058 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 129747 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 129747 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 157450 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 157450 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 271081 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 271081 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 11963 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8531 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 859742 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1058324 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1938560 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 11963 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8531 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 859742 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1058324 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 1152806 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 3091366 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 365781267 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 299632762 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 20823449883 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 23430974203 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 44919838115 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 51873044967 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 51873044967 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 27342939109 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 27342939109 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2649227223 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2649227223 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2380002247 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2380002247 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1949498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1949498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11193177649 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11193177649 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 365781267 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 299632762 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 20823449883 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34624151852 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 56113015764 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 365781267 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 299632762 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 20823449883 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34624151852 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 51873044967 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 107986060731 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5508458001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 9899528751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5233419500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5233419500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10741877501 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15132948251 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.186574 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.109364 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.746347 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.746347 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.648936 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.648936 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813285 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.813285 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.725161 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.725161 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.628747 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.628747 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.793519 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.793519 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231718 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231718 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.116585 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.024923 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056244 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.080855 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.199305 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.210133 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.210133 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.117225 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021620 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.051384 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.083404 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192091 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186617 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 25077.708478 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23802.344928 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 45624.567406 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 35111.301561 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 35111.301561 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16958.402220 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16958.402220 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13624.298374 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13624.298374 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 183500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36521.098204 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36521.098204 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25725.422121 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25317.508148 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26917.749302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22612.065882 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28251.910764 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 45624.567406 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33192.985440 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.186936 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29763.331275 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26938.772911 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 44997.202450 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43674.769924 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43674.769924 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20418.408310 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20418.408310 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15115.924084 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15115.924084 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 389899.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 389899.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41290.896998 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41290.896998 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28945.720413 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30576.048399 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 35122.818192 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24220.579991 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 32716.022553 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 44997.202450 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34931.503009 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1245,69 +1229,66 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 16482247 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 13994677 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 33105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 33105 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3733141 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1450559 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1135277 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 764525 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 439100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 331866 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 445825 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 56 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1265717 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1135924 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 19032980 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15771109 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 324159 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1044893 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 36173141 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 609055296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 597396947 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1171600 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3801480 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1211425323 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 5254625 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 24752436 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.199831 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.399873 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 17791242 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 15586246 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31969 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 31969 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4374599 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 1496771 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1185210 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 863337 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 459789 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 354172 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 478714 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 67 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1428335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1300035 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20720970 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18253192 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 368054 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1214499 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 40556715 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 663070976 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 695774006 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1328184 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4426744 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1364599910 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 5020747 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 27005623 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.173372 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.378569 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 19806132 80.02% 80.02% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 4946304 19.98% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 22323591 82.66% 82.66% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 4682032 17.34% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 24752436 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14477877088 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 27005623 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 16474086937 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 203336996 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 218344490 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 14303799012 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 15570026567 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 7760036291 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 9017811583 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 177959354 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 202360718 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 570171512 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 661550198 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 141025153 # Number of BP lookups -system.cpu1.branchPred.condPredicted 100933183 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6236213 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 106937612 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 78176713 # Number of BTB hits +system.cpu1.branchPred.lookups 120391711 # Number of BP lookups +system.cpu1.branchPred.condPredicted 86208358 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5520869 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 91435615 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 66348303 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.104974 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16283768 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 1021605 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.562866 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 13861535 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 936317 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1337,61 +1318,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 298651 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 298651 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11560 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94332 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 298651 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 298651 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 298651 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 105892 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 17805.770634 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15803.828904 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 14966.928967 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 104531 98.71% 98.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1148 1.08% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 61 0.06% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 60 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 63 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 16 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 5 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 105892 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1172907556 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1172907556 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1172907556 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 94332 89.08% 89.08% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11560 10.92% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 105892 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298651 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 259478 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 259478 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8847 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 78200 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 259478 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 259478 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 259478 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 87047 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 19103.472745 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17330.859199 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 14131.069495 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 82878 95.21% 95.21% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 3197 3.67% 98.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 459 0.53% 99.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 357 0.41% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 35 0.04% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 16 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 26 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 28 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 18 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 87047 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 492358444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 492358444 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 492358444 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 78200 89.84% 89.84% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 8847 10.16% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 87047 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259478 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298651 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105892 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259478 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 87047 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105892 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 404543 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 87047 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 346525 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 90905034 # DTB read hits -system.cpu1.dtb.read_misses 248418 # DTB read misses -system.cpu1.dtb.write_hits 78767149 # DTB write hits -system.cpu1.dtb.write_misses 50233 # DTB write misses +system.cpu1.dtb.read_hits 76628852 # DTB read hits +system.cpu1.dtb.read_misses 212787 # DTB read misses +system.cpu1.dtb.write_hits 67332330 # DTB write hits +system.cpu1.dtb.write_misses 46691 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 43819 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 923 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 8321 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 32755 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 660 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 6687 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 12272 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91153452 # DTB read accesses -system.cpu1.dtb.write_accesses 78817382 # DTB write accesses +system.cpu1.dtb.perms_faults 10091 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 76841639 # DTB read accesses +system.cpu1.dtb.write_accesses 67379021 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 169672183 # DTB hits -system.cpu1.dtb.misses 298651 # DTB misses -system.cpu1.dtb.accesses 169970834 # DTB accesses +system.cpu1.dtb.hits 143961182 # DTB hits +system.cpu1.dtb.misses 259478 # DTB misses +system.cpu1.dtb.accesses 144220660 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1421,179 +1408,178 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 67610 # Table walker walks requested -system.cpu1.itb.walker.walksLong 67610 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 497 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58418 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 67610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 67610 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 67610 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 58915 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 20253.386778 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 17562.612185 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17511.554701 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 57403 97.43% 97.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1356 2.30% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 66 0.11% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 56 0.10% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 19 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 59975 # Table walker walks requested +system.cpu1.itb.walker.walksLong 59975 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 467 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50555 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 59975 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 59975 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 59975 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 51022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21947.479421 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19426.626910 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17730.380785 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 49865 97.73% 97.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1035 2.03% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 47 0.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 47 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 12 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 58915 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1173450056 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1173450056 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1173450056 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 58418 99.16% 99.16% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 497 0.84% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 58915 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 51022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 491673944 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 491673944 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 491673944 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 50555 99.08% 99.08% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 467 0.92% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 51022 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67610 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67610 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 59975 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 59975 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 58915 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 58915 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 126525 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 252933263 # ITB inst hits -system.cpu1.itb.inst_misses 67610 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51022 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 110997 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 214508261 # ITB inst hits +system.cpu1.itb.inst_misses 59975 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 42371 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31594 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 42243 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1048 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 23598 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 222493 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 213038 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 253000873 # ITB inst accesses -system.cpu1.itb.hits 252933263 # DTB hits -system.cpu1.itb.misses 67610 # DTB misses -system.cpu1.itb.accesses 253000873 # DTB accesses -system.cpu1.numCycles 943783669 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 214568236 # ITB inst accesses +system.cpu1.itb.hits 214508261 # DTB hits +system.cpu1.itb.misses 59975 # DTB misses +system.cpu1.itb.accesses 214568236 # DTB accesses +system.cpu1.numCycles 819770260 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 461717275 # Number of instructions committed -system.cpu1.committedOps 543187389 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 49256164 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 5826 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 93768369123 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.044073 # CPI: cycles per instruction -system.cpu1.ipc 0.489219 # IPC: instructions per cycle +system.cpu1.committedInsts 389540668 # Number of instructions committed +system.cpu1.committedOps 459661719 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 43651844 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 5040 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 93895466763 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.104454 # CPI: cycles per instruction +system.cpu1.ipc 0.475183 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5890 # number of quiesce instructions executed -system.cpu1.tickCycles 748189458 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 195594211 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 5624476 # number of replacements -system.cpu1.dcache.tags.tagsinuse 426.107402 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 161270449 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5624987 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 28.670368 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8377201144000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 426.107402 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.832241 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.832241 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 342291215 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 342291215 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 83489779 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 83489779 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 73474609 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 73474609 # number of WriteReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 71990 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 71990 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1908367 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1908367 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1854336 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1854336 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 156964388 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 156964388 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 156964388 # number of overall hits -system.cpu1.dcache.overall_hits::total 156964388 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 4311289 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 4311289 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 2366929 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 2366929 # number of WriteReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 476593 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 476593 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 141331 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 141331 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193852 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 193852 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 6678218 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 6678218 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 6678218 # number of overall misses -system.cpu1.dcache.overall_misses::total 6678218 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 60722587231 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 60722587231 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 38093191666 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 38093191666 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11613108236 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11613108236 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1977833980 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 1977833980 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3982712056 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 3982712056 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2357000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2357000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 98815778897 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 98815778897 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 98815778897 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 98815778897 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 87801068 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 87801068 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 75841538 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 75841538 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 548583 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 548583 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2049698 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2049698 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2048188 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2048188 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 163642606 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 163642606 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 163642606 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 163642606 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049103 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049103 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.031209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.031209 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.868771 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.868771 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.068952 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.068952 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.094646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.094646 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040810 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040810 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040810 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.040810 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14084.555044 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14084.555044 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16093.930856 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16093.930856 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 24366.929930 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 24366.929930 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13994.339388 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 13994.339388 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 20545.117182 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 20545.117182 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5089 # number of quiesce instructions executed +system.cpu1.tickCycles 643812229 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 175958031 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 4705434 # number of replacements +system.cpu1.dcache.tags.tagsinuse 416.508572 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 136862260 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4705946 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 29.082837 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8379321114000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 416.508572 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.813493 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.813493 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 85 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 410 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 290353323 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 290353323 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 70292866 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 70292866 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 62721831 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 62721831 # number of WriteReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 37138 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 37138 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1710890 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1710890 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1626994 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1626994 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 133014697 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 133014697 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 133014697 # number of overall hits +system.cpu1.dcache.overall_hits::total 133014697 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3624776 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3624776 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 2086736 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 2086736 # number of WriteReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 382666 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 382666 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 105529 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 105529 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 188259 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 188259 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 5711512 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 5711512 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5711512 # number of overall misses +system.cpu1.dcache.overall_misses::total 5711512 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 50593739173 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 50593739173 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 36769582633 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 36769582633 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 10366896775 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 10366896775 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 1534806603 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 1534806603 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3974138991 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3974138991 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3324999 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3324999 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 87363321806 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 87363321806 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 87363321806 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 87363321806 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 73917642 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 73917642 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 64808567 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 64808567 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 419804 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 419804 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1816419 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1816419 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1815253 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1815253 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 138726209 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 138726209 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 138726209 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 138726209 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049038 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049038 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032198 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.032198 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.911535 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.911535 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.058097 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.058097 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103710 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103710 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041171 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.041171 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.041171 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.041171 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13957.756058 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13957.756058 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17620.620257 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17620.620257 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27091.240860 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27091.240860 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14543.932028 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14543.932028 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21109.954855 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21109.954855 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14796.728543 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14796.728543 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14796.728543 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15296.005997 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15296.005997 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15296.005997 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1602,88 +1588,88 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3711348 # number of writebacks -system.cpu1.dcache.writebacks::total 3711348 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 397792 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 397792 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 970938 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 970938 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 60 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 60 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 47 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 47 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.StoreCondReq_mshr_hits::total 68 # number of StoreCondReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1368730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1368730 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1368730 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1368730 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3913497 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 3913497 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1395991 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1395991 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 476533 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 476533 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 141284 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 141284 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193784 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 193784 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 5309488 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 5309488 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 5309488 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 5309488 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 46779736993 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 46779736993 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20386885918 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20386885918 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10653380764 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10653380764 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1693632498 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1693632498 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3584420895 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3584420895 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1830000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1830000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 67166622911 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 67166622911 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 67166622911 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 67166622911 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 548139751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 548139751 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 613571252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 613571252 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1161711003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1161711003 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044572 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018407 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018407 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.868662 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.868662 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.068929 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.068929 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.094612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.094612 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032446 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032446 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032446 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11953.436273 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11953.436273 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14603.880625 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14603.880625 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22356.018920 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22356.018920 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11987.433099 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11987.433099 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 18496.990954 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 18496.990954 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3043303 # number of writebacks +system.cpu1.dcache.writebacks::total 3043303 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 326021 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 326021 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 860988 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 860988 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 76 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 76 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 32 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 32 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::cpu1.data 53 # number of StoreCondReq MSHR hits +system.cpu1.dcache.StoreCondReq_mshr_hits::total 53 # number of StoreCondReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1187009 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1187009 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1187009 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1187009 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3298755 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 3298755 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1225748 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1225748 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 382590 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 382590 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 105497 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 105497 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 188206 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 188206 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4524503 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4524503 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4524503 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4524503 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 40628902084 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 40628902084 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20156955784 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20156955784 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9784547475 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 9784547475 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1375359879 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1375359879 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3682414982 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3682414982 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2828501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2828501 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60785857868 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 60785857868 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60785857868 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 60785857868 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 684362251 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 684362251 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 814922500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 814922500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1499284751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1499284751 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.044627 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.044627 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018913 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018913 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.911354 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.911354 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058080 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.058080 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103680 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103680 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032615 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032615 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032615 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12316.435165 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12316.435165 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16444.616499 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16444.616499 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25574.498745 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25574.498745 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13036.957250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13036.957250 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19565.874531 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19565.874531 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12650.301293 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12650.301293 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13434.814358 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13434.814358 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1691,58 +1677,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 9215030 # number of replacements -system.cpu1.icache.tags.tagsinuse 507.228865 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 243489253 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 9215542 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 26.421588 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8367568177500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.228865 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990681 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.990681 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 8513181 # number of replacements +system.cpu1.icache.tags.tagsinuse 507.039853 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 205775695 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 8513693 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 24.169969 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8369241421000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 507.039853 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.990312 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.990312 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 514625132 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 514625132 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 243489253 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 243489253 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 243489253 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 243489253 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 243489253 # number of overall hits -system.cpu1.icache.overall_hits::total 243489253 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 9215542 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 9215542 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 9215542 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 9215542 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 9215542 # number of overall misses -system.cpu1.icache.overall_misses::total 9215542 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 91468274167 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 91468274167 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 91468274167 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 91468274167 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 91468274167 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 91468274167 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 252704795 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 252704795 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 252704795 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 252704795 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 252704795 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 252704795 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.036468 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.036468 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.036468 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.036468 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.036468 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.036468 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9925.436200 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9925.436200 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9925.436200 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9925.436200 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9925.436200 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 437092471 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 437092471 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 205775695 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 205775695 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 205775695 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 205775695 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 205775695 # number of overall hits +system.cpu1.icache.overall_hits::total 205775695 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 8513694 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 8513694 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 8513694 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 8513694 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 8513694 # number of overall misses +system.cpu1.icache.overall_misses::total 8513694 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 84159322077 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 84159322077 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 84159322077 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 84159322077 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 84159322077 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 84159322077 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 214289389 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 214289389 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 214289389 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 214289389 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 214289389 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 214289389 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.039730 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.039730 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.039730 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.039730 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.039730 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.039730 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9885.171123 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9885.171123 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9885.171123 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9885.171123 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9885.171123 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1751,242 +1737,241 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 9215542 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 9215542 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 9215542 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 9215542 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 9215542 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 9215542 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 77617743273 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 77617743273 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 77617743273 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 77617743273 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 77617743273 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 77617743273 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8388750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8388750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8388750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8388750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.036468 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.036468 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036468 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.036468 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8422.482722 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8422.482722 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8422.482722 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 8513694 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 8513694 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 8513694 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 8513694 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 8513694 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 8513694 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 75624287377 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 75624287377 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 75624287377 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 75624287377 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 75624287377 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 75624287377 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8552000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8552000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8552000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8552000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.039730 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.039730 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.039730 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.039730 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8882.664491 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8882.664491 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8882.664491 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 11995647 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 12001276 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 4903 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 10121407 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 10125724 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 3757 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 1360052 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2569302 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13533.660217 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 15700970 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2584965 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.073958 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9611078525000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5526.220513 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 77.627317 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 76.256480 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3620.154380 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2817.959604 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1415.441924 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.337294 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004738 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004654 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.220957 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.171995 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086392 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.826029 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2491 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13080 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 600 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1302 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 576 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 72 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4875 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2499 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.152039 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.798340 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 321109712 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 321109712 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 544517 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 158528 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 8400098 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 3278512 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 12381655 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3711345 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3711345 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 202419 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 202419 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 77280 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 77280 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 41809 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 41809 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 939119 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 939119 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 544517 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 158528 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 8400098 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 4217631 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 13320774 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 544517 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 158528 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 8400098 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 4217631 # number of overall hits -system.cpu1.l2cache.overall_hits::total 13320774 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12561 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8870 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 815444 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 775983 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1612858 # number of ReadReq misses +system.cpu1.l2cache.prefetcher.pfSpanPage 1112844 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2221085 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13329.151476 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 13836589 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2237248 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.184647 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10494820402000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5280.158493 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 74.775550 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 82.006725 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3962.886937 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2390.470426 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1538.853345 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.322275 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004564 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005005 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.241875 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.145903 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.093924 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.813547 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2457 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13645 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 113 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 719 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 972 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 645 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 937 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 4967 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4448 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3191 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.149963 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.832825 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 282497183 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 282497183 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 472812 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141552 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 7799132 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2711848 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 11125344 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3043302 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3043302 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 157363 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 157363 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71855 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 71855 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 32392 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 32392 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 766594 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 766594 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 472812 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141552 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 7799132 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3478442 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 11891938 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 472812 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141552 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 7799132 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3478442 # number of overall hits +system.cpu1.l2cache.overall_hits::total 11891938 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12653 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 8998 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 714562 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 692201 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1428414 # number of ReadReq misses system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 272843 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 272843 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 137034 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 137034 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 151974 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 151974 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 244121 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 244121 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12561 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8870 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 815444 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1020104 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1856979 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12561 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8870 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 815444 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1020104 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1856979 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 455863233 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358991737 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 22574174788 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 24632424000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 48021453758 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 213581444 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 213581444 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2792930491 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2792930491 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3071034580 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3071034580 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1783500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1783500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9626384839 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 9626384839 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 455863233 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358991737 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 22574174788 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 34258808839 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 57647838597 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 455863233 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358991737 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 22574174788 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 34258808839 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 57647838597 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 557078 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 167398 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 9215542 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4054495 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 13994513 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3711346 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3711346 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 475262 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 475262 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 214314 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 214314 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 193783 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 193783 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1183240 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1183240 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 557078 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 167398 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 9215542 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5237735 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 15177753 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 557078 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 167398 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 9215542 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5237735 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 15177753 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052987 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.088486 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.191388 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.115249 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 224018 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 224018 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 142871 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 142871 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 155808 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 155808 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 245850 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 245850 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12653 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 8998 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 714562 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 938051 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1674264 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12653 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 8998 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 714562 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 938051 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1674264 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 449558190 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 345348999 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 20635717509 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 20877681975 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 42308306673 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 229084267 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 229084267 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3047787464 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 3047787464 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3209370896 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3209370896 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2764497 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2764497 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9785037151 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 9785037151 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 449558190 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 345348999 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20635717509 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 30662719126 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 52093343824 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 449558190 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 345348999 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20635717509 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 30662719126 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 52093343824 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 485465 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150550 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 8513694 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3404049 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 12553758 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3043303 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3043303 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 381381 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 381381 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 214726 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 214726 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 188200 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 188200 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1012444 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1012444 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 485465 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150550 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 8513694 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4416493 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 13566202 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 485465 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150550 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 8513694 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4416493 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 13566202 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026064 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.059768 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.083931 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.203346 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.113784 # miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.574090 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.574090 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.639408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.639408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.784248 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.784248 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.587386 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.587386 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.665364 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.665364 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.827885 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.827885 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.206316 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.206316 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052987 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.088486 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.194761 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.122349 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022548 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052987 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.088486 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.194761 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.122349 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40472.574634 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 27683.292523 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 31743.509845 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29774.136197 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 782.799793 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 782.799793 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20381.295817 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20381.295817 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20207.631437 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20207.631437 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 1783500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 1783500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39432.842070 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39432.842070 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27683.292523 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 33583.643275 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 31043.882886 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 36291.953905 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40472.574634 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27683.292523 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 33583.643275 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 31043.882886 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.242828 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.242828 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.026064 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.059768 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.083931 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.212397 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.123414 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.026064 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.059768 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.083931 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.212397 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.123414 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 35529.770805 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38380.640031 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28878.834180 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 30161.299933 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29619.078694 # average ReadReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 1022.615446 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 1022.615446 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21332.443001 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21332.443001 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20598.242041 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20598.242041 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 460749.500000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 460749.500000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 39800.842591 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 39800.842591 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 35529.770805 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38380.640031 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28878.834180 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32687.688757 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31114.175437 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 35529.770805 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38380.640031 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28878.834180 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32687.688757 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31114.175437 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1995,148 +1980,148 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1092301 # number of writebacks -system.cpu1.l2cache.writebacks::total 1092301 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 1804 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 1806 # number of ReadReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 45 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 45 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7072 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 7072 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 8876 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 8878 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 8876 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 8878 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12561 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8869 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 815443 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 774179 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1611052 # number of ReadReq MSHR misses +system.cpu1.l2cache.writebacks::writebacks 931967 # number of writebacks +system.cpu1.l2cache.writebacks::total 931967 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 3 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 1680 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 1690 # number of ReadReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 17 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 17 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5999 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 5999 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 3 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7679 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 7689 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 3 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7679 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 7689 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12653 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8995 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 714555 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 690521 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1426724 # number of ReadReq MSHR misses system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 1032302 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 272798 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 272798 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 137034 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 137034 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 151974 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 151974 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 237049 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 237049 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12561 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8869 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 815443 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1011228 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1848101 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12561 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8869 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 815443 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1011228 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 1032302 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2880403 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 296231251 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 16845762712 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 19051693106 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 36560910324 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 41289088164 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7103244766 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7103244766 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2312644672 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2312644672 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2076231085 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2076231085 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1461500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1461500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7288633813 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7288633813 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 296231251 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 16845762712 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 26340326919 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 43849544137 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 367223255 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 296231251 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 16845762712 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 26340326919 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 41289088164 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 85138632301 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7364250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 506877748 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 514241998 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 574249999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 574249999 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7364250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1081127747 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1088491997 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.190943 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.115120 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 936864 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 936864 # number of HardPFReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 224001 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 224001 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 142871 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 142871 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 155808 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 155808 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 239851 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 239851 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12653 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8995 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 714555 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 930372 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1666575 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12653 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8995 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 714555 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 930372 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 936864 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2603439 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 366720790 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 286315515 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 15972439241 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 16244239643 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 32869715189 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 33861408353 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 33861408353 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 6819895822 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 6819895822 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2772663634 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2772663634 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2270029922 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2270029922 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2361497 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2361497 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7617845684 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7617845684 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 366720790 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 286315515 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 15972439241 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 23862085327 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 40487560873 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 366720790 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 286315515 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 15972439241 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 23862085327 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 33861408353 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 74348969226 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7789000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 632822249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 640611249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 765196000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 765196000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7789000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1398018249 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1405807249 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.202853 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.113649 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.573995 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.573995 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.639408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.639408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.784248 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.784248 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.587342 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.587342 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.665364 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.665364 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827885 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.827885 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.200339 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.200339 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.121764 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022548 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052982 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.088486 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.193066 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.236903 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.236903 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.122848 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026064 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.059748 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.083930 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.210659 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.189778 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24608.899371 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22693.811450 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39997.101782 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 26038.478163 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 26038.478163 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16876.429733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16876.429733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13661.751912 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13661.751912 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1461500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1461500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30747.372117 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30747.372117 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23726.811542 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 29235.192660 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 33400.749915 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20658.418445 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 26047.861530 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39997.101782 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29557.889053 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191906 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 23524.613506 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23038.594142 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36143.355229 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30445.827572 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30445.827572 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19406.762982 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.762982 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14569.405435 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14569.405435 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 393582.833333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 393582.833333 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31760.741811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31760.741811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24293.872687 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 28982.912353 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31830.518621 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22352.987861 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25647.897107 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36143.355229 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28557.983969 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2146,66 +2131,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 16597851 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 14230777 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 5242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5242 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3711346 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1418597 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1143341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 475262 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 452039 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 340076 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 470072 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadReq 15445485 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 12769085 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6630 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6630 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3043303 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 1203167 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105360 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 381381 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 459466 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 345603 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 466676 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 58 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1342662 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1189275 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18431264 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16132557 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 369420 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1220438 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 36153679 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 589800448 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 609347251 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1339184 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4456624 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 1204943507 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5386490 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 25000724 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.203488 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.402593 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1177489 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1018273 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17027569 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13630896 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 329758 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1060916 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 32049139 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 544882176 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 508019480 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1204400 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3883720 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 1057989776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 5539420 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 22773399 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.231012 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.421480 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 19913365 79.65% 79.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 5087359 20.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 17512462 76.90% 76.90% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 5260937 23.10% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 25000724 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 14152090513 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 22773399 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 12190933688 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 175296997 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 175938985 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 13837074197 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 12781364350 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 8360530852 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7076644304 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 202402154 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 179556153 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 663973984 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 575808723 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40424 # Transaction distribution -system.iobus.trans_dist::ReadResp 40424 # Transaction distribution -system.iobus.trans_dist::WriteReq 136766 # Transaction distribution -system.iobus.trans_dist::WriteResp 30038 # Transaction distribution +system.iobus.trans_dist::ReadReq 40350 # Transaction distribution +system.iobus.trans_dist::ReadResp 40350 # Transaction distribution +system.iobus.trans_dist::WriteReq 136657 # Transaction distribution +system.iobus.trans_dist::WriteResp 29929 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48186 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47838 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2220,13 +2202,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123068 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231232 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231232 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122720 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231214 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48206 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47858 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2241,13 +2223,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156198 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338944 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338944 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338872 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497228 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36614000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36331000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2275,71 +2257,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1043031468 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607629108 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93033000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92794000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179210230 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148521376 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115597 # number of replacements -system.iocache.tags.tagsinuse 11.297216 # Cycle average of tags in use +system.iocache.tags.replacements 115588 # number of replacements +system.iocache.tags.tagsinuse 11.296723 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115613 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115604 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9126956441000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.841188 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.456028 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240074 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.466002 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706076 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9128912382000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.841062 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.455661 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240066 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465979 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.706045 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040901 # Number of tag accesses -system.iocache.tags.data_accesses 1040901 # Number of data accesses +system.iocache.tags.tag_accesses 1040820 # Number of tag accesses +system.iocache.tags.data_accesses 1040820 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8888 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8925 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8879 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8916 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8888 # number of demand (read+write) misses -system.iocache.demand_misses::total 8928 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8879 # number of demand (read+write) misses +system.iocache.demand_misses::total 8919 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8888 # number of overall misses -system.iocache.overall_misses::total 8928 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5659000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1934548608 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1940207608 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28977416630 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28977416630 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6016000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1934548608 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1940564608 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6016000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1934548608 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1940564608 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8879 # number of overall misses +system.iocache.overall_misses::total 8919 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1619625499 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1624820999 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871885233 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19871885233 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1619625499 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1625189999 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1619625499 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1625189999 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8888 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8925 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8879 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8916 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8888 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8928 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8919 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8888 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8928 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8919 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2353,55 +2335,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 152945.945946 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217658.484248 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217390.208179 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271507.164287 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271507.164287 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 150400 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217357.146953 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 150400 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217658.484248 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217357.146953 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228934 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182410.800653 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182236.540938 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186191.863738 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186191.863738 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182216.616100 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182410.800653 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182216.616100 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110413 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27737 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16202 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.253740 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.814776 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8888 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8925 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8879 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8916 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8888 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8928 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8879 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8919 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8888 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8928 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3735000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1472256614 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1475991614 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427107084 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427107084 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3936000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1472256614 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1476192614 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3936000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1472256614 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1476192614 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8879 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8919 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1156744203 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1160014703 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14321981281 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14321981281 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1156744203 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1160227703 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1156744203 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1160227703 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2415,558 +2397,564 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100945.945946 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165645.433618 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165377.211653 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219502.914737 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219502.914737 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 98400 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165645.433618 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165344.154794 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130278.657844 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130104.834343 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134191.414446 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134191.414446 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130278.657844 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 130084.953806 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1473453 # number of replacements -system.l2c.tags.tagsinuse 64480.086956 # Cycle average of tags in use -system.l2c.tags.total_refs 5089807 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1533812 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.318403 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8003493500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 16627.933383 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.809416 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 10.076521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4159.600580 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3523.314031 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 5733.726218 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 373.789781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 460.262003 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3670.846899 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10690.974499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 19215.753624 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.253722 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.063470 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.053762 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.087490 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005704 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.007023 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.163131 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.293209 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983888 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 14505 # Occupied blocks per task id +system.l2c.tags.replacements 1509391 # number of replacements +system.l2c.tags.tagsinuse 64395.788312 # Cycle average of tags in use +system.l2c.tags.total_refs 5071928 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1569787 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.230966 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8741120000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 18420.928371 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 254.564671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 327.558520 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5783.699822 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9967.407270 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 17191.318601 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 126.325801 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 133.881896 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2759.726372 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3037.353013 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6393.023977 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.281081 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003884 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004998 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.088252 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.152091 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.262319 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001928 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.002043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.046346 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097550 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.982602 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 14050 # Occupied blocks per task id system.l2c.tags.occ_task_id_blocks::1023 200 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 45654 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 147 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 696 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 13662 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 200 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1737 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4894 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 38831 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.221329 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_blocks::1024 46146 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 182 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 1105 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 12755 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::0 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4647 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 39226 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.214386 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.696625 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 65568567 # Number of tag accesses -system.l2c.tags.data_accesses 65568567 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6731 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4742 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 690690 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 361152 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 521850 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6817 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4499 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 759258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 428313 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 530462 # number of ReadReq hits -system.l2c.ReadReq_hits::total 3314514 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2491671 # number of Writeback hits -system.l2c.Writeback_hits::total 2491671 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 125819 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 140505 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 266324 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 29765 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 32403 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 62168 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 5875 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6386 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12261 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 56397 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53337 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 109734 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6731 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4742 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 690690 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 417549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 521850 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4499 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 759258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 481650 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 530462 # number of demand (read+write) hits -system.l2c.demand_hits::total 3424248 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6731 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4742 # number of overall hits -system.l2c.overall_hits::cpu0.inst 690690 # number of overall hits -system.l2c.overall_hits::cpu0.data 417549 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 521850 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6817 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4499 # number of overall hits -system.l2c.overall_hits::cpu1.inst 759258 # number of overall hits -system.l2c.overall_hits::cpu1.data 481650 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 530462 # number of overall hits -system.l2c.overall_hits::total 3424248 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1664 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1301 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 74535 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 94558 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2478 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2309 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 56185 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 106038 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq misses -system.l2c.ReadReq_misses::total 870286 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 435530 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 123517 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 559047 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 44959 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 45474 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 90433 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 8261 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 9038 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 17299 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76639 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 55158 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 131797 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1664 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1301 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 74535 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 171197 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2478 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2309 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 56185 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 161196 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) misses -system.l2c.demand_misses::total 1002083 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1664 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1301 # number of overall misses -system.l2c.overall_misses::cpu0.inst 74535 # number of overall misses -system.l2c.overall_misses::cpu0.data 171197 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 274703 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2478 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2309 # number of overall misses -system.l2c.overall_misses::cpu1.inst 56185 # number of overall misses -system.l2c.overall_misses::cpu1.data 161196 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 256515 # number of overall misses -system.l2c.overall_misses::total 1002083 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 138961746 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 111055248 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 5745942443 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 7810089637 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 202393999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 185177500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4301130982 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 8460963468 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 95981532857 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 36612963 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 35758482 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 72371445 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 213542030 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 216684315 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 430226345 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 36699987 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 41305269 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 78005256 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6278532917 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4207751582 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 10486284499 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 138961746 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 111055248 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 5745942443 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 14088622554 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 202393999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 185177500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4301130982 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 12668715050 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 106467817356 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 138961746 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 111055248 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 5745942443 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 14088622554 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 37505012849 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 202393999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 185177500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4301130982 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 12668715050 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 31520804985 # number of overall miss cycles -system.l2c.overall_miss_latency::total 106467817356 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8395 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6043 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 765225 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 455710 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 796553 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9295 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6808 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 815443 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 534351 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 786977 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 4184800 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2491671 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2491671 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 561349 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 264022 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 825371 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 74724 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 77877 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 152601 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 14136 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 15424 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 29560 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 133036 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 108495 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 241531 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8395 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6043 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 765225 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 588746 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 796553 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9295 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6808 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 815443 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 642846 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 786977 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4426331 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8395 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6043 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 765225 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 588746 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 796553 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9295 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6808 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 815443 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 642846 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 786977 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4426331 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.215290 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.097403 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.207496 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.339160 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.068901 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.198443 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.207964 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.775863 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.467828 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.677328 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.601667 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.583921 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.592611 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.584394 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.585970 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.585217 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.576077 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.508392 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.545673 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.215290 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.097403 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290782 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.339160 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.068901 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.250754 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.226391 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.198213 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.215290 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.097403 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290782 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.344865 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.266595 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.339160 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.068901 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.250754 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.325950 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.226391 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 85361.451191 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77090.527175 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 82595.757493 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80198.137722 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76553.012049 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 79791.805466 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 110287.345605 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 84.065307 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 289.502514 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 129.455028 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4749.705954 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4765.015503 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4757.404321 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4442.559860 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4570.178026 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4509.234985 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 81923.471301 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76285.426992 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 79563.908883 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 85361.451191 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 77090.527175 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 82294.798121 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 80198.137722 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76553.012049 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 78591.993908 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 106246.505884 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 83510.664663 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 85361.451191 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 77090.527175 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 82294.798121 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136529.316567 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81676.351493 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80198.137722 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76553.012049 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 78591.993908 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 122880.942576 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 106246.505884 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 5735 # number of cycles access was blocked +system.l2c.tags.occ_task_id_percent::1024 0.704132 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 65830537 # Number of tag accesses +system.l2c.tags.data_accesses 65830537 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 7044 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4822 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 775995 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 424099 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 575063 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6552 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4575 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 662903 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 363815 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 472407 # number of ReadReq hits +system.l2c.ReadReq_hits::total 3297275 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2504876 # number of Writeback hits +system.l2c.Writeback_hits::total 2504876 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 140601 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 125515 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 266116 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 34998 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 27403 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 62401 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 7236 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5610 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 12846 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 55428 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 53807 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 109235 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 7044 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4822 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 775995 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 479527 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 575063 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6552 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4575 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 662903 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 417622 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 472407 # number of demand (read+write) hits +system.l2c.demand_hits::total 3406510 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 7044 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4822 # number of overall hits +system.l2c.overall_hits::cpu0.inst 775995 # number of overall hits +system.l2c.overall_hits::cpu0.data 479527 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 575063 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6552 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4575 # number of overall hits +system.l2c.overall_hits::cpu1.inst 662903 # number of overall hits +system.l2c.overall_hits::cpu1.data 417622 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 472407 # number of overall hits +system.l2c.overall_hits::total 3406510 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2214 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2052 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 83747 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 137620 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 334397 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2082 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1771 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 51652 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 69122 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 204701 # number of ReadReq misses +system.l2c.ReadReq_misses::total 889358 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 476508 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 89488 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 565996 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 48344 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 44372 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 92716 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 10817 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7620 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 18437 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 83374 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 50998 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 134372 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2214 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2052 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 83747 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 220994 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 334397 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2082 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1771 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 51652 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 120120 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 204701 # number of demand (read+write) misses +system.l2c.demand_misses::total 1023730 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2214 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2052 # number of overall misses +system.l2c.overall_misses::cpu0.inst 83747 # number of overall misses +system.l2c.overall_misses::cpu0.data 220994 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 334397 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2082 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1771 # number of overall misses +system.l2c.overall_misses::cpu1.inst 51652 # number of overall misses +system.l2c.overall_misses::cpu1.data 120120 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 204701 # number of overall misses +system.l2c.overall_misses::total 1023730 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 196089257 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 182667757 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 7080624634 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 12249130737 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 43332889612 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 189088032 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 162443014 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4360864205 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 6107312919 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 26397681837 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 100258792004 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 50990906 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 47594001 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 98584907 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 312691152 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 283930496 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 596621648 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 58172655 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 50436899 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 108609554 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7528015770 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4219527160 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11747542930 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 196089257 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 182667757 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 7080624634 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 19777146507 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 43332889612 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 189088032 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 162443014 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4360864205 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 10326840079 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 26397681837 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 112006334934 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 196089257 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 182667757 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 7080624634 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 19777146507 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 43332889612 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 189088032 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 162443014 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4360864205 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 10326840079 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 26397681837 # number of overall miss cycles +system.l2c.overall_miss_latency::total 112006334934 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 9258 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6874 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 859742 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 561719 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 909460 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 8634 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 714555 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 432937 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 677108 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 4186633 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2504876 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2504876 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 617109 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 215003 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 832112 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 83342 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 71775 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 155117 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 18053 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 13230 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 31283 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 138802 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 104805 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 243607 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 9258 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6874 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 859742 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 700521 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 909460 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8634 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6346 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 714555 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 537742 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 677108 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4430240 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 9258 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6874 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 859742 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 700521 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 909460 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8634 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6346 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 714555 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 537742 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 677108 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4430240 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.239145 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.298516 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.097409 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.244998 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.367687 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.241140 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.279073 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.072286 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.159658 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.302317 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.212428 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.772162 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.416217 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.680192 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.580068 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.618210 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.597717 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.599180 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.575964 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.589362 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.600669 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.486599 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.551593 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.239145 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.298516 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.097409 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.315471 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.367687 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.241140 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.279073 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.072286 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.223378 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.302317 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.231078 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.239145 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.298516 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.097409 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.315471 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.367687 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.241140 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.279073 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.072286 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.223378 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.302317 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.231078 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88567.866757 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 89019.374756 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84547.800327 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 89006.908422 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 129585.162582 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 90820.380403 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 91723.892716 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84427.789921 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 88355.558563 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 128957.268587 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 112731.646878 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 107.009549 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 531.847857 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 174.179512 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6468.044680 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6398.866312 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 6434.937314 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5377.891744 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6619.015617 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5890.847426 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 90292.126682 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82739.071336 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 87425.527119 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88567.866757 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89019.374756 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 84547.800327 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 89491.780352 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 129585.162582 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90820.380403 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 91723.892716 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 84427.789921 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 85971.029629 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128957.268587 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 109410.034808 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88567.866757 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89019.374756 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 84547.800327 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 89491.780352 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 129585.162582 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90820.380403 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 91723.892716 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 84427.789921 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 85971.029629 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128957.268587 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 109410.034808 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 12831 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 156 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 343 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 36.762821 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 37.408163 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1116216 # number of writebacks -system.l2c.writebacks::total 1116216 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 188 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 162 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 387 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 188 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 22 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 162 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 387 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 188 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 22 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 162 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 387 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1664 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1301 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 74347 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 94536 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2478 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2309 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 56023 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 106023 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 869899 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 435530 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 123517 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 559047 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 44959 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 45474 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 90433 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 8261 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 9038 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 17299 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 76639 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 55158 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 131797 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1664 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1301 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 74347 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 171175 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2478 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2309 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 56023 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 161181 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1001696 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1664 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1301 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 74347 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 171175 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 274703 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2478 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2309 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 56023 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 161181 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 256515 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1001696 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 94777748 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4793355973 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 6621770205 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 156241500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3582053738 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 7131500722 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 85169385965 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 9786055012 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2515639470 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 12301694482 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 455524094 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 460871563 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 916395657 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 84887682 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 92374949 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 177262631 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5315349505 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3512186842 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8827536347 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 94777748 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 4793355973 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 11937119710 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 156241500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3582053738 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 10643687564 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 93996922312 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 118167746 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94777748 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 4793355973 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 11937119710 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34136893349 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171330499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 156241500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3582053738 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 10643687564 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28363294485 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 93996922312 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2759400500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4958794248 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5045750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 413259748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 8136500246 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4773990997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 484709502 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5258700499 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2759400500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9732785245 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5045750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 897969250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 13395200745 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.207448 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.198415 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.207871 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.775863 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.467828 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.677328 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.601667 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.583921 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.592611 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.584394 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.585970 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.585217 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.576077 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508392 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.545673 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.226304 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.198213 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.215290 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097157 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290745 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.344865 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.266595 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.339160 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.068703 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.250730 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.325950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.226304 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70044.958587 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 67263.713741 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 97907.212176 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22469.301798 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20366.746845 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 22004.758959 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10131.989012 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10134.836676 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10133.420953 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10275.715047 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10220.729033 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10246.987167 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69355.674069 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63675.021611 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 66978.279832 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71014.270433 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 72849.921599 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64472.755767 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69736.349993 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 124268.367470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 69140.637207 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 67666.305760 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63938.984667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66035.621841 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110571.679960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 93837.773448 # average overall mshr miss latency +system.l2c.writebacks::writebacks 1128341 # number of writebacks +system.l2c.writebacks::total 1128341 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 159 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 14 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 202 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 26 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 403 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 159 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 202 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 26 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 403 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 159 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 202 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 26 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 403 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2214 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2052 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 83588 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 137606 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 334397 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2082 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1771 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 51450 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 69096 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 204699 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 888955 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 476508 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 89488 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 565996 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 48344 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 44372 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 92716 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10817 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 7620 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 18437 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 83374 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 50998 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 134372 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2214 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2052 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 83588 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 220980 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 334397 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2082 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1771 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 51450 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 120094 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 204699 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 1023327 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2214 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2052 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 83588 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 220980 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 334397 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2082 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1771 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 51450 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 120094 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 204699 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 1023327 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 168187741 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 156820743 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 6020171116 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10522241263 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 39221401658 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 162840466 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 140086986 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3700419545 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 5238305331 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 23877031123 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 89207505972 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 15957398094 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2857214499 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 18814612593 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 860594555 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 788863623 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1649458178 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 192360767 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 135695087 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 328055854 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6486393230 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3581079840 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 10067473070 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 168187741 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 156820743 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 6020171116 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 17008634493 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 39221401658 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 162840466 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 140086986 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3700419545 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 8819385171 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 23877031123 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 99274979042 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 168187741 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 156820743 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 6020171116 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 17008634493 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 39221401658 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 162840466 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 140086986 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3700419545 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 8819385171 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 23877031123 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 99274979042 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4878632500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5702000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 506298251 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 8578645501 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4641261500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 642209001 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5283470501 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 3188012750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9519894000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5702000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1148507252 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13862116002 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.244973 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.159598 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.212332 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.772162 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.416217 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.680192 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.580068 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.618210 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.597717 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.599180 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.575964 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.589362 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.600669 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486599 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.551593 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.315451 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.223330 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.230987 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.239145 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.298516 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097225 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.315451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.367687 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.241140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.279073 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.072003 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.223330 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.302314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.230987 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 76466.442328 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75811.991013 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 100350.980614 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33488.206062 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31928.465258 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33241.599928 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17801.475985 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.410326 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.437228 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17783.190071 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17807.754199 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17793.342409 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 77798.752969 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70220.005490 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 74922.402509 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76969.112558 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73437.350500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 97011.980571 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 75965.556007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76423.364035 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72021.954300 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76969.112558 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 117289.932798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 78213.480307 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 79100.500282 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71922.634500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73437.350500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116644.590951 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 97011.980571 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2981,57 +2969,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 969598 # Transaction distribution -system.membus.trans_dist::ReadResp 969598 # Transaction distribution -system.membus.trans_dist::WriteReq 38347 # Transaction distribution -system.membus.trans_dist::WriteResp 38347 # Transaction distribution -system.membus.trans_dist::Writeback 1222910 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 662686 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 662686 # Transaction distribution -system.membus.trans_dist::UpgradeReq 426453 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 285961 # Transaction distribution -system.membus.trans_dist::UpgradeResp 115017 # Transaction distribution -system.membus.trans_dist::ReadExReq 144468 # Transaction distribution -system.membus.trans_dist::ReadExResp 127604 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123068 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 988965 # Transaction distribution +system.membus.trans_dist::ReadResp 988965 # Transaction distribution +system.membus.trans_dist::WriteReq 38599 # Transaction distribution +system.membus.trans_dist::WriteResp 38599 # Transaction distribution +system.membus.trans_dist::Writeback 1235035 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 669572 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 669572 # Transaction distribution +system.membus.trans_dist::UpgradeReq 443245 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 300309 # Transaction distribution +system.membus.trans_dist::UpgradeResp 118634 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution +system.membus.trans_dist::ReadExReq 147271 # Transaction distribution +system.membus.trans_dist::ReadExResp 130046 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122720 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5176712 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5324942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335765 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335765 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5660707 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156198 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5280771 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5430111 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5765953 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155850 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50220 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174186440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 174394182 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14086976 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 188481158 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 617229 # Total snoops (count) -system.membus.snoop_fanout::samples 3621307 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 53136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 176778952 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 176989262 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14092480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14092480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191081742 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 645066 # Total snoops (count) +system.membus.snoop_fanout::samples 3693594 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3621307 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3693594 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3621307 # Request fanout histogram -system.membus.reqLayer0.occupancy 109998990 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3693594 # Request fanout histogram +system.membus.reqLayer0.occupancy 110078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 34484 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 20906994 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22086998 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18632739306 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11288947920 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10660858032 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6557942197 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187340770 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151922124 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3075,45 +3064,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 5129422 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 5122206 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38347 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38347 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2491671 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 932101 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 825371 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 481339 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 298222 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 779561 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 103 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 103 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298688 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298688 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8006212 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7112719 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15118931 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 267664595 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 231600691 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 499265286 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1616950 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9541409 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012122 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109429 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 5164890 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 5157651 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38599 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38599 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2504876 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 938982 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 832112 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 498168 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 313155 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 811323 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 114 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 114 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 303337 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 303337 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8953428 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6273029 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15226457 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302864374 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 197929240 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 500793614 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1680481 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9632863 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012020 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.108976 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9425751 98.79% 98.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115658 1.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9517074 98.80% 98.80% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115789 1.20% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9541409 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 18624671874 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 9632863 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 8806822228 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7692000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2518500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 12569931680 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 5125474266 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 12640622488 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 4045471741 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt index f3459bbfc..72f54d4c6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-minor/stats.txt @@ -1,139 +1,139 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.728175 # Number of seconds simulated -sim_ticks 51728174627500 # Number of ticks simulated -final_tick 51728174627500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.690388 # Number of seconds simulated +sim_ticks 51690388482000 # Number of ticks simulated +final_tick 51690388482000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 121986 # Simulator instruction rate (inst/s) -host_op_rate 143338 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6618487836 # Simulator tick rate (ticks/s) -host_mem_usage 708088 # Number of bytes of host memory used -host_seconds 7815.71 # Real time elapsed on the host -sim_insts 953410832 # Number of instructions simulated -sim_ops 1120287994 # Number of ops (including micro ops) simulated +host_inst_rate 185969 # Simulator instruction rate (inst/s) +host_op_rate 218525 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 10104822635 # Simulator tick rate (ticks/s) +host_mem_usage 719212 # Number of bytes of host memory used +host_seconds 5115.42 # Real time elapsed on the host +sim_insts 951311494 # Number of instructions simulated +sim_ops 1117847862 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 394816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 334912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10241472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 67386632 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 424256 # Number of bytes read from this memory -system.physmem.bytes_read::total 78782088 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 10241472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 10241472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 95103808 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 413184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 346752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10436032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 67415176 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 415104 # Number of bytes read from this memory +system.physmem.bytes_read::total 79026248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 10436032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 10436032 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 95778368 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 95124388 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5233 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 160023 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1052929 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6629 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1230983 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1485997 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 95798948 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5418 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 163063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1053375 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6486 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1234798 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1496537 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1488570 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 7633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 6474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 197986 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1302707 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1523002 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 197986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 197986 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1838530 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1499110 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 7993 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 6708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 201895 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1304211 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1528838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 201895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 201895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1852924 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 398 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1838928 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1838530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 7633 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 6474 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 197986 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1303104 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3361929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1230983 # Number of read requests accepted -system.physmem.writeReqs 2135785 # Number of write requests accepted -system.physmem.readBursts 1230983 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2135785 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 78738176 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 44736 # Total number of bytes read from write queue -system.physmem.bytesWritten 136238784 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 78782088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 136546148 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 699 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7032 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 39789 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 72855 # Per bank write bursts -system.physmem.perBankRdBursts::1 77589 # Per bank write bursts -system.physmem.perBankRdBursts::2 71702 # Per bank write bursts -system.physmem.perBankRdBursts::3 69206 # Per bank write bursts -system.physmem.perBankRdBursts::4 71012 # Per bank write bursts -system.physmem.perBankRdBursts::5 79882 # Per bank write bursts -system.physmem.perBankRdBursts::6 74555 # Per bank write bursts -system.physmem.perBankRdBursts::7 73696 # Per bank write bursts -system.physmem.perBankRdBursts::8 66951 # Per bank write bursts -system.physmem.perBankRdBursts::9 130748 # Per bank write bursts -system.physmem.perBankRdBursts::10 72702 # Per bank write bursts -system.physmem.perBankRdBursts::11 77684 # Per bank write bursts -system.physmem.perBankRdBursts::12 73029 # Per bank write bursts -system.physmem.perBankRdBursts::13 75645 # Per bank write bursts -system.physmem.perBankRdBursts::14 69035 # Per bank write bursts -system.physmem.perBankRdBursts::15 73993 # Per bank write bursts -system.physmem.perBankWrBursts::0 130105 # Per bank write bursts -system.physmem.perBankWrBursts::1 136647 # Per bank write bursts -system.physmem.perBankWrBursts::2 132594 # Per bank write bursts -system.physmem.perBankWrBursts::3 132058 # Per bank write bursts -system.physmem.perBankWrBursts::4 132790 # Per bank write bursts -system.physmem.perBankWrBursts::5 135723 # Per bank write bursts -system.physmem.perBankWrBursts::6 131916 # Per bank write bursts -system.physmem.perBankWrBursts::7 135307 # Per bank write bursts -system.physmem.perBankWrBursts::8 129762 # Per bank write bursts -system.physmem.perBankWrBursts::9 138269 # Per bank write bursts -system.physmem.perBankWrBursts::10 133041 # Per bank write bursts -system.physmem.perBankWrBursts::11 135411 # Per bank write bursts -system.physmem.perBankWrBursts::12 131809 # Per bank write bursts -system.physmem.perBankWrBursts::13 134107 # Per bank write bursts -system.physmem.perBankWrBursts::14 128778 # Per bank write bursts -system.physmem.perBankWrBursts::15 130414 # Per bank write bursts +system.physmem.bw_write::total 1853322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1852924 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 7993 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 6708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 201895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1304609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3382161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1234798 # Number of read requests accepted +system.physmem.writeReqs 2155868 # Number of write requests accepted +system.physmem.readBursts 1234798 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 2155868 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 78985984 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 41088 # Total number of bytes read from write queue +system.physmem.bytesWritten 134775168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 79026248 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 137831460 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 642 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49988 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 39660 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 74085 # Per bank write bursts +system.physmem.perBankRdBursts::1 76722 # Per bank write bursts +system.physmem.perBankRdBursts::2 75273 # Per bank write bursts +system.physmem.perBankRdBursts::3 67779 # Per bank write bursts +system.physmem.perBankRdBursts::4 73670 # Per bank write bursts +system.physmem.perBankRdBursts::5 87218 # Per bank write bursts +system.physmem.perBankRdBursts::6 75623 # Per bank write bursts +system.physmem.perBankRdBursts::7 75034 # Per bank write bursts +system.physmem.perBankRdBursts::8 70647 # Per bank write bursts +system.physmem.perBankRdBursts::9 127770 # Per bank write bursts +system.physmem.perBankRdBursts::10 77193 # Per bank write bursts +system.physmem.perBankRdBursts::11 73706 # Per bank write bursts +system.physmem.perBankRdBursts::12 69495 # Per bank write bursts +system.physmem.perBankRdBursts::13 70758 # Per bank write bursts +system.physmem.perBankRdBursts::14 68705 # Per bank write bursts +system.physmem.perBankRdBursts::15 70478 # Per bank write bursts +system.physmem.perBankWrBursts::0 131375 # Per bank write bursts +system.physmem.perBankWrBursts::1 133100 # Per bank write bursts +system.physmem.perBankWrBursts::2 134570 # Per bank write bursts +system.physmem.perBankWrBursts::3 130352 # Per bank write bursts +system.physmem.perBankWrBursts::4 132576 # Per bank write bursts +system.physmem.perBankWrBursts::5 140660 # Per bank write bursts +system.physmem.perBankWrBursts::6 130709 # Per bank write bursts +system.physmem.perBankWrBursts::7 134220 # Per bank write bursts +system.physmem.perBankWrBursts::8 130946 # Per bank write bursts +system.physmem.perBankWrBursts::9 136651 # Per bank write bursts +system.physmem.perBankWrBursts::10 131424 # Per bank write bursts +system.physmem.perBankWrBursts::11 131217 # Per bank write bursts +system.physmem.perBankWrBursts::12 125851 # Per bank write bursts +system.physmem.perBankWrBursts::13 128099 # Per bank write bursts +system.physmem.perBankWrBursts::14 126227 # Per bank write bursts +system.physmem.perBankWrBursts::15 127885 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51728172924500 # Total gap between requests +system.physmem.numWrRetry 155 # Number of times write queue was full causing retry +system.physmem.totGap 51690386784000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1230968 # Read request sizes (log2) +system.physmem.readPktSize::6 1234783 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2133212 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1193516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30294 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2468 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 634 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 774 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 402 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 116 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 93 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 91 # What read queue length does an incoming req see +system.physmem.writePktSize::6 2153295 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1198377 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 29223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 559 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 484 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 471 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 497 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1896 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 116 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 75 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 59 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,161 +159,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 48810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 75161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 120471 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 133680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 129638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 132279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 134371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 139270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 139351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138718 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 134041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 121456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 116921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 112653 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 104822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 103529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 102348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101456 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3528 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1501 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 704 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 545 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 724941 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.543548 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 170.840359 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 329.964737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 292739 40.38% 40.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 175978 24.27% 64.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 64522 8.90% 73.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 36242 5.00% 78.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 25200 3.48% 82.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 17306 2.39% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 13334 1.84% 86.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 11857 1.64% 87.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 87763 12.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 724941 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98383 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.504427 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 125.607658 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 98380 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 52281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 61850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 106555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 108316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 116449 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 154618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 128128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 118111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 116108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 109682 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 109242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 142032 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 116099 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 124147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 111898 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 106882 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 105751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6448 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 6306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 7481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 6361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 753 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 377 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 272 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 737863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 289.702517 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 167.794717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.456499 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 301335 40.84% 40.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 180643 24.48% 65.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 66243 8.98% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 37149 5.03% 79.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 25772 3.49% 82.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 17225 2.33% 85.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 13400 1.82% 86.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 11666 1.58% 88.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 84430 11.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 737863 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 101448 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 12.165149 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 123.730461 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 101445 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98383 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 21.637183 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.054808 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.113777 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 71754 72.93% 72.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 19885 20.21% 93.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 3061 3.11% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 745 0.76% 97.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 867 0.88% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 408 0.41% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 354 0.36% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 234 0.24% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 298 0.30% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 183 0.19% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 211 0.21% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 51 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 56 0.06% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 41 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 125 0.13% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 21 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 37 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 9 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 12 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 4 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 7 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98383 # Writes before turning the bus around for reads -system.physmem.totQLat 15890716010 # Total ticks spent queuing -system.physmem.totMemAccLat 38958541010 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 6151420000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12916.30 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 101448 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 101448 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.758044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.253158 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.739377 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 97720 96.33% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 2404 2.37% 98.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 434 0.43% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 505 0.50% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 168 0.17% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 63 0.06% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 44 0.04% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 12 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 10 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 11 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 20 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 26 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 6 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::832-863 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-927 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-959 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1152-1183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 101448 # Writes before turning the bus around for reads +system.physmem.totQLat 16140892467 # Total ticks spent queuing +system.physmem.totMemAccLat 39281317467 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 6170780000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13078.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31666.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31828.49 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.53 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.61 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.67 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.58 # Average write queue length when enqueuing -system.physmem.readRowHits 953619 # Number of row buffer hits during reads -system.physmem.writeRowHits 1680454 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes -system.physmem.avgGap 15364341.39 # Average gap between requests -system.physmem.pageHitRate 78.42 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2748558960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1499709750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4605829800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6915067200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1310572243215 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29887277315250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34592251323855 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.731394 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49719326487750 # Time in different power states -system.physmem_0.memoryStateTime::REF 1727317280000 # Time in different power states +system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing +system.physmem.readRowHits 952465 # Number of row buffer hits during reads +system.physmem.writeRowHits 1649689 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.18 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes +system.physmem.avgGap 15244906.69 # Average gap between requests +system.physmem.pageHitRate 77.91 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2866207680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1563903000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4722104400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6917801760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1320834277260 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29855603520000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34568672372100 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.764092 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49666580122402 # Time in different power states +system.physmem_0.memoryStateTime::REF 1726055500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 281530424750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 297752382598 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2731995000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1490671875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4990338600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6879109680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3378632599680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1309819963770 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29887937201250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34592481879855 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.735851 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49720391571002 # Time in different power states -system.physmem_1.memoryStateTime::REF 1727317280000 # Time in different power states +system.physmem_1.actEnergy 2712036600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1479781875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4904265600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6728184000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3376164558000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1311236111385 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29864022963750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34567247901210 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.736534 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49680605946994 # Time in different power states +system.physmem_1.memoryStateTime::REF 1726055500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 280461298998 # Time in different power states +system.physmem_1.memoryStateTime::ACT 283722031756 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 704 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -337,15 +334,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 261740307 # Number of BP lookups -system.cpu.branchPred.condPredicted 183617747 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12193617 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 193974198 # Number of BTB lookups -system.cpu.branchPred.BTBHits 136954935 # Number of BTB hits +system.cpu.branchPred.lookups 261231631 # Number of BP lookups +system.cpu.branchPred.condPredicted 183305796 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12196019 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 193363774 # Number of BTB lookups +system.cpu.branchPred.BTBHits 136711559 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 70.604718 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31757981 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2120874 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 70.701743 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31664930 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 2143732 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -376,61 +373,68 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 587644 # Table walker walks requested -system.cpu.dtb.walker.walksLong 587644 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 20971 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 193860 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 587644 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 587644 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 587644 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 214831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 23073.231987 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 18856.280230 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 14797.492454 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 212337 98.84% 98.84% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2138 1.00% 99.83% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 152 0.07% 99.91% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 133 0.06% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 38 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 214831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples -243009796 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -243009796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total -243009796 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 193861 90.24% 90.24% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 20971 9.76% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 214832 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 587644 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 585994 # Table walker walks requested +system.cpu.dtb.walker.walksLong 585994 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 21793 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 191747 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 585994 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 585994 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 585994 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 213540 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 24710.005137 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 20824.581984 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15872.776829 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 123160 57.68% 57.68% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 87731 41.08% 98.76% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 1449 0.68% 99.44% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 786 0.37% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 33 0.02% 99.82% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 127 0.06% 99.88% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-229375 51 0.02% 99.90% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::229376-262143 62 0.03% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 77 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 22 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-360447 20 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::360448-393215 10 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::425984-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-491519 5 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 213540 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -15748296 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -15748296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -15748296 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 191748 89.79% 89.79% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 21793 10.21% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 213541 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 585994 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 587644 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 214832 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 585994 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 213541 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 214832 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 802476 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 213541 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 799535 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184101010 # DTB read hits -system.cpu.dtb.read_misses 486113 # DTB read misses -system.cpu.dtb.write_hits 163332837 # DTB write hits -system.cpu.dtb.write_misses 101531 # DTB write misses +system.cpu.dtb.read_hits 183604569 # DTB read hits +system.cpu.dtb.read_misses 484391 # DTB read misses +system.cpu.dtb.write_hits 162970808 # DTB write hits +system.cpu.dtb.write_misses 101603 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 79171 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 889 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 14871 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 80226 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 794 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 14405 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 23598 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184587123 # DTB read accesses -system.cpu.dtb.write_accesses 163434368 # DTB write accesses +system.cpu.dtb.perms_faults 23565 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 184088960 # DTB read accesses +system.cpu.dtb.write_accesses 163072411 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 347433847 # DTB hits -system.cpu.dtb.misses 587644 # DTB misses -system.cpu.dtb.accesses 348021491 # DTB accesses +system.cpu.dtb.hits 346575377 # DTB hits +system.cpu.dtb.misses 585994 # DTB misses +system.cpu.dtb.accesses 347161371 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -460,175 +464,175 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 136955 # Table walker walks requested -system.cpu.itb.walker.walksLong 136955 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1083 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 119238 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 136955 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 136955 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 136955 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 120321 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 25178.697160 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 21090.590253 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 16725.174106 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 117467 97.63% 97.63% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2593 2.16% 99.78% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 161 0.13% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 40 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 38 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 20 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 136676 # Table walker walks requested +system.cpu.itb.walker.walksLong 136676 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1079 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 118957 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 136676 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 136676 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 136676 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 120036 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 27117.842072 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 23228.726671 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 17468.785563 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 117053 97.51% 97.51% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 2702 2.25% 99.77% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 172 0.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 64 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 25 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 17 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 120321 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -243525796 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -243525796 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -243525796 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 119238 99.10% 99.10% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1083 0.90% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 120321 # Table walker page sizes translated +system.cpu.itb.walker.walkCompletionTime::total 120036 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -16365796 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -16365796 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -16365796 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 118957 99.10% 99.10% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1079 0.90% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 120036 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136955 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 136955 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 136676 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 136676 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120321 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 120321 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 257276 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 455989522 # ITB inst hits -system.cpu.itb.inst_misses 136955 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 120036 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 120036 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 256712 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 454948976 # ITB inst hits +system.cpu.itb.inst_misses 136676 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 47436 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_mva_asid 47405 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1113 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 56761 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 57709 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 364272 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 370702 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 456126477 # ITB inst accesses -system.cpu.itb.hits 455989522 # DTB hits -system.cpu.itb.misses 136955 # DTB misses -system.cpu.itb.accesses 456126477 # DTB accesses -system.cpu.numCycles 2523007146 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 455085652 # ITB inst accesses +system.cpu.itb.hits 454948976 # DTB hits +system.cpu.itb.misses 136676 # DTB misses +system.cpu.itb.accesses 455085652 # DTB accesses +system.cpu.numCycles 2543244455 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 953410832 # Number of instructions committed -system.cpu.committedOps 1120287994 # Number of ops (including micro ops) committed -system.cpu.discardedOps 97416264 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 7771 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 100934517430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.646296 # CPI: cycles per instruction -system.cpu.ipc 0.377887 # IPC: instructions per cycle +system.cpu.committedInsts 951311494 # Number of instructions committed +system.cpu.committedOps 1117847862 # Number of ops (including micro ops) committed +system.cpu.discardedOps 97312681 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 7756 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 100838701590 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.673409 # CPI: cycles per instruction +system.cpu.ipc 0.374054 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16631 # number of quiesce instructions executed -system.cpu.tickCycles 1807938889 # Number of cycles that the object actually ticked -system.cpu.idleCycles 715068257 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 11209162 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.959689 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 331084794 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11209674 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.535631 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4089991250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.959689 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999921 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999921 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16616 # number of quiesce instructions executed +system.cpu.tickCycles 1803568308 # Number of cycles that the object actually ticked +system.cpu.idleCycles 739676147 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 11160252 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.957398 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 330283218 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11160764 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.593245 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4320792250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.957398 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999917 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999917 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 395 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1391009936 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1391009936 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 169770938 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 169770938 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 152453541 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 152453541 # number of WriteReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337498 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 337498 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4114364 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4114364 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4358642 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4358642 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 322224479 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 322224479 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 322224479 # number of overall hits -system.cpu.dcache.overall_hits::total 322224479 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 8085158 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 8085158 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 4338895 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 4338895 # number of WriteReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245002 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245002 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 246013 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 246013 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 12424053 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 12424053 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 12424053 # number of overall misses -system.cpu.dcache.overall_misses::total 12424053 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 128824080247 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 128824080247 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 144514675403 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 144514675403 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 29607413192 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 29607413192 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3571422003 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 3571422003 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 273338755650 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 273338755650 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 273338755650 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 273338755650 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 177856096 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177856096 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 156792436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 156792436 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1582500 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1582500 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4360377 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4360377 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4358644 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4358644 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 334648532 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 334648532 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 334648532 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 334648532 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.045459 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.045459 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027673 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.027673 # miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786731 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786731 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.056420 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.056420 # miss rate for LoadLockedReq accesses +system.cpu.dcache.tags.tag_accesses 1387540349 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1387540349 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 169325544 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 169325544 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 152117254 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 152117254 # number of WriteReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 336638 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 336638 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4103260 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4103260 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4350721 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4350721 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 321442798 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 321442798 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 321442798 # number of overall hits +system.cpu.dcache.overall_hits::total 321442798 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 8046914 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 8046914 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 4320227 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 4320227 # number of WriteReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245138 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1245138 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 249194 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 249194 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 12367141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 12367141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 12367141 # number of overall misses +system.cpu.dcache.overall_misses::total 12367141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 131461867675 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 131461867675 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 154903534956 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 154903534956 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35707428702 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35707428702 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 3656528250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 3656528250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 82000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 286365402631 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 286365402631 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 286365402631 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 286365402631 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 177372458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177372458 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 156437481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 156437481 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1581776 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1581776 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4352454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4352454 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4350722 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4350722 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 333809939 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 333809939 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 333809939 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 333809939 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.045367 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.045367 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.027616 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.027616 # miss rate for WriteReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.787177 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.787177 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057254 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057254 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037126 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037126 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037126 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037126 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15933.402940 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15933.402940 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33306.792490 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33306.792490 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 23781.016570 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 23781.016570 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14517.208452 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14517.208452 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22000.771862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22000.771862 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22000.771862 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.037048 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037048 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037048 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037048 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16336.929620 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16336.929620 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.415689 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.415689 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28677.486915 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28677.486915 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14673.420106 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14673.420106 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23155.343877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23155.343877 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23155.343877 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,82 +641,82 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8593512 # number of writebacks -system.cpu.dcache.writebacks::total 8593512 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 755938 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 755938 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1899458 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1899458 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 141 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 141 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2655396 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2655396 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2655396 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2655396 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7329220 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7329220 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2439437 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2439437 # number of WriteReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244861 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244861 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 246009 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 246009 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9768657 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9768657 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9768657 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9768657 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 102525908749 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 102525908749 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 73694416463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 73694416463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 27114416558 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 27114416558 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3077572997 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3077572997 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 176220325212 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 176220325212 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 176220325212 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 176220325212 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727815999 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727815999 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5585117500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5585117500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11312933499 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11312933499 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041209 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041209 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015558 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786642 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786642 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.056419 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.056419 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.writebacks::writebacks 8571803 # number of writebacks +system.cpu.dcache.writebacks::total 8571803 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 759012 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 759012 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1891728 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1891728 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 152 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 152 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2650740 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2650740 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2650740 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2650740 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7287902 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7287902 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2428499 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2428499 # number of WriteReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1244986 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1244986 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 249191 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 249191 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 1 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9716401 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9716401 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9716401 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9716401 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 108232242328 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 108232242328 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 80044946410 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 80044946410 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33835516298 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33835516298 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 3281036750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 3281036750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 80500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 80500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 188277188738 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 188277188738 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 188277188738 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 188277188738 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5752052750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5752052750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5611431750 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5611431750 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11363484500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11363484500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041088 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015524 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015524 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787081 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787081 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.057253 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.057253 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029191 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029191 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029191 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13988.652101 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13988.652101 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30209.600192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30209.600192 # average WriteReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21781.079621 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 21781.079621 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12510.001654 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12510.001654 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18039.360499 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18039.360499 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029108 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029108 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029108 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14850.946449 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14850.946449 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32960.666819 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32960.666819 # average WriteReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27177.427134 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27177.427134 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.754618 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.754618 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19377.255914 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 19377.255914 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -720,58 +724,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 24725990 # number of replacements -system.cpu.icache.tags.tagsinuse 511.931995 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 430886861 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 24726502 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.426115 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 21192166000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.931995 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999867 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999867 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 24658319 # number of replacements +system.cpu.icache.tags.tagsinuse 511.926866 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 429907589 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 24658831 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.434224 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 23112715250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.926866 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999857 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999857 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 273 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 113 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 480339884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 480339884 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 430886861 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 430886861 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 430886861 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 430886861 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 430886861 # number of overall hits -system.cpu.icache.overall_hits::total 430886861 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 24726512 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 24726512 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 24726512 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 24726512 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 24726512 # number of overall misses -system.cpu.icache.overall_misses::total 24726512 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 328589993689 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 328589993689 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 328589993689 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 328589993689 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 328589993689 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 328589993689 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 455613373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 455613373 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 455613373 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 455613373 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 455613373 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 455613373 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054271 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.054271 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.054271 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.054271 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.054271 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.054271 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13288.974753 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13288.974753 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13288.974753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13288.974753 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13288.974753 # average overall miss latency +system.cpu.icache.tags.tag_accesses 479225270 # Number of tag accesses +system.cpu.icache.tags.data_accesses 479225270 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 429907589 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 429907589 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 429907589 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 429907589 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 429907589 # number of overall hits +system.cpu.icache.overall_hits::total 429907589 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 24658841 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 24658841 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 24658841 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 24658841 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 24658841 # number of overall misses +system.cpu.icache.overall_misses::total 24658841 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 328732138519 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 328732138519 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 328732138519 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 328732138519 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 328732138519 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 328732138519 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 454566430 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 454566430 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 454566430 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 454566430 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 454566430 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 454566430 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.054247 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.054247 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.054247 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.054247 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.054247 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.054247 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13331.208004 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13331.208004 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13331.208004 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13331.208004 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13331.208004 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13331.208004 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -780,208 +784,209 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24726512 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 24726512 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 24726512 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 24726512 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 24726512 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 24726512 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 279088621775 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 279088621775 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 279088621775 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 279088621775 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 279088621775 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 279088621775 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3812277750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3812277750 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3812277750 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 3812277750 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054271 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.054271 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054271 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.054271 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11287.019446 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11287.019446 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11287.019446 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11287.019446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11287.019446 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11287.019446 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 24658841 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 24658841 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 24658841 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 24658841 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 24658841 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 24658841 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 291693903909 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 291693903909 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 291693903909 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 291693903909 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 291693903909 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 291693903909 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 4024065500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 4024065500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 4024065500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 4024065500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.054247 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.054247 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.054247 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.054247 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11829.181425 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11829.181425 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11829.181425 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11829.181425 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11829.181425 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11829.181425 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1618545 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65358.053127 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 40402502 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1681764 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.023883 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 5745484000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 36067.634498 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 340.939586 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 425.072148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 8071.479946 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20452.926949 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.550348 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005202 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006486 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123161 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.312087 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.997285 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 346 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62873 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 346 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 1634699 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65328.398065 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 40258941 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1697658 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.714400 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 6394381000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36150.495855 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 348.587735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 419.061629 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8126.200133 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 20284.052712 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.551613 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.005319 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006394 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.123996 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.309510 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996832 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 298 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62661 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 297 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 513 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2402 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5577 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54331 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.005280 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.959366 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 371551924 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 371551924 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 967297 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 281175 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 24618722 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7240126 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 33107320 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8593512 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8593512 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 704117 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 704117 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 10834 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 10834 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1670528 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1670528 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 967297 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 281175 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 24618722 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8910654 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 34777848 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 967297 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 281175 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 24618722 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8910654 # number of overall hits -system.cpu.l2cache.overall_hits::total 34777848 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6169 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5233 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 107787 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 334891 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 454080 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 540744 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 540744 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 38969 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 38969 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 719318 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 719318 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6169 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5233 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 107787 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1054209 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1173398 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6169 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5233 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 107787 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1054209 # number of overall misses -system.cpu.l2cache.overall_misses::total 1173398 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 490563500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 420808500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 7986963739 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25374551222 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 34272886961 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 4498807 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4498807 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 431949947 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 431949947 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 53534470118 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 53534470118 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 490563500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 420808500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 7986963739 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 78909021340 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 87807357079 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 490563500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 420808500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 7986963739 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 78909021340 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 87807357079 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 973466 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 286408 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 24726509 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7575017 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 33561400 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 8593512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 8593512 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244861 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244861 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49803 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 49803 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2389846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2389846 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 973466 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 286408 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 24726509 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9964863 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 35951246 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 973466 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 286408 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 24726509 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9964863 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 35951246 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006337 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018271 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004359 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.044210 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013530 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.434381 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.434381 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.782463 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.782463 # miss rate for UpgradeReq accesses +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 526 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2409 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5622 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54054 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004547 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.956131 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 370467994 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 370467994 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 967855 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 283816 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 24548042 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7200740 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 33000453 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8571803 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8571803 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 694691 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 694691 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 10952 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 10952 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1660414 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1660414 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 967855 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 283816 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 24548042 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8861154 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 34660867 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 967855 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 283816 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 24548042 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8861154 # number of overall hits +system.cpu.l2cache.overall_hits::total 34660867 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6456 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5418 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 110797 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 336133 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 458804 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 550295 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 550295 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 38841 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 38841 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 718512 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 718512 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6456 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5418 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 110797 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1054645 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1177316 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6456 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5418 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 110797 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1054645 # number of overall misses +system.cpu.l2cache.overall_misses::total 1177316 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 558145500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 469017250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9061497564 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 28118014803 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 38206675117 # number of ReadReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 6284799 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 6284799 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 581575900 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 581575900 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 79500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 79500 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58834664128 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 58834664128 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 558145500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 469017250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9061497564 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 86952678931 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 97041339245 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 558145500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 469017250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9061497564 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 86952678931 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 97041339245 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 974311 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 289234 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 24658839 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7536873 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 33459257 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 8571803 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 8571803 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1244986 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::total 1244986 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 49793 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 49793 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2378926 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2378926 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 974311 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 289234 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 24658839 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9915799 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 35838183 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 974311 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 289234 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 24658839 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9915799 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 35838183 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.006626 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.018732 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004493 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.044598 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013712 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442009 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442009 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780049 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780049 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.300989 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.300989 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006337 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018271 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004359 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.105793 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.032639 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006337 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018271 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004359 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.105793 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.032639 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79520.748906 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80414.389452 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74099.508651 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75769.582407 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75477.640418 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 8.319661 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 8.319661 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11084.450384 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11084.450384 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72250 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74423.926717 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74423.926717 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74099.508651 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74851.401705 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74831.691446 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79520.748906 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80414.389452 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74099.508651 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74851.401705 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74831.691446 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.302032 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.302032 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.006626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.018732 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004493 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.106360 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.032851 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.006626 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.018732 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004493 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.106360 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.032851 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86453.763941 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 86566.491325 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81784.683376 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83651.455831 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83274.503093 # average ReadReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 11.420782 # average WriteInvalidateReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 11.420782 # average WriteInvalidateReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14973.247342 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14973.247342 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81884.038301 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81884.038301 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86453.763941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 86566.491325 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81784.683376 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82447.343828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82425.907101 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86453.763941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 86566.491325 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81784.683376 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82447.343828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82425.907101 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -990,117 +995,117 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1379367 # number of writebacks -system.cpu.l2cache.writebacks::total 1379367 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1389906 # number of writebacks +system.cpu.l2cache.writebacks::total 1389906 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 20 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 20 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 20 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6169 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5233 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 107785 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 334871 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 454058 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 540744 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 540744 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38969 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 38969 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 719318 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 719318 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6169 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5233 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 107785 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1054189 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1173376 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6169 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5233 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 107785 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1054189 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1173376 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 413632000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 355518000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6634859761 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21149756024 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28553765785 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 12667521943 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 12667521943 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 390061961 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 390061961 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44297743880 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44297743880 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 413632000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 355518000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6634859761 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 65447499904 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 72851509665 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 413632000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 355518000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6634859761 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 65447499904 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 72851509665 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2718370250 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5287998001 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8006368251 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5177591000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5177591000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2718370250 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465589001 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13183959251 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013529 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.434381 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.434381 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.782463 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.782463 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 23 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 6456 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5418 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 110795 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 336112 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 458781 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 550295 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 550295 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 38841 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 38841 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 718512 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 718512 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 6456 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5418 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 110795 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1054624 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1177293 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 6456 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5418 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 110795 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1054624 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1177293 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 477004500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 400897250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7672809436 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 23903949947 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32454661133 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 18536320703 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18536320703 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 689128833 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 689128833 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 67500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 67500 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49848772872 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49848772872 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 477004500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 400897250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7672809436 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 73752722819 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 82303434005 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 477004500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 400897250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7672809436 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 73752722819 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 82303434005 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 3108920000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279556250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 8388476250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5172564500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5172564500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 3108920000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10452120750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13561040750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.044596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013712 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.442009 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.442009 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780049 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.780049 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.300989 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.300989 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.105791 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.032638 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006337 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018271 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004359 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.105791 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.032638 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61556.429568 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63157.920584 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62885.723377 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 23426.098011 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 23426.098011 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10009.545049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10009.545049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61582.977042 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61582.977042 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67050.089155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 67937.703038 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61556.429568 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62083.269607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62087.097116 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.302032 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.302032 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.106358 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.032850 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.006626 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.018732 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004493 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.106358 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.032850 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73885.455390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 73993.586194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69252.307740 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71119.001842 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70741.075007 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 33684.334226 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33684.334226 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17742.304086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17742.304086 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69377.787528 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69377.787528 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73885.455390 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 73993.586194 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69252.307740 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69932.718029 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69909.048984 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73885.455390 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 73993.586194 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69252.307740 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69932.718029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69909.048984 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1110,62 +1115,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 34111380 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 34103268 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33870 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8593512 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244861 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 49806 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 49808 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2389846 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2389846 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49557548 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31248640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 695589 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2279215 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 83780992 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1585841408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1267646988 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2291264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7787728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2863567388 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 571370 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 46410026 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002490 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.049834 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 33999690 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 33991608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33707 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8571803 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1351764 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1244986 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 49796 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 49797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2378926 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2378926 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49422267 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 31128556 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 697608 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 2275060 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 83523491 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1581512448 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1263125858 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2313872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7794488 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2854746666 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 562001 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 46265986 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002499 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.049932 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 46294483 99.75% 99.75% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115543 0.25% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 46150346 99.75% 99.75% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115640 0.25% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 46410026 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 33063458385 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 46265986 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 32968786985 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1149000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1168500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 37204558207 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 37104005805 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 15864083234 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 15790852218 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 409855669 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 409077948 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1306481232 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1301562725 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40405 # Transaction distribution -system.iobus.trans_dist::ReadResp 40405 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40307 # Transaction distribution +system.iobus.trans_dist::ReadResp 40307 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1180,13 +1183,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231006 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231006 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230972 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230972 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354276 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353756 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1201,13 +1204,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334456 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334456 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334320 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334320 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492862 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1235,71 +1238,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042384689 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 606946752 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179052263 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148389141 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.452585 # Cycle average of tags in use +system.iocache.tags.replacements 115468 # number of replacements +system.iocache.tags.tagsinuse 10.447877 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115484 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13141230176000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.516704 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.935881 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219794 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.433493 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653287 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13143236480000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.519281 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.928596 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219955 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.433037 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.652992 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039884 # Number of tag accesses -system.iocache.tags.data_accesses 1039884 # Number of data accesses +system.iocache.tags.tag_accesses 1039731 # Number of tag accesses +system.iocache.tags.data_accesses 1039731 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8839 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8822 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8859 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8839 # number of demand (read+write) misses -system.iocache.demand_misses::total 8879 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8822 # number of demand (read+write) misses +system.iocache.demand_misses::total 8862 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8839 # number of overall misses -system.iocache.overall_misses::total 8879 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1924538358 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1930023358 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28851084068 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28851084068 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1924538358 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1930362358 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1924538358 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1930362358 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8822 # number of overall misses +system.iocache.overall_misses::total 8862 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1598742761 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1603814761 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19786721850 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19786721850 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1598742761 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1604167261 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1598742761 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1604167261 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8839 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8822 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8859 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8839 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8879 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8822 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8862 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8839 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8879 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8822 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8862 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1313,55 +1316,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217732.589433 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217442.920009 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270485.675279 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270485.675279 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217407.631265 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217732.589433 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217407.631265 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225366 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 181222.258105 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 181037.900553 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185505.154973 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185505.154973 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 181016.391447 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 181222.258105 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 181016.391447 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 108614 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27560 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16000 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.177286 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.788375 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106630 # number of writebacks -system.iocache.writebacks::total 106630 # number of writebacks +system.iocache.writebacks::writebacks 106631 # number of writebacks +system.iocache.writebacks::total 106631 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8839 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8876 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8822 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8859 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8839 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8879 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8822 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8862 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8839 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8879 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1464798862 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1468359862 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23304534090 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23304534090 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1464798862 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1468542862 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1464798862 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1468542862 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8822 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8862 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1138893007 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1142035007 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14240157886 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14240157886 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1138893007 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1142228507 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1138893007 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1142228507 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1375,71 +1378,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165719.975337 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165430.358495 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218485.469230 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218485.469230 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165719.975337 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165395.073995 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 129096.917592 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 128912.406254 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133504.817802 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133504.817802 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 129096.917592 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 128890.601106 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 548979 # Transaction distribution -system.membus.trans_dist::ReadResp 548979 # Transaction distribution -system.membus.trans_dist::WriteReq 33870 # Transaction distribution -system.membus.trans_dist::WriteResp 33870 # Transaction distribution -system.membus.trans_dist::Writeback 1485997 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 647215 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 647215 # Transaction distribution -system.membus.trans_dist::UpgradeReq 39795 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 39797 # Transaction distribution -system.membus.trans_dist::ReadExReq 718688 # Transaction distribution -system.membus.trans_dist::ReadExResp 718688 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 553634 # Transaction distribution +system.membus.trans_dist::ReadResp 553634 # Transaction distribution +system.membus.trans_dist::WriteReq 33707 # Transaction distribution +system.membus.trans_dist::WriteResp 33707 # Transaction distribution +system.membus.trans_dist::Writeback 1496537 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 656758 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 656758 # Transaction distribution +system.membus.trans_dist::UpgradeReq 39666 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 39667 # Transaction distribution +system.membus.trans_dist::ReadExReq 717891 # Transaction distribution +system.membus.trans_dist::ReadExResp 717891 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 32 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6926 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4994566 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5124714 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335466 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5460180 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6924 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5031846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5161506 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335307 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335307 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5496813 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13852 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 201253164 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 201424076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14075072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14075072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 215499148 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 2915 # Total snoops (count) -system.membus.snoop_fanout::samples 3354632 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 202791724 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 202962146 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14065984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14065984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 217028130 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3038 # Total snoops (count) +system.membus.snoop_fanout::samples 3378648 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3354632 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3378648 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3354632 # Request fanout histogram -system.membus.reqLayer0.occupancy 113785000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3378648 # Request fanout histogram +system.membus.reqLayer0.occupancy 100002500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5606499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5714500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 21358745741 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 12721299869 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 12484485177 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 7256295209 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186617737 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151537359 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1450,11 +1453,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 149 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 149 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt index 3916ea1cc..5a693d4ac 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-checker/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.320647 # Number of seconds simulated -sim_ticks 51320647066500 # Number of ticks simulated -final_tick 51320647066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.320469 # Number of seconds simulated +sim_ticks 51320468905000 # Number of ticks simulated +final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81694 # Simulator instruction rate (inst/s) -host_op_rate 95992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4889396972 # Simulator tick rate (ticks/s) -host_mem_usage 723156 # Number of bytes of host memory used -host_seconds 10496.31 # Real time elapsed on the host -sim_insts 857487967 # Number of instructions simulated -sim_ops 1007562352 # Number of ops (including micro ops) simulated +host_inst_rate 78766 # Simulator instruction rate (inst/s) +host_op_rate 92549 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4725007878 # Simulator tick rate (ticks/s) +host_mem_usage 722788 # Number of bytes of host memory used +host_seconds 10861.46 # Real time elapsed on the host +sim_insts 855512158 # Number of instructions simulated +sim_ops 1005211605 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 226752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 205312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5743904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 43053832 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 407232 # Number of bytes read from this memory -system.physmem.bytes_read::total 49637032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5743904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5743904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69718464 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 415488 # Number of bytes read from this memory +system.physmem.bytes_read::total 49196072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5755680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5755680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69369152 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69739044 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3543 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105701 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 672729 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6363 # Number of read requests responded to by this memory -system.physmem.num_reads::total 791544 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1089351 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69389732 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105885 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 666091 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6492 # Number of read requests responded to by this memory +system.physmem.num_reads::total 784654 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1083893 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1091924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 111922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 838918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 967194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 111922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1358488 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1086466 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 112152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 830643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 958605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 112152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1351686 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1358889 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1358488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 111922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 839319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2326083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 791544 # Number of read requests accepted -system.physmem.writeReqs 1694292 # Number of write requests accepted -system.physmem.readBursts 791544 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1694292 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 50622848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35968 # Total number of bytes read from write queue -system.physmem.bytesWritten 107999616 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49637032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 108290596 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 562 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6769 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35256 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 48315 # Per bank write bursts -system.physmem.perBankRdBursts::1 50150 # Per bank write bursts -system.physmem.perBankRdBursts::2 46175 # Per bank write bursts -system.physmem.perBankRdBursts::3 46946 # Per bank write bursts -system.physmem.perBankRdBursts::4 45323 # Per bank write bursts -system.physmem.perBankRdBursts::5 52981 # Per bank write bursts -system.physmem.perBankRdBursts::6 47646 # Per bank write bursts -system.physmem.perBankRdBursts::7 48748 # Per bank write bursts -system.physmem.perBankRdBursts::8 44337 # Per bank write bursts -system.physmem.perBankRdBursts::9 72322 # Per bank write bursts -system.physmem.perBankRdBursts::10 50834 # Per bank write bursts -system.physmem.perBankRdBursts::11 50772 # Per bank write bursts -system.physmem.perBankRdBursts::12 48451 # Per bank write bursts -system.physmem.perBankRdBursts::13 47387 # Per bank write bursts -system.physmem.perBankRdBursts::14 44232 # Per bank write bursts -system.physmem.perBankRdBursts::15 46363 # Per bank write bursts -system.physmem.perBankWrBursts::0 103979 # Per bank write bursts -system.physmem.perBankWrBursts::1 105038 # Per bank write bursts -system.physmem.perBankWrBursts::2 105754 # Per bank write bursts -system.physmem.perBankWrBursts::3 105161 # Per bank write bursts -system.physmem.perBankWrBursts::4 103562 # Per bank write bursts -system.physmem.perBankWrBursts::5 108435 # Per bank write bursts -system.physmem.perBankWrBursts::6 103867 # Per bank write bursts -system.physmem.perBankWrBursts::7 105467 # Per bank write bursts -system.physmem.perBankWrBursts::8 102645 # Per bank write bursts -system.physmem.perBankWrBursts::9 108407 # Per bank write bursts -system.physmem.perBankWrBursts::10 108582 # Per bank write bursts -system.physmem.perBankWrBursts::11 107982 # Per bank write bursts -system.physmem.perBankWrBursts::12 105330 # Per bank write bursts -system.physmem.perBankWrBursts::13 105345 # Per bank write bursts -system.physmem.perBankWrBursts::14 103911 # Per bank write bursts -system.physmem.perBankWrBursts::15 104029 # Per bank write bursts +system.physmem.bw_write::total 1352087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1351686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 112152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 831044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2310692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 784654 # Number of read requests accepted +system.physmem.writeReqs 1688539 # Number of write requests accepted +system.physmem.readBursts 784654 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1688539 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 50184064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33792 # Total number of bytes read from write queue +system.physmem.bytesWritten 104909952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49196072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 107922404 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 528 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49293 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35218 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 46664 # Per bank write bursts +system.physmem.perBankRdBursts::1 51485 # Per bank write bursts +system.physmem.perBankRdBursts::2 48018 # Per bank write bursts +system.physmem.perBankRdBursts::3 46409 # Per bank write bursts +system.physmem.perBankRdBursts::4 44064 # Per bank write bursts +system.physmem.perBankRdBursts::5 51949 # Per bank write bursts +system.physmem.perBankRdBursts::6 45895 # Per bank write bursts +system.physmem.perBankRdBursts::7 48923 # Per bank write bursts +system.physmem.perBankRdBursts::8 45299 # Per bank write bursts +system.physmem.perBankRdBursts::9 70789 # Per bank write bursts +system.physmem.perBankRdBursts::10 48156 # Per bank write bursts +system.physmem.perBankRdBursts::11 46739 # Per bank write bursts +system.physmem.perBankRdBursts::12 48771 # Per bank write bursts +system.physmem.perBankRdBursts::13 48997 # Per bank write bursts +system.physmem.perBankRdBursts::14 45133 # Per bank write bursts +system.physmem.perBankRdBursts::15 46835 # Per bank write bursts +system.physmem.perBankWrBursts::0 99610 # Per bank write bursts +system.physmem.perBankWrBursts::1 104326 # Per bank write bursts +system.physmem.perBankWrBursts::2 103481 # Per bank write bursts +system.physmem.perBankWrBursts::3 102430 # Per bank write bursts +system.physmem.perBankWrBursts::4 101747 # Per bank write bursts +system.physmem.perBankWrBursts::5 104971 # Per bank write bursts +system.physmem.perBankWrBursts::6 100056 # Per bank write bursts +system.physmem.perBankWrBursts::7 103888 # Per bank write bursts +system.physmem.perBankWrBursts::8 99840 # Per bank write bursts +system.physmem.perBankWrBursts::9 106110 # Per bank write bursts +system.physmem.perBankWrBursts::10 102643 # Per bank write bursts +system.physmem.perBankWrBursts::11 100858 # Per bank write bursts +system.physmem.perBankWrBursts::12 103355 # Per bank write bursts +system.physmem.perBankWrBursts::13 103593 # Per bank write bursts +system.physmem.perBankWrBursts::14 100350 # Per bank write bursts +system.physmem.perBankWrBursts::15 101960 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 51320645833500 # Total gap between requests +system.physmem.numWrRetry 560 # Number of times write queue was full causing retry +system.physmem.totGap 51320467654000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 770259 # Read request sizes (log2) +system.physmem.readPktSize::6 763369 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1691719 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 523893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 218096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1685966 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 521104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 214865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,163 +159,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 67146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 82141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 96477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 97233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 109038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 106907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 116227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 110532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 123491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 110542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 89628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 89775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 76304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 74747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 73803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 70600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 519566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.297267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.561612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.602188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210755 40.56% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 125086 24.08% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44418 8.55% 73.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23610 4.54% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15941 3.07% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10357 1.99% 82.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8070 1.55% 84.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7704 1.48% 85.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 73625 14.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 519566 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 66165 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 11.954266 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 69.214790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 66159 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 25954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 62903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 63057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 90168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 80361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 95410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 92759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 101527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 92557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 84728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 110064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 78687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 89131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 74275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 70833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 66282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 9334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 9103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 5765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1539 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 512637 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.540847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.812512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.509823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207576 40.49% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 124268 24.24% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44401 8.66% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23774 4.64% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16232 3.17% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10193 1.99% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8192 1.60% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7548 1.47% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 70453 13.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 512637 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 56080 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.981651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 75.084718 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 56073 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 5 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 66165 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 66165 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.504330 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 22.270889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 18.258332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 44141 66.71% 66.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 6693 10.12% 76.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 8637 13.05% 89.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 2199 3.32% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1176 1.78% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 430 0.65% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 581 0.88% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 510 0.77% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 438 0.66% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 204 0.31% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 335 0.51% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 211 0.32% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 211 0.32% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 55 0.08% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 142 0.21% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 25 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 36 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 38 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 22 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 24 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 66165 # Writes before turning the bus around for reads -system.physmem.totQLat 15484448260 # Total ticks spent queuing -system.physmem.totMemAccLat 30315360760 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3954910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19576.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 56080 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 56080 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 29.229993 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 22.064414 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 40.823681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 46001 82.03% 82.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 3837 6.84% 88.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 4190 7.47% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 975 1.74% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 304 0.54% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 127 0.23% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 99 0.18% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 80 0.14% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 114 0.20% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 122 0.22% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 75 0.13% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 40 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 26 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 17 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 12 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 8 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 13 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 10 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-799 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-927 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1184-1215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 56080 # Writes before turning the bus around for reads +system.physmem.totQLat 15388206863 # Total ticks spent queuing +system.physmem.totMemAccLat 30090569363 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3920630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38326.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.87 # Average write queue length when enqueuing -system.physmem.readRowHits 603455 # Number of row buffer hits during reads -system.physmem.writeRowHits 1355453 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes -system.physmem.avgGap 20645225.93 # Average gap between requests -system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1965463920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1072425750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3012968400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5451384240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1226370177675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29716624044750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34306511542575 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.473889 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49436215199501 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing +system.physmem.readRowHits 598254 # Number of row buffer hits during reads +system.physmem.writeRowHits 1312451 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.06 # Row buffer hit rate for writes +system.physmem.avgGap 20750692.59 # Average gap between requests +system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1947569400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1062661875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2990566800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5316898320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1226375853165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29716511616000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34306208546520 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.470318 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49436040472112 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713703160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 170722374999 # Time in different power states +system.physmem_0.memoryStateTime::ACT 170725136888 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1962455040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1070784000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3156644400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5483576880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1227684074985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29715471503250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34306844116395 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.480369 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49434282568001 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem_1.actEnergy 1927966320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1051965750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3125569200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5305234320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1229368112910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29713886826750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34306669056210 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.479291 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49431639282027 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713703160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 172653903249 # Time in different power states +system.physmem_1.memoryStateTime::ACT 175126075973 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -339,15 +336,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 226505876 # Number of BP lookups -system.cpu.branchPred.condPredicted 151515363 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12247822 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159926869 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104610641 # Number of BTB hits +system.cpu.branchPred.lookups 226088242 # Number of BP lookups +system.cpu.branchPred.condPredicted 151212051 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12236747 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159576730 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104394184 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.411548 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31076851 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 345252 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.419428 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31024336 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 344701 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -378,45 +375,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 200647 # Table walker walks requested -system.cpu.checker.dtb.walker.walksLong 200647 # Table walker walks initiated with long descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 200647 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 200647 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 200647 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 1467106000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 1467106000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 1467106000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 155618 91.17% 91.17% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::2M 15067 8.83% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 170685 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 200647 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 200795 # Table walker walks requested +system.cpu.checker.dtb.walker.walksLong 200795 # Table walker walks initiated with long descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 200795 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 200795 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 200795 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 1638530500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 1638530500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 1638530500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 155523 90.97% 90.97% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::2M 15432 9.03% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 170955 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 200795 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 200647 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 170685 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 200795 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 170955 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 170685 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 371332 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 170955 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 371750 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 161284967 # DTB read hits -system.cpu.checker.dtb.read_misses 149209 # DTB read misses -system.cpu.checker.dtb.write_hits 146334371 # DTB write hits -system.cpu.checker.dtb.write_misses 51438 # DTB write misses +system.cpu.checker.dtb.read_hits 160924630 # DTB read hits +system.cpu.checker.dtb.read_misses 149513 # DTB read misses +system.cpu.checker.dtb.write_hits 145982592 # DTB write hits +system.cpu.checker.dtb.write_misses 51282 # DTB write misses system.cpu.checker.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.dtb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.dtb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 72843 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.dtb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID +system.cpu.checker.dtb.flush_entries 72580 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 7088 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 7050 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.checker.dtb.perms_faults 19208 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 161434176 # DTB read accesses -system.cpu.checker.dtb.write_accesses 146385809 # DTB write accesses +system.cpu.checker.dtb.perms_faults 19166 # Number of TLB faults due to permissions restrictions +system.cpu.checker.dtb.read_accesses 161074143 # DTB read accesses +system.cpu.checker.dtb.write_accesses 146033874 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 307619338 # DTB hits -system.cpu.checker.dtb.misses 200647 # DTB misses -system.cpu.checker.dtb.accesses 307819985 # DTB accesses +system.cpu.checker.dtb.hits 306907222 # DTB hits +system.cpu.checker.dtb.misses 200795 # DTB misses +system.cpu.checker.dtb.accesses 307108017 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -446,46 +443,46 @@ system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.itb.walker.walks 120779 # Table walker walks requested -system.cpu.checker.itb.walker.walksLong 120779 # Table walker walks initiated with long descriptors -system.cpu.checker.itb.walker.walkWaitTime::samples 120779 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::0 120779 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walkWaitTime::total 120779 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 1466561000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 1466561000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 1466561000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walkPageSizes::4K 108783 98.83% 98.83% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::2M 1287 1.17% 100.00% # Table walker page sizes translated -system.cpu.checker.itb.walker.walkPageSizes::total 110070 # Table walker page sizes translated +system.cpu.checker.itb.walker.walks 120591 # Table walker walks requested +system.cpu.checker.itb.walker.walksLong 120591 # Table walker walks initiated with long descriptors +system.cpu.checker.itb.walker.walkWaitTime::samples 120591 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::0 120591 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walkWaitTime::total 120591 # Table walker wait (enqueue to first request) latency +system.cpu.checker.itb.walker.walksPending::samples 1637932000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 1637932000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 1637932000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walkPageSizes::4K 108617 98.83% 98.83% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::2M 1291 1.17% 100.00% # Table walker page sizes translated +system.cpu.checker.itb.walker.walkPageSizes::total 109908 # Table walker page sizes translated system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120779 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120779 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 120591 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 120591 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 110070 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 110070 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.walker.walkRequestOrigin::total 230849 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 857899518 # ITB inst hits -system.cpu.checker.itb.inst_misses 120779 # ITB inst misses +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 109908 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 109908 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.walker.walkRequestOrigin::total 230499 # Table walker requests started/completed, data/inst +system.cpu.checker.itb.inst_hits 855922330 # ITB inst hits +system.cpu.checker.itb.inst_misses 120591 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses system.cpu.checker.itb.write_hits 0 # DTB write hits system.cpu.checker.itb.write_misses 0 # DTB write misses system.cpu.checker.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.checker.itb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID -system.cpu.checker.itb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.checker.itb.flush_entries 52284 # Number of entries that have been flushed from TLB +system.cpu.checker.itb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID +system.cpu.checker.itb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID +system.cpu.checker.itb.flush_entries 52096 # Number of entries that have been flushed from TLB system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 858020297 # ITB inst accesses -system.cpu.checker.itb.hits 857899518 # DTB hits -system.cpu.checker.itb.misses 120779 # DTB misses -system.cpu.checker.itb.accesses 858020297 # DTB accesses -system.cpu.checker.numCycles 1008137807 # number of cpu cycles simulated +system.cpu.checker.itb.inst_accesses 856042921 # ITB inst accesses +system.cpu.checker.itb.hits 855922330 # DTB hits +system.cpu.checker.itb.misses 120591 # DTB misses +system.cpu.checker.itb.accesses 856042921 # DTB accesses +system.cpu.checker.numCycles 1005785493 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -517,87 +514,86 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 931379 # Table walker walks requested -system.cpu.dtb.walker.walksLong 931379 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16662 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 157071 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 405257 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 526122 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 1688.949521 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-32767 521687 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-65535 1343 0.26% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-98303 1868 0.36% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::98304-131071 570 0.11% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-163839 209 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::163840-196607 174 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-229375 58 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::229376-262143 108 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-294911 8 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-360447 36 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::360448-393215 45 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-425983 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 526122 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 461527 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 458117 99.26% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2510 0.54% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 628 0.14% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 155 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 42 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 461527 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 768881581580 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.740934 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.499994 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 767107299580 99.77% 99.77% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 970542000 0.13% 99.90% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 364225500 0.05% 99.94% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 157799500 0.02% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 120916000 0.02% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 94826000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 21620500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 42242000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2110500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 768881581580 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 157072 90.41% 90.41% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16662 9.59% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 173734 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 931379 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 945525 # Table walker walks requested +system.cpu.dtb.walker.walksLong 945525 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17037 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156802 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 426099 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 519426 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 1842.763936 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-32767 513062 98.77% 98.77% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-65535 3320 0.64% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-98303 1249 0.24% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::98304-131071 1137 0.22% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-163839 115 0.02% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::163840-196607 205 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-229375 84 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::229376-262143 60 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-294911 94 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::294912-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-360447 21 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::360448-393215 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-425983 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 519426 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 477950 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 472923 98.95% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4117 0.86% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 574 0.12% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 200 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 75 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 477950 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 768700308080 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.730043 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.512304 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 766743156580 99.75% 99.75% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1060609500 0.14% 99.88% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 401667500 0.05% 99.94% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 174666000 0.02% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 138312000 0.02% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 106588500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 24500000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 48487000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2321000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 768700308080 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 156803 90.20% 90.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 17037 9.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 173840 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 945525 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 931379 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173734 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 945525 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173840 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173734 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1105113 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173840 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1119365 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 171278986 # DTB read hits -system.cpu.dtb.read_misses 671795 # DTB read misses -system.cpu.dtb.write_hits 149102166 # DTB write hits -system.cpu.dtb.write_misses 259584 # DTB write misses +system.cpu.dtb.read_hits 170900022 # DTB read hits +system.cpu.dtb.read_misses 675244 # DTB read misses +system.cpu.dtb.write_hits 148749524 # DTB write hits +system.cpu.dtb.write_misses 270281 # DTB write misses system.cpu.dtb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 73098 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10235 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72825 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10420 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69082 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171950781 # DTB read accesses -system.cpu.dtb.write_accesses 149361750 # DTB write accesses +system.cpu.dtb.perms_faults 69816 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171575266 # DTB read accesses +system.cpu.dtb.write_accesses 149019805 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320381152 # DTB hits -system.cpu.dtb.misses 931379 # DTB misses -system.cpu.dtb.accesses 321312531 # DTB accesses +system.cpu.dtb.hits 319649546 # DTB hits +system.cpu.dtb.misses 945525 # DTB misses +system.cpu.dtb.accesses 320595071 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -627,214 +623,209 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 161841 # Table walker walks requested -system.cpu.itb.walker.walksLong 161841 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1421 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 122616 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17088 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144753 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 980.521993 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 6808.510178 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 144225 99.64% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 131 0.09% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 321 0.22% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 37 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 161869 # Table walker walks requested +system.cpu.itb.walker.walksLong 161869 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 122204 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17648 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144221 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1045.076653 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 6935.040907 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143697 99.64% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 129 0.09% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 259 0.18% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 98 0.07% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144753 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 141125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 24337.182009 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 134420 95.25% 95.25% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 4577 3.24% 98.49% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 1336 0.95% 99.44% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 512 0.36% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 95 0.07% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 88 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 22 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 28 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 15 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 141125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 657209390884 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.938693 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.240123 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 40327296652 6.14% 6.14% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 616846868232 93.86% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 34699000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 527000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 657209390884 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 122616 98.85% 98.85% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1421 1.15% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 124037 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144221 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141285 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26183.154631 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 139260 98.57% 98.57% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1739 1.23% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 189 0.13% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 61 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 141285 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 652736132088 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.935835 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.245289 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 41920855152 6.42% 6.42% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 610778213436 93.57% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 36269000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 794000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 652736132088 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 122204 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123637 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161841 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 161841 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161869 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161869 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 124037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 124037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 285878 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 360168043 # ITB inst hits -system.cpu.itb.inst_misses 161841 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123637 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123637 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 285506 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 359459512 # ITB inst hits +system.cpu.itb.inst_misses 161869 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 20 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 80016 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 2058 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53745 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 79718 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 2054 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53398 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372581 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372095 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 360329884 # ITB inst accesses -system.cpu.itb.hits 360168043 # DTB hits -system.cpu.itb.misses 161841 # DTB misses -system.cpu.itb.accesses 360329884 # DTB accesses -system.cpu.numCycles 1576983833 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 359621381 # ITB inst accesses +system.cpu.itb.hits 359459512 # DTB hits +system.cpu.itb.misses 161869 # DTB misses +system.cpu.itb.accesses 359621381 # DTB accesses +system.cpu.numCycles 1580751099 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 648826167 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1010661506 # Number of instructions fetch has processed -system.cpu.fetch.Branches 226505876 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135687492 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 852638415 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26165882 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3403646 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9234109 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1027275 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 359779044 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6134765 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47734 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1528240089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.774898 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 647898483 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1008720689 # Number of instructions fetch has processed +system.cpu.fetch.Branches 226088242 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135418520 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 855549558 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26139542 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3573192 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26865 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9268939 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1033386 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 427 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 359070671 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6123790 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1530420621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.772272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.159981 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 965897706 63.20% 63.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215974848 14.13% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70846962 4.64% 81.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 275520573 18.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 968902908 63.31% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215807485 14.10% 77.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71036994 4.64% 82.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 274673234 17.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1528240089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.143632 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.640883 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 527342057 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 504093722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 436470729 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51063982 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9269599 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33921165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3872416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1095869891 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29092135 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9269599 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 572608237 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46122541 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 363160924 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 442135288 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 94943500 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1076024490 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6785579 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4940621 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 314117 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 587788 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 42830435 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 21754 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1023810702 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1659713955 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1272840679 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1685189 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 958043687 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65767012 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27437914 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23747073 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104751050 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 175241778 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 152679763 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9977994 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9053000 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1040458161 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27741753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1056586315 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3302783 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53612674 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33630584 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 315276 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1528240089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691375 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.927907 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1530420621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.143026 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.638127 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 526178421 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 508648126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 435713994 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50619608 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9260472 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33861678 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3868815 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1093600087 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29077129 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9260472 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 571338545 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 48532565 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 364379914 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 441167933 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 95741192 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1073752213 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6802962 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5086497 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 358848 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 628248 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 43820548 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20190 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1021575372 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1655508848 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1270030956 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1469892 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 955737015 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65838354 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27320538 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23636945 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103635545 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 174900719 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 152333814 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9971771 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9081144 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1038303468 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53804457 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.688828 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.927358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 873840021 57.18% 57.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 338263818 22.13% 79.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 236701790 15.49% 94.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72838134 4.77% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6577115 0.43% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19211 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 877745445 57.35% 57.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 337069342 22.02% 79.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 236293073 15.44% 94.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72729594 4.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6564084 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19083 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1528240089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1530420621 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58408451 35.14% 35.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100871 0.06% 35.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26760 0.02% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 763 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44563063 26.81% 62.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63134312 37.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58206836 35.09% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99242 0.06% 35.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26725 0.02% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 744 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44573023 26.87% 62.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62969604 37.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 727619955 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2547357 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 123270 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 725956407 68.86% 68.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2542188 0.24% 69.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123122 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -856,102 +847,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 120690 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120904 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 175181818 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150993162 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174804143 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150649152 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1056586315 # Type of FU issued -system.cpu.iq.rate 0.670005 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166234220 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3808470802 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1121012820 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1038530652 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2478919 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 941723 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 907476 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1221261060 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1559463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4354414 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1054196021 # Type of FU issued +system.cpu.iq.rate 0.666896 # Inst issue rate +system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1118931433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 942754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4347401 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13859524 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14300 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143284 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6341204 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13878328 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14961 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143108 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6347044 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2565738 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1859911 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2552620 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1870361 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9269599 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6359819 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3950891 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1068424262 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9260472 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6554396 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3651492 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1066150871 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 175241778 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 152679763 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23316187 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 61516 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3818793 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143284 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3692717 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5135549 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8828266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1045377154 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 171268732 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10291027 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 174900719 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 152333814 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23208148 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59700 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3513413 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143108 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3675827 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5121930 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8797757 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1042985483 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170888878 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10276947 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224348 # number of nop insts executed -system.cpu.iew.exec_refs 320367802 # number of memory reference insts executed -system.cpu.iew.exec_branches 198404489 # Number of branches executed -system.cpu.iew.exec_stores 149099070 # Number of stores executed -system.cpu.iew.exec_rate 0.662897 # Inst execution rate -system.cpu.iew.wb_sent 1040225395 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1039438128 # cumulative count of insts written-back -system.cpu.iew.wb_producers 442335874 # num instructions producing a value -system.cpu.iew.wb_consumers 715873221 # num instructions consuming a value +system.cpu.iew.exec_nop 222943 # number of nop insts executed +system.cpu.iew.exec_refs 319634404 # number of memory reference insts executed +system.cpu.iew.exec_branches 197926826 # Number of branches executed +system.cpu.iew.exec_stores 148745526 # Number of stores executed +system.cpu.iew.exec_rate 0.659804 # Inst execution rate +system.cpu.iew.wb_sent 1037843882 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1037032766 # cumulative count of insts written-back +system.cpu.iew.wb_producers 441278048 # num instructions producing a value +system.cpu.iew.wb_consumers 713779914 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.659130 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.617897 # average fanout of values written-back +system.cpu.iew.wb_rate 0.656038 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618227 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51477037 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27426477 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8434480 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1516228883 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.664519 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.292276 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51563874 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27308999 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8427448 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1518403714 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.662019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.290608 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 998506921 65.85% 65.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 291444279 19.22% 85.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121999456 8.05% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36692084 2.42% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28614798 1.89% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14261229 0.94% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8588058 0.57% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4227240 0.28% 99.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11894818 0.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1001866977 65.98% 65.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 290832617 19.15% 85.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121646355 8.01% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36740427 2.42% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28447666 1.87% 97.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14105700 0.93% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8667985 0.57% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4229973 0.28% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11866014 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1516228883 # Number of insts commited each cycle -system.cpu.commit.committedInsts 857487967 # Number of instructions committed -system.cpu.commit.committedOps 1007562352 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1518403714 # Number of insts commited each cycle +system.cpu.commit.committedInsts 855512158 # Number of instructions committed +system.cpu.commit.committedOps 1005211605 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 307720812 # Number of memory references committed -system.cpu.commit.loads 161382253 # Number of loads committed -system.cpu.commit.membars 7017472 # Number of memory barriers committed -system.cpu.commit.branches 191417503 # Number of branches committed -system.cpu.commit.fp_insts 895898 # Number of committed floating point instructions. -system.cpu.commit.int_insts 925548459 # Number of committed integer instructions. -system.cpu.commit.function_calls 25509836 # Number of function calls committed. +system.cpu.commit.refs 307009160 # Number of memory references committed +system.cpu.commit.loads 161022390 # Number of loads committed +system.cpu.commit.membars 6998413 # Number of memory barriers committed +system.cpu.commit.branches 190975004 # Number of branches committed +system.cpu.commit.fp_insts 896164 # Number of committed floating point instructions. +system.cpu.commit.int_insts 923410198 # Number of committed integer instructions. +system.cpu.commit.function_calls 25456304 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 697466429 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2165110 0.21% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98436 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 695830631 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2161783 0.22% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98401 0.01% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction @@ -974,236 +965,236 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111588 0.01% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 161382253 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 146338559 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161022390 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 145986770 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1007562352 # Class of committed instruction -system.cpu.commit.bw_lim_events 11894818 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction +system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2555751551 # The number of ROB reads -system.cpu.rob.rob_writes 2129995502 # The number of ROB writes -system.cpu.timesIdled 8137427 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 48743744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101064310429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 857487967 # Number of Instructions Simulated -system.cpu.committedOps 1007562352 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.839074 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.839074 # CPI: Total CPI of All Threads -system.cpu.ipc 0.543752 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.543752 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237547063 # number of integer regfile reads -system.cpu.int_regfile_writes 738733253 # number of integer regfile writes -system.cpu.fp_regfile_reads 1457540 # number of floating regfile reads -system.cpu.fp_regfile_writes 782548 # number of floating regfile writes -system.cpu.cc_regfile_reads 228190122 # number of cc regfile reads -system.cpu.cc_regfile_writes 228796042 # number of cc regfile writes -system.cpu.misc_regfile_reads 5248690758 # number of misc regfile reads -system.cpu.misc_regfile_writes 27489325 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9822587 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.985266 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 286182485 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9823099 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.133625 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1485676250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.985266 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 2555711925 # The number of ROB reads +system.cpu.rob.rob_writes 2125474325 # The number of ROB writes +system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50330478 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101060186847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 855512158 # Number of Instructions Simulated +system.cpu.committedOps 1005211605 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.847725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.847725 # CPI: Total CPI of All Threads +system.cpu.ipc 0.541206 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.541206 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1234726115 # number of integer regfile reads +system.cpu.int_regfile_writes 737118920 # number of integer regfile writes +system.cpu.fp_regfile_reads 1461359 # number of floating regfile reads +system.cpu.fp_regfile_writes 784484 # number of floating regfile writes +system.cpu.cc_regfile_reads 227546613 # number of cc regfile reads +system.cpu.cc_regfile_writes 228200703 # number of cc regfile writes +system.cpu.misc_regfile_reads 5246257758 # number of misc regfile reads +system.cpu.misc_regfile_writes 27367002 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9794555 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983548 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 285502634 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9795067 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.147594 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1659133250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983548 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1249763399 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1249763399 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148780016 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148780016 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 129548885 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 129548885 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 381333 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 381333 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324563 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 324563 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352422 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3352422 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3751270 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3751270 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 278328901 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 278328901 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 278710234 # number of overall hits -system.cpu.dcache.overall_hits::total 278710234 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9497038 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9497038 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11468447 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11468447 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1197141 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1197141 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233328 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1233328 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 450623 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 450623 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20965485 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20965485 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22162626 # number of overall misses -system.cpu.dcache.overall_misses::total 22162626 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 140713387644 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 321962948230 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38655244426 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38655244426 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6327424004 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6327424004 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 462676335874 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 462676335874 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 462676335874 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 462676335874 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 158277054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 158277054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 141017332 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 141017332 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578474 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1578474 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557891 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1557891 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3803045 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3803045 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3751275 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3751275 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 299294386 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 299294386 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300872860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300872860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060003 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060003 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081327 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081327 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758417 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758417 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791665 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791665 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118490 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118490 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070050 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070050 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073661 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073661 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22068.477589 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20876.422129 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21410972 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 1246939843 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1246939843 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 148420477 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 148420477 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 129257116 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 129257116 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 380071 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 380071 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 323830 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 323830 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338713 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3338713 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3738459 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3738459 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 277677593 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 277677593 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 278057664 # number of overall hits +system.cpu.dcache.overall_hits::total 278057664 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9529450 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9529450 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11422113 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11422113 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1191409 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1191409 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233320 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1233320 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 451226 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 451226 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20951563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20951563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22142972 # number of overall misses +system.cpu.dcache.overall_misses::total 22142972 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 145395860730 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 145395860730 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 336812014094 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 336812014094 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35299806246 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35299806246 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6459718484 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6459718484 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 237001 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 237001 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 482207874824 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 482207874824 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 482207874824 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 482207874824 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 157949927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 157949927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 140679229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 140679229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1571480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1571480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557150 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1557150 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3789939 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3789939 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3738465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3738465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 298629156 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 298629156 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 300200636 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300200636 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060332 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060332 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081193 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081193 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758145 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758145 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.792037 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.792037 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.070159 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070159 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073761 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073761 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15257.529105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15257.529105 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29487.715110 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29487.715110 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28621.773948 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28621.773948 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14315.927017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23015.365241 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21777.016871 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20545206 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1402072 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1559097 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.270950 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.177632 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7597183 # number of writebacks -system.cpu.dcache.writebacks::total 7597183 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4319062 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4319062 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9426489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9426489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7148 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7148 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220034 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 220034 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13745551 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13745551 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13745551 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13745551 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5177976 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5177976 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041958 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2041958 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1190352 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1190352 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226180 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226180 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230589 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 230589 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7219934 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7219934 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8410286 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8410286 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70110899674 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70110899674 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53589743024 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53589743024 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18780468745 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18780468745 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35955294132 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35955294132 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2813771248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2813771248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123700642698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 142481111443 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729238749 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729238749 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587095483 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587095483 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316334232 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316334232 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032715 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032715 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.754116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.754116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787077 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787077 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060633 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060633 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024123 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024123 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027953 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027953 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 7577660 # number of writebacks +system.cpu.dcache.writebacks::total 7577660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4366240 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4366240 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9388231 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9388231 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7155 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7155 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220115 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 220115 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13754471 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13754471 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13754471 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13754471 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5163210 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5163210 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2033882 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2033882 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1184642 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1184642 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226165 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226165 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 231111 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 231111 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 56871439750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19552019274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19552019274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33205804688 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33205804688 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2956928250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2956928250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 227999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 227999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 130497994329 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 130497994329 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150050013603 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 150050013603 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5746385500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5746385500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5629281968 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5629281968 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11375667468 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11375667468 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032689 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032689 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014458 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014458 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753838 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753838 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787442 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787442 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024100 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024100 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027920 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027920 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14259.841180 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14259.841180 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27962.015373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27962.015373 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16504.580518 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16504.580518 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27081.024730 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27081.024730 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1211,277 +1202,276 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15084162 # number of replacements -system.cpu.icache.tags.tagsinuse 511.954207 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 343955623 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15084674 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.801661 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 14174936000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.954207 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999911 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15070815 # number of replacements +system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 343233622 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15071327 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.773948 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 14049577000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.953323 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 374842526 # Number of tag accesses -system.cpu.icache.tags.data_accesses 374842526 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 343955623 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 343955623 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 343955623 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 343955623 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 343955623 # number of overall hits -system.cpu.icache.overall_hits::total 343955623 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15802123 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15802123 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15802123 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15802123 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15802123 # number of overall misses -system.cpu.icache.overall_misses::total 15802123 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 208192919846 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 208192919846 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 208192919846 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 208192919846 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208192919846 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208192919846 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 359757746 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 359757746 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 359757746 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 359757746 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 359757746 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 359757746 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043924 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.043924 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.043924 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.043924 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.043924 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.043924 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13174.996793 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13174.996793 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13174.996793 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13174.996793 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 11061 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 374120916 # Number of tag accesses +system.cpu.icache.tags.data_accesses 374120916 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 343233622 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 343233622 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 343233622 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 343233622 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 343233622 # number of overall hits +system.cpu.icache.overall_hits::total 343233622 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15815747 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15815747 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15815747 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15815747 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15815747 # number of overall misses +system.cpu.icache.overall_misses::total 15815747 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 208885866517 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 208885866517 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 208885866517 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208885866517 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208885866517 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208885866517 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 359049369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 359049369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 359049369 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 359049369 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 359049369 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 359049369 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.461305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13207.461305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13207.461305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13207.461305 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 978 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1126 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 11.309816 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.152753 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 717343 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 717343 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 717343 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 717343 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 717343 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 717343 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15084780 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15084780 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15084780 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15084780 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15084780 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15084780 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171798629050 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 171798629050 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171798629050 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 171798629050 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171798629050 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 171798629050 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1412899000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1412899000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1412899000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1412899000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041930 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.041930 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.041930 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11388.872032 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11388.872032 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 744199 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 744199 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 744199 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 744199 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 744199 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 744199 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15071548 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15071548 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 179787086612 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 179787086612 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1585009250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1585009250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1585009250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1585009250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041976 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.041976 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.041976 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1166252 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65308.801684 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29080427 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1229042 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.661052 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2430267000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37210.550558 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 324.848912 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 496.111863 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7620.063188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19657.227164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004957 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007570 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116273 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.299945 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996533 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62489 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 300 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2670 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54081 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953506 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 273259305 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 273259305 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 799874 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299425 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 15000245 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6339023 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22438567 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7597183 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7597183 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730326 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 730326 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 9466 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 9466 # number of UpgradeReq hits +system.cpu.l2cache.tags.replacements 1159288 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 29043191 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1221496 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.776739 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2756226000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 319.528316 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 474.614102 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7535.726920 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19669.377573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.568752 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004876 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007242 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.114986 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.300131 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61904 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 579 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2674 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53473 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944580 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 272839925 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 272839925 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 805883 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 304376 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 14986718 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6321707 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 22418684 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7577660 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7577660 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730602 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 730602 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 9499 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 9499 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1583904 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1583904 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 799874 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 299425 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 15000245 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7922927 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24022471 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 799874 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 299425 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 15000245 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7922927 # number of overall hits -system.cpu.l2cache.overall_hits::total 24022471 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3543 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3208 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 84445 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 256196 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 347392 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495854 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 495854 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 34479 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 34479 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 417812 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 417812 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 3543 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3208 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 84445 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 674008 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 765204 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 3543 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3208 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 84445 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 674008 # number of overall misses -system.cpu.l2cache.overall_misses::total 765204 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 284358999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 261200750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6500329478 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21309046436 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28354935663 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 3493350 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 3493350 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 414507203 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 414507203 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 72000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 72000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34565495113 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 34565495113 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 284358999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 261200750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6500329478 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 55874541549 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 62920430776 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 284358999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 261200750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6500329478 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 55874541549 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 62920430776 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 803417 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302633 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15084690 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 6595219 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 22785959 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 7597183 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7597183 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226180 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226180 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 43945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2001716 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2001716 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 803417 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 302633 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 15084690 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 8596935 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 24787675 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 803417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 302633 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15084690 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 8596935 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 24787675 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004410 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010600 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005598 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038846 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015246 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404389 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404389 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.784594 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.784594 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.208727 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.208727 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004410 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010600 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005598 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.078401 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.030870 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004410 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010600 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005598 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.078401 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.030870 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 80259.384420 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81421.680175 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76977.079496 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83174.781948 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81622.304667 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 7.045118 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 7.045118 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12022.019287 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12022.019287 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 36000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 36000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82729.780650 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82729.780650 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82227.001918 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82227.001918 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 1579833 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1579833 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 805883 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 304376 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14986718 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7901540 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 23998517 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 805883 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 304376 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14986718 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7901540 # number of overall hits +system.cpu.l2cache.overall_hits::total 23998517 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3166 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3020 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 84629 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 253686 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 344501 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495562 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 495562 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 34430 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 34430 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 413693 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 413693 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 3166 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3020 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 84629 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 667379 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 758194 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 3166 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3020 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 84629 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 667379 # number of overall misses +system.cpu.l2cache.overall_misses::total 758194 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276962259 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 263518500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 7145038838 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22760355464 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30445875061 # number of ReadReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 4785347 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4785347 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 553374801 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 553374801 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36882340129 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 36882340129 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276962259 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 263518500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 7145038838 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 59642695593 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 67328215190 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276962259 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 263518500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 7145038838 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 59642695593 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 67328215190 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 809049 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 307396 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15071347 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 6575393 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 22763185 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7577660 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7577660 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226164 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226164 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43929 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 43929 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 6 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1993526 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1993526 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 809049 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 307396 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15071347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8568919 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 24756711 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 809049 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 307396 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15071347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8568919 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 24756711 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.003913 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009824 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005615 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038581 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015134 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404156 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404156 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783765 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783765 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.207518 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.207518 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.003913 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009824 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005615 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.077884 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.030626 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.003913 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009824 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005615 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.077884 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.030626 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87480.182881 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87257.781457 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 84427.782888 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89718.610660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88376.739287 # average ReadReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 9.656404 # average WriteInvalidateReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 9.656404 # average WriteInvalidateReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16072.460093 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16072.460093 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53000 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53000 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89153.889790 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89153.889790 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88800.775514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88800.775514 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1490,114 +1480,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 982720 # number of writebacks -system.cpu.l2cache.writebacks::total 982720 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 977263 # number of writebacks +system.cpu.l2cache.writebacks::total 977263 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3543 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3208 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84445 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256175 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 347371 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495854 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495854 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34479 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 34479 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 417812 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 417812 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3543 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3208 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 84445 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 673987 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 765183 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3543 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3208 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 84445 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 673987 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 765183 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 240086499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 221074750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5441255518 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18116835264 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24019252031 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 19575424791 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 19575424791 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345346475 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345346475 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29394156879 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29394156879 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 240086499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 221074750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5441255518 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47510992143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 53413408910 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 240086499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 221074750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5441255518 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47510992143 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 53413408910 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1103864500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5289749251 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6393613751 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176073500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176073500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1103864500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465822751 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569687251 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038843 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015245 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404389 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404389 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784594 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784594 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.208727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.208727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030869 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030869 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64435.496690 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.543628 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69145.818249 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39478.202840 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39478.202840 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10016.139534 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10016.139534 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3166 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3020 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84629 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 253665 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 344480 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495562 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495562 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34430 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 34430 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 413693 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 413693 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3166 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3020 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 84629 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 667358 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 758173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3166 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19591961036 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26140194449 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16855177398 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16855177398 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 611252927 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 611252927 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 153001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 153001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31729551871 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31729551871 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 237171251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 225518000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6085544162 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51321512907 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 57869746320 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 237171251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 225518000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6085544162 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51321512907 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 57869746320 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1276231250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5274563500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6550794750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5186666500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5186666500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1276231250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10461230000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11737461250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038578 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015133 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404156 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404156 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783765 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783765 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207518 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207518 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030625 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030625 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1607,66 +1597,62 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23340437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23332371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7597183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332844 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2001716 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2001716 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30212060 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27467336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 733813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1968769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 60381978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965760880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1115140164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2421064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6427336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2089749444 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 606880 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34513008 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9.003347 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.057757 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1993526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1993526 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30185484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27390990 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 736951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 583028 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.003382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 34397489 99.67% 99.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 115519 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 34071281 99.66% 99.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 115623 0.34% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34513008 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 26212619005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1180500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22673982421 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13673864954 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 432131982 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 430754363 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1166119344 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1154477924 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40381 # Transaction distribution -system.iobus.trans_dist::ReadResp 40381 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40283 # Transaction distribution +system.iobus.trans_dist::ReadResp 40283 # Transaction distribution +system.iobus.trans_dist::WriteReq 136558 # Transaction distribution +system.iobus.trans_dist::WriteResp 29894 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1676,18 +1662,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29496 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354228 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1697,18 +1683,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17529 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492670 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1728,7 +1714,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21908000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1736,71 +1722,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042349161 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607064814 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92761000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179004202 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148363066 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115461 # number of replacements -system.iocache.tags.tagsinuse 10.424617 # Cycle average of tags in use +system.iocache.tags.replacements 115456 # number of replacements +system.iocache.tags.tagsinuse 10.424607 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13092188806000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544621 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879997 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651539 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13092103918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544640 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879967 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429998 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039668 # Number of tag accesses -system.iocache.tags.data_accesses 1039668 # Number of data accesses +system.iocache.tags.tag_accesses 1039632 # Number of tag accesses +system.iocache.tags.data_accesses 1039632 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8815 # number of demand (read+write) misses -system.iocache.demand_misses::total 8855 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses +system.iocache.demand_misses::total 8851 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8815 # number of overall misses -system.iocache.overall_misses::total 8855 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1934147111 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1939674111 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28899223848 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28899223848 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1934147111 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1940013111 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1934147111 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1940013111 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8811 # number of overall misses +system.iocache.overall_misses::total 8851 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1609809480 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1614881480 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19830913268 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19830913268 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1609809480 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1615233980 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1609809480 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1615233980 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8815 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8855 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8815 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8855 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1814,55 +1800,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 219122.696679 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 219086.743196 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 219086.743196 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225873 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182513.729656 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182491.693594 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182491.693594 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110252 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27588 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.187364 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.825059 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8815 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8855 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8811 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8851 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8815 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8855 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1475641121 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1479244121 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23352302242 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23352302242 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1475641121 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1479427121 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1475641121 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1479427121 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8811 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8851 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150531536 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1153673536 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14284309344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14284309344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1150531536 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1153867036 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1150531536 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1153867036 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1876,71 +1862,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 411277 # Transaction distribution -system.membus.trans_dist::ReadResp 411277 # Transaction distribution -system.membus.trans_dist::WriteReq 33858 # Transaction distribution -system.membus.trans_dist::WriteResp 33858 # Transaction distribution -system.membus.trans_dist::Writeback 1089351 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 602368 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 602368 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35261 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35263 # Transaction distribution -system.membus.trans_dist::ReadExReq 417183 # Transaction distribution -system.membus.trans_dist::ReadExResp 417183 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 408284 # Transaction distribution +system.membus.trans_dist::ReadResp 408284 # Transaction distribution +system.membus.trans_dist::WriteReq 33682 # Transaction distribution +system.membus.trans_dist::WriteResp 33682 # Transaction distribution +system.membus.trans_dist::Writeback 1083893 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 602073 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 602073 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35223 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35226 # Transaction distribution +system.membus.trans_dist::ReadExReq 413056 # Transaction distribution +system.membus.trans_dist::ReadExResp 413056 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122652 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3620810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3750918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4086095 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3600651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3730211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4065512 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143869516 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144039988 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14058112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14058112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 158098100 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3154 # Total snoops (count) -system.membus.snoop_fanout::samples 2500418 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3023 # Total snoops (count) +system.membus.snoop_fanout::samples 2488136 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2500418 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2500418 # Request fanout histogram -system.membus.reqLayer0.occupancy 109711500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2488136 # Request fanout histogram +system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5440999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16316164477 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7830132924 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4726359104 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186594798 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151502434 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1985,6 +1971,6 @@ system.realview.ethernet.coalescedTotal 0 # av system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16160 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt index 828771ce9..b1b40f923 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt @@ -1,169 +1,169 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.345385 # Number of seconds simulated -sim_ticks 47345385235500 # Number of ticks simulated -final_tick 47345385235500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.305566 # Number of seconds simulated +sim_ticks 47305566199500 # Number of ticks simulated +final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 106392 # Simulator instruction rate (inst/s) -host_op_rate 125133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5453309126 # Simulator tick rate (ticks/s) -host_mem_usage 767036 # Number of bytes of host memory used -host_seconds 8681.96 # Real time elapsed on the host -sim_insts 923688991 # Number of instructions simulated -sim_ops 1086395427 # Number of ops (including micro ops) simulated +host_inst_rate 109110 # Simulator instruction rate (inst/s) +host_op_rate 128307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5804669404 # Simulator tick rate (ticks/s) +host_mem_usage 767140 # Number of bytes of host memory used +host_seconds 8149.57 # Real time elapsed on the host +sim_insts 889196991 # Number of instructions simulated +sim_ops 1045647845 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 161152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 146432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 4268768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 16023832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 20180672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 179840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 156416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3463536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 11559072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 14510464 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437312 # Number of bytes read from this memory -system.physmem.bytes_read::total 71087496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 4268768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3463536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7732304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 86253568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 75776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 60928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 4503136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 12909720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 13016640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 167424 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 164416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2523040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 10482528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 14576384 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 439104 # Number of bytes read from this memory +system.physmem.bytes_read::total 58919096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 4503136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2523040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7026176 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 75116864 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 86274384 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2518 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2288 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 82652 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 250394 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 315323 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2810 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2444 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 54162 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 180625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 226726 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6833 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1126775 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1347712 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 75137680 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1184 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 952 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86314 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 201736 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 203385 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2569 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39466 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 163804 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 227756 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6861 # Number of read requests responded to by this memory +system.physmem.num_reads::total 936643 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1173701 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1350315 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3093 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 90162 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 338445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 426244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3798 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3304 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 73155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 244144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 306481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1501466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 90162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 73155 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 163317 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1821795 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1176304 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 1602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 1288 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 95193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 272901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 275161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 221592 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 308133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1245500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 95193 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 53335 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 148527 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587908 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 440 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1822234 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1821795 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 90162 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 338885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 426244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3798 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3304 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 73155 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 244144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 306481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3323700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1126775 # Number of read requests accepted -system.physmem.writeReqs 2040290 # Number of write requests accepted -system.physmem.readBursts 1126775 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 2040290 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 72094336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19264 # Total number of bytes read from write queue -system.physmem.bytesWritten 130093376 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 71087496 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 130432784 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 301 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7556 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 121134 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 65675 # Per bank write bursts -system.physmem.perBankRdBursts::1 75833 # Per bank write bursts -system.physmem.perBankRdBursts::2 67256 # Per bank write bursts -system.physmem.perBankRdBursts::3 67290 # Per bank write bursts -system.physmem.perBankRdBursts::4 71240 # Per bank write bursts -system.physmem.perBankRdBursts::5 82191 # Per bank write bursts -system.physmem.perBankRdBursts::6 67013 # Per bank write bursts -system.physmem.perBankRdBursts::7 67787 # Per bank write bursts -system.physmem.perBankRdBursts::8 61707 # Per bank write bursts -system.physmem.perBankRdBursts::9 85775 # Per bank write bursts -system.physmem.perBankRdBursts::10 61014 # Per bank write bursts -system.physmem.perBankRdBursts::11 72520 # Per bank write bursts -system.physmem.perBankRdBursts::12 65793 # Per bank write bursts -system.physmem.perBankRdBursts::13 74631 # Per bank write bursts -system.physmem.perBankRdBursts::14 69278 # Per bank write bursts -system.physmem.perBankRdBursts::15 71471 # Per bank write bursts -system.physmem.perBankWrBursts::0 122526 # Per bank write bursts -system.physmem.perBankWrBursts::1 130111 # Per bank write bursts -system.physmem.perBankWrBursts::2 125889 # Per bank write bursts -system.physmem.perBankWrBursts::3 127486 # Per bank write bursts -system.physmem.perBankWrBursts::4 126972 # Per bank write bursts -system.physmem.perBankWrBursts::5 136977 # Per bank write bursts -system.physmem.perBankWrBursts::6 126845 # Per bank write bursts -system.physmem.perBankWrBursts::7 128268 # Per bank write bursts -system.physmem.perBankWrBursts::8 123854 # Per bank write bursts -system.physmem.perBankWrBursts::9 125736 # Per bank write bursts -system.physmem.perBankWrBursts::10 125360 # Per bank write bursts -system.physmem.perBankWrBursts::11 131761 # Per bank write bursts -system.physmem.perBankWrBursts::12 119984 # Per bank write bursts -system.physmem.perBankWrBursts::13 126166 # Per bank write bursts -system.physmem.perBankWrBursts::14 125889 # Per bank write bursts -system.physmem.perBankWrBursts::15 128885 # Per bank write bursts +system.physmem.bw_write::total 1588348 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587908 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 1602 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 1288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 95193 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 273341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 275161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 221592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 308133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9282 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2833848 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 936643 # Number of read requests accepted +system.physmem.writeReqs 1837953 # Number of write requests accepted +system.physmem.readBursts 936643 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1837953 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59924608 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 20544 # Total number of bytes read from write queue +system.physmem.bytesWritten 114470976 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 58919096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 117483216 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 321 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49325 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 117374 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 55305 # Per bank write bursts +system.physmem.perBankRdBursts::1 59995 # Per bank write bursts +system.physmem.perBankRdBursts::2 52034 # Per bank write bursts +system.physmem.perBankRdBursts::3 56018 # Per bank write bursts +system.physmem.perBankRdBursts::4 58058 # Per bank write bursts +system.physmem.perBankRdBursts::5 68871 # Per bank write bursts +system.physmem.perBankRdBursts::6 59545 # Per bank write bursts +system.physmem.perBankRdBursts::7 57406 # Per bank write bursts +system.physmem.perBankRdBursts::8 51483 # Per bank write bursts +system.physmem.perBankRdBursts::9 77850 # Per bank write bursts +system.physmem.perBankRdBursts::10 53930 # Per bank write bursts +system.physmem.perBankRdBursts::11 57982 # Per bank write bursts +system.physmem.perBankRdBursts::12 54532 # Per bank write bursts +system.physmem.perBankRdBursts::13 56851 # Per bank write bursts +system.physmem.perBankRdBursts::14 60976 # Per bank write bursts +system.physmem.perBankRdBursts::15 55486 # Per bank write bursts +system.physmem.perBankWrBursts::0 110085 # Per bank write bursts +system.physmem.perBankWrBursts::1 112883 # Per bank write bursts +system.physmem.perBankWrBursts::2 108062 # Per bank write bursts +system.physmem.perBankWrBursts::3 109070 # Per bank write bursts +system.physmem.perBankWrBursts::4 113169 # Per bank write bursts +system.physmem.perBankWrBursts::5 118310 # Per bank write bursts +system.physmem.perBankWrBursts::6 115499 # Per bank write bursts +system.physmem.perBankWrBursts::7 111959 # Per bank write bursts +system.physmem.perBankWrBursts::8 107874 # Per bank write bursts +system.physmem.perBankWrBursts::9 113071 # Per bank write bursts +system.physmem.perBankWrBursts::10 109141 # Per bank write bursts +system.physmem.perBankWrBursts::11 113654 # Per bank write bursts +system.physmem.perBankWrBursts::12 105244 # Per bank write bursts +system.physmem.perBankWrBursts::13 111328 # Per bank write bursts +system.physmem.perBankWrBursts::14 115976 # Per bank write bursts +system.physmem.perBankWrBursts::15 113284 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 614 # Number of times write queue was full causing retry -system.physmem.totGap 47345383810500 # Total gap between requests +system.physmem.numWrRetry 81608 # Number of times write queue was full causing retry +system.physmem.totGap 47305564753000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) -system.physmem.readPktSize::4 21334 # Read request sizes (log2) +system.physmem.readPktSize::4 21333 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1105404 # Read request sizes (log2) +system.physmem.readPktSize::6 915273 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 2037687 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 495851 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 234383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 118863 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 70028 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 51854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39852 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 34830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 31890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 7930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2742 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1780 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 844 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 607 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1835350 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 429452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 211261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 82392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 54481 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 35792 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 29912 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 27031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25347 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 22393 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 8038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1011 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 398 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see @@ -188,140 +188,136 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 44920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 58821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 69578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 77864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 89177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 97306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 106336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 112038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 121912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 121861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 124135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 125483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 131449 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 118558 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 117002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 113440 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 105060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 29238 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 25813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 22998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 20720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 18797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 16980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 15279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 13444 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 11652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 10311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 9180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 8124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 7426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 6654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 6134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 5597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 5145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 4620 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 4249 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 3863 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 3550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 3131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 2559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 2104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 1878 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 1591 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 1280 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1502 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1131657 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.664737 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 108.493979 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 249.059793 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 718344 63.48% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 219262 19.38% 82.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56669 5.01% 87.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 25497 2.25% 90.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20148 1.78% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11584 1.02% 92.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 9545 0.84% 93.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 8895 0.79% 94.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 61713 5.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1131657 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 74075 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 15.207155 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 65.468886 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 74072 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 25942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31294 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 42762 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 50992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 57625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 67617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 67331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 70370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 78632 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 77296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 79817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 88544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 82050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 81883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 102987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 87472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 82523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 74776 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 11408 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 9295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9951 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 10393 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 8966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 7640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7450 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7439 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 6226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 5791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 5896 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2893 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 2650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 4384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 7984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 354953 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 953575 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 182.885667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.719338 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 252.430373 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 592274 62.11% 62.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 190618 19.99% 82.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51298 5.38% 87.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 22604 2.37% 89.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16941 1.78% 91.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10334 1.08% 92.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7600 0.80% 93.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7080 0.74% 94.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54826 5.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 953575 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60764 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.409042 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 72.355469 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 60757 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 74075 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 74075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.441228 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.793858 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 451.068024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-1023 74039 99.95% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::1024-2047 13 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2048-3071 9 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3072-4095 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4096-5119 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5120-6143 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26624-27647 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33792-34815 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64512-65535 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 74075 # Writes before turning the bus around for reads -system.physmem.totQLat 56140564025 # Total ticks spent queuing -system.physmem.totMemAccLat 77261951525 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5632370000 # Total ticks spent in databus transfers -system.physmem.avgQLat 49837.43 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60764 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60764 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 29.435340 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.473917 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 995.068690 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-4095 60761 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::98304-102399 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::102400-106495 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192512-196607 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60764 # Writes before turning the bus around for reads +system.physmem.totQLat 43948740923 # Total ticks spent queuing +system.physmem.totMemAccLat 61504778423 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4681610000 # Total ticks spent in databus transfers +system.physmem.avgQLat 46937.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 68587.43 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.52 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.75 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.50 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.75 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 65687.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.25 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.48 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.34 # Average write queue length when enqueuing -system.physmem.readRowHits 851046 # Number of row buffer hits during reads -system.physmem.writeRowHits 1176475 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.88 # Row buffer hit rate for writes -system.physmem.avgGap 14949293.37 # Average gap between requests -system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4318120800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2356117500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4401423000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6642421200 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1163515422960 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27386602512000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31660206295860 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.707358 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45559855793000 # Time in different power states -system.physmem_0.memoryStateTime::REF 1580966400000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.58 # Average write queue length when enqueuing +system.physmem.readRowHits 706637 # Number of row buffer hits during reads +system.physmem.writeRowHits 1064717 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 59.53 # Row buffer hit rate for writes +system.physmem.avgGap 17049532.53 # Average gap between requests +system.physmem.pageHitRate 65.01 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3636465840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1984182750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3644362800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5825759760 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1155369631905 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27369856613250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31630086518865 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.633528 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45532077679143 # Time in different power states +system.physmem_0.memoryStateTime::REF 1579636760000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 204562609000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 193851315857 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4237153200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2311938750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 4385027400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6529429440 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3092370278400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1165548686490 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27384818947500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31660201461180 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.707256 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45556862760500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1580966400000 # Time in different power states +system.physmem_1.actEnergy 3572561160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1949314125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3658902000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5764426560 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1152447208560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27372420142500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31629582057465 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.622864 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45536350688414 # Time in different power states +system.physmem_1.memoryStateTime::REF 1579636760000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 207555509500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 189577142836 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -355,15 +351,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1670 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 145356452 # Number of BP lookups -system.cpu0.branchPred.condPredicted 96435082 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 7088203 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 101789401 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 67765064 # Number of BTB hits +system.cpu0.branchPred.lookups 136259129 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90543195 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 6799058 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 95853282 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 62504832 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.573792 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 20004195 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 205158 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 65.208860 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 18504887 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 186011 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -394,89 +390,85 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 580611 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 580611 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 13679 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 93135 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 259311 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 321300 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 1669.368192 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 10492.971715 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-32767 317448 98.80% 98.80% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-65535 2037 0.63% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-98303 845 0.26% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-131071 576 0.18% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-163839 232 0.07% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-196607 45 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-229375 28 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::229376-262143 26 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-294911 42 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::294912-327679 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-360447 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::425984-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::458752-491519 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 321300 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 293805 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 15781.864128 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 13334.413537 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 14277.098383 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 291279 99.14% 99.14% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1809 0.62% 99.76% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 367 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 189 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 105 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 21 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::524288-589823 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 293805 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 521650035508 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.610400 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.526555 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 520697119508 99.82% 99.82% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 543124000 0.10% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 195186500 0.04% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 85165500 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 70245500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 34070500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 11934000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 12740000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 448500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 521650035508 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 93135 87.19% 87.19% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 13679 12.81% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 106814 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 580611 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 520196 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 520196 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10690 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81668 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 225929 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 294267 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 1575.669375 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 10064.565371 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 292845 99.52% 99.52% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1067 0.36% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 263 0.09% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 47 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 294267 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 252771 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 15945.045037 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 13637.155107 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 11018.196964 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 241135 95.40% 95.40% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10520 4.16% 99.56% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-98303 548 0.22% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-131071 339 0.13% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::163840-196607 47 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-229375 65 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::360448-393215 6 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 252771 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 499007353192 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.597965 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.527283 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 498187132192 99.84% 99.84% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 450171500 0.09% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 169118500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 80846500 0.02% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 62229500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 34680000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 10096500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 12800000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 278500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 499007353192 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 81668 88.43% 88.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 10690 11.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 92358 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 520196 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 580611 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106814 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 520196 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92358 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106814 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 687425 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92358 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 612554 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 105404836 # DTB read hits -system.cpu0.dtb.read_misses 420652 # DTB read misses -system.cpu0.dtb.write_hits 86890500 # DTB write hits -system.cpu0.dtb.write_misses 159959 # DTB write misses +system.cpu0.dtb.read_hits 98496070 # DTB read hits +system.cpu0.dtb.read_misses 369414 # DTB read misses +system.cpu0.dtb.write_hits 81551465 # DTB write hits +system.cpu0.dtb.write_misses 150782 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 40944 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 605 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 8089 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 36102 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 400 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 5365 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 40127 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 105825488 # DTB read accesses -system.cpu0.dtb.write_accesses 87050459 # DTB write accesses +system.cpu0.dtb.perms_faults 40284 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 98865484 # DTB read accesses +system.cpu0.dtb.write_accesses 81702247 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 192295336 # DTB hits -system.cpu0.dtb.misses 580611 # DTB misses -system.cpu0.dtb.accesses 192875947 # DTB accesses +system.cpu0.dtb.hits 180047535 # DTB hits +system.cpu0.dtb.misses 520196 # DTB misses +system.cpu0.dtb.accesses 180567731 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -506,588 +498,584 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 84622 # Table walker walks requested -system.cpu0.itb.walker.walksLong 84622 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 994 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 61729 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 9515 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 75107 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1146.297948 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8819.384812 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 74551 99.26% 99.26% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 182 0.24% 99.50% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 223 0.30% 99.80% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 112 0.15% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 5 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 75107 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 72238 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 20242.257302 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17307.169845 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 18587.015651 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 70635 97.78% 97.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1318 1.82% 99.61% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 148 0.20% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 80 0.11% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 29 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 81590 # Table walker walks requested +system.cpu0.itb.walker.walksLong 81590 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 901 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59909 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 9188 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 72402 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 845.170023 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 6470.995618 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 72024 99.48% 99.48% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 242 0.33% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 56 0.08% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 61 0.08% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 72402 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 69998 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 20035.793294 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17827.568317 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 13688.582598 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-65535 69301 99.00% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-131071 578 0.83% 99.83% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-196607 67 0.10% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-262143 29 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 72238 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 405678068016 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.851697 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.355553 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 60184359568 14.84% 14.84% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 345473805948 85.16% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 18871000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 1025500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 6000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 405678068016 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 61729 98.42% 98.42% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 994 1.58% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 62723 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 69998 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 370135740312 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.825869 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.379347 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 64468447528 17.42% 17.42% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 305652352784 82.58% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 13699000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 1205500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 370135740312 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 59909 98.52% 98.52% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 901 1.48% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 60810 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84622 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84622 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81590 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81590 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 62723 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 62723 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 147345 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 229226252 # ITB inst hits -system.cpu0.itb.inst_misses 84622 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60810 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60810 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 142400 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 213929001 # ITB inst hits +system.cpu0.itb.inst_misses 81590 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 29308 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 25953 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 225641 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 203878 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 229310874 # ITB inst accesses -system.cpu0.itb.hits 229226252 # DTB hits -system.cpu0.itb.misses 84622 # DTB misses -system.cpu0.itb.accesses 229310874 # DTB accesses -system.cpu0.numCycles 787784387 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 214010591 # ITB inst accesses +system.cpu0.itb.hits 213929001 # DTB hits +system.cpu0.itb.misses 81590 # DTB misses +system.cpu0.itb.accesses 214010591 # DTB accesses +system.cpu0.numCycles 728554790 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 93175923 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 642526185 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 145356452 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 87769259 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 654798115 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 15283958 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 1702071 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 255624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 6308926 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 745987 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 671334 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 229000663 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 1782311 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 27660 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 765299959 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.983676 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.220176 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 88185009 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 601844339 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 136259129 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 81009719 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 601618645 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 14617520 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 1590376 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 274448 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 5655980 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 730298 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 721373 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 213725526 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 1720356 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 27419 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 706084889 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.998504 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.224315 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 404626902 52.87% 52.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 139960190 18.29% 71.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 49291261 6.44% 77.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 171421606 22.40% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 368651970 52.21% 52.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 130906496 18.54% 70.75% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 45457211 6.44% 77.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 161069212 22.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 765299959 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.184513 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.815612 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 110781464 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 368356745 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 241543971 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 39160465 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5457314 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 20998766 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 2230758 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 666506782 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 24554495 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5457314 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 147799214 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 53385858 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 247347968 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 243020975 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 68288630 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 648373688 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 6354822 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 9340488 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 358878 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 691420 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 31770877 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 13042 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 618836498 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1000163983 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 765756832 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 980941 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 557557100 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 61279388 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 16104693 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13959035 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 79116837 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 106280749 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 90455195 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 9698755 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 8363084 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 625354037 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 16149817 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 628774014 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 2896491 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 54006760 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 37569824 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 287316 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 765299959 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.821605 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.068919 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 706084889 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.187027 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.826080 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 103877352 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 333585554 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 228251571 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 35190646 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5179766 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19720762 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 2170804 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 623516514 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 23718954 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5179766 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 138234059 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 46790455 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 227164838 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 228535971 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 60179800 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 606373965 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 6065859 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 8641063 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 231610 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 454065 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 27284745 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 11061 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 577786095 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 931076470 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 716156173 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 752358 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 519674265 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 58111818 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 14452887 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 12546195 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 71496186 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 99205558 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 84922074 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 8773729 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 7651066 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 585335843 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 14506928 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 587846614 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 2739409 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 51306825 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 35502721 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 263475 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 706084889 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.832544 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.074450 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 423230722 55.30% 55.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 141522259 18.49% 73.79% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 122647115 16.03% 89.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 69647275 9.10% 98.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 8247243 1.08% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 5342 0.00% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 3 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 387752647 54.92% 54.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 129908491 18.40% 73.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 115071565 16.30% 89.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 65618038 9.29% 98.90% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 7729861 1.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 4287 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 765299959 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 706084889 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 65414267 45.68% 45.68% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 59912 0.04% 45.72% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 17829 0.01% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 19 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.73% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 37349884 26.08% 71.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 40363750 28.19% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 62081849 46.00% 46.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 53806 0.04% 46.04% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 26012 0.02% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 10 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 46.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 34882864 25.85% 71.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 37902238 28.09% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 430163495 68.41% 68.41% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1578221 0.25% 68.66% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 81407 0.01% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 125 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.68% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 78656 0.01% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 108646479 17.28% 85.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 88225631 14.03% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 401971331 68.38% 68.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1424969 0.24% 68.62% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 76351 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 44028 0.01% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 101506921 17.27% 85.91% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82822965 14.09% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 628774014 # Type of FU issued -system.cpu0.iq.rate 0.798155 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 143205661 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.227754 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 2167577171 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 695106277 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 611404783 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1372966 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 554126 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 508083 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 771129089 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 850586 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 2930031 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 587846614 # Type of FU issued +system.cpu0.iq.rate 0.806867 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 134946779 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.229561 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 2018256641 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 650811943 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 571438682 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 1207660 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 476069 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 443638 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 722040340 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 753051 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 2688850 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 13213228 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 17078 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 150900 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 6091069 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 12347690 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 15246 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 139538 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 5796061 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2819130 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 4221569 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2638151 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 4049170 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5457314 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 7826815 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 3783393 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 641629807 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 5179766 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 6081153 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 2925805 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 599957845 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 106280749 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 90455195 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13677015 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 59030 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3651240 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 150900 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2214888 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 3025224 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5240112 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 620548589 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 105398618 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 7653008 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 99205558 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 84922074 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 12284210 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 51884 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2819346 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 139538 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2067264 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2909526 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 4976790 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 580052597 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 98485742 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 7283117 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 125953 # number of nop insts executed -system.cpu0.iew.exec_refs 192287971 # number of memory reference insts executed -system.cpu0.iew.exec_branches 117275797 # Number of branches executed -system.cpu0.iew.exec_stores 86889353 # Number of stores executed -system.cpu0.iew.exec_rate 0.787714 # Inst execution rate -system.cpu0.iew.wb_sent 612710943 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 611912866 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 297952907 # num instructions producing a value -system.cpu0.iew.wb_consumers 488842231 # num instructions consuming a value +system.cpu0.iew.exec_nop 115074 # number of nop insts executed +system.cpu0.iew.exec_refs 180036231 # number of memory reference insts executed +system.cpu0.iew.exec_branches 109604684 # Number of branches executed +system.cpu0.iew.exec_stores 81550489 # Number of stores executed +system.cpu0.iew.exec_rate 0.796169 # Inst execution rate +system.cpu0.iew.wb_sent 572646335 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 571882320 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 278067639 # num instructions producing a value +system.cpu0.iew.wb_consumers 456095391 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.776752 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.609507 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.784954 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.609670 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 50177444 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 15862501 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4903538 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 755787028 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.772749 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.571704 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 47584416 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 14243453 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4670064 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 697066716 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.782257 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.580851 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 501065306 66.30% 66.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 130810768 17.31% 83.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 56911365 7.53% 91.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 19253126 2.55% 93.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 13929285 1.84% 95.53% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 9339201 1.24% 96.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6281388 0.83% 97.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 4033068 0.53% 98.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 14163521 1.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 460295975 66.03% 66.03% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 120461861 17.28% 83.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 53495228 7.67% 90.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 18161397 2.61% 93.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 13064824 1.87% 95.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 8746806 1.25% 96.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 5864289 0.84% 97.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3641188 0.52% 98.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 13335148 1.91% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 755787028 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 497564314 # Number of instructions committed -system.cpu0.commit.committedOps 584033993 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 697066716 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 464477894 # Number of instructions committed +system.cpu0.commit.committedOps 545285068 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 177431645 # Number of memory references committed -system.cpu0.commit.loads 93067519 # Number of loads committed -system.cpu0.commit.membars 3925399 # Number of memory barriers committed -system.cpu0.commit.branches 111370146 # Number of branches committed -system.cpu0.commit.fp_insts 496516 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 535821487 # Number of committed integer instructions. -system.cpu0.commit.function_calls 14891305 # Number of function calls committed. +system.cpu0.commit.refs 165983876 # Number of memory references committed +system.cpu0.commit.loads 86857868 # Number of loads committed +system.cpu0.commit.membars 3594521 # Number of memory barriers committed +system.cpu0.commit.branches 103961213 # Number of branches committed +system.cpu0.commit.fp_insts 434735 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 500421802 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13758946 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 405157799 69.37% 69.37% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1311833 0.22% 69.60% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 63039 0.01% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.61% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 69677 0.01% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.62% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 93067519 15.94% 85.55% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 84364126 14.45% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 378032624 69.33% 69.33% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1169798 0.21% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 60419 0.01% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 38309 0.01% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 86857868 15.93% 85.49% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 79126008 14.51% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 584033993 # Class of committed instruction -system.cpu0.commit.bw_lim_events 14163521 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 545285068 # Class of committed instruction +system.cpu0.commit.bw_lim_events 13335148 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1371348086 # The number of ROB reads -system.cpu0.rob.rob_writes 1277898548 # The number of ROB writes -system.cpu0.timesIdled 1050969 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 22484428 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 93902986117 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 497564314 # Number of Instructions Simulated -system.cpu0.committedOps 584033993 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.583282 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.583282 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.631600 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.631600 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 732616408 # number of integer regfile reads -system.cpu0.int_regfile_writes 435784003 # number of integer regfile writes -system.cpu0.fp_regfile_reads 812591 # number of floating regfile reads -system.cpu0.fp_regfile_writes 450624 # number of floating regfile writes -system.cpu0.cc_regfile_reads 135724425 # number of cc regfile reads -system.cpu0.cc_regfile_writes 136350840 # number of cc regfile writes -system.cpu0.misc_regfile_reads 3048491910 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15942846 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 6332598 # number of replacements -system.cpu0.dcache.tags.tagsinuse 484.098749 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 164710199 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6333110 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.007791 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1750140500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.098749 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.945505 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.945505 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 275 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 368140426 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 368140426 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 86285504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 86285504 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73342402 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73342402 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 227851 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 227851 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 264480 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 264480 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1878345 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1878345 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1911240 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1911240 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 159627906 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 159627906 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 159855757 # number of overall hits -system.cpu0.dcache.overall_hits::total 159855757 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 7088092 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 7088092 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 7774496 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 7774496 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 746133 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 746133 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 842824 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 842824 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 281020 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 281020 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 209055 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 209055 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 14862588 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 14862588 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 15608721 # number of overall misses -system.cpu0.dcache.overall_misses::total 15608721 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 105859717159 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 105859717159 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 137077029934 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 137077029934 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 45622327717 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 45622327717 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4025426932 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4025426932 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4395434712 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4395434712 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3232000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3232000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 242936747093 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 242936747093 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 242936747093 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 242936747093 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 93373596 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 93373596 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81116898 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81116898 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 973984 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 973984 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1107304 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1107304 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2159365 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2159365 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2120295 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2120295 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 174490494 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 174490494 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 175464478 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 175464478 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.075911 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.075911 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.095843 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.095843 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766063 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766063 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.761150 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.761150 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.130140 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.130140 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098597 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098597 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.085177 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.085177 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088957 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088957 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14934.867826 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14934.867826 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17631.629103 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 17631.629103 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 54130.313941 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 54130.313941 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14324.343221 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14324.343221 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21025.255134 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21025.255134 # average StoreCondReq miss latency +system.cpu0.rob.rob_reads 1272468420 # The number of ROB reads +system.cpu0.rob.rob_writes 1194722923 # The number of ROB writes +system.cpu0.timesIdled 998377 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 22469901 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 93882577668 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 464477894 # Number of Instructions Simulated +system.cpu0.committedOps 545285068 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.568546 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.568546 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.637533 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.637533 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 684802624 # number of integer regfile reads +system.cpu0.int_regfile_writes 407591789 # number of integer regfile writes +system.cpu0.fp_regfile_reads 737398 # number of floating regfile reads +system.cpu0.fp_regfile_writes 323628 # number of floating regfile writes +system.cpu0.cc_regfile_reads 126081114 # number of cc regfile reads +system.cpu0.cc_regfile_writes 126833812 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2842254449 # number of misc regfile reads +system.cpu0.misc_regfile_writes 14406777 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 5807270 # number of replacements +system.cpu0.dcache.tags.tagsinuse 503.185727 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 154700200 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5807781 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 26.636714 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1931738500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 503.185727 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.982785 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.982785 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 291 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 48 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 344453115 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 344453115 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80805507 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 80805507 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69071717 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69071717 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 209524 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 209524 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 255543 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 255543 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1772811 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1772811 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1798532 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1798532 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 149877224 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149877224 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150086748 # number of overall hits +system.cpu0.dcache.overall_hits::total 150086748 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6456855 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6456855 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6956516 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 6956516 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 664764 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 664764 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 829133 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 829133 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 256042 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 256042 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 194087 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 194087 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13413371 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13413371 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 14078135 # number of overall misses +system.cpu0.dcache.overall_misses::total 14078135 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 92345367100 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 92345367100 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 122121346040 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 122121346040 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 37689944158 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 37689944158 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3513328512 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3513328512 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4123602814 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 4123602814 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 5259500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 5259500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 214466713140 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 214466713140 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 214466713140 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 214466713140 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87262362 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 87262362 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76028233 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76028233 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 874288 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 874288 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1084676 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1084676 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2028853 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2028853 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1992619 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1992619 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 163290595 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 163290595 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164164883 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164164883 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.073994 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.073994 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.091499 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.091499 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.760349 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760349 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.764406 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.764406 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.126200 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.126200 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.097403 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.097403 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.082144 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.082144 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085756 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.085756 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14301.911240 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14301.911240 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17554.957976 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 17554.957976 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 45457.054728 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 45457.054728 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13721.688286 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13721.688286 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21246.156693 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21246.156693 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16345.521190 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 16345.521190 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15564.167435 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15564.167435 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 13488103 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 19786702 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 752105 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 757651 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.933803 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 26.115853 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15989.024171 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15989.024171 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15234.028736 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15234.028736 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10974284 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 17020056 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 751732 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 670987 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.598665 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 25.365702 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4276528 # number of writebacks -system.cpu0.dcache.writebacks::total 4276528 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3664529 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 3664529 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6233308 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 6233308 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4741 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4741 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 141328 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 141328 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9897837 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 9897837 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9897837 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 9897837 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3423563 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3423563 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1541188 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1541188 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 739665 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 739665 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 838083 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 838083 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 139692 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 139692 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 209050 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 209050 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4964751 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4964751 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5704416 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5704416 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 44975748199 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 44975748199 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 28501279892 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 28501279892 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 16804666332 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 16804666332 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 43773018566 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 43773018566 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1737566757 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1737566757 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3967184288 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3967184288 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3082000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3082000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 73477028091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 73477028091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 90281694423 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 90281694423 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5575976491 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5575976491 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5325987989 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5325987989 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10901964480 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10901964480 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036665 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036665 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019000 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019000 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759422 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759422 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.756868 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.756868 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064691 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064691 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098595 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098595 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028453 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028453 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.032510 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.032510 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13137.117149 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13137.117149 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18493.058531 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18493.058531 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22719.293642 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22719.293642 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 52229.932556 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 52229.932556 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12438.555945 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12438.555945 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 18977.203004 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 18977.203004 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3967066 # number of writebacks +system.cpu0.dcache.writebacks::total 3967066 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3312893 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 3312893 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5560546 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 5560546 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 4546 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4546 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 132684 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 132684 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 8873439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 8873439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 8873439 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 8873439 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3143962 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 3143962 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1395970 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1395970 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 657971 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 657971 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 824587 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 824587 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 123358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123358 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 194072 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 194072 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4539932 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4539932 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 5197903 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 5197903 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 41375173894 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41375173894 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26017592924 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 26017592924 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14556234769 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14556234769 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36285250520 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 36285250520 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1556312588 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1556312588 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3823478686 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3823478686 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 5096000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 5096000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67392766818 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 67392766818 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 81949001587 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 81949001587 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5745168998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5745168998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5504162016 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5504162016 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11249331014 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11249331014 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036029 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036029 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018361 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018361 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.752579 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.752579 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.760215 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.760215 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060802 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.060802 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.097395 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.097395 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027803 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027803 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031663 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031663 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13160.201648 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13160.201648 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18637.644737 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18637.644737 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22122.912361 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22122.912361 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 44004.150587 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 44004.150587 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12616.227468 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12616.227468 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19701.341183 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19701.341183 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14799.740831 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14799.740831 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15826.632283 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15826.632283 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14844.444106 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14844.444106 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15765.781237 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15765.781237 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1095,461 +1083,462 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 6368542 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.961816 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 222275153 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 6369054 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.899241 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 14184385750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.961816 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999925 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999925 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 6071622 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.960367 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 207290998 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 6072134 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.138080 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 14063099250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960367 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999923 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999923 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 329 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 92 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 464315009 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 464315009 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 222275153 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 222275153 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 222275153 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 222275153 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 222275153 # number of overall hits -system.cpu0.icache.overall_hits::total 222275153 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6697664 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 6697664 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6697664 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 6697664 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6697664 # number of overall misses -system.cpu0.icache.overall_misses::total 6697664 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 70928372732 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 70928372732 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 70928372732 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 70928372732 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 70928372732 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 70928372732 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 228972817 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 228972817 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 228972817 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 228972817 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 228972817 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 228972817 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029251 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.029251 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029251 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.029251 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029251 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.029251 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10590.016569 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10590.016569 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10590.016569 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10590.016569 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10590.016569 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 8781241 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 821 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 708037 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.402235 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 74.636364 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 433467798 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 433467798 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 207290998 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 207290998 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 207290998 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 207290998 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 207290998 # number of overall hits +system.cpu0.icache.overall_hits::total 207290998 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6406823 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 6406823 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6406823 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 6406823 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6406823 # number of overall misses +system.cpu0.icache.overall_misses::total 6406823 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 67980327142 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 67980327142 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 67980327142 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 67980327142 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 67980327142 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 67980327142 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 213697821 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 213697821 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 213697821 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 213697821 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 213697821 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 213697821 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029981 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.029981 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029981 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.029981 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029981 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.029981 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10610.614206 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10610.614206 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10610.614206 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10610.614206 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10610.614206 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 9344678 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 782 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 720412 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.971297 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 78.200000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 328289 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 328289 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 328289 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 328289 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 328289 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 328289 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6369375 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 6369375 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6369375 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 6369375 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6369375 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 6369375 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 57966761800 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 57966761800 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 57966761800 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 57966761800 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 57966761800 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 57966761800 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1699560248 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1699560248 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1699560248 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027817 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.027817 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027817 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.027817 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9100.855547 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9100.855547 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9100.855547 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 334667 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 334667 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 334667 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 334667 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 334667 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 334667 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6072156 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 6072156 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 6072156 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 6072156 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 6072156 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 6072156 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 58462486516 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 58462486516 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 58462486516 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 58462486516 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 58462486516 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 58462486516 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1881164498 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1881164498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1881164498 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028415 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028415 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028415 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028415 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9627.961883 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9627.961883 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9627.961883 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 8232125 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 8569505 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 292099 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7322641 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7635134 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 270741 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 1116447 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2928300 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16202.554411 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 13089790 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2944355 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.445724 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2067342500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7528.605833 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 71.466332 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 91.040507 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3487.680197 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 4098.714387 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 925.047154 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.459510 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004362 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005557 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.212871 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.250166 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.056460 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988925 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1513 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 121 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14421 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 66 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 709 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 196 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 537 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 13 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 70 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 818 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 6042 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2879 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4513 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.092346 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.007385 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.880188 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 298616625 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 298616625 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 582155 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 182687 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5666433 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 3184946 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 9616221 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4276521 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4276521 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 198743 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 198743 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 114761 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 114761 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 36815 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 36815 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 991246 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 991246 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 582155 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 182687 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 5666433 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 4176192 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 10607467 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 582155 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 182687 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 5666433 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 4176192 # number of overall hits -system.cpu0.l2cache.overall_hits::total 10607467 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 12607 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9261 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 702626 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1115482 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1839976 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 4 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 4 # number of Writeback misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 637762 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 637762 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 138114 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 138114 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 172230 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 172230 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 309290 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 309290 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 12607 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9261 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 702626 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1424772 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2149266 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 12607 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9261 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 702626 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1424772 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2149266 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 468497682 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 383886915 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 20661944862 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 39743352793 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 61257682252 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 212101792 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 212101792 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2828322980 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2828322980 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3448129857 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3448129857 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 3007000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 3007000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 16311576734 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 16311576734 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 468497682 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 383886915 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 20661944862 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 56054929527 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 77569258986 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 468497682 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 383886915 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 20661944862 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 56054929527 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 77569258986 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 594762 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 191948 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6369059 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4300428 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 11456197 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4276525 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4276525 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 836505 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 836505 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 252875 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 252875 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 209045 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 209045 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1300536 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1300536 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 594762 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 191948 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 6369059 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5600964 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 12756733 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 594762 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 191948 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 6369059 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5600964 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 12756733 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.021197 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.048247 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.110319 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.259389 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.160610 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000001 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000001 # miss rate for Writeback accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.762413 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.762413 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.546175 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.546175 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.823890 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.823890 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.prefetcher.pfSpanPage 993362 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2579397 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16158.447303 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 12271567 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2594941 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.729035 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 2266482500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 5660.592746 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 40.404376 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 30.912164 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5710.050306 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3705.001610 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1011.486101 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.345495 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002466 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001887 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.348514 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.226135 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.061736 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.986233 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1380 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 93 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14071 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 72 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 414 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 620 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 63 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 688 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5473 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2257 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 5451 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.084229 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005676 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.858826 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 277998240 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 277998240 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 501930 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 167379 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 5436143 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2922103 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 9027555 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3967054 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3967054 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 228126 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 228126 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 108640 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 108640 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 33975 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 33975 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 890755 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 890755 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 501930 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 167379 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 5436143 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3812858 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 9918310 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 501930 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 167379 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 5436143 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3812858 # number of overall hits +system.cpu0.l2cache.overall_hits::total 9918310 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10652 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8152 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 635995 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 1000489 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1655288 # number of ReadReq misses +system.cpu0.l2cache.Writeback_misses::writebacks 10 # number of Writeback misses +system.cpu0.l2cache.Writeback_misses::total 10 # number of Writeback misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 594866 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 594866 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 133117 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 133117 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 160078 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 160078 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 19 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 19 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 274591 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 274591 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10652 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8152 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 635995 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1275080 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1929879 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10652 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8152 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 635995 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1275080 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1929879 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 338313980 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 267505335 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 19973277607 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 34240699717 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 54819796639 # number of ReadReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 238254135 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 238254135 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2940744545 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2940744545 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3318665043 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3318665043 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 4985998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 4985998 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 14040093164 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 14040093164 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 338313980 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 267505335 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 19973277607 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 48280792881 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 68859889803 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 338313980 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 267505335 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 19973277607 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 48280792881 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 68859889803 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 512582 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 175531 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 6072138 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3922592 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 10682843 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 3967064 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 3967064 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 822992 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 822992 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 241757 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 241757 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 194053 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 194053 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 19 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 19 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1165346 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1165346 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 512582 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 175531 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 6072138 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5087938 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11848189 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 512582 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 175531 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 6072138 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5087938 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11848189 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.046442 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.104740 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.255058 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.154948 # miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000003 # miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_miss_rate::total 0.000003 # miss rate for Writeback accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.722809 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.722809 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.550623 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.550623 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.824919 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.824919 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.237817 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.237817 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.021197 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.048247 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.110319 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.254380 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.168481 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.021197 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.048247 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.110319 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.254380 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.168481 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37161.710320 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41451.993845 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29406.746779 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 35628.860701 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33292.652867 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 332.572013 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 332.572013 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20478.177303 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20478.177303 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20020.495018 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20020.495018 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 601400 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 601400 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 52738.778279 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 52738.778279 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37161.710320 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41451.993845 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29406.746779 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 39343.087545 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 36091.046425 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37161.710320 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41451.993845 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29406.746779 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 39343.087545 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 36091.046425 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 272 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.235630 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.235630 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.046442 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.104740 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.250608 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.162884 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.020781 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.046442 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.104740 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.250608 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.162884 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 32814.687807 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 31404.771432 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 34223.964199 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 33117.981064 # average ReadReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 400.517318 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 400.517318 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22091.427429 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22091.427429 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20731.549888 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20731.549888 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 262420.947368 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 262420.947368 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 51130.929870 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 51130.929870 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 32814.687807 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 31404.771432 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37864.912696 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 35680.936371 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 31760.606459 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 32814.687807 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 31404.771432 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37864.912696 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 35680.936371 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 38.857143 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1592666 # number of writebacks -system.cpu0.l2cache.writebacks::total 1592666 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 3 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 178 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 5842 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 6026 # number of ReadReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 65 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 65 # number of WriteInvalidateReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 39394 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 39394 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 3 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 178 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 45236 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 45420 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 3 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 178 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 45236 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 45420 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 12604 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9083 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 702623 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 1109640 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1833950 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 4 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 4 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 823501 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 823501 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 637697 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 637697 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 138114 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 138114 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 172230 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 172230 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 269896 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 269896 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 12604 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9083 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 702623 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1379536 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 2103846 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 12604 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9083 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 702623 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1379536 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 823501 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2927347 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 379527210 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 312895441 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 15722901634 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 31613467375 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 48028791660 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 55041075389 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 55041075389 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 36305734974 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 36305734974 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2408365451 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2408365451 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2333282169 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2333282169 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2482000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2482000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 11186143543 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 11186143543 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 379527210 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 312895441 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15722901634 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 42799610918 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 59214935203 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 379527210 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 312895441 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15722901634 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 42799610918 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 55041075389 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 114256010592 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5322353508 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6841527758 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5082599974 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5082599974 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1519174250 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10404953482 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11924127732 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.258030 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160084 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.writebacks::writebacks 1389796 # number of writebacks +system.cpu0.l2cache.writebacks::total 1389796 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 4 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 142 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 4324 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 4477 # number of ReadReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::cpu0.data 6 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.WriteInvalidateReq_mshr_hits::total 6 # number of WriteInvalidateReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 17304 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 17304 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 4 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 142 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 21628 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 21781 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 4 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 142 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 21628 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 21781 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10648 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8010 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 635988 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 996165 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 1650811 # number of ReadReq MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::writebacks 10 # number of Writeback MSHR misses +system.cpu0.l2cache.Writeback_mshr_misses::total 10 # number of Writeback MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 695022 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 695022 # number of HardPFReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 594860 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 594860 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 133117 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 133117 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 160078 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 160078 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 19 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 19 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 257287 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 257287 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10648 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8010 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 635988 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1253452 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1908098 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10648 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8010 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 635988 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1253452 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 695022 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2603120 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 209265519 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 15816568891 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 27389377929 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 43683913367 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34637549956 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 34637549956 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 28746452436 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 28746452436 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2662823288 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2662823288 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2368378420 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2368378420 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 4277498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 4277498 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10397244749 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10397244749 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 209265519 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 15816568891 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 37786622678 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 54081158116 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 268701028 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 209265519 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 15816568891 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 37786622678 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34637549956 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 88718708072 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5486110502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7197622502 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5256416460 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5256416460 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1711512000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10742526962 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12454038962 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253956 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.154529 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000003 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000003 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762335 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.762335 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.546175 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.546175 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823890 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823890 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.722802 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.722802 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.550623 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.550623 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.824919 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.824919 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.207527 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.207527 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.164920 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021192 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.047320 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.110318 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246303 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.220782 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.220782 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.161046 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.020773 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.045633 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.104739 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.246358 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229475 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 28489.841187 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26188.713793 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 66837.897451 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 56932.579225 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 56932.579225 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17437.518651 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17437.518651 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13547.478192 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13547.478192 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 496400 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 496400 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41446.125704 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41446.125704 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28146.040729 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30111.647890 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34448.468678 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22377.436597 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31024.642284 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 66837.897451 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 39030.566104 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.219706 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27494.820566 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26462.092491 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49836.623813 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48324.735965 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48324.735965 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20003.630551 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20003.630551 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14795.152488 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14795.152488 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 225131.473684 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 225131.473684 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40411.076926 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40411.076926 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28342.966722 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25234.882419 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 26125.532959 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24869.288243 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30146.046820 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49836.623813 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34081.682009 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1559,69 +1548,67 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 13921371 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 11750633 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31686 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 31686 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4276525 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1274288 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFResp 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1162561 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 836505 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 509905 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 381643 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 535354 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 87 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1437620 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1309284 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12781022 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 18390339 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414542 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1294088 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 32879991 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 407960480 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 693234728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1535584 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4758096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1107488888 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4767578 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 22911203 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.193957 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.395396 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 13109671 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10998966 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32265 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32265 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3967064 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 987402 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1170476 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 822992 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 487373 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355558 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 509064 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1297704 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1174184 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12186882 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16978089 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390292 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1142423 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30697686 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 388957536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 639747662 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404248 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4100656 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1034210102 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 4435865 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 21321710 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.191876 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.393776 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 18467409 80.60% 80.60% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 4443794 19.40% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 17230589 80.81% 80.81% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 4091121 19.19% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 22911203 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 14408211332 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 21321710 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 13464993223 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 208870495 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 208995484 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 9596174213 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 9149850308 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 9165770534 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 8376078494 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 223497560 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 215375806 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 700918244 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 630757127 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 124370032 # Number of BP lookups -system.cpu1.branchPred.condPredicted 83075187 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 6189003 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 87824878 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 56905034 # Number of BTB hits +system.cpu1.branchPred.lookups 124182653 # Number of BP lookups +system.cpu1.branchPred.condPredicted 82299269 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 6251064 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 87493813 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 57426824 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 64.793752 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 16687776 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 168367 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 65.635297 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17076023 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 176220 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1651,90 +1638,81 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 538943 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 538943 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11373 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 87574 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 237839 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 301104 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 1852.353340 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 11107.804354 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 297190 98.70% 98.70% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 2030 0.67% 99.37% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 795 0.26% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 637 0.21% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 257 0.09% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 66 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 39 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 29 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 48 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-425983 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 301104 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 268131 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 15772.437909 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 12981.371112 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15992.673962 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-65535 265367 98.97% 98.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1941 0.72% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-196607 396 0.15% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-262143 232 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-327679 106 0.04% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-393215 37 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-458751 35 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-524287 12 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 534049 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 534049 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11595 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85531 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 242787 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 291262 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2048.229773 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 11850.953616 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 289126 99.27% 99.27% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1672 0.57% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 329 0.11% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 62 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 291262 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 270383 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 17183.802917 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 14328.415565 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16454.576356 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 267229 98.83% 98.83% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2235 0.83% 99.66% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 352 0.13% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 368 0.14% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 149 0.06% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 268131 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 435751861088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.614829 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.532518 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 434859464588 99.80% 99.80% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 474800000 0.11% 99.90% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 202701000 0.05% 99.95% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 89682000 0.02% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 62866500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 34103000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 13310500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 14713000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 214000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::18-19 6500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 435751861088 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 87574 88.51% 88.51% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 11373 11.49% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 98947 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 538943 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 270383 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 438879688048 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.596096 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.540539 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 437883178548 99.77% 99.77% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 543837500 0.12% 99.90% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 218551000 0.05% 99.95% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 91365500 0.02% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 75836500 0.02% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 38561500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 12555000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 15271000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 530000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 438879688048 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 85532 88.06% 88.06% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 11595 11.94% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 97127 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 534049 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 538943 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 98947 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 534049 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97127 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 98947 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 637890 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97127 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 631176 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91392867 # DTB read hits -system.cpu1.dtb.read_misses 373745 # DTB read misses -system.cpu1.dtb.write_hits 75805429 # DTB write hits -system.cpu1.dtb.write_misses 165198 # DTB write misses +system.cpu1.dtb.read_hits 91849877 # DTB read hits +system.cpu1.dtb.read_misses 382442 # DTB read misses +system.cpu1.dtb.write_hits 75119650 # DTB write hits +system.cpu1.dtb.write_misses 151607 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 37451 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 309 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 5879 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 39274 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 401 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 5573 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 40297 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91766612 # DTB read accesses -system.cpu1.dtb.write_accesses 75970627 # DTB write accesses +system.cpu1.dtb.perms_faults 36948 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 92232319 # DTB read accesses +system.cpu1.dtb.write_accesses 75271257 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 167198296 # DTB hits -system.cpu1.dtb.misses 538943 # DTB misses -system.cpu1.dtb.accesses 167737239 # DTB accesses +system.cpu1.dtb.hits 166969527 # DTB hits +system.cpu1.dtb.misses 534049 # DTB misses +system.cpu1.dtb.accesses 167503576 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1764,587 +1742,589 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 85244 # Table walker walks requested -system.cpu1.itb.walker.walksLong 85244 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 675 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61262 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 9941 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 75303 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1139.330438 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8399.837182 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 74771 99.29% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 180 0.24% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 193 0.26% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 128 0.17% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 12 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 6 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 75303 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71878 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 20268.763168 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 17115.147893 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 19721.935997 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 70231 97.71% 97.71% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1324 1.84% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 179 0.25% 99.80% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.09% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 46 0.06% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 14 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 85651 # Table walker walks requested +system.cpu1.itb.walker.walksLong 85651 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 898 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61483 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 9913 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 75738 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1212.145818 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8774.873802 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 75006 99.03% 99.03% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 365 0.48% 99.52% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 180 0.24% 99.75% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 161 0.21% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 75738 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 72294 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21947.554182 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 18825.235250 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 19960.579515 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-65535 70492 97.51% 97.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-131071 1482 2.05% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-196607 157 0.22% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-262143 99 0.14% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71878 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 397094361424 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.878531 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.326828 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 48253813024 12.15% 12.15% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 348822790900 87.84% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 16535000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 1219500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 3000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 397094361424 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61262 98.91% 98.91% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 675 1.09% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 61937 # Table walker page sizes translated +system.cpu1.itb.walker.walkCompletionTime::total 72294 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 404519897680 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.847972 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.359205 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 61519279012 15.21% 15.21% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 342981503668 84.79% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 17484500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 1520000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 101500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 404519897680 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 61483 98.56% 98.56% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 898 1.44% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 62381 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85244 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85244 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85651 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85651 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61937 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61937 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 147181 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 196146030 # ITB inst hits -system.cpu1.itb.inst_misses 85244 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62381 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62381 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 148032 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 196330607 # ITB inst hits +system.cpu1.itb.inst_misses 85651 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 45064 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1074 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 26780 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 28544 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 213163 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 219679 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 196231274 # ITB inst accesses -system.cpu1.itb.hits 196146030 # DTB hits -system.cpu1.itb.misses 85244 # DTB misses -system.cpu1.itb.accesses 196231274 # DTB accesses -system.cpu1.numCycles 664388878 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 196416258 # ITB inst accesses +system.cpu1.itb.hits 196330607 # DTB hits +system.cpu1.itb.misses 85651 # DTB misses +system.cpu1.itb.accesses 196416258 # DTB accesses +system.cpu1.numCycles 659201565 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 79880322 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 552169788 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 124370032 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 73592810 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 551328487 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13340182 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 1707326 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 246511 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 6080767 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 727313 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 602439 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 195911596 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 1586691 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 28723 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 647243256 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.003235 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.226187 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 81623724 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 551229784 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 124182653 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 74502847 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 545141022 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13475474 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 1814701 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 236397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 6195125 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 729177 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 658891 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 196089515 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 1603144 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 28612 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 643136774 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.007577 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.226676 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 336573756 52.00% 52.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 120960986 18.69% 70.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 40749741 6.30% 76.99% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 148958773 23.01% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 333162826 51.80% 51.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 120232758 18.69% 70.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 41446819 6.44% 76.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 148294371 23.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 647243256 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.187195 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.831094 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 96356177 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 306396299 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 204571849 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 35206357 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 4712574 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 17589142 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1996203 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 573391383 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 21361954 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 4712574 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 129172911 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 40460241 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 212107385 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 206565063 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 54225082 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 557977037 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 5352379 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 8193976 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 222351 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 303036 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 21276416 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 13923 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 530659712 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 862978619 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 659902858 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 766208 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 478267677 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 52392029 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15246817 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13453544 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 71065053 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 91863812 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 78915989 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 8629555 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 7664780 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 536633802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15513444 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 541699362 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 2485495 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 46695905 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 31776612 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 271399 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 647243256 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.836933 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.069144 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 643136774 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.188383 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.836208 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 97937463 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 300403958 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 205522733 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 34511986 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 4760634 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 17730932 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 2017504 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 571814983 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 21511068 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 4760634 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 130465176 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 39849524 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 206232237 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 207101717 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 54727486 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 556322152 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 5380569 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 8461915 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 304416 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 605845 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 22227660 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 11247 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 528347539 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 856455710 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 657084844 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 755426 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 475426080 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 52921453 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 14732861 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 12829203 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 69624573 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 92331469 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 78236769 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 8977003 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 7612209 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 535459998 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 14979383 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 539826932 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 2475624 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 46992661 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 32301398 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 273094 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 643136774 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.839366 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.069808 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 349912497 54.06% 54.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 127097301 19.64% 73.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 103346931 15.97% 89.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 59640858 9.21% 98.88% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 7242720 1.12% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 2949 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 347132433 53.97% 53.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 125915806 19.58% 73.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 103467009 16.09% 89.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 59513725 9.25% 98.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 7103072 1.10% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 4729 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 647243256 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 643136774 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 54464030 43.99% 43.99% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 55578 0.04% 44.03% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 15828 0.01% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 9 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.05% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 33234382 26.84% 70.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 36043585 29.11% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 53820631 43.79% 43.79% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 63940 0.05% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 7561 0.01% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.85% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 33515144 27.27% 71.12% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 35487446 28.88% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 369233279 68.16% 68.16% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1193564 0.22% 68.38% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 69127 0.01% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 2 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 1 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 25 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 46847 0.01% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94164053 17.38% 85.79% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 76992429 14.21% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 367420702 68.06% 68.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1281309 0.24% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 73255 0.01% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 2 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 83298 0.02% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.33% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 94677124 17.54% 85.87% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 76291227 14.13% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 541699362 # Type of FU issued -system.cpu1.iq.rate 0.815335 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 123813412 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.228565 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1855831634 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 598546046 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 526634223 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1109251 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 439129 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 408402 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 664822270 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 690492 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 2431611 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 539826932 # Type of FU issued +system.cpu1.iq.rate 0.818910 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 122894739 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227656 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1846883379 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 597058317 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 524462260 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1277620 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 514947 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 476158 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 661932910 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 788750 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 2478321 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 11396985 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 16347 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 143339 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 5491640 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 11570290 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 16551 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 142141 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 5437069 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 2526857 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 3486247 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 2465198 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 3688063 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 4712574 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 5829545 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 1427417 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 552265728 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 4760634 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6603988 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 1453249 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 550562460 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 91863812 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 78915989 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13236985 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 56254 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 1314129 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 143339 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 1858186 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2653609 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4511795 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 534690067 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 91388435 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 6481283 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 92331469 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 78236769 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12610859 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52882 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 1339609 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 142141 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 1900150 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2649580 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 4549730 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 532747017 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 91844367 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6553150 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 118482 # number of nop insts executed -system.cpu1.iew.exec_refs 167194328 # number of memory reference insts executed -system.cpu1.iew.exec_branches 100087893 # Number of branches executed -system.cpu1.iew.exec_stores 75805893 # Number of stores executed -system.cpu1.iew.exec_rate 0.804785 # Inst execution rate -system.cpu1.iew.wb_sent 527704335 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 527042625 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 254576573 # num instructions producing a value -system.cpu1.iew.wb_consumers 416898701 # num instructions consuming a value +system.cpu1.iew.exec_nop 123079 # number of nop insts executed +system.cpu1.iew.exec_refs 166962398 # number of memory reference insts executed +system.cpu1.iew.exec_branches 99765376 # Number of branches executed +system.cpu1.iew.exec_stores 75118031 # Number of stores executed +system.cpu1.iew.exec_rate 0.808170 # Inst execution rate +system.cpu1.iew.wb_sent 525632708 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 524938418 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 254712512 # num instructions producing a value +system.cpu1.iew.wb_consumers 416314102 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.793274 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.610644 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.796325 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.611828 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 43642021 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15242045 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4231486 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 638973832 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.786200 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.579868 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 43862550 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14706289 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4273961 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 634802902 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.788218 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.581621 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 417556945 65.35% 65.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 116379063 18.21% 83.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 48152991 7.54% 91.10% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 16068254 2.51% 93.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 11811974 1.85% 95.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 7886914 1.23% 96.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5403679 0.85% 97.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3345009 0.52% 98.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 12369003 1.94% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 414870625 65.35% 65.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 114759147 18.08% 83.43% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 48245889 7.60% 91.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 16373665 2.58% 93.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 11678245 1.84% 95.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 7925650 1.25% 96.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 5354812 0.84% 97.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3238197 0.51% 98.05% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 12356672 1.95% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 638973832 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 426124677 # Number of instructions committed -system.cpu1.commit.committedOps 502361434 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 634802902 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 424719097 # Number of instructions committed +system.cpu1.commit.committedOps 500362777 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 153891175 # Number of memory references committed -system.cpu1.commit.loads 80466826 # Number of loads committed -system.cpu1.commit.membars 3635433 # Number of memory barriers committed -system.cpu1.commit.branches 94895008 # Number of branches committed -system.cpu1.commit.fp_insts 399904 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 461321486 # Number of committed integer instructions. -system.cpu1.commit.function_calls 12405087 # Number of function calls committed. +system.cpu1.commit.refs 153560878 # Number of memory references committed +system.cpu1.commit.loads 80761178 # Number of loads committed +system.cpu1.commit.membars 3652883 # Number of memory barriers committed +system.cpu1.commit.branches 94624372 # Number of branches committed +system.cpu1.commit.fp_insts 463166 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 459868567 # Number of committed integer instructions. +system.cpu1.commit.function_calls 12685398 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 347396188 69.15% 69.15% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 977319 0.19% 69.35% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 55389 0.01% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.36% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 41321 0.01% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.37% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 80466826 16.02% 85.38% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 73424349 14.62% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 345616008 69.07% 69.07% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1054252 0.21% 69.28% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 58059 0.01% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.30% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 73580 0.01% 69.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 80761178 16.14% 85.45% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 72799700 14.55% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 502361434 # Class of committed instruction -system.cpu1.commit.bw_lim_events 12369003 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction +system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1168820475 # The number of ROB reads -system.cpu1.rob.rob_writes 1100237743 # The number of ROB writes -system.cpu1.timesIdled 913492 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 17145622 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 94026381638 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 426124677 # Number of Instructions Simulated -system.cpu1.committedOps 502361434 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.559142 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.559142 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.641378 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.641378 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 632226075 # number of integer regfile reads -system.cpu1.int_regfile_writes 374528717 # number of integer regfile writes -system.cpu1.fp_regfile_reads 661926 # number of floating regfile reads -system.cpu1.fp_regfile_writes 331836 # number of floating regfile writes -system.cpu1.cc_regfile_reads 114587184 # number of cc regfile reads -system.cpu1.cc_regfile_writes 115385602 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2619636946 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15333141 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 5236220 # number of replacements -system.cpu1.dcache.tags.tagsinuse 457.332610 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 143091306 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 5236730 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.324553 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8478701081000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 457.332610 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.893228 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.893228 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 159 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 334 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 319394188 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 319394188 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 74655263 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 74655263 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 64023189 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 64023189 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 163779 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 163779 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 39797 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 39797 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1738928 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1738928 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1751406 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1751406 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 138678452 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 138678452 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 138842231 # number of overall hits -system.cpu1.dcache.overall_hits::total 138842231 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 6126939 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 6126939 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 6982821 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 6982821 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 659533 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 659533 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 425377 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 425377 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 260578 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 260578 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 204152 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 204152 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 13109760 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 13109760 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 13769293 # number of overall misses -system.cpu1.dcache.overall_misses::total 13769293 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 92549514245 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 92549514245 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 116311286360 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 116311286360 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11708163921 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11708163921 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3758503444 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 3758503444 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4320848660 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4320848660 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3489000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3489000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 208860800605 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 208860800605 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 208860800605 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 208860800605 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 80782202 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 80782202 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 71006010 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 71006010 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823312 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 823312 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 465174 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 465174 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1999506 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1999506 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1955558 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1955558 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 151788212 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 151788212 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 152611524 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 152611524 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.075845 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.075845 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098341 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.098341 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.801073 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.801073 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.914447 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.914447 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.130321 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130321 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104396 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104396 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086369 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.086369 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.090224 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.090224 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15105.342855 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15105.342855 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16656.776160 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16656.776160 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27524.205401 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27524.205401 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14423.717444 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14423.717444 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21164.860790 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21164.860790 # average StoreCondReq miss latency +system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads +system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes +system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 16064791 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 93951930875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 424719097 # Number of Instructions Simulated +system.cpu1.committedOps 500362777 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.552088 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.552088 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.644293 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.644293 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 629086185 # number of integer regfile reads +system.cpu1.int_regfile_writes 373708704 # number of integer regfile writes +system.cpu1.fp_regfile_reads 742781 # number of floating regfile reads +system.cpu1.fp_regfile_writes 462024 # number of floating regfile writes +system.cpu1.cc_regfile_reads 113147370 # number of cc regfile reads +system.cpu1.cc_regfile_writes 113825607 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2613251902 # number of misc regfile reads +system.cpu1.misc_regfile_writes 14637394 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 5151228 # number of replacements +system.cpu1.dcache.tags.tagsinuse 427.693854 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 143143391 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5151740 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.785445 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8478589557500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.693854 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835340 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.835340 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 318663535 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 318663535 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 75155961 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 75155961 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 63737585 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 63737585 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 169811 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 169811 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 58007 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 58007 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1657429 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1657429 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1683439 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1683439 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 138893546 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 138893546 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 139063357 # number of overall hits +system.cpu1.dcache.overall_hits::total 139063357 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 6025315 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 6025315 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 6706823 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 6706823 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630176 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 630176 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 421123 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 421123 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 264252 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 264252 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195781 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 195781 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 12732138 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 12732138 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 13362314 # number of overall misses +system.cpu1.dcache.overall_misses::total 13362314 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87326420147 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 87326420147 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 117804291686 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 117804291686 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13004978477 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13004978477 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3882326694 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 3882326694 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4150746008 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 4150746008 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4758000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4758000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 205130711833 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 205130711833 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 205130711833 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 205130711833 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 81181276 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 81181276 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 70444408 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 70444408 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 799987 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 799987 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 479130 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 479130 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1921681 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1921681 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1879220 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1879220 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 151625684 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 151625684 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 152425671 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 152425671 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074221 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.074221 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095207 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.095207 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787733 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787733 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.878933 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.878933 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137511 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104182 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104182 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083971 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.083971 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.087664 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.087664 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14493.253904 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14493.253904 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17564.842801 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 17564.842801 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 30881.662785 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 30881.662785 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14691.758980 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14691.758980 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21200.964384 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21200.964384 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15931.702839 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15931.702839 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15168.592941 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15168.592941 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 2855420 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 17544431 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 337066 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 700468 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.471397 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 25.046727 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16111.254200 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16111.254200 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15351.436273 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15351.436273 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 3328310 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18296285 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 353421 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 675053 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.417409 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 27.103479 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3392584 # number of writebacks -system.cpu1.dcache.writebacks::total 3392584 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3127909 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 3127909 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5647115 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 5647115 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3296 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3296 # number of WriteInvalidateReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132105 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132105 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 8775024 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 8775024 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 8775024 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 8775024 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2999030 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2999030 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1335706 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1335706 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 659449 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 659449 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 422081 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 422081 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 128473 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 128473 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 204145 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 204145 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4334736 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4334736 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4994185 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4994185 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38225367292 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38225367292 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21845579142 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21845579142 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 15240654080 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 15240654080 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 10753431338 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 10753431338 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1629520255 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1629520255 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3904363340 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3904363340 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3325000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3325000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 60070946434 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 60070946434 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 75311600514 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 75311600514 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 796916503 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 796916503 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 897774501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 897774501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1694691004 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1694691004 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037125 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037125 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018811 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018811 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.800971 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.800971 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.907362 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.907362 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064252 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064252 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104392 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104392 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028558 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.028558 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032725 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.032725 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12745.910275 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12745.910275 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16355.080491 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16355.080491 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 23111.194467 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 23111.194467 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25477.174613 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25477.174613 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12683.756548 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12683.756548 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19125.441916 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19125.441916 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3264704 # number of writebacks +system.cpu1.dcache.writebacks::total 3264704 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3035971 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 3035971 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5416489 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 5416489 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3258 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3258 # number of WriteInvalidateReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 136728 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 136728 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 8452460 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 8452460 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 8452460 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 8452460 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2989344 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2989344 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1290334 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1290334 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630111 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 630111 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 417865 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 417865 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127524 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127524 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195781 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 195781 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 4279678 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 4279678 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4909789 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4909789 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39357294362 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39357294362 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22683763866 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22683763866 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12612160940 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12612160940 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12265252837 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12265252837 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1674709739 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1674709739 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3848237992 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3848237992 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4609500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4609500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62041058228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 62041058228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74653219168 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 74653219168 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 688989750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 688989750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 785556502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 785556502 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1474546252 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1474546252 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036823 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036823 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018317 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018317 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787652 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787652 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.872133 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.872133 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066361 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066361 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104182 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104182 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028225 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.028225 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032211 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.032211 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13165.863267 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13165.863267 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17579.761415 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17579.761415 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20015.776490 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20015.776490 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 29352.189911 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29352.189911 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13132.506344 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13132.506344 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19655.829687 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19655.829687 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13858.040359 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13858.040359 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15079.857978 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15079.857978 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14496.664989 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14496.664989 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15204.975034 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15204.975034 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2352,461 +2332,458 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 5522406 # number of replacements -system.cpu1.icache.tags.tagsinuse 501.856310 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 190094169 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 5522918 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 34.419155 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8518418347000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.856310 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980188 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.980188 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5667991 # number of replacements +system.cpu1.icache.tags.tagsinuse 501.848972 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 190104103 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5668503 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 33.536915 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8518313865250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.848972 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980174 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.980174 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 335 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 397333844 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 397333844 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 190094169 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 190094169 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 190094169 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 190094169 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 190094169 # number of overall hits -system.cpu1.icache.overall_hits::total 190094169 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 5811281 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 5811281 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 5811281 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 5811281 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 5811281 # number of overall misses -system.cpu1.icache.overall_misses::total 5811281 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61520167992 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 61520167992 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 61520167992 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 61520167992 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 61520167992 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 61520167992 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 195905450 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 195905450 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 195905450 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 195905450 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 195905450 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 195905450 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029664 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029664 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029664 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029664 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029664 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029664 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10586.335094 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10586.335094 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10586.335094 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10586.335094 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10586.335094 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10586.335094 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 7857995 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 642168 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 397835903 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 397835903 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 190104103 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 190104103 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 190104103 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 190104103 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 190104103 # number of overall hits +system.cpu1.icache.overall_hits::total 190104103 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5979587 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5979587 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5979587 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5979587 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5979587 # number of overall misses +system.cpu1.icache.overall_misses::total 5979587 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61433525378 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 61433525378 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 61433525378 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 61433525378 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 61433525378 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 61433525378 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 196083690 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 196083690 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 196083690 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 196083690 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 196083690 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 196083690 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030495 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030495 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030495 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030495 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030495 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030495 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10273.874329 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 10273.874329 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 10273.874329 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 10273.874329 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 8139519 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 675212 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.236665 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 39 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.054761 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 288337 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 288337 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 288337 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 288337 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 288337 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 288337 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5522944 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 5522944 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 5522944 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 5522944 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 5522944 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 5522944 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 50254087338 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 50254087338 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 50254087338 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 50254087338 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 50254087338 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 50254087338 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5802498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 5802498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5802498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 5802498 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028192 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.028192 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028192 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.028192 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9099.148450 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9099.148450 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 9099.148450 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 311064 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 311064 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 311064 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 311064 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 311064 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 311064 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5668523 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5668523 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5668523 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5668523 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5668523 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5668523 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 52921398555 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 52921398555 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 52921398555 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 52921398555 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 52921398555 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 52921398555 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6131248 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6131248 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6131248 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 6131248 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028909 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.028909 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.028909 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9336.011966 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 7021877 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 7194867 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 149461 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 6924956 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 7115948 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 165163 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 884477 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2159012 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13531.891931 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11463233 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2175036 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.270365 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9606894527000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5515.011217 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.352016 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.650961 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3854.550779 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3125.340880 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 867.986079 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.336610 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004965 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005350 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.235263 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.190756 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052978 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.825921 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1495 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 53 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14476 # Occupied blocks per task id +system.cpu1.l2cache.prefetcher.pfSpanPage 889052 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 2136964 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13504.433199 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 11477625 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2153158 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 5.330600 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9723406338993 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5663.402040 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.532496 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 97.953204 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3050.006780 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3697.963934 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 913.574746 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.345667 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004976 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005979 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.186158 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225706 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055760 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.824245 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1347 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14805 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 465 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 510 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 477 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 237 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 720 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 360 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1150 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5680 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4086 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3438 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.091248 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003235 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.883545 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 250860566 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 250860566 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 536921 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 182584 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4917912 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2781477 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 8418894 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3392565 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3392565 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 191757 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 191757 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 71744 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 71744 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31465 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 31465 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 867581 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 867581 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 536921 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 182584 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4917912 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3649058 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 9286475 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 536921 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 182584 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4917912 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3649058 # number of overall hits -system.cpu1.l2cache.overall_hits::total 9286475 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12339 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9008 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 605020 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1001664 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1628031 # number of ReadReq misses -system.cpu1.l2cache.Writeback_misses::writebacks 17 # number of Writeback misses -system.cpu1.l2cache.Writeback_misses::total 17 # number of Writeback misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 228944 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 228944 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 145584 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 145584 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 172667 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 172667 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 13 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 13 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 259180 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 259180 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12339 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9008 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 605020 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1260844 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1887211 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12339 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9008 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 605020 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1260844 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1887211 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 492758189 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 397546188 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 17874502757 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 34268686598 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 53033493732 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 241449363 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 241449363 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2956550746 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2956550746 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3438458831 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3438458831 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 3243000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 3243000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 10870225593 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 10870225593 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 492758189 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 397546188 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17874502757 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 45138912191 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 63903719325 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 492758189 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 397546188 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17874502757 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 45138912191 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 63903719325 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 549260 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 191592 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5522932 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3783141 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 10046925 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3392582 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3392582 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 420701 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 420701 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 217328 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 217328 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 204132 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 204132 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 13 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 13 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1126761 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1126761 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 549260 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 191592 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 5522932 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4909902 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 11173686 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 549260 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 191592 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 5522932 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4909902 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 11173686 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022465 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.047017 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.109547 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.264770 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.162043 # miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000005 # miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_miss_rate::total 0.000005 # miss rate for Writeback accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.544196 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.544196 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.669881 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.669881 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.845860 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.845860 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1369 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5255 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5224 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2823 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.082214 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903625 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 249290678 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 249290678 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 527309 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 181952 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5073722 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2781354 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 8564337 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3264689 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3264689 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 166971 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 166971 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 66098 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 66098 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34177 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 34177 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 845253 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 845253 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 527309 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 181952 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 5073722 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3626607 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 9409590 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 527309 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 181952 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5073722 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3626607 # number of overall hits +system.cpu1.l2cache.overall_hits::total 9409590 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12633 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9907 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 594787 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 963518 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1580845 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 14 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 14 # number of Writeback misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 249743 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 249743 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 139723 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 139723 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 161589 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 161589 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 15 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 15 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 245189 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 245189 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12633 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9907 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 594787 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1208707 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1826034 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12633 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9907 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 594787 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1208707 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1826034 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 491583485 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 427969129 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 16999057098 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 31500874862 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 49419484574 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 236089966 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 236089966 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 3003661220 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 3003661220 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3342420381 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3342420381 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 4508496 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 4508496 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11309728111 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 11309728111 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 491583485 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 427969129 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16999057098 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 42810602973 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 60729212685 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 491583485 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 427969129 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16999057098 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 42810602973 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 60729212685 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 539942 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 191859 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5668509 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3744872 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 10145182 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3264703 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3264703 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 416714 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 416714 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 205821 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 205821 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195766 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 195766 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 15 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 15 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1090442 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1090442 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 539942 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 191859 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5668509 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4835314 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 11235624 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 539942 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 191859 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5668509 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4835314 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 11235624 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051637 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.104928 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.257290 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.155822 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.599315 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.599315 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.678857 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.678857 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.825419 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.825419 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.230022 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.230022 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022465 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.047017 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.109547 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.256796 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.168898 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022465 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.047017 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.109547 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.256796 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.168898 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39935.018154 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 44132.569716 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29543.656006 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 34211.758232 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 32575.235811 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 1054.621929 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 1054.621929 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20308.212070 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20308.212070 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19913.815790 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19913.815790 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 249461.538462 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 249461.538462 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 41940.834914 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 41940.834914 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39935.018154 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 44132.569716 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29543.656006 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35800.552797 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 33861.459755 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39935.018154 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 44132.569716 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29543.656006 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35800.552797 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 33861.459755 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.224853 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.224853 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051637 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.104928 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.249975 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.162522 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.023397 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051637 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.104928 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.249975 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.162522 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 43198.660442 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 28580.075049 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32693.602882 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31261.435861 # average ReadReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 945.331665 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 945.331665 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21497.256858 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21497.256858 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20684.702430 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20684.702430 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 300566.400000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 300566.400000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 46126.572199 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 46126.572199 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 43198.660442 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 28580.075049 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 35418.511660 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 33257.438079 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 38912.648223 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 43198.660442 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 28580.075049 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 35418.511660 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 33257.438079 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 100 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 25 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 971322 # number of writebacks -system.cpu1.l2cache.writebacks::total 971322 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 2 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 153 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 6612 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 6768 # number of ReadReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 63 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 63 # number of WriteInvalidateReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 20490 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 20490 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 2 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 153 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 27102 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 27258 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 2 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 153 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 27102 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 27258 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12337 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 8855 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 605019 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 995052 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1621263 # number of ReadReq MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::writebacks 17 # number of Writeback MSHR misses -system.cpu1.l2cache.Writeback_mshr_misses::total 17 # number of Writeback MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 705681 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 705681 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 228881 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 228881 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 145584 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 145584 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 172667 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 172667 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 13 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 13 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 238690 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 238690 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12337 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 8855 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 605019 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1233742 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1859953 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12337 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 8855 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 605019 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1233742 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 705681 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2565634 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 327287462 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 13621135743 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 26954578760 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 41308601196 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 39485552404 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 39485552404 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 6916972959 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 6916972959 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2477712924 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2477712924 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2304203121 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2304203121 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2669000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2669000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7509818481 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7509818481 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 327287462 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13621135743 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 34464397241 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 48818419677 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 405599231 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 327287462 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13621135743 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 34464397241 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 39485552404 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 88303972081 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5233250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 741632996 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 746866246 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 846035990 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 846035990 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5233250 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1587668986 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1592902236 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.263023 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.161369 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000005 # mshr miss rate for Writeback accesses -system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000005 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.writebacks::writebacks 969171 # number of writebacks +system.cpu1.l2cache.writebacks::total 969171 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 3 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 194 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 3035 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 3232 # number of ReadReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 1 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 1 # number of WriteInvalidateReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 16069 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 16069 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 3 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 194 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 19104 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 19301 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 3 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 194 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 19104 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 19301 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 12630 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9713 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 594787 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 960483 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1577613 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 14 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 14 # number of Writeback MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 688186 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 688186 # number of HardPFReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 249742 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 249742 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 139723 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 139723 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 161589 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 161589 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 15 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 15 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 229120 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 229120 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 12630 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9713 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 594787 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1189603 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1806733 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 12630 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9713 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 594787 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1189603 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 688186 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 2494919 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 358018255 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 13119737402 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 25025673719 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 38912076401 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 36938967043 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 36938967043 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8412735671 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 8412735671 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2759951656 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2759951656 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2380296086 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2380296086 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 3864996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 3864996 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7878318651 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7878318651 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 358018255 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 13119737402 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32903992370 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 46790395052 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 408647025 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 358018255 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 13119737402 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32903992370 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 36938967043 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 83729362095 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 5602750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 639050750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 644653500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 738464498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 738464498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 5602750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1377515248 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1383117998 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.256480 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.155504 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.544047 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.544047 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.669881 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.669881 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.845860 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.845860 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.599313 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.599313 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.678857 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.678857 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825419 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.825419 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.211837 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.211837 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.166458 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022461 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.046218 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.109547 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.251276 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.210117 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.210117 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.160804 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023391 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050626 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.229614 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 27088.613218 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25479.272145 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55953.826735 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30220.826364 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 30220.826364 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17019.129327 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17019.129327 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13344.779958 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13344.779958 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 205307.692308 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 205307.692308 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31462.643936 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31462.643936 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26247.125426 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32876.649996 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36960.752343 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22513.566918 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27934.849621 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55953.826735 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34417.992621 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222054 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26055.301051 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24665.159580 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53675.847871 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33685.706333 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33685.706333 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19753.023167 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19753.023167 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14730.557686 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14730.557686 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 257666.400000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 257666.400000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34385.119811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34385.119811 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25897.791789 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 36859.698857 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 53675.847871 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33559.952085 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2816,66 +2793,64 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 12802922 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 10291743 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6895 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6895 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3392582 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 1076196 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1156933 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 420701 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 464615 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 376292 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 486818 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 88 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1296360 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1132878 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11046012 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15089863 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 415115 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1210522 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27761512 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353468736 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 564735319 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1532736 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4394080 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 924130871 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 5316111 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 20559073 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.243524 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.429209 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 12589327 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 10390309 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6277 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6277 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3264703 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 969369 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1138126 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 416714 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 449544 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355754 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 472453 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1246255 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1097731 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11337166 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14775069 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416528 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186159 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27714922 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 362785648 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 551966772 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1534872 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4319536 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 920606828 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4866324 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 20006897 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.227379 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.419140 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15552442 75.65% 75.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 5006631 24.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 15457744 77.26% 77.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 4549153 22.74% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 20559073 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 11602796673 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 20006897 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 11420254845 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 182870488 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 196151972 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 8299279905 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8513145317 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7848510644 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7729223292 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 224378946 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 225599484 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 662954125 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 647309419 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40399 # Transaction distribution -system.iobus.trans_dist::ReadResp 40399 # Transaction distribution -system.iobus.trans_dist::WriteReq 136785 # Transaction distribution -system.iobus.trans_dist::WriteResp 30057 # Transaction distribution +system.iobus.trans_dist::ReadReq 40298 # Transaction distribution +system.iobus.trans_dist::ReadResp 40298 # Transaction distribution +system.iobus.trans_dist::WriteReq 136633 # Transaction distribution +system.iobus.trans_dist::WriteResp 29905 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48154 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47726 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2885,18 +2860,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123088 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231200 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231200 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122608 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231174 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231174 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354368 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48174 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353862 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47746 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2906,18 +2881,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156195 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338816 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338712 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7497097 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36604000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36251000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2937,7 +2912,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2945,71 +2920,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1043087367 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607686128 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93034000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92706000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179187461 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148478785 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115604 # number of replacements -system.iocache.tags.tagsinuse 11.301402 # Cycle average of tags in use +system.iocache.tags.replacements 115568 # number of replacements +system.iocache.tags.tagsinuse 11.294495 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115620 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115584 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9117040369000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 7.419209 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 3.882193 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.463701 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.242637 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.706338 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9116942023000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.849176 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.445319 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240573 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.465332 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705906 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040757 # Number of tag accesses -system.iocache.tags.data_accesses 1040757 # Number of data accesses +system.iocache.tags.tag_accesses 1040640 # Number of tag accesses +system.iocache.tags.data_accesses 1040640 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8872 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8909 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8859 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8896 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8872 # number of demand (read+write) misses -system.iocache.demand_misses::total 8912 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8859 # number of demand (read+write) misses +system.iocache.demand_misses::total 8899 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8872 # number of overall misses -system.iocache.overall_misses::total 8912 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1954318592 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1960025592 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28939092314 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28939092314 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1954318592 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1960382592 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1954318592 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1960382592 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8859 # number of overall misses +system.iocache.overall_misses::total 8899 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1636729691 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1641925191 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19864825652 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19864825652 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1636729691 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1642294191 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1636729691 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1642294191 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8872 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8859 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8896 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8872 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8912 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8859 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8899 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8872 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8912 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8859 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8899 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -3023,55 +2998,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 220279.372408 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 220005.117522 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271148.080298 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271148.080298 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 219971.116697 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 220279.372408 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 219971.116697 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228427 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 184753.323287 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 184568.928844 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186125.718200 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186125.718200 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 184548.172941 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 184753.323287 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 184548.172941 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 112586 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27535 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16234 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.295878 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.935198 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106702 # number of writebacks -system.iocache.writebacks::total 106702 # number of writebacks +system.iocache.writebacks::writebacks 106694 # number of writebacks +system.iocache.writebacks::total 106694 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8872 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8909 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8859 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8896 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8872 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8912 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8859 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8899 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8872 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8912 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1492830122 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1496613122 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23388843706 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23388843706 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1492830122 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1496814122 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1492830122 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1496814122 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8859 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8899 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1174861151 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1178131651 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14314859762 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14314859762 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1174861151 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1178344651 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1174861151 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1178344651 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -3085,562 +3060,567 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 168263.088593 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167988.901336 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219144.401713 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219144.401713 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 168263.088593 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 167954.905969 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 132617.806863 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 132433.863647 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134124.688573 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134124.688573 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 132617.806863 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 132413.153276 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1613331 # number of replacements -system.l2c.tags.tagsinuse 64339.343113 # Cycle average of tags in use -system.l2c.tags.total_refs 4797018 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1673818 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.865914 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 3243842500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 19101.398352 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 185.742619 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 228.186438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3981.341018 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 11353.199987 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 11643.208368 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 179.349370 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 266.651363 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3248.685748 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 4974.329517 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 9177.250333 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.291464 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002834 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003482 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.060750 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.173236 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.177661 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002737 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.004069 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.049571 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.075902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.140034 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.981740 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 10683 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49559 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 76 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 157 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 995 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9444 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 227 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3090 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3968 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 42149 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.163010 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.756210 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 64781750 # Number of tag accesses -system.l2c.tags.data_accesses 64781750 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 6508 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4319 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 640995 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 651108 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 307248 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 6236 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 4043 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 550704 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 545723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 278481 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2995365 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2564009 # number of Writeback hits -system.l2c.Writeback_hits::total 2564009 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 138658 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 123170 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 261828 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 30955 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 32781 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 63736 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6525 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5847 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12372 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 54058 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 53543 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107601 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 6508 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4319 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 640995 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 705166 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 307248 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 6236 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 4043 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 550704 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 599266 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 278481 # number of demand (read+write) hits -system.l2c.demand_hits::total 3102966 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 6508 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4319 # number of overall hits -system.l2c.overall_hits::cpu0.inst 640995 # number of overall hits -system.l2c.overall_hits::cpu0.data 705166 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 307248 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 6236 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 4043 # number of overall hits -system.l2c.overall_hits::cpu1.inst 550704 # number of overall hits -system.l2c.overall_hits::cpu1.data 599266 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 278481 # number of overall hits -system.l2c.overall_hits::total 3102966 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2518 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2288 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 61626 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 165027 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 315511 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2810 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2444 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 54313 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 130678 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 226783 # number of ReadReq misses -system.l2c.ReadReq_misses::total 963998 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 490361 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 96104 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 586465 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 48125 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 46732 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 94857 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 10442 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 8446 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 18888 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 87770 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 52309 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140079 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2518 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2288 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 61626 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 252797 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 315511 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2810 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2444 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 54313 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 182987 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 226783 # number of demand (read+write) misses -system.l2c.demand_misses::total 1104077 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2518 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2288 # number of overall misses -system.l2c.overall_misses::cpu0.inst 61626 # number of overall misses -system.l2c.overall_misses::cpu0.data 252797 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 315511 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2810 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2444 # number of overall misses -system.l2c.overall_misses::cpu1.inst 54313 # number of overall misses -system.l2c.overall_misses::cpu1.data 182987 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 226783 # number of overall misses -system.l2c.overall_misses::total 1104077 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 214285749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 198628497 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 4954310957 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 15651071560 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 48231685466 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 246385494 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 217660244 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4359245951 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 12707402041 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 33186692902 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 119967368861 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 38113099 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 39381504 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 77494603 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 206747895 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 214995003 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 421742898 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 39945327 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 36079463 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 76024790 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 7797935308 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4285574180 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 12083509488 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 214285749 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 198628497 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 4954310957 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 23449006868 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 48231685466 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 246385494 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 217660244 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 4359245951 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 16992976221 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 33186692902 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 132050878349 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 214285749 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 198628497 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 4954310957 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 23449006868 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 48231685466 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 246385494 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 217660244 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 4359245951 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 16992976221 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 33186692902 # number of overall miss cycles -system.l2c.overall_miss_latency::total 132050878349 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 9026 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6607 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 702621 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 816135 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 622759 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9046 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6487 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 605017 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 676401 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 505264 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3959363 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2564009 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2564009 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 629019 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 219274 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 848293 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 79080 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 79513 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 158593 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 16967 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 14293 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 31260 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 141828 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 105852 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247680 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 9026 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6607 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 702621 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 957963 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 622759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9046 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6487 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 605017 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 782253 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 505264 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4207043 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 9026 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6607 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 702621 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 957963 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 622759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9046 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6487 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 605017 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 782253 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 505264 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4207043 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.278972 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.346299 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.087709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.202206 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.506634 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.310635 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.376754 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.089771 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.193196 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.448841 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.243473 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.779565 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.438283 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.691347 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.608561 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.587728 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.598116 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.615430 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.590919 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.604223 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.618848 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.494171 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.565564 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.278972 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.346299 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.087709 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.263890 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.506634 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.310635 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.376754 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.089771 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.233923 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.448841 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.262435 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.278972 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.346299 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.087709 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.263890 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.506634 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.310635 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.376754 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.089771 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.233923 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.448841 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.262435 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85101.568308 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 86813.154283 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80393.193733 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 94839.459967 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87681.670463 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89059.019640 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 80261.557104 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 97242.091561 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 124447.736262 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 77.724572 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 409.780072 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 132.138496 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 4296.060156 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4600.594946 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4446.091464 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3825.447903 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4271.781080 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4025.031237 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 88845.110038 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81928.046416 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 86262.105583 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85101.568308 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 86813.154283 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 80393.193733 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 92758.248191 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87681.670463 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89059.019640 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 80261.557104 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 92864.390481 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 119602.960979 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85101.568308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 86813.154283 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 80393.193733 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 92758.248191 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152868.475159 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87681.670463 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89059.019640 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 80261.557104 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 92864.390481 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 146336.775252 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 119602.960979 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 13381 # number of cycles access was blocked +system.l2c.tags.replacements 1377424 # number of replacements +system.l2c.tags.tagsinuse 64428.474571 # Cycle average of tags in use +system.l2c.tags.total_refs 4496154 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1437791 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.127126 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 3245891000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 17415.702003 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 13.555673 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 13.071281 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4037.254225 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5874.753333 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 3721.003209 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 357.239386 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 523.990627 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2776.282665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11847.144423 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 17848.477746 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.265743 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000207 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000199 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061604 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.089642 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.056778 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.005451 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.007995 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.042363 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.180773 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.272346 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983101 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 10320 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 289 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49758 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 29 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 178 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 260 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9845 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 285 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2371 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4137 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 42888 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.157471 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.004410 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.759247 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 59850638 # Number of tag accesses +system.l2c.tags.data_accesses 59850638 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6609 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5089 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 570808 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 585040 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 302541 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 6014 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4366 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 555272 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 535796 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 269863 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2841398 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2358990 # number of Writeback hits +system.l2c.Writeback_hits::total 2358990 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 147857 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 120344 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 268201 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 33100 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 25345 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 58445 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6120 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5439 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11559 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 54193 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 49865 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 104058 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6609 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5089 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 570808 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 639233 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 302541 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 6014 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4366 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 555272 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 585661 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 269863 # number of demand (read+write) hits +system.l2c.demand_hits::total 2945456 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6609 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5089 # number of overall hits +system.l2c.overall_hits::cpu0.inst 570808 # number of overall hits +system.l2c.overall_hits::cpu0.data 639233 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 302541 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 6014 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4366 # number of overall hits +system.l2c.overall_hits::cpu1.inst 555272 # number of overall hits +system.l2c.overall_hits::cpu1.data 585661 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 269863 # number of overall hits +system.l2c.overall_hits::total 2945456 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1186 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 952 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 65177 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 129551 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 203502 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2616 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2569 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 39512 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 114014 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 227886 # number of ReadReq misses +system.l2c.ReadReq_misses::total 786965 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 437920 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 120290 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 558210 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 45660 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 46311 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 91971 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 9121 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 8967 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 18088 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 74847 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 51643 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 126490 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1186 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 952 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 65177 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 204398 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 203502 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2616 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2569 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 39512 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 165657 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 227886 # number of demand (read+write) misses +system.l2c.demand_misses::total 913455 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1186 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 952 # number of overall misses +system.l2c.overall_misses::cpu0.inst 65177 # number of overall misses +system.l2c.overall_misses::cpu0.data 204398 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 203502 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2616 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2569 # number of overall misses +system.l2c.overall_misses::cpu1.inst 39512 # number of overall misses +system.l2c.overall_misses::cpu1.data 165657 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 227886 # number of overall misses +system.l2c.overall_misses::total 913455 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 111035273 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 90655016 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 5679579933 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 12742001076 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 236867766 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 230645249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3413499724 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 10938718079 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 95639804522 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 58893966 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 45248781 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 104142747 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 276167379 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 268661108 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 544828487 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46772512 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 48520461 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 95292973 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 6912544305 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4650422855 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11562967160 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 111035273 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 90655016 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 5679579933 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 19654545381 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 236867766 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 230645249 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3413499724 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 15589140934 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 107202771682 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 111035273 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 90655016 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 5679579933 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 19654545381 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 29753788309 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 236867766 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 230645249 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3413499724 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 15589140934 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 32443014097 # number of overall miss cycles +system.l2c.overall_miss_latency::total 107202771682 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 7795 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6041 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 635985 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 714591 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 506043 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 8630 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 6935 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 594784 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 649810 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 497749 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 3628363 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2358990 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2358990 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 585777 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 240634 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 826411 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 78760 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 71656 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 150416 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 15241 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 14406 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 29647 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 129040 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 101508 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 230548 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 7795 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6041 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 635985 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 843631 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 506043 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 8630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 6935 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 594784 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 751318 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 497749 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3858911 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 7795 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6041 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 635985 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 843631 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 506043 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 8630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 6935 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 594784 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 751318 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 497749 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3858911 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.157590 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.102482 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.181294 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.370440 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.066431 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.175457 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.216893 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.747588 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.499888 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.675463 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.579736 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.646296 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.611444 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.598452 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.622449 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.610112 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.580029 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.508758 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.548649 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.157590 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.102482 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.242284 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.370440 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.066431 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.220489 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.236713 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.152149 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.157590 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.102482 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.242284 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.402144 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.303129 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.370440 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.066431 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.220489 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.457833 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.236713 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 95225.857143 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 87140.861546 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 98355.096263 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89780.166991 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 86391.469022 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 95941.885023 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 121529.934015 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 134.485673 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 376.164112 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 186.565534 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6048.343824 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5801.237460 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5923.916093 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5128.002631 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5411.002676 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 5268.297932 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 92355.662952 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 90049.432740 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 91414.081429 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 95225.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 87140.861546 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 96158.207913 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89780.166991 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 86391.469022 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 94104.933290 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 117359.663784 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 93621.646712 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 95225.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 87140.861546 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 96158.207913 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 146208.825019 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 90545.782110 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89780.166991 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 86391.469022 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 94104.933290 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 142365.104030 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 117359.663784 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 11943 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 234 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 84 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 57.183761 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 142.178571 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1241010 # number of writebacks -system.l2c.writebacks::total 1241010 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 230 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 68 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 210 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 83 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 591 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 230 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 68 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 210 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 83 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 591 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 230 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 68 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 210 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 83 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 591 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2518 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2288 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 61396 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 164959 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 315511 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2810 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2444 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 54103 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 130595 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 226783 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 963407 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 490361 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 96104 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 586465 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 48125 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 46732 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 94857 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10442 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8446 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 18888 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 87770 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 52309 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140079 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2518 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2288 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 61396 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 252729 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 315511 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2810 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2444 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 54103 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 182904 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 226783 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 1103486 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2518 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2288 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 61396 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 252729 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 315511 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2810 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2444 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 54103 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 182904 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 226783 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 1103486 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 182832749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 170078497 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4169491707 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 13595488810 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 44400149466 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 211305994 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 187184244 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3666713475 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11080588209 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 30429379906 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 108093213057 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 23987646886 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2627282944 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 26614929830 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 490076505 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 479520804 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 969597309 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 106392293 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 85816866 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 192209159 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6696791958 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3633299230 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 10330091188 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 182832749 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 170078497 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 4169491707 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 20292280768 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 44400149466 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 211305994 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 187184244 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3666713475 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 14713887439 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 30429379906 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 118423304245 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 182832749 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 170078497 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 4169491707 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 20292280768 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 44400149466 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 211305994 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 187184244 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3666713475 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 14713887439 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 30429379906 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 118423304245 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1103208750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4750572496 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 3896750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 616502003 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6474179999 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4542606997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 728363997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5270970994 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1103208750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9293179493 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 3896750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1344866000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11745150993 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.278972 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.346299 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.087381 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.202122 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.506634 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.310635 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.376754 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089424 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.193073 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448841 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.243324 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.779565 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.438283 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.691347 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.608561 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.587728 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.598116 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.615430 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.590919 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.604223 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.618848 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.494171 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.565564 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.278972 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.346299 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.087381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.263819 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.506634 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.310635 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.376754 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089424 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.233817 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448841 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.262295 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.278972 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.346299 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.087381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.263819 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.506634 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.310635 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.376754 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089424 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.233817 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.448841 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.262295 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67911.455258 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 82417.381349 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 84846.955925 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 112198.907686 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48918.341561 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27337.914593 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 45381.957713 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10183.407896 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10261.080288 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10221.673772 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10188.880770 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10160.651906 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10176.257889 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76299.327310 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69458.395878 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 73744.752518 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67911.455258 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 80292.648521 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 80445.957655 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 107317.450557 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 72610.305401 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74335.007430 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67911.455258 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 80292.648521 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140724.568925 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75197.862633 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76589.297872 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67772.830989 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 80445.957655 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 134178.399201 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 107317.450557 # average overall mshr miss latency +system.l2c.writebacks::writebacks 1067007 # number of writebacks +system.l2c.writebacks::total 1067007 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.inst 133 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 90 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.dtb.walker 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 133 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 17 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 90 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 264 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.dtb.walker 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 133 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 17 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 90 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 264 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1184 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 952 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 65044 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 129534 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 203500 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2616 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2569 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 39422 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 113994 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 227886 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 786701 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 437920 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 120290 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 558210 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 45660 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 46311 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 91971 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9121 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 8967 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 18088 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 74847 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 51643 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 126490 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1184 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 952 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 65044 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 204381 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 203500 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2616 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2569 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 39422 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 165637 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 227886 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 913191 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1184 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 952 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 65044 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 204381 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 203500 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2616 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2569 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 39422 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 165637 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 227886 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 913191 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 78660484 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 4853701817 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11124617158 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 198329749 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2912777274 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9514272921 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 85885889998 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17416176424 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3960645719 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 21376822143 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 814816958 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 825298541 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1640115499 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 162191592 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 159645428 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 321837020 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5979693683 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4008215143 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9987908826 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 78660484 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 4853701817 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 17104310841 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 198329749 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 2912777274 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 13522488064 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 95873798824 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 95681979 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 78660484 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 4853701817 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 17104310841 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 27259941357 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 203927234 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 198329749 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 2912777274 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 13522488064 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29643980025 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 95873798824 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4853989000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 4264250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 516390251 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6660266501 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4658794041 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 621932502 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5280726543 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1285623000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9512783041 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 4264250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1138322753 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11940993044 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181270 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.175427 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.216820 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.747588 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.499888 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.675463 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.579736 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.646296 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.611444 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.598452 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.622449 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.610112 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.580029 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.508758 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.548649 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.236645 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.151892 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.157590 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102273 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.242264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.402140 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.303129 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.370440 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.066280 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.220462 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.457833 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.236645 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 85881.831473 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 83462.927180 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 109172.214092 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39770.223840 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32925.810283 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38295.304891 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.312265 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.788603 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17832.963641 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17782.215985 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.660979 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17792.847192 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79892.229254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 77613.909784 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 78962.043055 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80812.482264 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 82626.558824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74621.822413 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83688.360665 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 133955.485784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77953.835627 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77201.147917 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 73887.100452 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 81639.295954 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 130082.497499 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 104987.673799 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3655,57 +3635,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 1032278 # Transaction distribution -system.membus.trans_dist::ReadResp 1032278 # Transaction distribution -system.membus.trans_dist::WriteReq 38581 # Transaction distribution -system.membus.trans_dist::WriteResp 38581 # Transaction distribution -system.membus.trans_dist::Writeback 1347712 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 689975 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 689975 # Transaction distribution -system.membus.trans_dist::UpgradeReq 447979 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 332386 # Transaction distribution -system.membus.trans_dist::UpgradeResp 121150 # Transaction distribution -system.membus.trans_dist::ReadExReq 152231 # Transaction distribution -system.membus.trans_dist::ReadExResp 135895 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123088 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 855568 # Transaction distribution +system.membus.trans_dist::ReadResp 855568 # Transaction distribution +system.membus.trans_dist::WriteReq 38542 # Transaction distribution +system.membus.trans_dist::WriteResp 38542 # Transaction distribution +system.membus.trans_dist::Writeback 1173701 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 661649 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 661649 # Transaction distribution +system.membus.trans_dist::UpgradeReq 438223 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 309934 # Transaction distribution +system.membus.trans_dist::UpgradeResp 117397 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution +system.membus.trans_dist::ReadExReq 139893 # Transaction distribution +system.membus.trans_dist::ReadExResp 122444 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122608 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25972 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5571157 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5720295 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6056198 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156195 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26394 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4925384 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5074464 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335910 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5410374 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155738 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 51944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 187423448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 187632159 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14096832 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 201728991 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 678374 # Total snoops (count) -system.membus.snoop_fanout::samples 3943213 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52788 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 162304200 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 162513298 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14098112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14098112 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 176611410 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 651055 # Total snoops (count) +system.membus.snoop_fanout::samples 3600660 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3943213 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3600660 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3943213 # Request fanout histogram -system.membus.reqLayer0.occupancy 98700492 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3600660 # Request fanout histogram +system.membus.reqLayer0.occupancy 98274497 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 45500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 21600991 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 22081484 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 19952700228 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10699049257 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 11115498245 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5725496770 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187180539 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151866715 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3749,49 +3730,49 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4932840 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4925609 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38581 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38581 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2564009 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 955023 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 848293 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 504313 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 344758 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 849071 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 157 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 157 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 306644 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 306644 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8600677 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6275419 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 14876096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 289885704 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198430935 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 488316639 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1740265 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9550575 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012108 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.109370 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 4566673 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 4559437 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38542 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38542 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2358990 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 933261 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 826411 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 489333 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 321493 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 810826 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 208 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 288168 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 288168 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7677415 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6169065 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 13846480 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255017262 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196496484 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 451513746 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1675443 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 8934179 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012956 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.113084 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9434933 98.79% 98.79% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115642 1.21% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 8818430 98.70% 98.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115749 1.30% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9550575 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 18722164156 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 8934179 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 7984163233 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7552500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2491500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 13115425494 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 4301185209 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 11201753623 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3898685571 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13602 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 13668 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 5345 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 5222 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt index 48ca1dfde..6f7d21c4e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3/stats.txt @@ -1,141 +1,141 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.320647 # Number of seconds simulated -sim_ticks 51320647066500 # Number of ticks simulated -final_tick 51320647066500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.320469 # Number of seconds simulated +sim_ticks 51320468905000 # Number of ticks simulated +final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 114690 # Simulator instruction rate (inst/s) -host_op_rate 134762 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6864170011 # Simulator tick rate (ticks/s) -host_mem_usage 721888 # Number of bytes of host memory used -host_seconds 7476.60 # Real time elapsed on the host -sim_insts 857487967 # Number of instructions simulated -sim_ops 1007562352 # Number of ops (including micro ops) simulated +host_inst_rate 114377 # Simulator instruction rate (inst/s) +host_op_rate 134391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6861255780 # Simulator tick rate (ticks/s) +host_mem_usage 720736 # Number of bytes of host memory used +host_seconds 7479.75 # Real time elapsed on the host +sim_insts 855512158 # Number of instructions simulated +sim_ops 1005211605 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 226752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 205312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5743904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 43053832 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 407232 # Number of bytes read from this memory -system.physmem.bytes_read::total 49637032 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5743904 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5743904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 69718464 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 202624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 193280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5755680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 42629000 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 415488 # Number of bytes read from this memory +system.physmem.bytes_read::total 49196072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5755680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5755680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 69369152 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 69739044 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 3543 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 105701 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 672729 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6363 # Number of read requests responded to by this memory -system.physmem.num_reads::total 791544 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1089351 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 69389732 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 3166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3020 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 105885 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 666091 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6492 # Number of read requests responded to by this memory +system.physmem.num_reads::total 784654 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1083893 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1091924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 4418 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 4001 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 111922 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 838918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7935 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 967194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 111922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 111922 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1358488 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1086466 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 3948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 3766 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 112152 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 830643 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8096 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 958605 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 112152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 112152 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1351686 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1358889 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1358488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 4418 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 4001 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 111922 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 839319 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2326083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 791544 # Number of read requests accepted -system.physmem.writeReqs 1694292 # Number of write requests accepted -system.physmem.readBursts 791544 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1694292 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 50622848 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 35968 # Total number of bytes read from write queue -system.physmem.bytesWritten 107999616 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 49637032 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 108290596 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 562 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6769 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35256 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 48315 # Per bank write bursts -system.physmem.perBankRdBursts::1 50150 # Per bank write bursts -system.physmem.perBankRdBursts::2 46175 # Per bank write bursts -system.physmem.perBankRdBursts::3 46946 # Per bank write bursts -system.physmem.perBankRdBursts::4 45323 # Per bank write bursts -system.physmem.perBankRdBursts::5 52981 # Per bank write bursts -system.physmem.perBankRdBursts::6 47646 # Per bank write bursts -system.physmem.perBankRdBursts::7 48748 # Per bank write bursts -system.physmem.perBankRdBursts::8 44337 # Per bank write bursts -system.physmem.perBankRdBursts::9 72322 # Per bank write bursts -system.physmem.perBankRdBursts::10 50834 # Per bank write bursts -system.physmem.perBankRdBursts::11 50772 # Per bank write bursts -system.physmem.perBankRdBursts::12 48451 # Per bank write bursts -system.physmem.perBankRdBursts::13 47387 # Per bank write bursts -system.physmem.perBankRdBursts::14 44232 # Per bank write bursts -system.physmem.perBankRdBursts::15 46363 # Per bank write bursts -system.physmem.perBankWrBursts::0 103979 # Per bank write bursts -system.physmem.perBankWrBursts::1 105038 # Per bank write bursts -system.physmem.perBankWrBursts::2 105754 # Per bank write bursts -system.physmem.perBankWrBursts::3 105161 # Per bank write bursts -system.physmem.perBankWrBursts::4 103562 # Per bank write bursts -system.physmem.perBankWrBursts::5 108435 # Per bank write bursts -system.physmem.perBankWrBursts::6 103867 # Per bank write bursts -system.physmem.perBankWrBursts::7 105467 # Per bank write bursts -system.physmem.perBankWrBursts::8 102645 # Per bank write bursts -system.physmem.perBankWrBursts::9 108407 # Per bank write bursts -system.physmem.perBankWrBursts::10 108582 # Per bank write bursts -system.physmem.perBankWrBursts::11 107982 # Per bank write bursts -system.physmem.perBankWrBursts::12 105330 # Per bank write bursts -system.physmem.perBankWrBursts::13 105345 # Per bank write bursts -system.physmem.perBankWrBursts::14 103911 # Per bank write bursts -system.physmem.perBankWrBursts::15 104029 # Per bank write bursts +system.physmem.bw_write::total 1352087 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1351686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 3948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 3766 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 112152 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 831044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2310692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 784654 # Number of read requests accepted +system.physmem.writeReqs 1688539 # Number of write requests accepted +system.physmem.readBursts 784654 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1688539 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 50184064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 33792 # Total number of bytes read from write queue +system.physmem.bytesWritten 104909952 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 49196072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 107922404 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 528 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49293 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 35218 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 46664 # Per bank write bursts +system.physmem.perBankRdBursts::1 51485 # Per bank write bursts +system.physmem.perBankRdBursts::2 48018 # Per bank write bursts +system.physmem.perBankRdBursts::3 46409 # Per bank write bursts +system.physmem.perBankRdBursts::4 44064 # Per bank write bursts +system.physmem.perBankRdBursts::5 51949 # Per bank write bursts +system.physmem.perBankRdBursts::6 45895 # Per bank write bursts +system.physmem.perBankRdBursts::7 48923 # Per bank write bursts +system.physmem.perBankRdBursts::8 45299 # Per bank write bursts +system.physmem.perBankRdBursts::9 70789 # Per bank write bursts +system.physmem.perBankRdBursts::10 48156 # Per bank write bursts +system.physmem.perBankRdBursts::11 46739 # Per bank write bursts +system.physmem.perBankRdBursts::12 48771 # Per bank write bursts +system.physmem.perBankRdBursts::13 48997 # Per bank write bursts +system.physmem.perBankRdBursts::14 45133 # Per bank write bursts +system.physmem.perBankRdBursts::15 46835 # Per bank write bursts +system.physmem.perBankWrBursts::0 99610 # Per bank write bursts +system.physmem.perBankWrBursts::1 104326 # Per bank write bursts +system.physmem.perBankWrBursts::2 103481 # Per bank write bursts +system.physmem.perBankWrBursts::3 102430 # Per bank write bursts +system.physmem.perBankWrBursts::4 101747 # Per bank write bursts +system.physmem.perBankWrBursts::5 104971 # Per bank write bursts +system.physmem.perBankWrBursts::6 100056 # Per bank write bursts +system.physmem.perBankWrBursts::7 103888 # Per bank write bursts +system.physmem.perBankWrBursts::8 99840 # Per bank write bursts +system.physmem.perBankWrBursts::9 106110 # Per bank write bursts +system.physmem.perBankWrBursts::10 102643 # Per bank write bursts +system.physmem.perBankWrBursts::11 100858 # Per bank write bursts +system.physmem.perBankWrBursts::12 103355 # Per bank write bursts +system.physmem.perBankWrBursts::13 103593 # Per bank write bursts +system.physmem.perBankWrBursts::14 100350 # Per bank write bursts +system.physmem.perBankWrBursts::15 101960 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 30 # Number of times write queue was full causing retry -system.physmem.totGap 51320645833500 # Total gap between requests +system.physmem.numWrRetry 560 # Number of times write queue was full causing retry +system.physmem.totGap 51320467654000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 21272 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 770259 # Read request sizes (log2) +system.physmem.readPktSize::6 763369 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1691719 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 523893 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 218096 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 11428 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 784 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 412 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 327 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 234 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 123 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 68 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1685966 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 521104 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 214865 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12339 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 553 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 459 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 103 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 81 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 65 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -159,163 +159,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35494 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 67146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 82141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 96477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 97233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 109038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 106907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 116227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 110532 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 123491 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 110542 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 98237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 89628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 89775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 76304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 74747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 73803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 70600 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3795 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3049 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2918 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2759 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2364 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1090 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 882 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 125 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 89 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 519566 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 305.297267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 172.561612 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.602188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 210755 40.56% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 125086 24.08% 64.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 44418 8.55% 73.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 23610 4.54% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15941 3.07% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10357 1.99% 82.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8070 1.55% 84.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7704 1.48% 85.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 73625 14.17% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 519566 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 66165 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 11.954266 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 69.214790 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 66159 99.99% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 25954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 62903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 63057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 90168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 80361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 95410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 92759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 101527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 92557 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 84728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 110064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 78687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 89131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 74275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 70833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 66282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 8883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 7376 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8392 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 9334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 9103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9266 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8245 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 7132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 5765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 2921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1862 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1539 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 512637 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 302.540847 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 171.812512 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.509823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 207576 40.49% 40.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 124268 24.24% 64.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 44401 8.66% 73.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 23774 4.64% 78.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 16232 3.17% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 10193 1.99% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8192 1.60% 84.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 7548 1.47% 86.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 70453 13.74% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 512637 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 56080 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 13.981651 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 75.084718 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 56073 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-1023 5 0.01% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 66165 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 66165 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 25.504330 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 22.270889 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 18.258332 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 44141 66.71% 66.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 6693 10.12% 76.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 8637 13.05% 89.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 2199 3.32% 93.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 1176 1.78% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 430 0.65% 95.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 581 0.88% 96.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 510 0.77% 97.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 438 0.66% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 204 0.31% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 335 0.51% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 211 0.32% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 211 0.32% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 55 0.08% 99.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 142 0.21% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 25 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 36 0.05% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 38 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 22 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 24 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 6 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 9 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-279 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 66165 # Writes before turning the bus around for reads -system.physmem.totQLat 15484448260 # Total ticks spent queuing -system.physmem.totMemAccLat 30315360760 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3954910000 # Total ticks spent in databus transfers -system.physmem.avgQLat 19576.23 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 56080 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 56080 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 29.229993 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 22.064414 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 40.823681 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 46001 82.03% 82.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 3837 6.84% 88.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 4190 7.47% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 975 1.74% 98.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 304 0.54% 98.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 127 0.23% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 99 0.18% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 80 0.14% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 114 0.20% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 122 0.22% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 75 0.13% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 40 0.07% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 26 0.05% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 17 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 12 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 8 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 13 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 10 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 5 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 3 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 4 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-735 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-799 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::896-927 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::992-1023 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1056-1087 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1184-1215 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 56080 # Writes before turning the bus around for reads +system.physmem.totQLat 15388206863 # Total ticks spent queuing +system.physmem.totMemAccLat 30090569363 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3920630000 # Total ticks spent in databus transfers +system.physmem.avgQLat 19624.66 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 38326.23 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 0.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.10 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.97 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.11 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 38374.66 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.96 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.10 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.87 # Average write queue length when enqueuing -system.physmem.readRowHits 603455 # Number of row buffer hits during reads -system.physmem.writeRowHits 1355453 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 80.32 # Row buffer hit rate for writes -system.physmem.avgGap 20645225.93 # Average gap between requests -system.physmem.pageHitRate 79.04 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1965463920 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1072425750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3012968400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5451384240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1226370177675 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29716624044750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34306511542575 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.473889 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49436215199501 # Time in different power states -system.physmem_0.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.46 # Average write queue length when enqueuing +system.physmem.readRowHits 598254 # Number of row buffer hits during reads +system.physmem.writeRowHits 1312451 # Number of row buffer hits during writes +system.physmem.readRowHitRate 76.30 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 80.06 # Row buffer hit rate for writes +system.physmem.avgGap 20750692.59 # Average gap between requests +system.physmem.pageHitRate 78.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1947569400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1062661875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2990566800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5316898320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1226375853165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29716511616000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34306208546520 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.470318 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49436040472112 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713703160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 170722374999 # Time in different power states +system.physmem_0.memoryStateTime::ACT 170725136888 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1962455040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1070784000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3156644400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5483576880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3352015077840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1227684074985 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29715471503250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34306844116395 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.480369 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49434282568001 # Time in different power states -system.physmem_1.memoryStateTime::REF 1713709140000 # Time in different power states +system.physmem_1.actEnergy 1927966320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1051965750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3125569200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5305234320 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3352003380960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1229368112910 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29713886826750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34306669056210 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.479291 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49431639282027 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713703160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 172653903249 # Time in different power states +system.physmem_1.memoryStateTime::ACT 175126075973 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 400 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -339,15 +336,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu.branchPred.lookups 226505876 # Number of BP lookups -system.cpu.branchPred.condPredicted 151515363 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12247822 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 159926869 # Number of BTB lookups -system.cpu.branchPred.BTBHits 104610641 # Number of BTB hits +system.cpu.branchPred.lookups 226088242 # Number of BP lookups +system.cpu.branchPred.condPredicted 151212051 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12236747 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 159576730 # Number of BTB lookups +system.cpu.branchPred.BTBHits 104394184 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 65.411548 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 31076851 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 345252 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 65.419428 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 31024336 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 344701 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -378,87 +375,86 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 931379 # Table walker walks requested -system.cpu.dtb.walker.walksLong 931379 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16662 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 157071 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 405257 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 526122 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 1688.949521 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 11140.838823 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-32767 521687 99.16% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-65535 1343 0.26% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::65536-98303 1868 0.36% 99.77% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::98304-131071 570 0.11% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::131072-163839 209 0.04% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::163840-196607 174 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::196608-229375 58 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::229376-262143 108 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::262144-294911 8 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::294912-327679 3 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::327680-360447 36 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::360448-393215 45 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::393216-425983 11 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 526122 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 461527 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 19818.024831 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 15276.155056 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 15119.150483 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-65535 458117 99.26% 99.26% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-131071 2510 0.54% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-196607 628 0.14% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-262143 155 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-327679 55 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-393215 42 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-458751 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-524287 11 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 461527 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 768881581580 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.740934 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.499994 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 767107299580 99.77% 99.77% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 970542000 0.13% 99.90% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 364225500 0.05% 99.94% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 157799500 0.02% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 120916000 0.02% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 94826000 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 21620500 0.00% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 42242000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 2110500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 768881581580 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 157072 90.41% 90.41% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16662 9.59% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 173734 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 931379 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 945525 # Table walker walks requested +system.cpu.dtb.walker.walksLong 945525 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 17037 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 156802 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 426099 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 519426 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 1842.763936 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 11883.435839 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-32767 513062 98.77% 98.77% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-65535 3320 0.64% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::65536-98303 1249 0.24% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::98304-131071 1137 0.22% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::131072-163839 115 0.02% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::163840-196607 205 0.04% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::196608-229375 84 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::229376-262143 60 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::262144-294911 94 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::294912-327679 5 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::327680-360447 21 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::360448-393215 44 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::393216-425983 30 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 519426 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 477950 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 21079.702044 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 16676.748393 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15514.599645 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 472923 98.95% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 4117 0.86% 99.81% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 574 0.12% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 200 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 75 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 25 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 26 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::589824-655359 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 477950 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 768700308080 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.730043 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.512304 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 766743156580 99.75% 99.75% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 1060609500 0.14% 99.88% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 401667500 0.05% 99.94% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 174666000 0.02% 99.96% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 138312000 0.02% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 106588500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 24500000 0.00% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 48487000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 2321000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 768700308080 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 156803 90.20% 90.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 17037 9.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 173840 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 945525 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 931379 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173734 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 945525 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 173840 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173734 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 1105113 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 173840 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 1119365 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 171278986 # DTB read hits -system.cpu.dtb.read_misses 671795 # DTB read misses -system.cpu.dtb.write_hits 149102166 # DTB write hits -system.cpu.dtb.write_misses 259584 # DTB write misses +system.cpu.dtb.read_hits 170900022 # DTB read hits +system.cpu.dtb.read_misses 675244 # DTB read misses +system.cpu.dtb.write_hits 148749524 # DTB write hits +system.cpu.dtb.write_misses 270281 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 73098 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 106 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 10235 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_tlb_mva_asid 39859 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1027 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 72825 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 117 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 10420 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 69082 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 171950781 # DTB read accesses -system.cpu.dtb.write_accesses 149361750 # DTB write accesses +system.cpu.dtb.perms_faults 69816 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 171575266 # DTB read accesses +system.cpu.dtb.write_accesses 149019805 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 320381152 # DTB hits -system.cpu.dtb.misses 931379 # DTB misses -system.cpu.dtb.accesses 321312531 # DTB accesses +system.cpu.dtb.hits 319649546 # DTB hits +system.cpu.dtb.misses 945525 # DTB misses +system.cpu.dtb.accesses 320595071 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -488,214 +484,209 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 161841 # Table walker walks requested -system.cpu.itb.walker.walksLong 161841 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1421 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 122616 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 17088 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 144753 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 980.521993 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 6808.510178 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-32767 144225 99.64% 99.64% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-65535 131 0.09% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-98303 321 0.22% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::98304-131071 37 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::131072-163839 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 161869 # Table walker walks requested +system.cpu.itb.walker.walksLong 161869 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1433 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 122204 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 17648 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 144221 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 1045.076653 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 6935.040907 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-32767 143697 99.64% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::32768-65535 129 0.09% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-98303 259 0.18% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::98304-131071 98 0.07% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::131072-163839 18 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::163840-196607 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::196608-229375 6 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::229376-262143 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::262144-294911 5 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::229376-262143 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 144753 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 141125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 24337.182009 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 19877.340891 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 15937.232369 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-32767 134420 95.25% 95.25% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-65535 4577 3.24% 98.49% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-98303 1336 0.95% 99.44% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::98304-131071 512 0.36% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-163839 95 0.07% 99.87% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::163840-196607 88 0.06% 99.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-229375 22 0.02% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::229376-262143 28 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-294911 15 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-360447 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::360448-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 141125 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 657209390884 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.938693 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.240123 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 40327296652 6.14% 6.14% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 616846868232 93.86% 99.99% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 34699000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 527000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 657209390884 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 122616 98.85% 98.85% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1421 1.15% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 124037 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 144221 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 141285 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26183.154631 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 21986.379296 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 16137.175101 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-65535 139260 98.57% 98.57% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-131071 1739 1.23% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-196607 189 0.13% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-262143 61 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 141285 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 652736132088 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.935835 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.245289 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 41920855152 6.42% 6.42% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 610778213436 93.57% 99.99% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 36269000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 794000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 652736132088 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 122204 98.84% 98.84% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1433 1.16% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 123637 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161841 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 161841 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 161869 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 161869 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 124037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 124037 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 285878 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 360168043 # ITB inst hits -system.cpu.itb.inst_misses 161841 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 123637 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 123637 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 285506 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 359459512 # ITB inst hits +system.cpu.itb.inst_misses 161869 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 40008 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1029 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 53745 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 39859 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1027 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53398 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 372581 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 372095 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 360329884 # ITB inst accesses -system.cpu.itb.hits 360168043 # DTB hits -system.cpu.itb.misses 161841 # DTB misses -system.cpu.itb.accesses 360329884 # DTB accesses -system.cpu.numCycles 1576983833 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 359621381 # ITB inst accesses +system.cpu.itb.hits 359459512 # DTB hits +system.cpu.itb.misses 161869 # DTB misses +system.cpu.itb.accesses 359621381 # DTB accesses +system.cpu.numCycles 1580751099 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 648826167 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1010661506 # Number of instructions fetch has processed -system.cpu.fetch.Branches 226505876 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 135687492 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 852638415 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 26165882 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 3403646 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 27150 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 9234109 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1027275 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 386 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 359779044 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6134765 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 47734 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 1528240089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.774898 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161407 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 647898483 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1008720689 # Number of instructions fetch has processed +system.cpu.fetch.Branches 226088242 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 135418520 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 855549558 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 26139542 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 3573192 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 26865 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 9268939 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1033386 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 427 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 359070671 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 6123790 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 48662 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 1530420621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.772272 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.159981 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 965897706 63.20% 63.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 215974848 14.13% 77.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 70846962 4.64% 81.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 275520573 18.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 968902908 63.31% 63.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 215807485 14.10% 77.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 71036994 4.64% 82.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 274673234 17.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1528240089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.143632 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.640883 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 527342057 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 504093722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 436470729 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 51063982 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 9269599 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 33921165 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 3872416 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1095869891 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29092135 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 9269599 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 572608237 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 46122541 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 363160924 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 442135288 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 94943500 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1076024490 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 6785579 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 4940621 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 314117 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 587788 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 42830435 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 21754 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 1023810702 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1659713955 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1272840679 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1685189 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 958043687 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 65767012 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 27437914 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23747073 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 104751050 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 175241778 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 152679763 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9977994 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9053000 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1040458161 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 27741753 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1056586315 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 3302783 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 53612674 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 33630584 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 315276 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1528240089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691375 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.927907 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 1530420621 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.143026 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.638127 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 526178421 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 508648126 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 435713994 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 50619608 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 9260472 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 33861678 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 3868815 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1093600087 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 29077129 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 9260472 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 571338545 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 48532565 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 364379914 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 441167933 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 95741192 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1073752213 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 6802962 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 5086497 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 358848 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 628248 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 43820548 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 20190 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 1021575372 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1655508848 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1270030956 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1469892 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 955737015 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 65838354 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27320538 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23636945 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 103635545 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 174900719 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 152333814 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 9971771 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9081144 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1038303468 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 27624460 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1054196021 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 3299994 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 53804457 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 33847358 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 315461 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1530420621 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.688828 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.927358 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 873840021 57.18% 57.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 338263818 22.13% 79.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 236701790 15.49% 94.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 72838134 4.77% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6577115 0.43% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 19211 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 877745445 57.35% 57.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 337069342 22.02% 79.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 236293073 15.44% 94.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 72729594 4.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6564084 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 19083 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1528240089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1530420621 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 58408451 35.14% 35.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 100871 0.06% 35.20% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 26760 0.02% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 763 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.21% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44563063 26.81% 62.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63134312 37.98% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 58206836 35.09% 35.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 99242 0.06% 35.15% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 26725 0.02% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 744 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.17% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44573023 26.87% 62.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 62969604 37.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 727619955 68.87% 68.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2547357 0.24% 69.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 123270 0.01% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 5 0.00% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 57 0.00% 0.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 725956407 68.86% 68.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2542188 0.24% 69.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 123122 0.01% 69.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 69.12% # Type of FU issued @@ -717,102 +708,102 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 69.12% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 15 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 23 0.00% 69.12% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 69.12% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 120690 0.01% 69.13% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 120904 0.01% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.13% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 175181818 16.58% 85.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 150993162 14.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 174804143 16.58% 85.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 150649152 14.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1056586315 # Type of FU issued -system.cpu.iq.rate 0.670005 # Inst issue rate -system.cpu.iq.fu_busy_cnt 166234220 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157331 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3808470802 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1121012820 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1038530652 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 2478919 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 941723 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 907476 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1221261060 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 1559463 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 4354414 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1054196021 # Type of FU issued +system.cpu.iq.rate 0.666896 # Inst issue rate +system.cpu.iq.fu_busy_cnt 165876174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157349 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3805514237 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1118931433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1036122901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 2474593 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 942754 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 909865 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1218517790 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 1554348 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 4347401 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 13859524 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14300 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 143284 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6341204 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 13878328 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14961 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 143108 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6347044 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2565738 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 1859911 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2552620 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1870361 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 9269599 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 6359819 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3950891 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1068424262 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 9260472 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 6554396 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3651492 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1066150871 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 175241778 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 152679763 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23316187 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 61516 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3818793 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 143284 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3692717 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 5135549 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 8828266 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1045377154 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 171268732 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10291027 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 174900719 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 152333814 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23208148 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 59700 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3513413 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 143108 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3675827 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 5121930 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 8797757 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1042985483 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 170888878 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10276947 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 224348 # number of nop insts executed -system.cpu.iew.exec_refs 320367802 # number of memory reference insts executed -system.cpu.iew.exec_branches 198404489 # Number of branches executed -system.cpu.iew.exec_stores 149099070 # Number of stores executed -system.cpu.iew.exec_rate 0.662897 # Inst execution rate -system.cpu.iew.wb_sent 1040225395 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1039438128 # cumulative count of insts written-back -system.cpu.iew.wb_producers 442335874 # num instructions producing a value -system.cpu.iew.wb_consumers 715873221 # num instructions consuming a value +system.cpu.iew.exec_nop 222943 # number of nop insts executed +system.cpu.iew.exec_refs 319634404 # number of memory reference insts executed +system.cpu.iew.exec_branches 197926826 # Number of branches executed +system.cpu.iew.exec_stores 148745526 # Number of stores executed +system.cpu.iew.exec_rate 0.659804 # Inst execution rate +system.cpu.iew.wb_sent 1037843882 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1037032766 # cumulative count of insts written-back +system.cpu.iew.wb_producers 441278048 # num instructions producing a value +system.cpu.iew.wb_consumers 713779914 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.659130 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.617897 # average fanout of values written-back +system.cpu.iew.wb_rate 0.656038 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618227 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 51477037 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 27426477 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 8434480 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1516228883 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.664519 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.292276 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 51563874 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 27308999 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 8427448 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1518403714 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.662019 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.290608 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 998506921 65.85% 65.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 291444279 19.22% 85.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 121999456 8.05% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 36692084 2.42% 95.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28614798 1.89% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14261229 0.94% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8588058 0.57% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4227240 0.28% 99.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 11894818 0.78% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 1001866977 65.98% 65.98% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 290832617 19.15% 85.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 121646355 8.01% 93.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 36740427 2.42% 95.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28447666 1.87% 97.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14105700 0.93% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8667985 0.57% 98.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4229973 0.28% 99.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 11866014 0.78% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1516228883 # Number of insts commited each cycle -system.cpu.commit.committedInsts 857487967 # Number of instructions committed -system.cpu.commit.committedOps 1007562352 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 1518403714 # Number of insts commited each cycle +system.cpu.commit.committedInsts 855512158 # Number of instructions committed +system.cpu.commit.committedOps 1005211605 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 307720812 # Number of memory references committed -system.cpu.commit.loads 161382253 # Number of loads committed -system.cpu.commit.membars 7017472 # Number of memory barriers committed -system.cpu.commit.branches 191417503 # Number of branches committed -system.cpu.commit.fp_insts 895898 # Number of committed floating point instructions. -system.cpu.commit.int_insts 925548459 # Number of committed integer instructions. -system.cpu.commit.function_calls 25509836 # Number of function calls committed. +system.cpu.commit.refs 307009160 # Number of memory references committed +system.cpu.commit.loads 161022390 # Number of loads committed +system.cpu.commit.membars 6998413 # Number of memory barriers committed +system.cpu.commit.branches 190975004 # Number of branches committed +system.cpu.commit.fp_insts 896164 # Number of committed floating point instructions. +system.cpu.commit.int_insts 923410198 # Number of committed integer instructions. +system.cpu.commit.function_calls 25456304 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 697466429 69.22% 69.22% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 2165110 0.21% 69.44% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 98436 0.01% 69.45% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 695830631 69.22% 69.22% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 2161783 0.22% 69.44% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 98401 0.01% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 69.45% # Class of committed instruction @@ -835,236 +826,236 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 69.45% # system.cpu.commit.op_class_0::SimdFloatCmp 13 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 21 0.00% 69.45% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 69.45% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 111523 0.01% 69.46% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 111588 0.01% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.46% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 161382253 16.02% 85.48% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 146338559 14.52% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 161022390 16.02% 85.48% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 145986770 14.52% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 1007562352 # Class of committed instruction -system.cpu.commit.bw_lim_events 11894818 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 1005211605 # Class of committed instruction +system.cpu.commit.bw_lim_events 11866014 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2555751551 # The number of ROB reads -system.cpu.rob.rob_writes 2129995502 # The number of ROB writes -system.cpu.timesIdled 8137427 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 48743744 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 101064310429 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 857487967 # Number of Instructions Simulated -system.cpu.committedOps 1007562352 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.839074 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.839074 # CPI: Total CPI of All Threads -system.cpu.ipc 0.543752 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.543752 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237547063 # number of integer regfile reads -system.cpu.int_regfile_writes 738733043 # number of integer regfile writes -system.cpu.fp_regfile_reads 1457540 # number of floating regfile reads -system.cpu.fp_regfile_writes 782548 # number of floating regfile writes -system.cpu.cc_regfile_reads 228190122 # number of cc regfile reads -system.cpu.cc_regfile_writes 228796042 # number of cc regfile writes -system.cpu.misc_regfile_reads 5248690758 # number of misc regfile reads -system.cpu.misc_regfile_writes 27489325 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9822587 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.985266 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 286182485 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9823099 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.133625 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1485676250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.985266 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999971 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999971 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 2555711925 # The number of ROB reads +system.cpu.rob.rob_writes 2125474325 # The number of ROB writes +system.cpu.timesIdled 8142220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 50330478 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 101060186847 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 855512158 # Number of Instructions Simulated +system.cpu.committedOps 1005211605 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.847725 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.847725 # CPI: Total CPI of All Threads +system.cpu.ipc 0.541206 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.541206 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1234726115 # number of integer regfile reads +system.cpu.int_regfile_writes 737118708 # number of integer regfile writes +system.cpu.fp_regfile_reads 1461359 # number of floating regfile reads +system.cpu.fp_regfile_writes 784484 # number of floating regfile writes +system.cpu.cc_regfile_reads 227546613 # number of cc regfile reads +system.cpu.cc_regfile_writes 228200703 # number of cc regfile writes +system.cpu.misc_regfile_reads 5246257758 # number of misc regfile reads +system.cpu.misc_regfile_writes 27367002 # number of misc regfile writes +system.cpu.dcache.tags.replacements 9794555 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.983548 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 285502634 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9795067 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.147594 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1659133250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.983548 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 380 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 409 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1249763399 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1249763399 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 148780016 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 148780016 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 129548885 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 129548885 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 381333 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 381333 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 324563 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 324563 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3352422 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3352422 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 3751270 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 3751270 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 278328901 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 278328901 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 278710234 # number of overall hits -system.cpu.dcache.overall_hits::total 278710234 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9497038 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9497038 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 11468447 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 11468447 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1197141 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1197141 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233328 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1233328 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 450623 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 450623 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 20965485 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 20965485 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 22162626 # number of overall misses -system.cpu.dcache.overall_misses::total 22162626 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 140713387644 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 140713387644 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 321962948230 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 321962948230 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 38655244426 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 38655244426 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6327424004 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 6327424004 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 139001 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 139001 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 462676335874 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 462676335874 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 462676335874 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 462676335874 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 158277054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 158277054 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 141017332 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 141017332 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1578474 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1578474 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557891 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1557891 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3803045 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 3803045 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 3751275 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 3751275 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 299294386 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 299294386 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 300872860 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 300872860 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060003 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.060003 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081327 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.081327 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758417 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.758417 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.791665 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.791665 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.118490 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.118490 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.070050 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.070050 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.073661 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.073661 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14816.555187 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14816.555187 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28073.805305 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28073.805305 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 31342.225609 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 31342.225609 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14041.502551 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14041.502551 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 27800.200000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 27800.200000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22068.477589 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22068.477589 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 20876.422129 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 20876.422129 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21410972 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 1246939843 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1246939843 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 148420477 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 148420477 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 129257116 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 129257116 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 380071 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 380071 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 323830 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 323830 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3338713 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3338713 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3738459 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3738459 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 277677593 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 277677593 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 278057664 # number of overall hits +system.cpu.dcache.overall_hits::total 278057664 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9529450 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9529450 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 11422113 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 11422113 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1191409 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1191409 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1233320 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1233320 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 451226 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 451226 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 6 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 20951563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 20951563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 22142972 # number of overall misses +system.cpu.dcache.overall_misses::total 22142972 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 145395860730 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 145395860730 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 336812014094 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 336812014094 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 35299806246 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 35299806246 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 6459718484 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 6459718484 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 237001 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 237001 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 482207874824 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 482207874824 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 482207874824 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 482207874824 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 157949927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 157949927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 140679229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 140679229 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1571480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1571480 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1557150 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1557150 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3789939 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3789939 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3738465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3738465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 298629156 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 298629156 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 300200636 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 300200636 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.060332 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.060332 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081193 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081193 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.758145 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.758145 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.792037 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.792037 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.119059 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.070159 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.070159 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.073761 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.073761 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15257.529105 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15257.529105 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29487.715110 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29487.715110 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 28621.773948 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 28621.773948 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14315.927017 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14315.927017 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 39500.166667 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 39500.166667 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23015.365241 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23015.365241 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21777.016871 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21777.016871 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20545206 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1402072 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1559097 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.270950 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.177632 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7597183 # number of writebacks -system.cpu.dcache.writebacks::total 7597183 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4319062 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4319062 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9426489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9426489 # number of WriteReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7148 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7148 # number of WriteInvalidateReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220034 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 220034 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 13745551 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 13745551 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 13745551 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 13745551 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5177976 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5177976 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2041958 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2041958 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1190352 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1190352 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226180 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226180 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 230589 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 230589 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7219934 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7219934 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8410286 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8410286 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70110899674 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 70110899674 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53589743024 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53589743024 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 18780468745 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 18780468745 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 35955294132 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 35955294132 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2813771248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2813771248 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 128999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 128999 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123700642698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123700642698 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 142481111443 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 142481111443 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5729238749 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5729238749 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5587095483 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5587095483 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11316334232 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11316334232 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032715 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032715 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014480 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.754116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.754116 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787077 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787077 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060633 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060633 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024123 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024123 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027953 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.027953 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13540.213333 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13540.213333 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26244.292500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26244.292500 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15777.239627 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15777.239627 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 29323.014673 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29323.014673 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12202.538924 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12202.538924 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 25799.800000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17133.209625 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17133.209625 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16941.292061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16941.292061 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 7577660 # number of writebacks +system.cpu.dcache.writebacks::total 7577660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4366240 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4366240 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9388231 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9388231 # number of WriteReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::cpu.data 7155 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.WriteInvalidateReq_mshr_hits::total 7155 # number of WriteInvalidateReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 220115 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 220115 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 13754471 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 13754471 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 13754471 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 13754471 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5163210 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5163210 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2033882 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2033882 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1184642 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1184642 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1226165 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1226165 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 231111 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 231111 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 7197092 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 56871439750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19552019274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19552019274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 33205804688 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 33205804688 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2956928250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2956928250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 227999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 227999 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 130497994329 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 130497994329 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150050013603 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 150050013603 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5746385500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5746385500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5629281968 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5629281968 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11375667468 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11375667468 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032689 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032689 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014458 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014458 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.753838 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.753838 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.787442 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787442 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.060980 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024100 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024100 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.027920 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.027920 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14259.841180 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14259.841180 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27962.015373 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27962.015373 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 16504.580518 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 16504.580518 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 27081.024730 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27081.024730 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12794.407233 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12794.407233 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 37999.833333 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 37999.833333 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18132.044766 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1072,277 +1063,276 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 15084162 # number of replacements -system.cpu.icache.tags.tagsinuse 511.954207 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 343955623 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 15084674 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 22.801661 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 14174936000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.954207 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999911 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 15070815 # number of replacements +system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 343233622 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 15071327 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 22.773948 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 14049577000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.953323 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 102 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 374842526 # Number of tag accesses -system.cpu.icache.tags.data_accesses 374842526 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 343955623 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 343955623 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 343955623 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 343955623 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 343955623 # number of overall hits -system.cpu.icache.overall_hits::total 343955623 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 15802123 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 15802123 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 15802123 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 15802123 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 15802123 # number of overall misses -system.cpu.icache.overall_misses::total 15802123 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 208192919846 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 208192919846 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 208192919846 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 208192919846 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 208192919846 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 208192919846 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 359757746 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 359757746 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 359757746 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 359757746 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 359757746 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 359757746 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043924 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.043924 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.043924 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.043924 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.043924 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.043924 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13174.996793 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13174.996793 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13174.996793 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13174.996793 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13174.996793 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 11061 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 374120916 # Number of tag accesses +system.cpu.icache.tags.data_accesses 374120916 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 343233622 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 343233622 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 343233622 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 343233622 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 343233622 # number of overall hits +system.cpu.icache.overall_hits::total 343233622 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 15815747 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 15815747 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 15815747 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 15815747 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 15815747 # number of overall misses +system.cpu.icache.overall_misses::total 15815747 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 208885866517 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 208885866517 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 208885866517 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 208885866517 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 208885866517 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 208885866517 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 359049369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 359049369 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 359049369 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 359049369 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 359049369 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 359049369 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.044049 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.044049 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.044049 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.044049 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.044049 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.044049 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13207.461305 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13207.461305 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13207.461305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.461305 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13207.461305 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 13684 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 978 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1126 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 11.309816 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 12.152753 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 717343 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 717343 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 717343 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 717343 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 717343 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 717343 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15084780 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 15084780 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 15084780 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 15084780 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 15084780 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 15084780 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 171798629050 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 171798629050 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 171798629050 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 171798629050 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 171798629050 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 171798629050 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1412899000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1412899000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1412899000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 1412899000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041930 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.041930 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041930 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.041930 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11388.872032 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11388.872032 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11388.872032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11388.872032 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 744199 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 744199 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 744199 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 744199 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 744199 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 744199 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 15071548 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 15071548 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 15071548 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 179787086612 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 179787086612 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 179787086612 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 1585009250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 1585009250 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 1585009250 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 1585009250 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.041976 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.041976 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.041976 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.041976 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11928.906481 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11928.906481 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1166252 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65308.801684 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29080427 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1229042 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 23.661052 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 2430267000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37210.550558 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 324.848912 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 496.111863 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 7620.063188 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19657.227164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.567788 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004957 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007570 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.116273 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.299945 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996533 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 301 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62489 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 300 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 518 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2670 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54081 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004593 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953506 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 273259305 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 273259305 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 799874 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 299425 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 15000245 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6339023 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22438567 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7597183 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7597183 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730326 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 730326 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 9466 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 9466 # number of UpgradeReq hits +system.cpu.l2cache.tags.replacements 1159288 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 29043191 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1221496 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.776739 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2756226000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 37273.751083 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 319.528316 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 474.614102 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 7535.726920 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19669.377573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.568752 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004876 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.007242 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.114986 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.300131 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 61904 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 579 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2674 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5116 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 53473 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.944580 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 272839925 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 272839925 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 805883 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 304376 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 14986718 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6321707 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 22418684 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7577660 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7577660 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 730602 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 730602 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 9499 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 9499 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1583904 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1583904 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 799874 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 299425 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 15000245 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7922927 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24022471 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 799874 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 299425 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 15000245 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7922927 # number of overall hits -system.cpu.l2cache.overall_hits::total 24022471 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3543 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3208 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 84445 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 256196 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 347392 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495854 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 495854 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 34479 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 34479 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 417812 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 417812 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 3543 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 3208 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 84445 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 674008 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 765204 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 3543 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 3208 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 84445 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 674008 # number of overall misses -system.cpu.l2cache.overall_misses::total 765204 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 284358999 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 261200750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6500329478 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21309046436 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28354935663 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 3493350 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 3493350 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 414507203 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 414507203 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 72000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 72000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34565495113 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 34565495113 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 284358999 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 261200750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6500329478 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 55874541549 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 62920430776 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 284358999 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 261200750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6500329478 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 55874541549 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 62920430776 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 803417 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 302633 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 15084690 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 6595219 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 22785959 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 7597183 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7597183 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226180 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226180 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 43945 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2001716 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2001716 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 803417 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 302633 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 15084690 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 8596935 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 24787675 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 803417 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 302633 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 15084690 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 8596935 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 24787675 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.004410 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.010600 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005598 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038846 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015246 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404389 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404389 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.784594 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.784594 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.208727 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.208727 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.004410 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.010600 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005598 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.078401 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.030870 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.004410 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.010600 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005598 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.078401 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.030870 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 80259.384420 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81421.680175 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76977.079496 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83174.781948 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 81622.304667 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 7.045118 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 7.045118 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12022.019287 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12022.019287 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 36000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 36000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82729.780650 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82729.780650 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82227.001918 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 80259.384420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81421.680175 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76977.079496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82898.929314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82227.001918 # average overall miss latency +system.cpu.l2cache.ReadExReq_hits::cpu.data 1579833 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1579833 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 805883 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 304376 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14986718 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7901540 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 23998517 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 805883 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 304376 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14986718 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 7901540 # number of overall hits +system.cpu.l2cache.overall_hits::total 23998517 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 3166 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3020 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 84629 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 253686 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 344501 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 495562 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 495562 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 34430 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 34430 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 413693 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 413693 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 3166 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3020 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 84629 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 667379 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 758194 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 3166 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3020 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 84629 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 667379 # number of overall misses +system.cpu.l2cache.overall_misses::total 758194 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 276962259 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 263518500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 7145038838 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22760355464 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30445875061 # number of ReadReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 4785347 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 4785347 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 553374801 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 553374801 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 36882340129 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 36882340129 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 276962259 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 263518500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 7145038838 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 59642695593 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 67328215190 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 276962259 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 263518500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 7145038838 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 59642695593 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 67328215190 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 809049 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 307396 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 15071347 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 6575393 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 22763185 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7577660 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7577660 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1226164 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::total 1226164 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 43929 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 43929 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 6 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1993526 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1993526 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 809049 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 307396 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 15071347 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8568919 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 24756711 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 809049 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 307396 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 15071347 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8568919 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 24756711 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.003913 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.009824 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005615 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.038581 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015134 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.404156 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.404156 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783765 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783765 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.207518 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.207518 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.003913 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.009824 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005615 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.077884 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.030626 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.003913 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.009824 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005615 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.077884 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.030626 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87480.182881 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 87257.781457 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 84427.782888 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89718.610660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 88376.739287 # average ReadReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 9.656404 # average WriteInvalidateReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 9.656404 # average WriteInvalidateReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16072.460093 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16072.460093 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 53000 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 53000 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89153.889790 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89153.889790 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 88800.775514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87480.182881 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 87257.781457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84427.782888 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89368.553091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 88800.775514 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1351,114 +1341,114 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 982720 # number of writebacks -system.cpu.l2cache.writebacks::total 982720 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 977263 # number of writebacks +system.cpu.l2cache.writebacks::total 977263 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 21 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 21 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 21 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 21 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3543 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3208 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84445 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256175 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 347371 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495854 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495854 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34479 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 34479 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 417812 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 417812 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3543 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3208 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 84445 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 673987 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 765183 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3543 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3208 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 84445 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 673987 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 765183 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 240086499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 221074750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5441255518 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18116835264 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24019252031 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 19575424791 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 19575424791 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 345346475 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 345346475 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 70001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 70001 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 29394156879 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 29394156879 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 240086499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 221074750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5441255518 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47510992143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 53413408910 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 240086499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 221074750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5441255518 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47510992143 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 53413408910 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1103864500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5289749251 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6393613751 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5176073500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5176073500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1103864500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10465822751 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11569687251 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038843 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015245 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404389 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404389 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.784594 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.784594 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.208727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.208727 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.030869 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.004410 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.010600 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005598 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.078399 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.030869 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64435.496690 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.543628 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69145.818249 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 39478.202840 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 39478.202840 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10016.139534 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10016.139534 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 35000.500000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70352.591307 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70352.591307 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67763.618120 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68913.575436 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64435.496690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70492.445912 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69804.751164 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 3166 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3020 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 84629 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 253665 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 344480 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 495562 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 495562 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 34430 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 34430 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 413693 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 413693 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 3166 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3020 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 84629 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 667358 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 758173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 3166 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3020 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19591961036 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26140194449 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16855177398 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16855177398 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 611252927 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 611252927 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 153001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 153001 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31729551871 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31729551871 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 237171251 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 225518000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6085544162 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51321512907 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 57869746320 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 237171251 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 225518000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6085544162 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51321512907 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 57869746320 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 1276231250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5274563500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 6550794750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5186666500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5186666500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 1276231250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10461230000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11737461250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.038578 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015133 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.404156 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.404156 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783765 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783765 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.207518 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.207518 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.030625 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.003913 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.009824 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005615 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.077881 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.030625 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71908.496638 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77235.570678 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75883.054021 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 34012.247505 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34012.247505 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17753.497735 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17753.497735 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 51000.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 51000.333333 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76698.304953 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76698.304953 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 74911.955464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 74674.834437 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1468,62 +1458,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23340437 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23332371 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33858 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7597183 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332844 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226180 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 43948 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 43953 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2001716 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2001716 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30212060 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27467336 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 733813 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1968769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 60381978 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 965760880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1115140164 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2421064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6427336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2089749444 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 606880 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 34513008 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003347 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.057757 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7577660 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1332936 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1226164 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 43932 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 6 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 43938 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1993526 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1993526 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 30185484 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27390990 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 736951 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1962535 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 60275960 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 964906864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1112084525 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2459168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 583028 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.003382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 34397489 99.67% 99.67% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115519 0.33% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 34071281 99.66% 99.66% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115623 0.34% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 34513008 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 26212619005 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1180500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 22673982421 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 22654600125 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 13673864954 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 13659008538 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 432131982 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 430754363 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 1166119344 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 1154477924 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40381 # Transaction distribution -system.iobus.trans_dist::ReadResp 40381 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40283 # Transaction distribution +system.iobus.trans_dist::ReadResp 40283 # Transaction distribution +system.iobus.trans_dist::WriteReq 136558 # Transaction distribution +system.iobus.trans_dist::WriteResp 29894 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1533,18 +1521,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29496 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122652 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230950 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354228 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353682 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1554,18 +1542,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17529 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334264 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334264 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155805 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334232 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492670 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492123 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1585,7 +1573,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 21947000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21908000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -1593,71 +1581,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042349161 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607064814 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92761000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179004202 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148363066 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115461 # number of replacements -system.iocache.tags.tagsinuse 10.424617 # Cycle average of tags in use +system.iocache.tags.replacements 115456 # number of replacements +system.iocache.tags.tagsinuse 10.424607 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115472 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13092188806000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.544621 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.879997 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221539 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430000 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651539 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13092103918000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544640 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.879967 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429998 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651538 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039668 # Number of tag accesses -system.iocache.tags.data_accesses 1039668 # Number of data accesses +system.iocache.tags.tag_accesses 1039632 # Number of tag accesses +system.iocache.tags.data_accesses 1039632 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8815 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8852 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8811 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8848 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8815 # number of demand (read+write) misses -system.iocache.demand_misses::total 8855 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8811 # number of demand (read+write) misses +system.iocache.demand_misses::total 8851 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8815 # number of overall misses -system.iocache.overall_misses::total 8855 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5527000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1934147111 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1939674111 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28899223848 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28899223848 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5866000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1934147111 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1940013111 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5866000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1934147111 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1940013111 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8811 # number of overall misses +system.iocache.overall_misses::total 8851 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1609809480 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1614881480 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19830913268 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19830913268 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1609809480 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1615233980 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1609809480 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1615233980 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8815 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8852 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8811 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8848 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8815 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8855 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8811 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8851 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8815 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8855 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8811 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8851 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1671,55 +1659,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 149378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 219415.440839 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 219122.696679 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270936.997000 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270936.997000 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 219086.743196 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 146650 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 219415.440839 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 219086.743196 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 225873 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 182704.514811 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 182513.729656 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185919.459874 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185919.459874 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 182491.693594 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 182704.514811 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 182491.693594 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110252 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27588 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16154 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.187364 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.825059 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8815 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8852 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8811 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8848 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8815 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8855 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8811 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8851 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8815 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8855 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3603000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1475641121 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1479244121 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23352302242 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23352302242 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3786000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1475641121 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1479427121 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3786000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1475641121 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1479427121 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8811 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8851 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1150531536 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1153673536 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14284309344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14284309344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1150531536 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1153867036 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1150531536 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1153867036 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1733,71 +1721,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 97378.378378 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 167401.148157 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 167108.463737 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218933.306851 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218933.306851 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 94650 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 167401.148157 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 167072.515076 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 130578.996255 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 130388.057866 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133918.748069 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133918.748069 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 130578.996255 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 130365.725455 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 411277 # Transaction distribution -system.membus.trans_dist::ReadResp 411277 # Transaction distribution -system.membus.trans_dist::WriteReq 33858 # Transaction distribution -system.membus.trans_dist::WriteResp 33858 # Transaction distribution -system.membus.trans_dist::Writeback 1089351 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 602368 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 602368 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35261 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35263 # Transaction distribution -system.membus.trans_dist::ReadExReq 417183 # Transaction distribution -system.membus.trans_dist::ReadExResp 417183 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 408284 # Transaction distribution +system.membus.trans_dist::ReadResp 408284 # Transaction distribution +system.membus.trans_dist::WriteReq 33682 # Transaction distribution +system.membus.trans_dist::WriteResp 33682 # Transaction distribution +system.membus.trans_dist::Writeback 1083893 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 602073 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 602073 # Transaction distribution +system.membus.trans_dist::UpgradeReq 35223 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.membus.trans_dist::UpgradeResp 35226 # Transaction distribution +system.membus.trans_dist::ReadExReq 413056 # Transaction distribution +system.membus.trans_dist::ReadExResp 413056 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122652 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6858 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3620810 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3750918 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335177 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4086095 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6848 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3600651 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3730211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335301 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4065512 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155805 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 436 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13716 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143869516 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 144039988 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14058112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14058112 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 158098100 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3154 # Total snoops (count) -system.membus.snoop_fanout::samples 2500418 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13696 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 143052172 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 143222109 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14066304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3023 # Total snoops (count) +system.membus.snoop_fanout::samples 2488136 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2500418 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2500418 # Request fanout histogram -system.membus.reqLayer0.occupancy 109711500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2488136 # Request fanout histogram +system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 42500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5440999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5439500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16316164477 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9540063820 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 7830132924 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4726359104 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186594798 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151502434 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -1842,6 +1830,6 @@ system.realview.ethernet.coalescedTotal 0 # av system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16179 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 16160 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt index e7103dcb2..8e7b17b1a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-full/stats.txt @@ -1,173 +1,173 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.234984 # Number of seconds simulated -sim_ticks 51234983764500 # Number of ticks simulated -final_tick 51234983764500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.274696 # Number of seconds simulated +sim_ticks 51274696167500 # Number of ticks simulated +final_tick 51274696167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 293597 # Simulator instruction rate (inst/s) -host_op_rate 345003 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16999127000 # Simulator tick rate (ticks/s) -host_mem_usage 723216 # Number of bytes of host memory used -host_seconds 3013.98 # Real time elapsed on the host -sim_insts 884896163 # Number of instructions simulated -sim_ops 1039832130 # Number of ops (including micro ops) simulated +host_inst_rate 298693 # Simulator instruction rate (inst/s) +host_op_rate 350975 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17280969451 # Simulator tick rate (ticks/s) +host_mem_usage 723560 # Number of bytes of host memory used +host_seconds 2967.12 # Real time elapsed on the host +sim_insts 886256415 # Number of instructions simulated +sim_ops 1041383802 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 129856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 125184 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2903796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24969352 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 34560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 29888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 811648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 7348736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 94656 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 89280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 2169408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 17774080 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 413120 # Number of bytes read from this memory -system.physmem.bytes_read::total 56893564 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2903796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 811648 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 2169408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5884852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 77105472 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 116160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 120000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2956980 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 25219400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 40192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 37376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 753536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 7117376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 92544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 94080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 2191808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 17867136 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 430080 # Number of bytes read from this memory +system.physmem.bytes_read::total 57036668 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2956980 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 753536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 2191808 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5902324 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77190720 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 77126052 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 85779 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 390159 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 467 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 114824 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 1479 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1395 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 33897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 277720 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6455 # Number of read requests responded to by this memory -system.physmem.num_reads::total 929382 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1204773 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77211300 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1815 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1875 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 86610 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 394066 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 584 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 11774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 111209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 1446 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1470 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 34247 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 279174 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6720 # Number of read requests responded to by this memory +system.physmem.num_reads::total 931618 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1206105 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1207346 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2443 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 56676 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 487350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 675 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 15842 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 143432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 1847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 1743 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 42342 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 346913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1110444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 56676 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 15842 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 42342 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 114860 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1504938 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1505340 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1504938 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2443 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 56676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 487751 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 675 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 15842 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 143432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 1847 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 1743 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 42342 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 346913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2615783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 443127 # Number of read requests accepted -system.physmem.writeReqs 607625 # Number of write requests accepted -system.physmem.readBursts 443127 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 607625 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28344960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 15168 # Total number of bytes read from write queue -system.physmem.bytesWritten 38801344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28360128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 38888000 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 237 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 1354 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 18550 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25211 # Per bank write bursts -system.physmem.perBankRdBursts::1 29295 # Per bank write bursts -system.physmem.perBankRdBursts::2 27890 # Per bank write bursts -system.physmem.perBankRdBursts::3 27887 # Per bank write bursts -system.physmem.perBankRdBursts::4 27824 # Per bank write bursts -system.physmem.perBankRdBursts::5 30839 # Per bank write bursts -system.physmem.perBankRdBursts::6 26245 # Per bank write bursts -system.physmem.perBankRdBursts::7 26732 # Per bank write bursts -system.physmem.perBankRdBursts::8 26610 # Per bank write bursts -system.physmem.perBankRdBursts::9 29578 # Per bank write bursts -system.physmem.perBankRdBursts::10 29152 # Per bank write bursts -system.physmem.perBankRdBursts::11 31219 # Per bank write bursts -system.physmem.perBankRdBursts::12 26466 # Per bank write bursts -system.physmem.perBankRdBursts::13 26838 # Per bank write bursts -system.physmem.perBankRdBursts::14 25148 # Per bank write bursts -system.physmem.perBankRdBursts::15 25956 # Per bank write bursts -system.physmem.perBankWrBursts::0 36103 # Per bank write bursts -system.physmem.perBankWrBursts::1 37925 # Per bank write bursts -system.physmem.perBankWrBursts::2 36544 # Per bank write bursts -system.physmem.perBankWrBursts::3 38823 # Per bank write bursts -system.physmem.perBankWrBursts::4 41056 # Per bank write bursts -system.physmem.perBankWrBursts::5 42229 # Per bank write bursts -system.physmem.perBankWrBursts::6 37594 # Per bank write bursts -system.physmem.perBankWrBursts::7 36950 # Per bank write bursts -system.physmem.perBankWrBursts::8 37999 # Per bank write bursts -system.physmem.perBankWrBursts::9 38649 # Per bank write bursts -system.physmem.perBankWrBursts::10 38477 # Per bank write bursts -system.physmem.perBankWrBursts::11 38558 # Per bank write bursts -system.physmem.perBankWrBursts::12 34649 # Per bank write bursts -system.physmem.perBankWrBursts::13 36757 # Per bank write bursts -system.physmem.perBankWrBursts::14 36686 # Per bank write bursts -system.physmem.perBankWrBursts::15 37272 # Per bank write bursts +system.physmem.num_writes::total 1208678 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2265 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 57669 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 491849 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 138809 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 1805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 1835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 42746 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 348459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1112375 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 57669 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14696 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 42746 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 115112 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1505435 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1505836 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1505435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2265 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 57669 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 492250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 138809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 1805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 1835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 42746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 348459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8388 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2618211 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 440592 # Number of read requests accepted +system.physmem.writeReqs 615308 # Number of write requests accepted +system.physmem.readBursts 440592 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 615308 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 28181248 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue +system.physmem.bytesWritten 38332736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 28197888 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 39379712 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 16359 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 18561 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25854 # Per bank write bursts +system.physmem.perBankRdBursts::1 28544 # Per bank write bursts +system.physmem.perBankRdBursts::2 25469 # Per bank write bursts +system.physmem.perBankRdBursts::3 27506 # Per bank write bursts +system.physmem.perBankRdBursts::4 26728 # Per bank write bursts +system.physmem.perBankRdBursts::5 30588 # Per bank write bursts +system.physmem.perBankRdBursts::6 26415 # Per bank write bursts +system.physmem.perBankRdBursts::7 27502 # Per bank write bursts +system.physmem.perBankRdBursts::8 26500 # Per bank write bursts +system.physmem.perBankRdBursts::9 31676 # Per bank write bursts +system.physmem.perBankRdBursts::10 27941 # Per bank write bursts +system.physmem.perBankRdBursts::11 30917 # Per bank write bursts +system.physmem.perBankRdBursts::12 25895 # Per bank write bursts +system.physmem.perBankRdBursts::13 27920 # Per bank write bursts +system.physmem.perBankRdBursts::14 25066 # Per bank write bursts +system.physmem.perBankRdBursts::15 25811 # Per bank write bursts +system.physmem.perBankWrBursts::0 36067 # Per bank write bursts +system.physmem.perBankWrBursts::1 36031 # Per bank write bursts +system.physmem.perBankWrBursts::2 34636 # Per bank write bursts +system.physmem.perBankWrBursts::3 37309 # Per bank write bursts +system.physmem.perBankWrBursts::4 37132 # Per bank write bursts +system.physmem.perBankWrBursts::5 40234 # Per bank write bursts +system.physmem.perBankWrBursts::6 38375 # Per bank write bursts +system.physmem.perBankWrBursts::7 37986 # Per bank write bursts +system.physmem.perBankWrBursts::8 35542 # Per bank write bursts +system.physmem.perBankWrBursts::9 42123 # Per bank write bursts +system.physmem.perBankWrBursts::10 38624 # Per bank write bursts +system.physmem.perBankWrBursts::11 39603 # Per bank write bursts +system.physmem.perBankWrBursts::12 35582 # Per bank write bursts +system.physmem.perBankWrBursts::13 38033 # Per bank write bursts +system.physmem.perBankWrBursts::14 36333 # Per bank write bursts +system.physmem.perBankWrBursts::15 35339 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 11 # Number of times write queue was full causing retry -system.physmem.totGap 51233787261500 # Total gap between requests +system.physmem.numWrRetry 73 # Number of times write queue was full causing retry +system.physmem.totGap 51273531025000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 443127 # Read request sizes (log2) +system.physmem.readPktSize::6 440592 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 607625 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 312054 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 88763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 29344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12555 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 615308 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 297815 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 95022 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 32137 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -180,199 +180,206 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 477 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 472 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 474 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 474 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 469 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 468 # What write queue length does an incoming req see system.physmem.wrQLenPdf::8 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 465 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 464 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 457 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 12737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 24672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 28080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 33366 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 36383 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 37105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 38583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 39124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 40093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 39396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 38019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 37237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 37691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 33410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 31074 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1296 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 828 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 536 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 490 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 435 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 54 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 274343 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 244.749383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.139289 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 288.784627 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 125431 45.72% 45.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 68607 25.01% 70.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 24542 8.95% 79.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12363 4.51% 84.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8633 3.15% 87.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 5464 1.99% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4467 1.63% 90.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3979 1.45% 92.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20857 7.60% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 274343 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 29886 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 14.819313 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 10.330264 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-15 12451 41.66% 41.66% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16-31 16121 53.94% 95.60% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::32-47 1059 3.54% 99.15% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::48-63 175 0.59% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::64-79 53 0.18% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::80-95 15 0.05% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::96-111 5 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::9 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 12335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 14792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 22598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 26146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 30213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 32129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 33829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 34268 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 34523 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 35690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 34679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 37755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 35326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 34217 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 40396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 33787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 31090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2306 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1698 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1514 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 914 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 367 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 335 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 148 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 182 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 276595 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 240.471737 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 144.485529 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.203347 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 127319 46.03% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 69542 25.14% 71.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 24812 8.97% 80.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 12377 4.47% 84.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 8866 3.21% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 5372 1.94% 89.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4514 1.63% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3651 1.32% 92.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20142 7.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 276595 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 29231 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 15.063871 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10.425422 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-15 11898 40.70% 40.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::16-31 15954 54.58% 95.28% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::32-47 1083 3.70% 98.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::48-63 204 0.70% 99.69% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::64-79 56 0.19% 99.88% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::80-95 22 0.08% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::96-111 6 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::112-127 2 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::128-143 2 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::160-175 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-271 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::304-319 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 29886 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 29886 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.286121 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.739916 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.649180 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 14 0.05% 0.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 35 0.12% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 26501 88.67% 88.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 1006 3.37% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 913 3.05% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 433 1.45% 96.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 255 0.85% 97.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 96 0.32% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 167 0.56% 98.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 135 0.45% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 90 0.30% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 37 0.12% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 67 0.22% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 27 0.09% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 22 0.07% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 15 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 37 0.12% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 6 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 2 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 4 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 7 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 4 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 3 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 3 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 29886 # Writes before turning the bus around for reads -system.physmem.totQLat 10134279500 # Total ticks spent queuing -system.physmem.totMemAccLat 18438467000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2214450000 # Total ticks spent in databus transfers -system.physmem.avgQLat 22882.16 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::176-191 2 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::288-303 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::320-335 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 29231 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 29231 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.490199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.518949 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 18.634153 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 58 0.20% 0.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 27476 94.00% 94.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 804 2.75% 96.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 250 0.86% 97.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 169 0.58% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 102 0.35% 98.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 99 0.34% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 124 0.42% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 61 0.21% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 8 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 19 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 14 0.05% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 5 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 2 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 1 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 3 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 7 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 29231 # Writes before turning the bus around for reads +system.physmem.totQLat 10175638298 # Total ticks spent queuing +system.physmem.totMemAccLat 18431863298 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2201660000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23109.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41632.16 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 41859.01 # Average memory access latency per DRAM burst system.physmem.avgRdBW 0.55 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 0.75 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 0.55 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.76 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.77 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.01 # Data bus utilization in percentage system.physmem.busUtilRead 0.00 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.35 # Average write queue length when enqueuing -system.physmem.readRowHits 333517 # Number of row buffer hits during reads -system.physmem.writeRowHits 441289 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 72.79 # Row buffer hit rate for writes -system.physmem.avgGap 48759162.26 # Average gap between requests -system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1059231600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 575701500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1730999400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1990714320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3304502351280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1163638516455 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29573392417500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34046889932055 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.714209 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 48801846776250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1689418380000 # Time in different power states +system.physmem.avgWrQLen 25.67 # Average write queue length when enqueuing +system.physmem.readRowHits 330665 # Number of row buffer hits during reads +system.physmem.writeRowHits 432014 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.09 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 72.13 # Row buffer hit rate for writes +system.physmem.avgGap 48559078.53 # Average gap between requests +system.physmem.pageHitRate 73.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1047672360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 569481000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1705126800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1929536640 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3307165171440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1163738784870 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29596559989500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34072715762610 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.713146 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 48842268608197 # Time in different power states +system.physmem_0.memoryStateTime::REF 1690779740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 103138521750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102045610303 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1014703200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 551648625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1723542600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 1937720880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3304502351280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1160546619285 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29579668954500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34049945540370 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.696345 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 48806318983250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1689418380000 # Time in different power states +system.physmem_1.actEnergy 1043355600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 567088500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1729462800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 1951549200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3307165171440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1164487973490 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29604202640250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34081147241280 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.697375 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 48841133395944 # Time in different power states +system.physmem_1.memoryStateTime::REF 1690779740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 98691186250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 103204176556 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu2.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 196 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 96 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu2.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 29 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu2.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 30 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 3 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu2.inst 1 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 2 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu2.inst 1 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 3 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu2.inst 1 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). @@ -409,48 +416,48 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 113519 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 113519 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 113519 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 113519 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 113519 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 1125423795568 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.567721 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.495393 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 486496827068 43.23% 43.23% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 638926968500 56.77% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 1125423795568 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 82853 84.60% 84.60% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 15081 15.40% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 97934 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 113519 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 113114 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 113114 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 113114 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 113114 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 113114 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 1113616699016 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.572841 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.494666 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 475691482516 42.72% 42.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 637925216500 57.28% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1113616699016 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 82726 84.85% 84.85% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 14770 15.15% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 97496 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 113114 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 113519 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97934 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 113114 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 97496 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97934 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 211453 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 97496 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 210610 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 78562985 # DTB read hits -system.cpu0.dtb.read_misses 85240 # DTB read misses -system.cpu0.dtb.write_hits 72018023 # DTB write hits -system.cpu0.dtb.write_misses 28279 # DTB write misses -system.cpu0.dtb.flush_tlb 1287 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 78321186 # DTB read hits +system.cpu0.dtb.read_misses 84847 # DTB read misses +system.cpu0.dtb.write_hits 71529400 # DTB write hits +system.cpu0.dtb.write_misses 28267 # DTB write misses +system.cpu0.dtb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21013 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 51639 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 20997 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 507 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 51007 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 3776 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4028 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9794 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 78648225 # DTB read accesses -system.cpu0.dtb.write_accesses 72046302 # DTB write accesses +system.cpu0.dtb.perms_faults 9780 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 78406033 # DTB read accesses +system.cpu0.dtb.write_accesses 71557667 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 150581008 # DTB hits -system.cpu0.dtb.misses 113519 # DTB misses -system.cpu0.dtb.accesses 150694527 # DTB accesses +system.cpu0.dtb.hits 149850586 # DTB hits +system.cpu0.dtb.misses 113114 # DTB misses +system.cpu0.dtb.accesses 149963700 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -480,432 +487,430 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 63212 # Table walker walks requested -system.cpu0.itb.walker.walksLong 63212 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 63212 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 63212 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 63212 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 1125423794068 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.567766 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.495387 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 486446960568 43.22% 43.22% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 638976833500 56.78% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 1125423794068 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54978 95.14% 95.14% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2806 4.86% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 57784 # Table walker page sizes translated +system.cpu0.itb.walker.walks 63285 # Table walker walks requested +system.cpu0.itb.walker.walksLong 63285 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 63285 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 63285 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 63285 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 1113616695516 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.572887 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.494659 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 475639854016 42.71% 42.71% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 637976841500 57.29% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1113616695516 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 55054 95.20% 95.20% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2776 4.80% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 57830 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63212 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63212 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 63285 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 63285 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57784 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57784 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 120996 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 421062407 # ITB inst hits -system.cpu0.itb.inst_misses 63212 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 57830 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 57830 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 121115 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 419986176 # ITB inst hits +system.cpu0.itb.inst_misses 63285 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1287 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1285 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21013 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 511 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 36180 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 20997 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 507 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 35884 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 421125619 # ITB inst accesses -system.cpu0.itb.hits 421062407 # DTB hits -system.cpu0.itb.misses 63212 # DTB misses -system.cpu0.itb.accesses 421125619 # DTB accesses -system.cpu0.numCycles 506570818 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 420049461 # ITB inst accesses +system.cpu0.itb.hits 419986176 # DTB hits +system.cpu0.itb.misses 63285 # DTB misses +system.cpu0.itb.accesses 420049461 # DTB accesses +system.cpu0.numCycles 505091044 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 420869800 # Number of instructions committed -system.cpu0.committedOps 495253800 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 454669961 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 407169 # Number of float alu accesses -system.cpu0.num_func_calls 25355566 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 64011433 # number of instructions that are conditional controls -system.cpu0.num_int_insts 454669961 # number of integer instructions -system.cpu0.num_fp_insts 407169 # number of float instructions -system.cpu0.num_int_register_reads 669912724 # number of times the integer registers were read -system.cpu0.num_int_register_writes 361261423 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 658306 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 339356 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 110690043 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 110438637 # number of times the CC registers were written -system.cpu0.num_mem_refs 150674741 # number of memory refs -system.cpu0.num_load_insts 78636195 # Number of load instructions -system.cpu0.num_store_insts 72038546 # Number of store instructions -system.cpu0.num_idle_cycles 494843268.961767 # Number of idle cycles -system.cpu0.num_busy_cycles 11727549.038232 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023151 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976849 # Percentage of idle cycles -system.cpu0.Branches 93932517 # Number of branches fetched +system.cpu0.committedInsts 419794202 # Number of instructions committed +system.cpu0.committedOps 493796806 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 453197936 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 421943 # Number of float alu accesses +system.cpu0.num_func_calls 25265539 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 63928321 # number of instructions that are conditional controls +system.cpu0.num_int_insts 453197936 # number of integer instructions +system.cpu0.num_fp_insts 421943 # number of float instructions +system.cpu0.num_int_register_reads 668318275 # number of times the integer registers were read +system.cpu0.num_int_register_writes 360308744 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 682016 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 353392 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 110766057 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 110481712 # number of times the CC registers were written +system.cpu0.num_mem_refs 149944655 # number of memory refs +system.cpu0.num_load_insts 78394551 # Number of load instructions +system.cpu0.num_store_insts 71550104 # Number of store instructions +system.cpu0.num_idle_cycles 493080351.361326 # Number of idle cycles +system.cpu0.num_busy_cycles 12010692.638674 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023779 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976221 # Percentage of idle cycles +system.cpu0.Branches 93737042 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 343715794 69.36% 69.36% # Class of executed instruction -system.cpu0.op_class::IntMult 1059861 0.21% 69.57% # Class of executed instruction -system.cpu0.op_class::IntDiv 47874 0.01% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 49044 0.01% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction -system.cpu0.op_class::MemRead 78636195 15.87% 85.46% # Class of executed instruction -system.cpu0.op_class::MemWrite 72038546 14.54% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 342973363 69.42% 69.42% # Class of executed instruction +system.cpu0.op_class::IntMult 1071330 0.22% 69.63% # Class of executed instruction +system.cpu0.op_class::IntDiv 48623 0.01% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.64% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 51721 0.01% 69.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.65% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.65% # Class of executed instruction +system.cpu0.op_class::MemRead 78394551 15.87% 85.52% # Class of executed instruction +system.cpu0.op_class::MemWrite 71550104 14.48% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 495547316 # Class of executed instruction +system.cpu0.op_class::total 494089735 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16313 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 10214702 # number of replacements +system.cpu0.dcache.tags.replacements 10220953 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.999720 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 304791830 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10215214 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.837048 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 305187926 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10221465 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.857552 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.816800 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 4.965643 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 10.217276 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970345 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.009699 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.019956 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.221457 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 6.755911 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 8.022352 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971136 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.013195 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.015669 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 305 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1295808199 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1295808199 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 73344072 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 23670257 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 59561251 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 156575580 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68109688 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 21690684 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 50098487 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 139898859 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 192172 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58926 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 140820 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 391918 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 149127 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 52869 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 128452 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 330448 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1807582 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 555748 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1239879 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3603209 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1920927 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 598964 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1426295 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3946186 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 141453760 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 45360941 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 109659738 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 296474439 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 141645932 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 45419867 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 109800558 # number of overall hits -system.cpu0.dcache.overall_hits::total 296866357 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2534039 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 789361 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 4745712 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 8069112 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1082533 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 339457 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 4257122 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 5679112 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 624926 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 200468 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 451799 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1277193 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 751391 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 141795 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu2.data 340989 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1234175 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 114175 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 43476 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 234793 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 392444 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses +system.cpu0.dcache.tags.tag_accesses 1297346809 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1297346809 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 73103498 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 24004695 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 59713819 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156822012 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67621876 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 22136915 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 50273570 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 140032361 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 191205 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 58550 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 144781 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 394536 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 151179 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 54099 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu2.data 126065 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 331343 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1805832 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 567281 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 1240318 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3613431 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1916828 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 614023 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 1418006 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3948857 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 140725374 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 46141610 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 109987389 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 296854373 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 140916579 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 46200160 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 110132170 # number of overall hits +system.cpu0.dcache.overall_hits::total 297248909 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2537446 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 778664 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 4676407 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 7992517 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1084233 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 329896 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 4337927 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 5752056 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 625359 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 184328 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 464541 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1274228 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 751309 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 143971 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu2.data 338834 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1234114 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 111816 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 47069 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 226989 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 385874 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3616572 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 1128818 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 9002834 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 13748224 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4241498 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 1329286 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 9454633 # number of overall misses -system.cpu0.dcache.overall_misses::total 15025417 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 12043106000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 81409169465 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 93452275465 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9835188618 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 156717505281 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 166552693899 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 2497645002 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu2.data 10654218293 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 13151863295 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 638788250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 3294649532 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 3933437782 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 150500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 64501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 215001 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 21878294618 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 238126674746 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 260004969364 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 21878294618 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 238126674746 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 260004969364 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75878111 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 24459618 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 64306963 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 164644692 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 69192221 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 22030141 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 54355609 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 145577971 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 817098 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 259394 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 592619 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1669111 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 900518 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 194664 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data 469441 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1564623 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1921757 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 599224 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 1474672 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3995653 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1920928 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 598966 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 1426299 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3946193 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 145070332 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 46489759 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 118662572 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 310222663 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 145887430 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 46749153 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 119255191 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 311891774 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033396 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032272 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.073798 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.049009 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015645 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015409 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.078320 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.039011 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.764812 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.772832 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.762377 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765194 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.834399 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.728409 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu2.data 0.726372 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.788800 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059412 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.072554 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.159217 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.098218 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 3621679 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 1108560 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 9014334 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 13744573 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4247038 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 1292888 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 9478875 # number of overall misses +system.cpu0.dcache.overall_misses::total 15018801 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 12082220500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 71708819033 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 83791039533 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 9788716367 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 139964630413 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 149753346780 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 2906340501 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu2.data 7459202639 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 10365543140 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 670206750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 2926933738 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 3597140488 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 164000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 190000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 21870936867 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 211673449446 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 233544386313 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 21870936867 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 211673449446 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 233544386313 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75640944 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 24783359 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 64390226 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 164814529 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 68706109 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 22466811 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 54611497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 145784417 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 816564 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 242878 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 609322 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1668764 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 902488 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 198070 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu2.data 464899 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1565457 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1917648 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 614350 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 1467307 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 3999305 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1916828 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 614025 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 1418008 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 3948861 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 144347053 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 47250170 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 119001723 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 310598946 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 145163617 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 47493048 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 119611045 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 312267710 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033546 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031419 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.072626 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.048494 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015781 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014684 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.079432 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.039456 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.765842 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.758932 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.762390 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.763576 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.832486 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.726869 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu2.data 0.728834 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.788341 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.058309 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076616 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.154698 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.096485 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024930 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024281 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.075869 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.044317 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029074 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028434 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079281 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.048175 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15256.778584 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 17154.258300 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11581.482010 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 28973.297407 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 36813.017170 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29327.242340 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 17614.478663 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 31245.049820 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 10656.400668 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14692.893780 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14032.145473 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10022.927557 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 75250 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16125.250000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 30714.428571 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19381.596163 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26450.190545 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18911.895047 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16458.681291 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25186.241999 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 17304.342992 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 16525094 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 18605 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1165104 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 417 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.183364 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 44.616307 # average number of cycles each access was blocked +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025090 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023462 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.075750 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.044252 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029257 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027223 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.079247 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.048096 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15516.603439 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15334.169809 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10483.686120 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 29672.128086 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32265.326367 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 26034.751188 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 20186.985580 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu2.data 22014.327485 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 8399.177985 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14238.814294 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12894.606073 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9322.059760 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 47500 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19729.141289 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 23481.873364 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 16991.752768 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16916.342999 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 22331.072986 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15550.135215 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 14700393 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 25808 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1130734 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 457 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.000753 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 56.472648 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7876656 # number of writebacks -system.cpu0.dcache.writebacks::total 7876656 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 1060 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 2696706 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 2697766 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 3203 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3527121 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 3530324 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu2.data 2450 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 2450 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 10619 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 143143 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 153762 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 4263 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 6223827 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 6228090 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 4263 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 6223827 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 6228090 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 788301 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 2049006 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 2837307 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 336254 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 730001 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1066255 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 200411 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 444940 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 645351 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 141795 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu2.data 338539 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 480334 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 32857 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 91650 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 124507 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 7872498 # number of writebacks +system.cpu0.dcache.writebacks::total 7872498 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 2189 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 2608868 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 2611057 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1745 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 3598244 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 3599989 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu2.data 2407 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 2407 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 10418 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 138207 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 148625 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 3934 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 6207112 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 6211046 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 3934 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 6207112 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 6211046 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 776475 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 2067539 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2844014 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 328151 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 739683 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1067834 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 184212 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 454745 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 638957 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 143971 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu2.data 336427 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 480398 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 36651 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 88782 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125433 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 1124555 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 2779007 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 3903562 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 1324966 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 3223947 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 4548913 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10385481000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30772790199 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41158271199 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9025287882 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 24823347673 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33848635555 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2966996500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 9186505955 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12153502455 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2214054998 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data 9890086456 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 12104141454 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 409377500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1158107131 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1567484631 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 146500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 202999 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 19410768882 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 55596137872 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 75006906754 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22377765382 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 64782643827 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 87160409209 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 886387500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1429299000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2315686500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 799886500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1453115957 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2253002457 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1686274000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2882414957 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4568688957 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032229 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031863 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017233 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015263 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013430 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007324 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.772612 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.750803 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.386644 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.728409 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.721153 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.306997 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054833 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.062149 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031161 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 1104626 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 2807222 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 3911848 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 1288838 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 3261967 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4550805 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10846992750 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30627833111 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41474825861 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 9219061633 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 24093607640 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33312669273 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2717019500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 8086528259 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10803547759 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2690383999 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu2.data 6865304661 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 9555688660 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 463968000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 1147138011 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1611106011 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 23000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 184000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 20066054383 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 54721440751 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 74787495134 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 22783073883 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 62807969010 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 85591042893 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 895108750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1474898001 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2370006751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 895104500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1438317956 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2333422456 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1790213250 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2913215957 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4703429207 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031330 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.032110 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017256 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014606 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013544 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758455 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.746313 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.382892 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.726869 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.723656 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.306874 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059658 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060507 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.031364 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024189 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023419 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.012583 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028342 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027034 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.014585 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13174.512020 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15018.399262 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14506.104274 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26840.685559 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34004.539272 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31745.347553 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14804.559131 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 20646.617420 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 18832.391141 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 15614.478635 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 29214.023956 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25199.426761 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12459.369389 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12636.193464 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12589.530155 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73250 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 33833.166667 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17260.844407 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 20005.756686 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19214.990502 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16889.312920 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 20094.202488 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19160.711407 # average overall mshr miss latency +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023378 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023590 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.012595 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027137 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027271 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.014573 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13969.532503 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14813.666446 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14583.200315 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28093.961722 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 32572.882762 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31196.486788 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14749.416433 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 17782.555628 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16908.098290 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 18686.985567 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 20406.521061 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 19891.191595 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12659.081608 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12920.839934 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12844.355241 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 46000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18165.473548 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19493.093439 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19118.200690 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17677.220786 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19254.630415 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18807.890668 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -916,142 +921,142 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 14521093 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.976902 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 611027566 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14521605 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 42.077137 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 9055108500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 497.542496 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 4.290435 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.143971 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.971763 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.008380 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019812 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 14550991 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.976833 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 611237841 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14551503 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 42.005135 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 9058621500 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 496.705744 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 5.210417 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.060673 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.970128 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.010177 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019650 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999955 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 251 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 79 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 640492964 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 640492964 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 414512221 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 132673632 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 63841713 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 611027566 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 414512221 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 132673632 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 63841713 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 611027566 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 414512221 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 132673632 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 63841713 # number of overall hits -system.cpu0.icache.overall_hits::total 611027566 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6607970 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 2066459 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 6269243 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14943672 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6607970 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 2066459 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 6269243 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14943672 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6607970 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 2066459 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 6269243 # number of overall misses -system.cpu0.icache.overall_misses::total 14943672 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 27753435750 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 83574446765 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 111327882515 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 27753435750 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 83574446765 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 111327882515 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 27753435750 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 83574446765 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 111327882515 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 421120191 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 134740091 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 70110956 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 625971238 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 421120191 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 134740091 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 70110956 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 625971238 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 421120191 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 134740091 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 70110956 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 625971238 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015691 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015337 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089419 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.023873 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015691 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015337 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089419 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.023873 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015691 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015337 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089419 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.023873 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13430.431356 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13330.867342 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 7449.834453 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13430.431356 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13330.867342 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 7449.834453 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13430.431356 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13330.867342 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 7449.834453 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 42762 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 640780747 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 640780747 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 413451033 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 134065919 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 63720889 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 611237841 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 413451033 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 134065919 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 63720889 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 611237841 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 413451033 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 134065919 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 63720889 # number of overall hits +system.cpu0.icache.overall_hits::total 611237841 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 6592973 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 2115468 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 6282843 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14991284 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 6592973 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 2115468 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 6282843 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14991284 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 6592973 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 2115468 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 6282843 # number of overall misses +system.cpu0.icache.overall_misses::total 14991284 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 28339007992 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 82279227443 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 110618235435 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 28339007992 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 82279227443 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 110618235435 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 28339007992 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 82279227443 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 110618235435 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 420044006 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 136181387 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 70003732 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 626229125 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 420044006 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 136181387 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 70003732 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 626229125 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 420044006 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 136181387 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 70003732 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 626229125 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015696 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015534 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.089750 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.023939 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015696 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015534 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.089750 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.023939 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015696 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015534 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.089750 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.023939 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13396.093910 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13095.859222 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 7378.836625 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13396.093910 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13095.859222 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 7378.836625 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13396.093910 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13095.859222 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 7378.836625 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 51965 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 3542 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 3925 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.072840 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.239490 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 421946 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 421946 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 421946 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 421946 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 421946 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 421946 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2066459 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5847297 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 7913756 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 2066459 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 5847297 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 7913756 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 2066459 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 5847297 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 7913756 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 23615838750 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 68291553899 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 91907392649 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 23615838750 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 68291553899 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 91907392649 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 23615838750 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 68291553899 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 91907392649 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015337 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083401 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012642 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015337 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083401 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012642 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015337 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083401 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012642 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11428.167096 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11679.166271 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11613.624763 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11428.167096 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11679.166271 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11613.624763 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11428.167096 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11679.166271 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11613.624763 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 439662 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 439662 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 439662 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 439662 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 439662 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 439662 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 2115468 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 5843181 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 7958649 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 2115468 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 5843181 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 7958649 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 2115468 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 5843181 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 7958649 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 25161480508 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 69932206790 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 95093687298 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 25161480508 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 69932206790 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 95093687298 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 25161480508 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 69932206790 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 95093687298 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012709 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012709 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015534 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.083470 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012709 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11948.471066 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11948.471066 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11894.049217 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11968.173977 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11948.471066 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1082,72 +1087,70 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 39379 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 39379 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 5977 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 28234 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 39373 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.279379 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 55.436197 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-1023 39372 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::10240-11263 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 39373 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 34217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 21462.701289 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 17640.355852 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13201.639709 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 33415 97.66% 97.66% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 571 1.67% 99.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 171 0.50% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 26 0.08% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 5 0.01% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 9 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 6 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 6 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 34217 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1508431008 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.298098 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.457423 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1058770000 70.19% 70.19% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 449661008 29.81% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1508431008 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 28234 82.53% 82.53% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 5977 17.47% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 34211 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 39379 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 40069 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 40069 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6011 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 28822 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 3 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 40066 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.287026 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 57.452621 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-1023 40065 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 40066 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 34836 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23148.919221 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 19687.951217 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13456.896972 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 22742 65.28% 65.28% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 11809 33.90% 99.18% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 149 0.43% 99.61% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 100 0.29% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.90% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 13 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 2 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 8 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 9 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 34836 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2552299344 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.586801 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.492408 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1054607500 41.32% 41.32% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 1497691844 58.68% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2552299344 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 28822 82.74% 82.74% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 6011 17.26% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 34833 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 40069 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 39379 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 34211 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 40069 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 34833 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 34211 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 73590 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 34833 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 74902 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25323699 # DTB read hits -system.cpu1.dtb.read_misses 30085 # DTB read misses -system.cpu1.dtb.write_hits 22831654 # DTB write hits -system.cpu1.dtb.write_misses 9294 # DTB write misses -system.cpu1.dtb.flush_tlb 1278 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 25646035 # DTB read hits +system.cpu1.dtb.read_misses 30818 # DTB read misses +system.cpu1.dtb.write_hits 23287178 # DTB write hits +system.cpu1.dtb.write_misses 9251 # DTB write misses +system.cpu1.dtb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 6693 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 149 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 21869 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 6462 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 159 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 22057 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 1270 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 1362 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 3016 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25353784 # DTB read accesses -system.cpu1.dtb.write_accesses 22840948 # DTB write accesses +system.cpu1.dtb.perms_faults 2875 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25676853 # DTB read accesses +system.cpu1.dtb.write_accesses 23296429 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 48155353 # DTB hits -system.cpu1.dtb.misses 39379 # DTB misses -system.cpu1.dtb.accesses 48194732 # DTB accesses +system.cpu1.dtb.hits 48933213 # DTB hits +system.cpu1.dtb.misses 40069 # DTB misses +system.cpu1.dtb.accesses 48973282 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1177,135 +1180,137 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 23659 # Table walker walks requested -system.cpu1.itb.walker.walksLong 23659 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1141 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20683 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 23659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 23659 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 23659 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 21824 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24542.418897 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21182.327207 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14187.388293 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 20284 92.94% 92.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 1308 5.99% 98.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 160 0.73% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 37 0.17% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 9 0.04% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 7 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 21824 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 23826 # Table walker walks requested +system.cpu1.itb.walker.walksLong 23826 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1156 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 20921 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 23826 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 23826 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 23826 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 22077 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26240.136794 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22930.281403 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 15976.450560 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 11277 51.08% 51.08% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 10485 47.49% 98.57% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 121 0.55% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 153 0.69% 99.81% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 7 0.03% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 4 0.02% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 22077 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 20683 94.77% 94.77% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 1141 5.23% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 21824 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 20921 94.76% 94.76% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 1156 5.24% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 22077 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23659 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23659 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 23826 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 23826 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 21824 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 21824 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 45483 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 134740091 # ITB inst hits -system.cpu1.itb.inst_misses 23659 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 22077 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 22077 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 45903 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 136181387 # ITB inst hits +system.cpu1.itb.inst_misses 23826 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1278 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1276 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 6693 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 149 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 16092 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 6462 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 159 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 16176 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 134763750 # ITB inst accesses -system.cpu1.itb.hits 134740091 # DTB hits -system.cpu1.itb.misses 23659 # DTB misses -system.cpu1.itb.accesses 134763750 # DTB accesses -system.cpu1.numCycles 1278124825 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 136205213 # ITB inst accesses +system.cpu1.itb.hits 136181387 # DTB hits +system.cpu1.itb.misses 23826 # DTB misses +system.cpu1.itb.accesses 136205213 # DTB accesses +system.cpu1.numCycles 1276125055 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 134646225 # Number of instructions committed -system.cpu1.committedOps 158126706 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 145069492 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 137737 # Number of float alu accesses -system.cpu1.num_func_calls 7885244 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 20644863 # number of instructions that are conditional controls -system.cpu1.num_int_insts 145069492 # number of integer instructions -system.cpu1.num_fp_insts 137737 # number of float instructions -system.cpu1.num_int_register_reads 212132646 # number of times the integer registers were read -system.cpu1.num_int_register_writes 115229722 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 221669 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 118820 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 35576682 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 35511484 # number of times the CC registers were written -system.cpu1.num_mem_refs 48152949 # number of memory refs -system.cpu1.num_load_insts 25322940 # Number of load instructions -system.cpu1.num_store_insts 22830009 # Number of store instructions -system.cpu1.num_idle_cycles 1251340382.439470 # Number of idle cycles -system.cpu1.num_busy_cycles 26784442.560530 # Number of busy cycles -system.cpu1.not_idle_fraction 0.020956 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.979044 # Percentage of idle cycles -system.cpu1.Branches 30070128 # Number of branches fetched +system.cpu1.committedInsts 136088494 # Number of instructions committed +system.cpu1.committedOps 159971532 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 146914767 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 136439 # Number of float alu accesses +system.cpu1.num_func_calls 8067189 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 20777484 # number of instructions that are conditional controls +system.cpu1.num_int_insts 146914767 # number of integer instructions +system.cpu1.num_fp_insts 136439 # number of float instructions +system.cpu1.num_int_register_reads 213265371 # number of times the integer registers were read +system.cpu1.num_int_register_writes 116491926 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 215836 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 125376 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 35465151 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 35400633 # number of times the CC registers were written +system.cpu1.num_mem_refs 48930269 # number of memory refs +system.cpu1.num_load_insts 25645213 # Number of load instructions +system.cpu1.num_store_insts 23285056 # Number of store instructions +system.cpu1.num_idle_cycles 1249288140.787440 # Number of idle cycles +system.cpu1.num_busy_cycles 26836914.212560 # Number of busy cycles +system.cpu1.not_idle_fraction 0.021030 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.978970 # Percentage of idle cycles +system.cpu1.Branches 30426471 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 109684380 69.32% 69.32% # Class of executed instruction -system.cpu1.op_class::IntMult 350403 0.22% 69.55% # Class of executed instruction -system.cpu1.op_class::IntDiv 14329 0.01% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 18470 0.01% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu1.op_class::MemRead 25322940 16.00% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 22830009 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 110766463 69.20% 69.20% # Class of executed instruction +system.cpu1.op_class::IntMult 334649 0.21% 69.41% # Class of executed instruction +system.cpu1.op_class::IntDiv 13512 0.01% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.42% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 19532 0.01% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.43% # Class of executed instruction +system.cpu1.op_class::MemRead 25645213 16.02% 85.45% # Class of executed instruction +system.cpu1.op_class::MemWrite 23285056 14.55% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 158220572 # Class of executed instruction +system.cpu1.op_class::total 160064425 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 97203672 # Number of BP lookups -system.cpu2.branchPred.condPredicted 66186757 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 4359750 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 65808751 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 47109720 # Number of BTB hits +system.cpu2.branchPred.lookups 97087615 # Number of BP lookups +system.cpu2.branchPred.condPredicted 66103650 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 4347660 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 66231841 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 47108077 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.585799 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 12465679 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 131865 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.126027 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 12454763 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 133862 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1335,81 +1340,88 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 641865 # Table walker walks requested -system.cpu2.dtb.walker.walksLong 641865 # Table walker walks initiated with long descriptors -system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11159 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 66692 # Level at which table walker walks with long descriptors terminate -system.cpu2.dtb.walker.walksSquashedBefore 388613 # Table walks squashed before starting -system.cpu2.dtb.walker.walkWaitTime::samples 253252 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::mean 1931.812977 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::stdev 11499.357470 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0-65535 251854 99.45% 99.45% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::65536-131071 1074 0.42% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::131072-196607 172 0.07% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::196608-262143 83 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::262144-327679 31 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::327680-393215 33 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 253252 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 288612 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 20860.236245 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 16529.214515 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 15237.417207 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-65535 285772 99.02% 99.02% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::65536-131071 2386 0.83% 99.84% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::131072-196607 259 0.09% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::196608-262143 137 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::262144-327679 41 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::327680-393215 7 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 288612 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walksPending::samples 644386966916 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::mean 0.557890 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::stdev 0.603276 # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::0-3 643756648416 99.90% 99.90% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::4-7 358289000 0.06% 99.96% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::8-11 119891000 0.02% 99.98% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::12-15 74898000 0.01% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::16-19 28944500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::20-23 14290500 0.00% 99.99% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::24-27 13699500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::28-31 16934500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::32-35 3107500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walks 649855 # Table walker walks requested +system.cpu2.dtb.walker.walksLong 649855 # Table walker walks initiated with long descriptors +system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 11017 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 66935 # Level at which table walker walks with long descriptors terminate +system.cpu2.dtb.walker.walksSquashedBefore 396890 # Table walks squashed before starting +system.cpu2.dtb.walker.walkWaitTime::samples 252965 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::mean 2053.590418 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::stdev 12193.038070 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0-65535 251454 99.40% 99.40% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::65536-131071 1182 0.47% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::131072-196607 177 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::262144-327679 45 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::327680-393215 26 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::393216-458751 17 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 252965 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 293492 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 21382.093181 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 17292.884496 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 15231.620197 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-65535 288902 98.44% 98.44% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::65536-131071 4097 1.40% 99.83% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::131072-196607 265 0.09% 99.92% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::196608-262143 159 0.05% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::262144-327679 56 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::327680-393215 9 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 293492 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walksPending::samples 636867012660 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::mean 0.530422 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::stdev 0.615162 # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::0-3 636197778160 99.89% 99.89% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::4-7 383895000 0.06% 99.96% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::8-11 122059000 0.02% 99.97% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::12-15 78250500 0.01% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::16-19 30640500 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::20-23 15817000 0.00% 99.99% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::24-27 14461500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::28-31 20012000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::32-35 3793500 0.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::36-39 253000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::40-43 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.dtb.walker.walksPending::total 644386966916 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 66692 85.67% 85.67% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::2M 11159 14.33% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 77851 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 641865 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walksPending::40-43 22000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::44-47 10000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::48-51 6500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::52-55 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::56-59 11000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.dtb.walker.walksPending::total 636867012660 # Table walker pending requests distribution +system.cpu2.dtb.walker.walkPageSizes::4K 66935 85.87% 85.87% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::2M 11017 14.13% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 77952 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 649855 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 641865 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 77851 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 649855 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 77952 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 77851 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 719716 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 77952 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 727807 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 77755602 # DTB read hits -system.cpu2.dtb.read_misses 445998 # DTB read misses -system.cpu2.dtb.write_hits 59736492 # DTB write hits -system.cpu2.dtb.write_misses 195867 # DTB write misses -system.cpu2.dtb.flush_tlb 1279 # Number of times complete TLB was flushed +system.cpu2.dtb.read_hits 77417011 # DTB read hits +system.cpu2.dtb.read_misses 450124 # DTB read misses +system.cpu2.dtb.write_hits 59942200 # DTB write hits +system.cpu2.dtb.write_misses 199731 # DTB write misses +system.cpu2.dtb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 14489 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 395 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 38251 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 105 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 6104 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 14741 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 38279 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 93 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 6471 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 37697 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 78201600 # DTB read accesses -system.cpu2.dtb.write_accesses 59932359 # DTB write accesses +system.cpu2.dtb.perms_faults 38915 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 77867135 # DTB read accesses +system.cpu2.dtb.write_accesses 60141931 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 137492094 # DTB hits -system.cpu2.dtb.misses 641865 # DTB misses -system.cpu2.dtb.accesses 138133959 # DTB accesses +system.cpu2.dtb.hits 137359211 # DTB hits +system.cpu2.dtb.misses 649855 # DTB misses +system.cpu2.dtb.accesses 138009066 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1439,396 +1451,397 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 80363 # Table walker walks requested -system.cpu2.itb.walker.walksLong 80363 # Table walker walks initiated with long descriptors -system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2481 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksLongTerminationLevel::Level3 55642 # Level at which table walker walks with long descriptors terminate -system.cpu2.itb.walker.walksSquashedBefore 10291 # Table walks squashed before starting -system.cpu2.itb.walker.walkWaitTime::samples 70072 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::mean 1335.283708 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::stdev 8007.621087 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0-32767 69580 99.30% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::32768-65535 258 0.37% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::65536-98303 168 0.24% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::98304-131071 29 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::131072-163839 18 0.03% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::196608-229375 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walks 80378 # Table walker walks requested +system.cpu2.itb.walker.walksLong 80378 # Table walker walks initiated with long descriptors +system.cpu2.itb.walker.walksLongTerminationLevel::Level2 2425 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksLongTerminationLevel::Level3 55766 # Level at which table walker walks with long descriptors terminate +system.cpu2.itb.walker.walksSquashedBefore 10589 # Table walks squashed before starting +system.cpu2.itb.walker.walkWaitTime::samples 69789 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::mean 1377.194114 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::stdev 8185.559112 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0-32767 69315 99.32% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::32768-65535 221 0.32% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::65536-98303 162 0.23% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::98304-131071 61 0.09% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::163840-196607 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu2.itb.walker.walkWaitTime::262144-294911 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu2.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 70072 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 68414 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 25615.416172 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 21446.317164 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 15929.809681 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::0-32767 60316 88.16% 88.16% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::32768-65535 7055 10.31% 98.48% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::65536-98303 610 0.89% 99.37% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::98304-131071 277 0.40% 99.77% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::131072-163839 68 0.10% 99.87% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::163840-196607 37 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::196608-229375 13 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::229376-262143 11 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::294912-327679 11 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::327680-360447 7 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 68414 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walksPending::samples 468293315780 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::mean 0.887572 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::stdev 0.316276 # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::0 52695891356 11.25% 11.25% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::1 415558218424 88.74% 99.99% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::2 33808000 0.01% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::3 3984500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::4 940500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::5 404000 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::6 21500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::7 47500 0.00% 100.00% # Table walker pending requests distribution -system.cpu2.itb.walker.walksPending::total 468293315780 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 55642 95.73% 95.73% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::2M 2481 4.27% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 58123 # Table walker page sizes translated +system.cpu2.itb.walker.walkWaitTime::total 69789 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 68780 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 26602.237307 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 22568.644275 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 16910.110071 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::0-32767 37031 53.84% 53.84% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::32768-65535 30619 44.52% 98.36% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::65536-98303 406 0.59% 98.95% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::98304-131071 526 0.76% 99.71% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::131072-163839 70 0.10% 99.81% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::163840-196607 66 0.10% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::196608-229375 22 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::229376-262143 14 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::360448-393215 3 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 68780 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksPending::samples 465075818820 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::mean 0.908790 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::stdev 0.288323 # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::0 42467517784 9.13% 9.13% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::1 422566839536 90.86% 99.99% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::2 36100000 0.01% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::3 4751500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::4 426500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::5 73000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::6 66000 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::7 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu2.itb.walker.walksPending::total 465075818820 # Table walker pending requests distribution +system.cpu2.itb.walker.walkPageSizes::4K 55766 95.83% 95.83% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::2M 2425 4.17% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 58191 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 80363 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 80363 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 80378 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 80378 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 58123 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 58123 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 138486 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 70281222 # ITB inst hits -system.cpu2.itb.inst_misses 80363 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 58191 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 58191 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 138569 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 70175055 # ITB inst hits +system.cpu2.itb.inst_misses 80378 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.itb.flush_tlb 1279 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb 1277 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 14489 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 395 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 29841 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 14741 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 389 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 30057 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 147172 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 147979 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 70361585 # ITB inst accesses -system.cpu2.itb.hits 70281222 # DTB hits -system.cpu2.itb.misses 80363 # DTB misses -system.cpu2.itb.accesses 70361585 # DTB accesses -system.cpu2.numCycles 465003102 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 70255433 # ITB inst accesses +system.cpu2.itb.hits 70175055 # DTB hits +system.cpu2.itb.misses 80378 # DTB misses +system.cpu2.itb.accesses 70255433 # DTB accesses +system.cpu2.numCycles 460136549 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 180276648 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 431826640 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 97203672 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 59575399 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 257301281 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 9838745 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 1858453 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 8409 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 1979 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 3769521 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 119476 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 4195 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 70111000 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 2676908 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 31653 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 448259178 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.125687 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.367693 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 178152693 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 431776536 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 97087615 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 59562840 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 255654820 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 9805571 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 1895155 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 7918 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 1866 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 3768954 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 115299 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 5484 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 70003785 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 2663761 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 31715 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 444504807 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.135202 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.375157 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 341932387 76.28% 76.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 13442109 3.00% 79.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 13673824 3.05% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 9898176 2.21% 84.54% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 19945540 4.45% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 6633561 1.48% 90.47% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 7181223 1.60% 92.07% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 6340938 1.41% 93.48% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 29211420 6.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 338236255 76.09% 76.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 13308034 2.99% 79.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 13681319 3.08% 82.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 9908939 2.23% 84.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 20069262 4.51% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 6632314 1.49% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 7130783 1.60% 92.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 6321378 1.42% 93.43% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 29216523 6.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 448259178 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.209039 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.928653 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 147221492 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 209051737 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 78610938 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 9453516 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 3919439 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 14421531 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 1013878 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 471467563 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 3120361 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 3919439 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 152659562 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 18224952 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 165892682 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 82476717 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 25083567 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 460107253 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 59923 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 1862817 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 1245864 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 11710592 # Number of times rename has blocked due to SQ full -system.cpu2.rename.FullRegisterEvents 3796 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 439693345 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 700325975 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 542687716 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 700561 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 367082877 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 72610468 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 9962331 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 8523572 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 52244758 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 74674759 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 62877107 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 9528051 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 10323504 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 437324992 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 9951593 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 435965427 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 606984 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 56598171 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 39504404 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 237598 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 448259178 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.972574 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.684760 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 444504807 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.210997 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.938366 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 145587242 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 206867789 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 78822121 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 9322949 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 3902682 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 14396196 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 1015243 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 471778409 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 3111772 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 3902682 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 151005109 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 15075303 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 166939616 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 82595953 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 24983877 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 460482983 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 55875 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 1575989 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 1122405 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 11824382 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 2747 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 440049969 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 701739830 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 543201034 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 591948 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 368298602 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 71751367 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 10111591 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 8659381 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 51276485 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 74779146 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 63098170 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 9504759 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 10253668 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 437555873 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 10088471 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 436351243 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 628919 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 55749778 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 38531819 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 239828 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 444504807 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.981657 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.695270 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 279914977 62.44% 62.44% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 68317821 15.24% 77.69% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 32057682 7.15% 84.84% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 22901153 5.11% 89.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 17277675 3.85% 93.80% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 11955785 2.67% 96.47% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 7990147 1.78% 98.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 4753228 1.06% 99.31% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 3090710 0.69% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 276381275 62.18% 62.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 68338590 15.37% 77.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 31936602 7.18% 84.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 22769301 5.12% 89.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 16982310 3.82% 93.68% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 11978521 2.69% 96.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 8056839 1.81% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 4822285 1.08% 99.27% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 3239084 0.73% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 448259178 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 444504807 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 2208249 25.46% 25.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 17979 0.21% 25.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 1386 0.02% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 1 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.68% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 3543832 40.86% 66.55% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 2901485 33.45% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 2174414 25.25% 25.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 16907 0.20% 25.44% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 1448 0.02% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.46% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 3443156 39.98% 65.43% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 2977212 34.57% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 294954302 67.66% 67.66% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 1046783 0.24% 67.90% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 49286 0.01% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 204 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.91% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 50291 0.01% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.92% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 79323839 18.19% 86.11% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 60540722 13.89% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 20 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 295429003 67.70% 67.70% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 1051015 0.24% 67.95% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 50004 0.01% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 103 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.96% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 46521 0.01% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.97% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 79012045 18.11% 86.07% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 60762532 13.93% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 435965427 # Type of FU issued -system.cpu2.iq.rate 0.937554 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 8672932 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.019894 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 1328634186 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 503978442 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 419353037 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 835762 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 397688 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 361980 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 444191291 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 447068 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 3425545 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 436351243 # Type of FU issued +system.cpu2.iq.rate 0.948308 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 8613137 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.019739 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 1325660566 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 503495404 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 420349481 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 788783 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 388209 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 352523 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 444542452 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 421908 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 3464909 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 12352202 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 15972 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 509888 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 6626020 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 12199650 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 16692 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 497657 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 6603925 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 2713782 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 6189069 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 2708670 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 5665546 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 3919439 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 10963120 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 5851568 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 447374999 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 1338773 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 74674759 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 62877107 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 8331773 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 175433 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 5598830 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 509888 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 2010429 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1729641 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 3740070 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 430866261 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77742862 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 4466264 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 3902682 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 10385108 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 3443992 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 447742813 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 1337786 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 74779146 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 63098170 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 8466807 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 165633 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 3216656 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 497657 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 2020710 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1734931 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 3755641 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 431226765 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 77404459 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 4484174 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 98414 # number of nop insts executed -system.cpu2.iew.exec_refs 137478821 # number of memory reference insts executed -system.cpu2.iew.exec_branches 79993995 # Number of branches executed -system.cpu2.iew.exec_stores 59735959 # Number of stores executed -system.cpu2.iew.exec_rate 0.926588 # Inst execution rate -system.cpu2.iew.wb_sent 420591447 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 419715017 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 207428552 # num instructions producing a value -system.cpu2.iew.wb_consumers 360230847 # num instructions consuming a value +system.cpu2.iew.exec_nop 98469 # number of nop insts executed +system.cpu2.iew.exec_refs 137346126 # number of memory reference insts executed +system.cpu2.iew.exec_branches 80126150 # Number of branches executed +system.cpu2.iew.exec_stores 59941667 # Number of stores executed +system.cpu2.iew.exec_rate 0.937171 # Inst execution rate +system.cpu2.iew.wb_sent 421619050 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 420702004 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 208179390 # num instructions producing a value +system.cpu2.iew.wb_consumers 361509938 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.902607 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.575821 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.914298 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.575861 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 60870503 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 9713995 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 3359660 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 437963055 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.882384 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.879484 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 60056737 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 9848643 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 3347389 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 434346973 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.892410 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.889968 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 298875540 68.24% 68.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 66218430 15.12% 83.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 24721461 5.64% 89.01% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 11149325 2.55% 91.55% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 8001884 1.83% 93.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 4923567 1.12% 94.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 4422174 1.01% 95.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 3021510 0.69% 96.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 16629164 3.80% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 295032576 67.93% 67.93% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 66481508 15.31% 83.23% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 24486149 5.64% 88.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 11154018 2.57% 91.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 8043816 1.85% 93.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 4878030 1.12% 94.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 4540806 1.05% 95.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 2951206 0.68% 96.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 16778864 3.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 437963055 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 329380138 # Number of instructions committed -system.cpu2.commit.committedOps 386451624 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 434346973 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 330373719 # Number of instructions committed +system.cpu2.commit.committedOps 387615464 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 118573644 # Number of memory references committed -system.cpu2.commit.loads 62322557 # Number of loads committed -system.cpu2.commit.membars 2596368 # Number of memory barriers committed -system.cpu2.commit.branches 73601182 # Number of branches committed -system.cpu2.commit.fp_insts 348235 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 355043998 # Number of committed integer instructions. -system.cpu2.commit.function_calls 9589619 # Number of function calls committed. +system.cpu2.commit.refs 119073741 # Number of memory references committed +system.cpu2.commit.loads 62579496 # Number of loads committed +system.cpu2.commit.membars 2588612 # Number of memory barriers committed +system.cpu2.commit.branches 73762518 # Number of branches committed +system.cpu2.commit.fp_insts 337914 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 356071087 # Number of committed integer instructions. +system.cpu2.commit.function_calls 9588871 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 267002089 69.09% 69.09% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 796041 0.21% 69.30% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 36743 0.01% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.31% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 43107 0.01% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.32% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 62322557 16.13% 85.44% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 56251087 14.56% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 267662094 69.05% 69.05% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 802922 0.21% 69.26% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 37337 0.01% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 69.27% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 39370 0.01% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.28% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 62579496 16.14% 85.43% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 56494245 14.57% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 386451624 # Class of committed instruction -system.cpu2.commit.bw_lim_events 16629164 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 387615464 # Class of committed instruction +system.cpu2.commit.bw_lim_events 16778864 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 866035132 # The number of ROB reads -system.cpu2.rob.rob_writes 904953656 # The number of ROB writes -system.cpu2.timesIdled 2976137 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 16743924 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 99448354933 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 329380138 # Number of Instructions Simulated -system.cpu2.committedOps 386451624 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.411752 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.411752 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.708340 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.708340 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 506713870 # number of integer regfile reads -system.cpu2.int_regfile_writes 300217827 # number of integer regfile writes -system.cpu2.fp_regfile_reads 684649 # number of floating regfile reads -system.cpu2.fp_regfile_writes 429068 # number of floating regfile writes -system.cpu2.cc_regfile_reads 91867416 # number of cc regfile reads -system.cpu2.cc_regfile_writes 92641749 # number of cc regfile writes -system.cpu2.misc_regfile_reads 1672272175 # number of misc regfile reads -system.cpu2.misc_regfile_writes 9817116 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40335 # Transaction distribution -system.iobus.trans_dist::ReadResp 40335 # Transaction distribution -system.iobus.trans_dist::WriteReq 136665 # Transaction distribution -system.iobus.trans_dist::WriteResp 30001 # Transaction distribution +system.cpu2.rob.rob_reads 862595097 # The number of ROB reads +system.cpu2.rob.rob_writes 905518660 # The number of ROB writes +system.cpu2.timesIdled 2960768 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 15631742 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 99536690500 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 330373719 # Number of Instructions Simulated +system.cpu2.committedOps 387615464 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.392776 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.392776 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.717991 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.717991 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 507371314 # number of integer regfile reads +system.cpu2.int_regfile_writes 300778245 # number of integer regfile writes +system.cpu2.fp_regfile_reads 673893 # number of floating regfile reads +system.cpu2.fp_regfile_writes 409456 # number of floating regfile writes +system.cpu2.cc_regfile_reads 92253105 # number of cc regfile reads +system.cpu2.cc_regfile_writes 93114012 # number of cc regfile writes +system.cpu2.misc_regfile_reads 1670741863 # number of misc regfile reads +system.cpu2.misc_regfile_writes 9943766 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40265 # Transaction distribution +system.iobus.trans_dist::ReadResp 40265 # Transaction distribution +system.iobus.trans_dist::WriteReq 136537 # Transaction distribution +system.iobus.trans_dist::WriteResp 29873 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48070 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47686 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1843,13 +1856,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230968 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230968 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122568 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354000 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48090 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353604 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47706 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1864,87 +1877,87 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156082 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334304 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155698 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492472 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13687000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492040 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13825000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 7449000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 8203000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 16992000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 16991000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 331631076 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 196611881 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 38629000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 39351000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36767371 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36922037 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 144000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 80000 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115465 # number of replacements -system.iocache.tags.tagsinuse 10.417241 # Cycle average of tags in use +system.iocache.tags.replacements 115459 # number of replacements +system.iocache.tags.tagsinuse 10.421568 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115481 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115475 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13085934181009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.549977 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.867264 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221874 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.429204 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651078 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13085930884009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.547277 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.874291 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221705 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.429643 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651348 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039713 # Number of tag accesses -system.iocache.tags.data_accesses 1039713 # Number of data accesses +system.iocache.tags.tag_accesses 1039659 # Number of tag accesses +system.iocache.tags.data_accesses 1039659 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8820 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8857 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8820 # number of demand (read+write) misses -system.iocache.demand_misses::total 8860 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses +system.iocache.demand_misses::total 8854 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8820 # number of overall misses -system.iocache.overall_misses::total 8860 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 2752000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 78330160 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 81082160 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9376503545 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9376503545 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 2752000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 78330160 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 81082160 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 2752000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 78330160 # number of overall miss cycles -system.iocache.overall_miss_latency::total 81082160 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8814 # number of overall misses +system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 2432000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 61206163 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 63638163 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6636577681 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6636577681 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 2432000 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 61206163 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 63638163 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 2432000 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 61206163 # number of overall miss cycles +system.iocache.overall_miss_latency::total 63638163 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8820 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8857 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8820 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8860 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8820 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8860 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1958,416 +1971,410 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 74378.378378 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 8880.970522 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 9154.585074 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 87906.918407 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 87906.918407 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 8880.970522 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 9151.485327 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 68800 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 8880.970522 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 9151.485327 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 58174 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 65729.729730 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 6944.198207 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 7189.940459 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 62219.471246 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 62219.471246 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 60800 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 6944.198207 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 7187.504292 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 60800 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 6944.198207 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 7187.504292 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 24555 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7340 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3712 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.925613 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.615032 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 16 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 459 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 34504 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 34504 # number of WriteInvalidateReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 424 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 35584 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 35584 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 16 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 459 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 424 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 16 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 459 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 475 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1920000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 54458660 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 56378660 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7582053787 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7582053787 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 1920000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 54458660 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 56378660 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 1920000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 54458660 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 56378660 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 424 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 440 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 1600000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 38938201 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 40538201 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4786173717 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4786173717 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 1600000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 38938201 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 40538201 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 1600000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 38938201 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 40538201 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 0.432432 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.053630 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.323483 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.323483 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.049712 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 0.333608 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.333608 # mshr miss rate for WriteInvalidateReq accesses system.iocache.demand_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.053612 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.049695 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ethernet 0.400000 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::realview.ide 0.052041 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.053612 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 120000 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 118646.318083 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 118691.915789 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219744.197397 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219744.197397 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 118646.318083 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 118691.915789 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 120000 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 118646.318083 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 118691.915789 # average overall mshr miss latency +system.iocache.overall_mshr_miss_rate::realview.ide 0.048105 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.049695 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 100000 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 91835.379717 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 92132.275000 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134503.532964 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134503.532964 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 100000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 91835.379717 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 92132.275000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 100000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 91835.379717 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 92132.275000 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1296056 # number of replacements -system.l2c.tags.tagsinuse 65324.265743 # Cycle average of tags in use -system.l2c.tags.total_refs 28829950 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1358778 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.217557 # Average number of references to valid blocks. +system.l2c.tags.replacements 1296366 # number of replacements +system.l2c.tags.tagsinuse 65320.100787 # Cycle average of tags in use +system.l2c.tags.total_refs 28848747 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1358615 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.233938 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37285.924880 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 168.149057 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 240.751709 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3675.446789 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 8312.608354 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 50.722331 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 75.631311 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1066.604817 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3135.281683 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 117.351685 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 183.998379 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2140.151911 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 8871.642837 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.568938 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003674 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.056083 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.126840 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000774 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001154 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.016275 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.047841 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001791 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.002808 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.032656 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.135371 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996769 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 311 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62411 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 310 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 564 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2760 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4926 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54001 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.004745 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.952316 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 273473120 # Number of tag accesses -system.l2c.tags.data_accesses 273473120 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 199000 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 127150 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 6565279 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3138242 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 69576 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 49228 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 2053777 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 983926 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 389952 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 151346 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 5813280 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 2472232 # number of ReadReq hits -system.l2c.ReadReq_hits::total 22012988 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7876656 # number of Writeback hits -system.l2c.Writeback_hits::total 7876656 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 347388 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 111332 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu2.data 265723 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 724443 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4844 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 1532 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 3474 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9850 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 804234 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 251858 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 549088 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1605180 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 199000 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 127150 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6565279 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3942476 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 69576 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 49228 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 2053777 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 1235784 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 389952 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 151346 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 5813280 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 3021320 # number of demand (read+write) hits -system.l2c.demand_hits::total 23618168 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 199000 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 127150 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6565279 # number of overall hits -system.l2c.overall_hits::cpu0.data 3942476 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 69576 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 49228 # number of overall hits -system.l2c.overall_hits::cpu1.inst 2053777 # number of overall hits -system.l2c.overall_hits::cpu1.data 1235784 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 389952 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 151346 # number of overall hits -system.l2c.overall_hits::cpu2.inst 5813280 # number of overall hits -system.l2c.overall_hits::cpu2.data 3021320 # number of overall hits -system.l2c.overall_hits::total 23618168 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2029 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1956 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 42691 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 134898 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 540 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 467 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 12682 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 37643 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 1489 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.itb.walker 1413 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 33897 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 109098 # number of ReadReq misses -system.l2c.ReadReq_misses::total 378803 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 404003 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 30463 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu2.data 72816 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 507282 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17431 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 5541 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 12769 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 35741 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses +system.l2c.tags.occ_blocks::writebacks 37068.766455 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 192.906222 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 268.941849 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3824.960525 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 8195.071890 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 57.414493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 82.820036 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 874.447112 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2433.555862 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 94.156487 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 158.776869 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2237.420000 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 9830.862987 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.565624 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002944 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.004104 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.058364 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.125047 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.001264 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.013343 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.037133 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.001437 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.002423 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.034140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.150007 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996706 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 358 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61891 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 358 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 140 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 590 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2804 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4928 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53429 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005463 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.944382 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 273721010 # Number of tag accesses +system.l2c.tags.data_accesses 273721010 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 197948 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 127305 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 6549451 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3139875 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 71739 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 49467 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 2103694 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 962152 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 389616 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 148852 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 5808812 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 2494651 # number of ReadReq hits +system.l2c.ReadReq_hits::total 22043562 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7872498 # number of Writeback hits +system.l2c.Writeback_hits::total 7872498 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 348712 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 112622 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu2.data 261017 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 722351 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 4748 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 1579 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 3377 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9704 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 802024 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 244881 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 560523 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1607428 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 197948 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 127305 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6549451 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 3941899 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 71739 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 49467 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 2103694 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 1207033 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 389616 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 148852 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 5808812 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 3055174 # number of demand (read+write) hits +system.l2c.demand_hits::total 23650990 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 197948 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 127305 # number of overall hits +system.l2c.overall_hits::cpu0.inst 6549451 # number of overall hits +system.l2c.overall_hits::cpu0.data 3941899 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 71739 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 49467 # number of overall hits +system.l2c.overall_hits::cpu1.inst 2103694 # number of overall hits +system.l2c.overall_hits::cpu1.data 1207033 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 389616 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 148852 # number of overall hits +system.l2c.overall_hits::cpu2.inst 5808812 # number of overall hits +system.l2c.overall_hits::cpu2.data 3055174 # number of overall hits +system.l2c.overall_hits::total 23650990 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1815 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1875 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 43522 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 134746 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 628 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 584 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 11774 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 35186 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 1454 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1485 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 34248 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 112174 # number of ReadReq misses +system.l2c.ReadReq_misses::total 379491 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 402597 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 31349 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu2.data 75410 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 509356 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 17318 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 5542 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 12758 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 35618 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 256024 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 77323 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 168936 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 502283 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2029 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1956 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 42691 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 390922 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 540 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 467 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 12682 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 114966 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 1489 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.itb.walker 1413 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 33897 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 278034 # number of demand (read+write) misses -system.l2c.demand_misses::total 881086 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2029 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1956 # number of overall misses -system.l2c.overall_misses::cpu0.inst 42691 # number of overall misses -system.l2c.overall_misses::cpu0.data 390922 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 540 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 467 # number of overall misses -system.l2c.overall_misses::cpu1.inst 12682 # number of overall misses -system.l2c.overall_misses::cpu1.data 114966 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 1489 # number of overall misses -system.l2c.overall_misses::cpu2.itb.walker 1413 # number of overall misses -system.l2c.overall_misses::cpu2.inst 33897 # number of overall misses -system.l2c.overall_misses::cpu2.data 278034 # number of overall misses -system.l2c.overall_misses::total 881086 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 42872750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 37951500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 933873500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 2861563000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 118320496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.itb.walker 114835749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 2671771250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 9419729454 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16200917699 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 46498 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu2.data 719469 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 765967 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 64020248 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 151807971 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 215828219 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 144500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 144500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 5737082423 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 16065175620 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 21802258043 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 42872750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 37951500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 933873500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 8598645423 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 118320496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.itb.walker 114835749 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 2671771250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 25484905074 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 38003175742 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 42872750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 37951500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 933873500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 8598645423 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 118320496 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.itb.walker 114835749 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 2671771250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 25484905074 # number of overall miss cycles -system.l2c.overall_miss_latency::total 38003175742 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 201029 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 129106 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 6607970 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3273140 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 70116 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 49695 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 2066459 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 1021569 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 391441 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 152759 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 5847177 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 2581330 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 22391791 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 7876656 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 7876656 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 751391 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 141795 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu2.data 338539 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1231725 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 22275 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 7073 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16243 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 45591 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 260143 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76149 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 167266 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 503558 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1815 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1875 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 43522 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 394889 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 628 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 584 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 11774 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 111335 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 1454 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1485 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 34248 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 279440 # number of demand (read+write) misses +system.l2c.demand_misses::total 883049 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1815 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1875 # number of overall misses +system.l2c.overall_misses::cpu0.inst 43522 # number of overall misses +system.l2c.overall_misses::cpu0.data 394889 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 628 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 584 # number of overall misses +system.l2c.overall_misses::cpu1.inst 11774 # number of overall misses +system.l2c.overall_misses::cpu1.data 111335 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 1454 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1485 # number of overall misses +system.l2c.overall_misses::cpu2.inst 34248 # number of overall misses +system.l2c.overall_misses::cpu2.data 279440 # number of overall misses +system.l2c.overall_misses::total 883049 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 53034750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 51385500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 957183750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 2927898000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 131170504 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 133193759 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 2952102750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 10395270751 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 17601239764 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 30999 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu2.data 902971 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 933970 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 83997793 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 205155438 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 289153231 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 159000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 6131099175 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 16871513594 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 23002612769 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 53034750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 51385500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 957183750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 9058997175 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 131170504 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 133193759 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 2952102750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 27266784345 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 40603852533 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 53034750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 51385500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 957183750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 9058997175 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 131170504 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 133193759 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 2952102750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 27266784345 # number of overall miss cycles +system.l2c.overall_miss_latency::total 40603852533 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 199763 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 129180 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 6592973 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 3274621 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 72367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 50051 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 2115468 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 997338 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 391070 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 150337 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 5843060 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 2606825 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 22423053 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 7872498 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 7872498 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 751309 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 143971 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu2.data 336427 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 1231707 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 22066 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 7121 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 16135 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 45322 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1060258 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 329181 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 718024 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2107463 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 201029 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 129106 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 6607970 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4333398 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 70116 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 49695 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 2066459 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1350750 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 391441 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 152759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 5847177 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 3299354 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 24499254 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 201029 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 129106 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 6607970 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 4333398 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 70116 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 49695 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 2066459 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1350750 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 391441 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 152759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 5847177 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 3299354 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 24499254 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.010093 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.015150 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.006461 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.041214 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.007702 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.009397 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.006137 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.036848 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003804 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.009250 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.005797 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.042264 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016917 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.537673 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.214838 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu2.data 0.215089 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.411847 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.782536 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.783402 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.786123 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.783949 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1062167 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 321030 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 727789 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2110986 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 199763 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 129180 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 6592973 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 4336788 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 72367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 50051 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 2115468 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1318368 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 391070 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 150337 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 5843060 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 3334614 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 24534039 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 199763 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 129180 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 6592973 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 4336788 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 72367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 50051 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 2115468 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1318368 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 391070 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 150337 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 5843060 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 3334614 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 24534039 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.009086 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.014515 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.006601 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.041149 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.008678 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011668 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.005566 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.035280 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003718 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.009878 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.005861 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.043031 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016924 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.535861 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.217745 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu2.data 0.224150 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.413537 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784827 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.778261 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.790703 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.785888 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.250000 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.571429 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.241473 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.234895 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.235279 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.238335 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.010093 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.015150 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006461 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.090211 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.007702 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.009397 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.006137 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.085113 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003804 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.itb.walker 0.009250 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.005797 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.084269 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.035964 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.010093 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.015150 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006461 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.090211 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.007702 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.009397 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.006137 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.085113 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003804 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.itb.walker 0.009250 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.005797 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.084269 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.035964 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79393.981481 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 81266.595289 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 73637.714871 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76018.462928 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 79463.059772 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 81270.876858 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 78820.286456 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 86341.907771 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 42768.715398 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 1.526376 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu2.data 9.880644 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 1.509943 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11553.915900 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11888.790900 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6038.673204 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 72250 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 36125 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 74196.324806 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 95096.223540 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 43406.322816 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79393.981481 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 81266.595289 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 73637.714871 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74792.942461 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 79463.059772 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.itb.walker 81270.876858 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 78820.286456 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 91661.110058 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 43132.197926 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79393.981481 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 81266.595289 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 73637.714871 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74792.942461 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 79463.059772 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.itb.walker 81270.876858 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 78820.286456 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 91661.110058 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 43132.197926 # average overall miss latency +system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.244917 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.237202 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.229828 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.238542 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.009086 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.014515 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006601 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.091056 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.008678 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.011668 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005566 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.084449 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003718 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.009878 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.005861 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.083800 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.035993 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.009086 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.014515 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006601 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.091056 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.008678 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.011668 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005566 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.084449 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003718 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.009878 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.005861 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.083800 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.035993 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84450.238854 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87988.869863 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81296.394598 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 83212.016143 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 90213.551582 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 89692.767003 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86197.814471 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 92670.946485 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 46381.178378 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 0.988835 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu2.data 11.974155 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 1.833629 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15156.584807 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 16080.532842 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 8118.177073 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80514.506756 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 100866.366111 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 45680.165480 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84450.238854 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87988.869863 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81296.394598 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81367.020030 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 90213.551582 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 89692.767003 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 86197.814471 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 97576.525712 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 45981.426323 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84450.238854 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87988.869863 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81296.394598 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81367.020030 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 90213.551582 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 89692.767003 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 86197.814471 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 97576.525712 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 45981.426323 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2376,185 +2383,181 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1098143 # number of writebacks -system.l2c.writebacks::total 1098143 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.itb.walker 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.dtb.walker 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.itb.walker 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.dtb.walker 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.itb.walker 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 32 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 540 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 467 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 12682 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 37643 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 1479 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1395 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 33897 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 109094 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 197197 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 30463 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu2.data 72816 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 103279 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 5541 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 12769 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 18310 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 1099475 # number of writebacks +system.l2c.writebacks::total 1099475 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.dtb.walker 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.itb.walker 15 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.dtb.walker 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.itb.walker 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.dtb.walker 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.itb.walker 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 25 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 628 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 584 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 11774 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 35186 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 1446 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1470 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 34248 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 112172 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 197508 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 31349 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu2.data 75410 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 106759 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 5542 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 12758 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 18300 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 2 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 77323 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 168936 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 246259 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 540 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 467 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 12682 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 114966 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 1479 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.itb.walker 1395 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 33897 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 278030 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 443456 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 540 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 467 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 12682 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 114966 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 1479 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.itb.walker 1395 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 33897 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 278030 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 443456 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 36126250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 32115000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 772955000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 2388239500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 99058496 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 96418749 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2247455250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 8064803454 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 13737171699 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 623178002 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu2.data 1961937066 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 2585115068 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 55415541 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 127748768 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 183164309 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 120500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 130501 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4745725577 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 13959138378 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 18704863955 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 36126250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 32115000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 772955000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 7133965077 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 99058496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 96418749 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 2247455250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 22023941832 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 32442035654 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 36126250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 32115000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 772955000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 7133965077 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 99058496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 96418749 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 2247455250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 22023941832 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 32442035654 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 815320500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1324756000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 2140076500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 741768000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1356119999 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2097887999 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1557088500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2680875999 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4237964499 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.007702 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.009397 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.006137 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.036848 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003778 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.009132 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005797 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.042263 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.008807 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.214838 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.215089 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.083849 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.783402 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.786123 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.401614 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76149 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 167266 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 243415 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 628 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 584 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 11774 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 111335 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 1446 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1470 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 34248 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 279438 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 440923 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 628 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 584 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 11774 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 111335 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 1446 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1470 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 34248 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 279438 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 440923 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 44046000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 809585750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 2487118500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 112189752 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 113691259 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2523258750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 8999138499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 15134168260 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 987692501 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu2.data 2488109529 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 3475802030 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 97166042 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 226510254 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 323676296 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 135000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5178636325 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 14796575906 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 19975212231 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 44046000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 809585750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 7665754825 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 112189752 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 113691259 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 2523258750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 23795714405 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 35109380491 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 44046000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 809585750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 7665754825 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 112189752 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 113691259 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 2523258750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 23795714405 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 35109380491 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 818834500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1358915500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 2177750000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 825245000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1335319496 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2160564496 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1644079500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2694234996 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4338314496 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.035280 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.043030 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.008808 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.217745 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu2.data 0.224150 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.086676 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.778261 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.790703 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.403777 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.428571 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.234895 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.235279 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.116851 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007702 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009397 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006137 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.085113 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003778 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.009132 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005797 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.084268 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.018101 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007702 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009397 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006137 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.085113 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003778 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.009132 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005797 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.084268 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.018101 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63444.451824 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 73925.270446 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 69662.173862 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20456.882185 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 26943.763266 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 25030.403741 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10004.602396 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10003.512234 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60250 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 43500.333333 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61375.342097 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 82629.743678 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 75956.062337 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62052.824983 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 79214.264043 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 73157.282017 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66900.462963 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68768.736617 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60948.982810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62052.824983 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 66976.670723 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 69117.382796 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 66302.482521 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 79214.264043 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 73157.282017 # average overall mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.237202 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.229828 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.115309 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.084449 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.083799 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.017972 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011668 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005566 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.084449 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.009778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005861 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.083799 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.017972 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70684.888876 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 80226.246291 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 76625.596229 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31506.347922 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu2.data 32994.424201 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32557.461479 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17532.667268 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17754.370121 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17687.229290 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68006.622871 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 88461.348427 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 82062.371797 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68853.054520 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 71878.582803 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 75421.232877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 68760.467980 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68853.054520 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77586.273859 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 77340.992517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2565,55 +2568,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 464425 # Transaction distribution -system.membus.trans_dist::ReadResp 464425 # Transaction distribution -system.membus.trans_dist::WriteReq 33772 # Transaction distribution -system.membus.trans_dist::WriteResp 33772 # Transaction distribution -system.membus.trans_dist::Writeback 1204773 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 613884 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 613884 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36393 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36397 # Transaction distribution -system.membus.trans_dist::ReadExReq 501696 # Transaction distribution -system.membus.trans_dist::ReadExResp 501696 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122952 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 465050 # Transaction distribution +system.membus.trans_dist::ReadResp 465050 # Transaction distribution +system.membus.trans_dist::WriteReq 33644 # Transaction distribution +system.membus.trans_dist::WriteResp 33644 # Transaction distribution +system.membus.trans_dist::Writeback 1206105 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 615969 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 615969 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36256 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 36258 # Transaction distribution +system.membus.trans_dist::ReadExReq 502974 # Transaction distribution +system.membus.trans_dist::ReadExResp 502974 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 60 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6750 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4037435 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4167195 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337326 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337326 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4504521 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156082 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4046690 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4176068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337286 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4513354 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155698 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13500 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159270496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 159440210 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14195136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14195136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173635346 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 600 # Total snoops (count) -system.membus.snoop_fanout::samples 2744389 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159620960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 159790354 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14192960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173983314 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 541 # Total snoops (count) +system.membus.snoop_fanout::samples 2749696 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2744389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2749696 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2744389 # Request fanout histogram -system.membus.reqLayer0.occupancy 42480999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2749696 # Request fanout histogram +system.membus.reqLayer0.occupancy 47655000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1323000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 1342002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 6141947499 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 3662717737 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 4337026701 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2514330197 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 38901629 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37911963 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2657,55 +2662,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 22911195 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 22910936 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33772 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33772 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7876656 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1266229 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1231725 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 45591 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 45598 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2107463 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2107463 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29129582 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28533410 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 850957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760816 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 60274765 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 929555284 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1158084670 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3113192 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6291728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2097044874 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 377016 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 34216462 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003376 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.058008 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 22942749 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 22942559 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33644 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33644 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7872498 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1267320 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1231707 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45322 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 45326 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2110986 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2110986 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 29189373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28540858 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 848998 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1760970 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 60340199 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 931468564 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1158220350 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3098688 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6299696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2099087298 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 376855 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 34241641 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003374 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.057992 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 34100938 99.66% 99.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115524 0.34% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 34126094 99.66% 99.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115547 0.34% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 34216462 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 26470973727 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 972000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 34241641 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 13384646524 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 375000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 35634626823 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 21264279204 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 11949873226 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 7318478020 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 276240027 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 275201891 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 654460701 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 650856160 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt index 726dee18b..6fc6c48c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-o3/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.358448 # Number of seconds simulated -sim_ticks 51358448410500 # Number of ticks simulated -final_tick 51358448410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.318118 # Number of seconds simulated +sim_ticks 51318118168000 # Number of ticks simulated +final_tick 51318118168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 129809 # Simulator instruction rate (inst/s) -host_op_rate 152542 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7366025588 # Simulator tick rate (ticks/s) -host_mem_usage 732256 # Number of bytes of host memory used -host_seconds 6972.34 # Real time elapsed on the host -sim_insts 905073903 # Number of instructions simulated -sim_ops 1063573170 # Number of ops (including micro ops) simulated +host_inst_rate 134411 # Simulator instruction rate (inst/s) +host_op_rate 157933 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7593762336 # Simulator tick rate (ticks/s) +host_mem_usage 732664 # Number of bytes of host memory used +host_seconds 6757.93 # Real time elapsed on the host +sim_insts 908340493 # Number of instructions simulated +sim_ops 1067303522 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 167040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 151040 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3952000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 28582936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 161216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 144320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3546944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 27869040 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 401920 # Number of bytes read from this memory -system.physmem.bytes_read::total 64976456 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3952000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3546944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 7498944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 83152960 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 160000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 146112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3855296 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 28386264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 162496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 145216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 3634496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 27952240 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 430656 # Number of bytes read from this memory +system.physmem.bytes_read::total 64872776 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3855296 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 3634496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 7489792 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 83283200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 83173540 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2610 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2360 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 61750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 446616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 2519 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2255 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 55421 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 435459 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6280 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1015270 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1299265 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 83303780 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2500 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2283 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 60239 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 443543 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2539 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2269 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 56789 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 436759 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6729 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1013650 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1301300 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1301838 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3252 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 76949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 556538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 3139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2810 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 69063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 542638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1265156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 76949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 69063 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 146012 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1619071 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1303873 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 75125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 553143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 3166 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2830 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 70823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 544686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1264130 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 75125 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 70823 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 145948 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1622881 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1619471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1619071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3252 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2941 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 76949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 556939 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 3139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 69063 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 542638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2884628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1015270 # Number of read requests accepted -system.physmem.writeReqs 1929008 # Number of write requests accepted -system.physmem.readBursts 1015270 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1929008 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 64941248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 36032 # Total number of bytes read from write queue -system.physmem.bytesWritten 123000896 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 64976456 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 123312420 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 563 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 7116 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 37405 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 61592 # Per bank write bursts -system.physmem.perBankRdBursts::1 63105 # Per bank write bursts -system.physmem.perBankRdBursts::2 59504 # Per bank write bursts -system.physmem.perBankRdBursts::3 58627 # Per bank write bursts -system.physmem.perBankRdBursts::4 63182 # Per bank write bursts -system.physmem.perBankRdBursts::5 72471 # Per bank write bursts -system.physmem.perBankRdBursts::6 63664 # Per bank write bursts -system.physmem.perBankRdBursts::7 61386 # Per bank write bursts -system.physmem.perBankRdBursts::8 55404 # Per bank write bursts -system.physmem.perBankRdBursts::9 84358 # Per bank write bursts -system.physmem.perBankRdBursts::10 61903 # Per bank write bursts -system.physmem.perBankRdBursts::11 68457 # Per bank write bursts -system.physmem.perBankRdBursts::12 58658 # Per bank write bursts -system.physmem.perBankRdBursts::13 64087 # Per bank write bursts -system.physmem.perBankRdBursts::14 58698 # Per bank write bursts -system.physmem.perBankRdBursts::15 59611 # Per bank write bursts -system.physmem.perBankWrBursts::0 118843 # Per bank write bursts -system.physmem.perBankWrBursts::1 118980 # Per bank write bursts -system.physmem.perBankWrBursts::2 119959 # Per bank write bursts -system.physmem.perBankWrBursts::3 120276 # Per bank write bursts -system.physmem.perBankWrBursts::4 119980 # Per bank write bursts -system.physmem.perBankWrBursts::5 124689 # Per bank write bursts -system.physmem.perBankWrBursts::6 121042 # Per bank write bursts -system.physmem.perBankWrBursts::7 120315 # Per bank write bursts -system.physmem.perBankWrBursts::8 116178 # Per bank write bursts -system.physmem.perBankWrBursts::9 121715 # Per bank write bursts -system.physmem.perBankWrBursts::10 120153 # Per bank write bursts -system.physmem.perBankWrBursts::11 124890 # Per bank write bursts -system.physmem.perBankWrBursts::12 118317 # Per bank write bursts -system.physmem.perBankWrBursts::13 123673 # Per bank write bursts -system.physmem.perBankWrBursts::14 117041 # Per bank write bursts -system.physmem.perBankWrBursts::15 115838 # Per bank write bursts +system.physmem.bw_write::total 1623282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1622881 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 75125 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 553544 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 3166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 70823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 544686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2887412 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1013650 # Number of read requests accepted +system.physmem.writeReqs 1930075 # Number of write requests accepted +system.physmem.readBursts 1013650 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1930075 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 64838144 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 35456 # Total number of bytes read from write queue +system.physmem.bytesWritten 120356480 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 64872776 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 123380708 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49498 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 37388 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 61871 # Per bank write bursts +system.physmem.perBankRdBursts::1 62981 # Per bank write bursts +system.physmem.perBankRdBursts::2 60043 # Per bank write bursts +system.physmem.perBankRdBursts::3 58309 # Per bank write bursts +system.physmem.perBankRdBursts::4 58023 # Per bank write bursts +system.physmem.perBankRdBursts::5 70636 # Per bank write bursts +system.physmem.perBankRdBursts::6 62371 # Per bank write bursts +system.physmem.perBankRdBursts::7 61877 # Per bank write bursts +system.physmem.perBankRdBursts::8 57508 # Per bank write bursts +system.physmem.perBankRdBursts::9 84884 # Per bank write bursts +system.physmem.perBankRdBursts::10 63101 # Per bank write bursts +system.physmem.perBankRdBursts::11 65471 # Per bank write bursts +system.physmem.perBankRdBursts::12 60660 # Per bank write bursts +system.physmem.perBankRdBursts::13 66399 # Per bank write bursts +system.physmem.perBankRdBursts::14 58532 # Per bank write bursts +system.physmem.perBankRdBursts::15 60430 # Per bank write bursts +system.physmem.perBankWrBursts::0 115217 # Per bank write bursts +system.physmem.perBankWrBursts::1 115969 # Per bank write bursts +system.physmem.perBankWrBursts::2 118272 # Per bank write bursts +system.physmem.perBankWrBursts::3 117255 # Per bank write bursts +system.physmem.perBankWrBursts::4 115771 # Per bank write bursts +system.physmem.perBankWrBursts::5 124355 # Per bank write bursts +system.physmem.perBankWrBursts::6 120059 # Per bank write bursts +system.physmem.perBankWrBursts::7 119259 # Per bank write bursts +system.physmem.perBankWrBursts::8 113485 # Per bank write bursts +system.physmem.perBankWrBursts::9 118397 # Per bank write bursts +system.physmem.perBankWrBursts::10 117107 # Per bank write bursts +system.physmem.perBankWrBursts::11 118510 # Per bank write bursts +system.physmem.perBankWrBursts::12 116303 # Per bank write bursts +system.physmem.perBankWrBursts::13 122603 # Per bank write bursts +system.physmem.perBankWrBursts::14 113656 # Per bank write bursts +system.physmem.perBankWrBursts::15 114352 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 47 # Number of times write queue was full causing retry -system.physmem.totGap 51358447292000 # Total gap between requests +system.physmem.numWrRetry 644 # Number of times write queue was full causing retry +system.physmem.totGap 51318117066500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1015255 # Read request sizes (log2) +system.physmem.readPktSize::6 1013635 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1926435 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 609091 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 267826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 93793 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 40314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1010 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 457 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 239 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 126 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 99 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 98 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1927502 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 564185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 294633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 102008 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 45915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 724 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 557 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 502 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 491 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 159 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see @@ -162,210 +162,175 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 758 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 754 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 753 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 749 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 38881 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 70996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 81306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 95128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 107299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 121019 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 120126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 130475 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 126860 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 138884 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 129040 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 115411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 107895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 107384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 92996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 90709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 88958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 85252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 5055 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 4246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 3661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 3304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3180 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 3084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 2834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2755 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2645 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 2574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 2347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 2185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 2183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 1979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 1838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 1672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 1507 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 1241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 1063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 113 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 633988 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 296.443718 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 168.837628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.480307 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 262069 41.34% 41.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 150940 23.81% 65.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 56528 8.92% 74.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28800 4.54% 78.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20482 3.23% 81.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13112 2.07% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10788 1.70% 85.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9843 1.55% 87.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 81426 12.84% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 633988 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 79397 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 12.779954 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 57.830581 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 79390 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 729 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 731 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 721 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 732 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 29010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 66066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 62259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 89013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 88926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 107579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 106733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 116711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 108023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 122723 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 101978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 129145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 103612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 95256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 108517 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 90319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 86324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 81769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 9575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 8389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 9986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 8806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 9359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 9979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 8573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 8083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 7257 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 7806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 7695 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 6239 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 6318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 4640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 3932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 3740 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 3115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 3218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 2806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 3055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 2506 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 3036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 2297 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 2830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 4689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 976 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2118 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 627585 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 295.090291 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 168.534210 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 332.652886 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 259317 41.32% 41.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 149298 23.79% 65.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 56496 9.00% 74.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28437 4.53% 78.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 21665 3.45% 82.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12676 2.02% 84.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 11310 1.80% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8646 1.38% 87.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 79740 12.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 627585 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 69573 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 14.561338 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 62.076495 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 69566 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::512-1023 3 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2559 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-2047 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::11776-12287 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 79397 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 79397 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.206066 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.327441 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 16.891492 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 78 0.10% 0.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 11 0.01% 0.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 8 0.01% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 74 0.09% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 53395 67.25% 67.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 2838 3.57% 71.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 719 0.91% 71.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 6583 8.29% 80.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 7477 9.42% 89.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 1320 1.66% 91.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1452 1.83% 93.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 838 1.06% 94.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 841 1.06% 95.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 314 0.40% 95.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 349 0.44% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 180 0.23% 96.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 342 0.43% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 280 0.35% 97.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 234 0.29% 97.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 238 0.30% 97.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 362 0.46% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 134 0.17% 98.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 99 0.12% 98.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 90 0.11% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 295 0.37% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 94 0.12% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 72 0.09% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 132 0.17% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 106 0.13% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 42 0.05% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 41 0.05% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 32 0.04% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 104 0.13% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 22 0.03% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 10 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 15 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 22 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 21 0.03% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 15 0.02% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 11 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 20 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 17 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 9 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 5 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 5 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 6 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::236-239 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-243 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 79397 # Writes before turning the bus around for reads -system.physmem.totQLat 27026112263 # Total ticks spent queuing -system.physmem.totMemAccLat 46051868513 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 5073535000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26634.40 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 69573 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 69573 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.030170 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 20.998159 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 37.100716 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-31 59064 84.90% 84.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-63 4267 6.13% 91.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-95 4153 5.97% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-127 990 1.42% 98.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-159 298 0.43% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-191 151 0.22% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-223 89 0.13% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-255 92 0.13% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-287 109 0.16% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-319 106 0.15% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-351 80 0.11% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-383 57 0.08% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-415 25 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-447 19 0.03% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-479 14 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-511 19 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-543 11 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-575 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-607 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-639 3 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-671 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-703 6 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-767 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::768-799 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::960-991 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1152-1183 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1600-1631 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 69573 # Writes before turning the bus around for reads +system.physmem.totQLat 27603415095 # Total ticks spent queuing +system.physmem.totMemAccLat 46598965095 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 5065480000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27246.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45384.40 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 45996.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.26 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBW 2.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.26 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.40 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 10.31 # Average write queue length when enqueuing -system.physmem.readRowHits 781715 # Number of row buffer hits during reads -system.physmem.writeRowHits 1520891 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.04 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes -system.physmem.avgGap 17443477.58 # Average gap between requests -system.physmem.pageHitRate 78.41 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2437517880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1329994875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3927541800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6247264320 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3354484136640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1237564295100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29729485998000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34335476748615 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.545842 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49457442122001 # Time in different power states -system.physmem_0.memoryStateTime::REF 1714971440000 # Time in different power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 8.19 # Average write queue length when enqueuing +system.physmem.readRowHits 781690 # Number of row buffer hits during reads +system.physmem.writeRowHits 1484389 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.93 # Row buffer hit rate for writes +system.physmem.avgGap 17433054.06 # Average gap between requests +system.physmem.pageHitRate 78.31 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2390683680 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1304440500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3869626800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 6131097360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3351849795840 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1233875646405 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29708521981500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34307943272085 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.534751 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49422598441359 # Time in different power states +system.physmem_0.memoryStateTime::REF 1713624640000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 186034306749 # Time in different power states +system.physmem_0.memoryStateTime::ACT 181894714141 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2355431400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1285205625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3987126000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6206576400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3354484136640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1235795450580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29731037607750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34335151534395 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.539510 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49460023829001 # Time in different power states -system.physmem_1.memoryStateTime::REF 1714971440000 # Time in different power states +system.physmem_1.actEnergy 2353858920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1284347625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 4032475200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 6054996240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3351849795840 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1235994503985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29706663342750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34308233320560 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.540403 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49419482573169 # Time in different power states +system.physmem_1.memoryStateTime::REF 1713624640000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 183452804499 # Time in different power states +system.physmem_1.memoryStateTime::ACT 185010821331 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 768 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -395,15 +360,15 @@ system.cf0.dma_read_txs 122 # Nu system.cf0.dma_write_full_pages 1666 # Number of full page size DMA writes. system.cf0.dma_write_bytes 6826496 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 1669 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 134182977 # Number of BP lookups -system.cpu0.branchPred.condPredicted 91246699 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 5930019 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 92418572 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 65829087 # Number of BTB hits +system.cpu0.branchPred.lookups 133240776 # Number of BP lookups +system.cpu0.branchPred.condPredicted 90773806 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 5898398 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 90806413 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 65300191 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.229284 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 17386110 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 187768 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.911431 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 17271308 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 187435 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -434,97 +399,86 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 898809 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 898809 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 17395 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 94113 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 544060 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 354749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 2049.828188 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 11956.771667 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-32767 349905 98.63% 98.63% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-65535 2560 0.72% 99.36% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::65536-98303 1330 0.37% 99.73% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-131071 450 0.13% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::131072-163839 167 0.05% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::163840-196607 126 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::196608-229375 45 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::229376-262143 59 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::262144-294911 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::294912-327679 16 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::327680-360447 24 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::360448-393215 21 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::393216-425983 8 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 354749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 411281 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 21163.528109 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 16798.259479 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15588.127658 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 367100 89.26% 89.26% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 39499 9.60% 98.86% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 2985 0.73% 99.59% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 830 0.20% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 180 0.04% 99.83% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 394 0.10% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 143 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 73 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 22 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 14 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 12 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 17 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 10 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 411281 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 359646036796 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.131612 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.643594 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-3 358749976796 99.75% 99.75% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-7 501279000 0.14% 99.89% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-11 178636500 0.05% 99.94% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-15 105104000 0.03% 99.97% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-19 41922000 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::20-23 20797500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::24-27 20431000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::28-31 22734000 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::32-35 4793500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::36-39 308500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::40-43 38000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walks 900960 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 900960 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 16847 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 91388 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 546326 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 354634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 2141.455698 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 12590.575916 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-65535 352292 99.34% 99.34% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-131071 1866 0.53% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::131072-196607 247 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::196608-262143 95 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::262144-327679 68 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::327680-393215 37 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 354634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 411836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 21432.646658 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 17288.307814 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 16337.255715 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 405278 98.41% 98.41% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 5723 1.39% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 333 0.08% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 332 0.08% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 90 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 39 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 17 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 21 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 411836 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 323720569592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.132299 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.681450 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-3 322818413592 99.72% 99.72% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-7 497609500 0.15% 99.88% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-11 179612000 0.06% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-15 106469500 0.03% 99.96% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-19 44651500 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::20-23 21065000 0.01% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::24-27 19836500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::28-31 27755000 0.01% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::32-35 4822000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::36-39 304000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::40-43 19500 0.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::44-47 8500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::48-51 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::52-55 3500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 359646036796 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 94113 84.40% 84.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 17395 15.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 111508 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 898809 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walksPending::48-51 3000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 323720569592 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 91388 84.43% 84.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 16847 15.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 108235 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 900960 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 898809 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 111508 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 900960 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 108235 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 111508 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 1010317 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 108235 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 1009195 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 106848795 # DTB read hits -system.cpu0.dtb.read_misses 623268 # DTB read misses -system.cpu0.dtb.write_hits 83024984 # DTB write hits -system.cpu0.dtb.write_misses 275541 # DTB write misses -system.cpu0.dtb.flush_tlb 1088 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 105886901 # DTB read hits +system.cpu0.dtb.read_misses 623655 # DTB read misses +system.cpu0.dtb.write_hits 81874264 # DTB write hits +system.cpu0.dtb.write_misses 277305 # DTB write misses +system.cpu0.dtb.flush_tlb 1077 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 21670 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56194 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 160 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 9669 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_tlb_mva_asid 22243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 520 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 54719 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 205 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 9949 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 56033 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 107472063 # DTB read accesses -system.cpu0.dtb.write_accesses 83300525 # DTB write accesses +system.cpu0.dtb.perms_faults 55268 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 106510556 # DTB read accesses +system.cpu0.dtb.write_accesses 82151569 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 189873779 # DTB hits -system.cpu0.dtb.misses 898809 # DTB misses -system.cpu0.dtb.accesses 190772588 # DTB accesses +system.cpu0.dtb.hits 187761165 # DTB hits +system.cpu0.dtb.misses 900960 # DTB misses +system.cpu0.dtb.accesses 188662125 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -554,673 +508,680 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 108604 # Table walker walks requested -system.cpu0.itb.walker.walksLong 108604 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 3026 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 75552 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 14309 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 94295 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 1394.214964 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 8384.902945 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-32767 93563 99.22% 99.22% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-65535 326 0.35% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::65536-98303 303 0.32% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::98304-131071 55 0.06% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::131072-163839 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::196608-229375 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::229376-262143 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::262144-294911 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 94295 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 92887 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25650.201395 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21071.590317 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 17522.957706 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 91125 98.10% 98.10% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1488 1.60% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 173 0.19% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 55 0.06% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 22 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 17 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 92887 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 604413242668 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.909243 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.287630 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 54912274056 9.09% 9.09% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 549448743612 90.91% 99.99% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 47582500 0.01% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 4106500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::4 406500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::5 121000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::6 8500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 604413242668 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 75552 96.15% 96.15% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 3026 3.85% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 78578 # Table walker page sizes translated +system.cpu0.itb.walker.walks 103995 # Table walker walks requested +system.cpu0.itb.walker.walksLong 103995 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 2920 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 70184 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 13953 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 90042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 1564.791986 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 9356.128105 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-32767 89344 99.22% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-65535 299 0.33% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::65536-98303 238 0.26% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::98304-131071 101 0.11% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::131072-163839 19 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::196608-229375 12 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::229376-262143 4 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::262144-294911 7 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 90042 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 87057 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26438.085553 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 21999.622082 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 18398.516639 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 48630 55.86% 55.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 36690 42.14% 98.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 630 0.72% 98.73% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 790 0.91% 99.64% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 103 0.12% 99.75% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 96 0.11% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 32 0.04% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 31 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 24 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 18 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 10 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::425984-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 87057 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 276399275336 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.905006 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -250074257964 -90.48% -90.48% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 526414060300 190.45% 99.98% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 52102500 0.02% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 6093500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::4 943000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::5 232500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::6 42500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::7 59000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 276399275336 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 70184 96.01% 96.01% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2920 3.99% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 73104 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 108604 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 108604 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 103995 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 103995 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 78578 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 78578 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 187182 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 96451691 # ITB inst hits -system.cpu0.itb.inst_misses 108604 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 73104 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 73104 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 177099 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 95374234 # ITB inst hits +system.cpu0.itb.inst_misses 103995 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 1088 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 1077 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 21670 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 527 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 42484 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 22243 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 520 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40386 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 204587 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 207806 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 96560295 # ITB inst accesses -system.cpu0.itb.hits 96451691 # DTB hits -system.cpu0.itb.misses 108604 # DTB misses -system.cpu0.itb.accesses 96560295 # DTB accesses -system.cpu0.numCycles 678169162 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 95478229 # ITB inst accesses +system.cpu0.itb.hits 95374234 # DTB hits +system.cpu0.itb.misses 103995 # DTB misses +system.cpu0.itb.accesses 95478229 # DTB accesses +system.cpu0.numCycles 670757384 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 248888472 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 597668364 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 134182977 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 83215197 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 388705337 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 13495131 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 2539677 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 21156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 4430 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 5365960 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 171714 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 1942 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 96228071 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 3656691 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 42208 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 652445982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.071952 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.318616 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 244295585 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 592642803 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 133240776 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 82571499 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 387821427 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 13413764 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 2417197 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 21066 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 3440 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 5441880 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 164758 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 2028 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 95148929 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 3635106 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 41714 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 646873994 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.071808 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.317751 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 504779765 77.37% 77.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 18600914 2.85% 80.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 18675892 2.86% 83.08% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 13601130 2.08% 85.17% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 28939785 4.44% 89.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 9186194 1.41% 91.01% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 9881419 1.51% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 8590984 1.32% 93.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 40189899 6.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 500514392 77.37% 77.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 18314774 2.83% 80.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 18453367 2.85% 83.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 13440049 2.08% 85.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 29078999 4.50% 89.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 9061143 1.40% 91.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 9714650 1.50% 92.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 8499613 1.31% 93.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 39797007 6.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 652445982 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.197861 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.881297 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 202230502 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 323725330 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 107157055 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 13964232 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 5366791 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 19957602 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 1400195 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 652122035 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4310941 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 5366791 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 210017200 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 28890111 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 254295095 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 113145299 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 40729265 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 636448025 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 83808 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 2425012 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 1797238 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 20704845 # Number of times rename has blocked due to SQ full -system.cpu0.rename.FullRegisterEvents 5054 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 608929978 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 980367872 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 752692960 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 918645 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 510273791 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 98656187 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 15296129 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 13303285 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 78526904 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 102548023 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 87419598 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 13782768 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 14655222 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 603808817 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 15342366 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 603678166 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 829707 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 77491896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 54214041 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 352970 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 652445982 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.925254 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.646571 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 646873994 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.198642 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.883543 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 198183326 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 323426019 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 105981621 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 13950733 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 5329290 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 19638547 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 1397625 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 646526277 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4318123 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 5329290 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 205971985 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 23697587 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 259101155 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 111995163 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 40775442 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 631047036 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 83751 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 2209243 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 1613560 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 20761963 # Number of times rename has blocked due to SQ full +system.cpu0.rename.FullRegisterEvents 3444 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 605295621 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 976490610 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 746368883 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 733214 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 508351996 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 96943625 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 15774650 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 13795198 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 78408950 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 101681556 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 86254396 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 13698017 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 14540360 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 598113520 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 15856672 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 599090036 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 857856 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 76035125 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 52627296 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 360655 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 646873994 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.926131 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.649248 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 415092251 63.62% 63.62% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 100237257 15.36% 78.98% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 44034564 6.75% 85.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 31483239 4.83% 90.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 23657330 3.63% 94.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 16258445 2.49% 96.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 10998020 1.69% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 6466609 0.99% 99.35% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 4218267 0.65% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 410738698 63.50% 63.50% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 100810060 15.58% 79.08% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 43443549 6.72% 85.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 31018554 4.80% 90.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 22931602 3.54% 94.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 16104373 2.49% 96.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 11033021 1.71% 98.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 6462279 1.00% 99.33% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 4331858 0.67% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 652445982 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 646873994 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 3031745 25.47% 25.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 22352 0.19% 25.65% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 2380 0.02% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 2 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4899657 41.16% 66.83% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 3948703 33.17% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 2999808 25.24% 25.24% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 22948 0.19% 25.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 2663 0.02% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 3 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 25.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4871857 40.99% 66.45% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 3988147 33.55% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 408914830 67.74% 67.74% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 1483700 0.25% 67.98% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 67594 0.01% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 189 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 10 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 26 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 67735 0.01% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.01% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 109003987 18.06% 86.06% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 84140078 13.94% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 4 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 406422040 67.84% 67.84% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 1476912 0.25% 68.09% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 65361 0.01% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 96 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 1 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 58788 0.01% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 108073598 18.04% 86.15% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82993236 13.85% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 603678166 # Type of FU issued -system.cpu0.iq.rate 0.890159 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 11904839 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.019721 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1871435984 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 696824280 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 580857585 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 1100876 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 525941 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 475487 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 614994656 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 588349 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 4797344 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 599090036 # Type of FU issued +system.cpu0.iq.rate 0.893155 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 11885426 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.019839 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1856813329 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 690194574 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 576693438 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 984019 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 484790 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 438468 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 610449620 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 525838 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 4726109 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 16957941 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 22519 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 718505 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 9238289 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 16731454 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 21127 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 684950 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 9161643 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 3918093 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 8730401 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 3853062 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 8592397 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 5366791 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 15638409 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 11458161 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 619287399 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 1818065 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 102548023 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 87419598 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 13010956 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 256814 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 11089494 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 718505 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 2724850 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 2330540 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 5055390 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 596785117 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 106839289 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 6007087 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 5329290 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14836046 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 7169747 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 614106722 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 1810261 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 101681556 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 86254396 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 13499171 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 248453 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 6830033 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 684950 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 2723761 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 2339558 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 5063319 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 592213762 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 105878130 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 5990174 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 136216 # number of nop insts executed -system.cpu0.iew.exec_refs 189866682 # number of memory reference insts executed -system.cpu0.iew.exec_branches 110402162 # Number of branches executed -system.cpu0.iew.exec_stores 83027393 # Number of stores executed -system.cpu0.iew.exec_rate 0.879994 # Inst execution rate -system.cpu0.iew.wb_sent 582539449 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 581333072 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 286508471 # num instructions producing a value -system.cpu0.iew.wb_consumers 497555384 # num instructions consuming a value +system.cpu0.iew.exec_nop 136530 # number of nop insts executed +system.cpu0.iew.exec_refs 187756937 # number of memory reference insts executed +system.cpu0.iew.exec_branches 109862908 # Number of branches executed +system.cpu0.iew.exec_stores 81878807 # Number of stores executed +system.cpu0.iew.exec_rate 0.882903 # Inst execution rate +system.cpu0.iew.wb_sent 578421970 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 577131906 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 284711853 # num instructions producing a value +system.cpu0.iew.wb_consumers 494921051 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.857210 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.575832 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.860418 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.575267 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 83249738 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 14989396 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 4548973 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 638320811 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.839633 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.833868 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 81841846 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 15496017 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 4520537 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 632994694 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.840706 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.831217 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 441333872 69.14% 69.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 97259629 15.24% 84.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 33853962 5.30% 89.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 15327337 2.40% 92.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 10781377 1.69% 93.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 6688169 1.05% 94.82% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 6042869 0.95% 95.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 4086388 0.64% 96.41% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 22947208 3.59% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 436057133 68.89% 68.89% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 98370072 15.54% 84.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 33369017 5.27% 89.70% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 15116509 2.39% 92.09% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 10820224 1.71% 93.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 6529796 1.03% 94.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 6075579 0.96% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 3929496 0.62% 96.41% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 22726868 3.59% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 638320811 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 456208771 # Number of instructions committed -system.cpu0.commit.committedOps 535955511 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 632994694 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453175477 # Number of instructions committed +system.cpu0.commit.committedOps 532162399 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 163771391 # Number of memory references committed -system.cpu0.commit.loads 85590082 # Number of loads committed -system.cpu0.commit.membars 3686850 # Number of memory barriers committed -system.cpu0.commit.branches 101715990 # Number of branches committed -system.cpu0.commit.fp_insts 455933 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 492018334 # Number of committed integer instructions. -system.cpu0.commit.function_calls 13342246 # Number of function calls committed. +system.cpu0.commit.refs 162042855 # Number of memory references committed +system.cpu0.commit.loads 84950102 # Number of loads committed +system.cpu0.commit.membars 3716655 # Number of memory barriers committed +system.cpu0.commit.branches 101218853 # Number of branches committed +system.cpu0.commit.fp_insts 419354 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 488117298 # Number of committed integer instructions. +system.cpu0.commit.function_calls 13243427 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 370951931 69.21% 69.21% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 1123996 0.21% 69.42% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 50135 0.01% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 58016 0.01% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.44% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 85590082 15.97% 85.41% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 78181309 14.59% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 368889724 69.32% 69.32% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 1132190 0.21% 69.53% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 48139 0.01% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.54% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 49491 0.01% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 84950102 15.96% 85.51% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 77092753 14.49% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 535955511 # Class of committed instruction -system.cpu0.commit.bw_lim_events 22947208 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 532162399 # Class of committed instruction +system.cpu0.commit.bw_lim_events 22726868 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 1230638929 # The number of ROB reads -system.cpu0.rob.rob_writes 1252557383 # The number of ROB writes -system.cpu0.timesIdled 4102528 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 25723180 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 48923483834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 456208771 # Number of Instructions Simulated -system.cpu0.committedOps 535955511 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.486532 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.486532 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.672706 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.672706 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 703703491 # number of integer regfile reads -system.cpu0.int_regfile_writes 414789220 # number of integer regfile writes -system.cpu0.fp_regfile_reads 851205 # number of floating regfile reads -system.cpu0.fp_regfile_writes 517790 # number of floating regfile writes -system.cpu0.cc_regfile_reads 127713204 # number of cc regfile reads -system.cpu0.cc_regfile_writes 128825628 # number of cc regfile writes -system.cpu0.misc_regfile_reads 2353610328 # number of misc regfile reads -system.cpu0.misc_regfile_writes 15112961 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 10694855 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.983549 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 305873629 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 10695367 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 28.598703 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1654841000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 310.817389 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 201.166160 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.607065 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.392903 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999968 # Average percentage of cache occupancy +system.cpu0.rob.rob_reads 1220262369 # The number of ROB reads +system.cpu0.rob.rob_writes 1241914021 # The number of ROB writes +system.cpu0.timesIdled 4040058 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 23883390 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 52531652861 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 453175477 # Number of Instructions Simulated +system.cpu0.committedOps 532162399 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.480127 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.480127 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.675618 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.675618 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 698520758 # number of integer regfile reads +system.cpu0.int_regfile_writes 411524007 # number of integer regfile writes +system.cpu0.fp_regfile_reads 797183 # number of floating regfile reads +system.cpu0.fp_regfile_writes 468068 # number of floating regfile writes +system.cpu0.cc_regfile_reads 128308023 # number of cc regfile reads +system.cpu0.cc_regfile_writes 129504102 # number of cc regfile writes +system.cpu0.misc_regfile_reads 2335799510 # number of misc regfile reads +system.cpu0.misc_regfile_writes 15629054 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 10737693 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.983333 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 307043958 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10738205 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.593602 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1675743000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 201.777727 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 310.205606 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.394097 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.605870 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999967 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 313 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 24 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1351414929 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1351414929 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 81475453 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 80033887 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 161509340 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 68849485 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 67022058 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 135871543 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 201211 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202496 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 403707 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 171344 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 154502 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 325846 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1773976 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1825826 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3599802 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028728 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2086704 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4115432 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 150324938 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 147055945 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 297380883 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150526149 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 147258441 # number of overall hits -system.cpu0.dcache.overall_hits::total 297784590 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 6522961 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 6552499 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 13075460 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 6494487 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 6576721 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 13071208 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 662604 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 664801 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1327405 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 630242 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 610465 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1240707 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 318489 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 320942 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 639431 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu1.data 6 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 13017448 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 13129220 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 26146668 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 13680052 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 13794021 # number of overall misses -system.cpu0.dcache.overall_misses::total 27474073 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 112227265953 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 112380964165 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 224608230118 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 258123381451 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 251959078660 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 510082460111 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 25291195259 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 24024875532 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 49316070791 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4598532454 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4591438187 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 9189970641 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 13000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 148500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 161500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 370350647404 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 364340042825 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 734690690229 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 370350647404 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 364340042825 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 734690690229 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 87998414 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 86586386 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 174584800 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 75343972 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 73598779 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 148942751 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 863815 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 867297 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1731112 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 801586 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 764967 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1566553 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2092465 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2146768 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4239233 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2028729 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2086710 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4115439 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 163342386 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 160185165 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 323527551 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164206201 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 161052462 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 325258663 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074126 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.075676 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.074895 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.086198 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.089359 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.087760 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.767067 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.766521 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766793 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.786244 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.798028 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.791998 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.152208 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.149500 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.150836 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000003 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000002 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.079694 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.081963 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.080817 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.083310 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.085649 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.084468 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 17204.957373 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 17150.855600 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 17177.845377 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39744.999328 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38310.744619 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39023.360359 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 40129.339617 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 39355.041701 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39748.361854 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14438.591141 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14306.130662 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14372.106828 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24750 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23071.428571 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 28450.326623 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 27750.318970 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 28098.826597 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 27072.312839 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 26412.896053 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 26741.236737 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 59451650 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 40861 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 3737259 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 929 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.907822 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 43.983854 # average number of cycles each access was blocked +system.cpu0.dcache.tags.tag_accesses 1354997138 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1354997138 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 80652766 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 81489620 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 162142386 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 67583074 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 68792819 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 136375893 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205065 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 202220 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 407285 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 153643 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 172343 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 325986 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1812235 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1802328 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3614563 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2053127 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2077480 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4130607 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 148235840 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 150282439 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 298518279 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148440905 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 150484659 # number of overall hits +system.cpu0.dcache.overall_hits::total 298925564 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 6532573 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 6224591 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 12757164 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 6661148 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 6436273 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 13097421 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 707910 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 622488 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1330398 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 634041 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 606833 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1240874 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 305625 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 336516 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 642141 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 9 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu1.data 3 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 13193721 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 12660864 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 25854585 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 13901631 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 13283352 # number of overall misses +system.cpu0.dcache.overall_misses::total 27184983 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 101439335987 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 96122979264 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 197562315251 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 231140325721 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 230924128196 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 462064453917 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 18916873838 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 17351565044 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 36268438882 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 3997419982 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 4421548736 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 8418968718 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 187500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 109500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 297000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 332579661708 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 327047107460 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 659626769168 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 332579661708 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 327047107460 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 659626769168 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 87185339 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 87714211 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 174899550 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74244222 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 75229092 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 149473314 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 912975 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 824708 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1737683 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 787684 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 779176 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1566860 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2117860 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2138844 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4256704 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2053136 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2077483 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4130619 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 161429561 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 162943303 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 324372864 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 162342536 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 163768011 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 326110547 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.074927 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.070964 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.072940 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.089719 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.085556 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.087624 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.775388 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.754798 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.765616 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.804943 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.778814 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.791950 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.144308 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.150854 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000004 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000003 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081731 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.077701 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.079706 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085631 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.081111 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.083361 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15528.236116 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15442.457065 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15486.382024 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34699.773331 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35878.547755 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35279.041112 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 29835.411019 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 28593.641157 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 29228.139909 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13079.492784 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13139.193191 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13110.778969 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 20833.333333 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 36500 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24750 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25207.419628 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 25831.341957 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 25512.951346 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 23923.787195 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 24620.826690 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 24264.380418 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 52126007 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 51266 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 3578465 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 1028 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.566583 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 49.869650 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8181117 # number of writebacks -system.cpu0.dcache.writebacks::total 8181117 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3664959 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3663666 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 7328625 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5405222 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5470276 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 10875498 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 3366 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3580 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 6946 # number of WriteInvalidateReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 193804 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 194772 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 388576 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 9070181 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 9133942 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 18204123 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 9070181 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 9133942 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 18204123 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2858002 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2888833 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 5746835 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1089265 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1106445 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 2195710 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 655865 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 659095 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 1314960 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 626876 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 606885 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1233761 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 124685 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 126170 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 250855 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 6 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 3947267 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 3995278 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 7942545 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4603132 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 4654373 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 9257505 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43426889493 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 44103833792 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 87530723285 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 40333598117 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 39629888189 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 79963486306 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12970544028 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12958416533 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 25928960561 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 23908668069 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 22678349912 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 46587017981 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1638689162 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1618682187 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3257371349 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 11000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 136500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 147500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 83760487610 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 83733721981 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 167494209591 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 96731031638 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 96692138514 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 193423170152 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2840564251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2875998253 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5716562504 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2826497047 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2753568465 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5580065512 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5667061298 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5629566718 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11296628016 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032478 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033364 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032917 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014457 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.015033 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014742 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759266 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.759942 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759604 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.782045 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.793348 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787564 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059588 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058772 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059175 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000003 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000002 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024166 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024942 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024550 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028033 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028900 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028462 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15194.842233 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15267.007055 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15231.118222 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37028.269629 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35817.314181 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36418.054436 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19776.240580 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19660.923741 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19718.440531 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38139.389718 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 37368.446925 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 37760.164230 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.632730 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12829.374550 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12985.076435 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22750 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21071.428571 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21219.868737 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20958.171617 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21088.229225 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21014.177225 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20774.471344 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20893.660889 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 8209351 # number of writebacks +system.cpu0.dcache.writebacks::total 8209351 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3628927 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3346283 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 6975210 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 5547863 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 5347347 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 10895210 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu0.data 3396 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3377 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 6773 # number of WriteInvalidateReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 184138 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 204631 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 388769 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 9176790 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 8693630 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 17870420 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 9176790 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 8693630 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 17870420 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2903646 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2878308 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5781954 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1113285 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1088926 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2202211 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 695379 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 617800 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1313179 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 630645 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 603456 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1234101 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 121487 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 131885 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 253372 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 9 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 3 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4016931 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3967234 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7984165 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4712310 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4585034 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 9297344 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43556644701 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43095096417 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 86651741118 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 39142786504 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 39217956097 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 78360742601 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 11875956517 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9839614769 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 21715571286 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 17839341538 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 16312287276 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 34151628814 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1586128009 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1744790264 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 3330918273 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 174000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 105000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 279000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 82699431205 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 82313052514 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 165012483719 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 94575387722 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 92152667283 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 186728055005 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2796204500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2965118250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5761322750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2832162536 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2783504957 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5615667493 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5628367036 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5748623207 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11376990243 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033304 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032815 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033059 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014995 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014475 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014733 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.761663 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749114 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.755707 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.800632 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.774480 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.787627 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057363 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061662 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059523 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000004 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000003 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024883 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024347 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024614 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029027 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027997 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028510 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15000.673188 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14972.371413 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14986.584314 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35159.717866 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36015.262834 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35582.758692 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17078.393965 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15926.861070 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16536.642214 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 28287.454175 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27031.444341 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 27673.285099 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13055.948447 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13229.633878 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13146.355055 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19333.333333 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 35000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23250 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20587.715150 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 20748.222191 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20667.469137 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20069.856975 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20098.578829 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20084.021308 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1231,137 +1192,137 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 16173930 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.955160 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 173933615 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 16174442 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.753608 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13621642000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 273.473305 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 238.481855 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.534128 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.465785 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999912 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 16169102 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.955735 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 173971503 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 16169614 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.759162 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13124671250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 233.058192 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 278.897543 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.455192 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.544722 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999914 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 207440760 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 207440760 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 87577793 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 86355822 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 173933615 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87577793 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 86355822 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 173933615 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87577793 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 86355822 # number of overall hits -system.cpu0.icache.overall_hits::total 173933615 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 8637755 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 8694581 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 17332336 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 8637755 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 8694581 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 17332336 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 8637755 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 8694581 # number of overall misses -system.cpu0.icache.overall_misses::total 17332336 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 115405674014 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 116006330283 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 231412004297 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 115405674014 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 116006330283 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 231412004297 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 115405674014 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 116006330283 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 231412004297 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 96215548 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 95050403 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 191265951 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 96215548 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 95050403 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 191265951 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 96215548 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 95050403 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 191265951 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.089775 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091473 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.090619 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.089775 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.091473 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.090619 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.089775 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.091473 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.090619 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13360.609790 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13342.371563 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13351.460778 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13360.609790 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13342.371563 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13351.460778 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13360.609790 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13342.371563 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13351.460778 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 66509 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 207520278 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 207520278 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 86520761 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 87450742 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 173971503 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 86520761 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 87450742 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 173971503 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 86520761 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 87450742 # number of overall hits +system.cpu0.icache.overall_hits::total 173971503 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 8615803 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 8763236 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 17379039 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 8615803 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 8763236 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 17379039 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 8615803 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 8763236 # number of overall misses +system.cpu0.icache.overall_misses::total 17379039 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 112931076635 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 114850105161 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 227781181796 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 112931076635 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 114850105161 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 227781181796 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 112931076635 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 114850105161 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 227781181796 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 95136564 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 96213978 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 191350542 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 95136564 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 96213978 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 191350542 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 95136564 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 96213978 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 191350542 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.090562 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.091081 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.090823 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.090562 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.091081 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.090823 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.090562 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.091081 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.090823 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13107.434865 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13105.901195 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13106.661525 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13107.434865 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13105.901195 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13106.661525 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13107.434865 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13105.901195 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13106.661525 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 82244 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 6230 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 6699 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 10.675602 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.277056 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 574540 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 582987 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 1157527 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 574540 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu1.inst 582987 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 1157527 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 574540 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu1.inst 582987 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 1157527 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8063215 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8111594 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 16174809 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 8063215 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 8111594 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 16174809 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 8063215 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 8111594 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 16174809 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 94312224420 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 94761792489 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 189074016909 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 94312224420 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 94761792489 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 189074016909 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 94312224420 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 94761792489 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 189074016909 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 916338250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 595537750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1511876000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 916338250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 595537750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 1511876000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.083804 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.085340 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084567 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.083804 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.085340 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.084567 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.083804 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.085340 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.084567 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11696.602958 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11682.265223 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11689.412648 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11696.602958 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11682.265223 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11689.412648 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11696.602958 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11682.265223 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11689.412648 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 602016 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 607287 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 1209303 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 602016 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu1.inst 607287 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 1209303 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 602016 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu1.inst 607287 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 1209303 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 8013787 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 8155949 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 16169736 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 8013787 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 8155949 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 16169736 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 8013787 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 8155949 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 16169736 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95968094429 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 97614087232 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 193582181661 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 95968094429 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 97614087232 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 193582181661 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 95968094429 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 97614087232 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 193582181661 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 951349751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 639066000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 1590415751 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 951349751 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 639066000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 1590415751 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084503 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.084503 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084235 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.084769 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.084503 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11971.882637 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1369,15 +1330,15 @@ system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 132595782 # Number of BP lookups -system.cpu1.branchPred.condPredicted 89991047 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 5894262 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 90157022 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 64704998 # Number of BTB hits +system.cpu1.branchPred.lookups 133788555 # Number of BP lookups +system.cpu1.branchPred.condPredicted 90573571 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 5908759 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 92439735 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 65341745 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 71.769227 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 17429206 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 189878 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 70.685777 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 17599042 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 188594 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1407,95 +1368,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 890417 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 890417 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17386 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91593 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 535956 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 354461 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 2058.191169 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 12119.324471 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-32767 349672 98.65% 98.65% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-65535 2519 0.71% 99.36% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::65536-98303 1342 0.38% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::98304-131071 424 0.12% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::131072-163839 149 0.04% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::163840-196607 114 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::196608-229375 53 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::229376-262143 71 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::262144-294911 38 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::294912-327679 10 0.00% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::327680-360447 34 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::360448-393215 29 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::393216-425983 6 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 354461 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 404532 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 20689.820452 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 16434.872295 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 15113.304602 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 363916 89.96% 89.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 36589 9.04% 99.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 2703 0.67% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 595 0.15% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 189 0.05% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 278 0.07% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 138 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 43 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 30 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 13 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 13 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::393216-425983 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 8 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 6 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 404532 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 334236526020 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.086173 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.625283 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-3 333380386520 99.74% 99.74% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-7 477486500 0.14% 99.89% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-11 168839000 0.05% 99.94% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-15 100636500 0.03% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-19 41145500 0.01% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::20-23 20471500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::24-27 20409500 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::28-31 23342000 0.01% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::32-35 3487500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::36-39 317500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::40-43 4000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 334236526020 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 91594 84.05% 84.05% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17386 15.95% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 108980 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 890417 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 918015 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 918015 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 17288 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94464 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 562013 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 356002 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 2214.229134 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 13073.684616 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-65535 353584 99.32% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::65536-131071 1851 0.52% 99.84% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::131072-196607 299 0.08% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::196608-262143 120 0.03% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::262144-327679 79 0.02% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::327680-393215 40 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::393216-458751 25 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 356002 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 421643 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 21453.513266 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17357.718896 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 16015.202358 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 415023 98.43% 98.43% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 5756 1.37% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 364 0.09% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 366 0.09% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 85 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 33 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 421643 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 354035793664 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.135779 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.675726 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-3 353071895664 99.73% 99.73% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-7 535230500 0.15% 99.88% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-11 190116000 0.05% 99.93% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-15 115191500 0.03% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-19 44312000 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::20-23 22451500 0.01% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::24-27 21588500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::28-31 29378000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::32-35 5201500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::36-39 359000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::40-43 41000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::44-47 22500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::48-51 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 354035793664 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94465 84.53% 84.53% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 17288 15.47% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 111753 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 918015 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 890417 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 108980 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 918015 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 111753 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 108980 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 999397 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 111753 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 1029768 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 105460349 # DTB read hits -system.cpu1.dtb.read_misses 614707 # DTB read misses -system.cpu1.dtb.write_hits 81263219 # DTB write hits -system.cpu1.dtb.write_misses 275710 # DTB write misses -system.cpu1.dtb.flush_tlb 1092 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 105548583 # DTB read hits +system.cpu1.dtb.read_misses 631805 # DTB read misses +system.cpu1.dtb.write_hits 82907544 # DTB write hits +system.cpu1.dtb.write_misses 286210 # DTB write misses +system.cpu1.dtb.flush_tlb 1083 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 21988 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 544 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 55487 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 238 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 9789 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_tlb_mva_asid 21604 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 553 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56278 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 216 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 9625 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 55163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 106075056 # DTB read accesses -system.cpu1.dtb.write_accesses 81538929 # DTB write accesses +system.cpu1.dtb.perms_faults 55021 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 106180388 # DTB read accesses +system.cpu1.dtb.write_accesses 83193754 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 186723568 # DTB hits -system.cpu1.dtb.misses 890417 # DTB misses -system.cpu1.dtb.accesses 187613985 # DTB accesses +system.cpu1.dtb.hits 188456127 # DTB hits +system.cpu1.dtb.misses 918015 # DTB misses +system.cpu1.dtb.accesses 189374142 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1525,392 +1481,399 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 101825 # Table walker walks requested -system.cpu1.itb.walker.walksLong 101825 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2978 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 69124 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 13788 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 88037 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 1472.687620 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 8948.821118 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-32767 87265 99.12% 99.12% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-65535 389 0.44% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::65536-98303 275 0.31% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::98304-131071 48 0.05% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::131072-163839 27 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::163840-196607 13 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::229376-262143 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::262144-294911 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 88037 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 85890 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 25260.851287 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 20589.361475 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 17130.840101 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-65535 84234 98.07% 98.07% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-131071 1438 1.67% 99.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-196607 145 0.17% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-262143 40 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-327679 24 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-393215 4 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 85890 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 299874193152 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 1.837074 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -250957583628 -83.69% -83.69% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 550779312780 183.67% 99.98% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 46468000 0.02% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::3 5344000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::4 484000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::5 65500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::6 54500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::7 48000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 299874193152 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 69124 95.87% 95.87% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2978 4.13% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 72102 # Table walker page sizes translated +system.cpu1.itb.walker.walks 104751 # Table walker walks requested +system.cpu1.itb.walker.walksLong 104751 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 2979 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 72067 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 14103 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 90648 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 1509.569985 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 8604.112743 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-32767 89986 99.27% 99.27% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-65535 255 0.28% 99.55% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::65536-98303 242 0.27% 99.82% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::98304-131071 116 0.13% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::131072-163839 27 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::163840-196607 14 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::196608-229375 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 90648 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 89149 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 26484.081515 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 22228.139492 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17447.399907 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 48433 54.33% 54.33% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 39159 43.93% 98.25% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 575 0.64% 98.90% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 708 0.79% 99.69% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 93 0.10% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 80 0.09% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 45 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 20 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 10 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 6 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 89149 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 396982969624 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 1.388871 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -154312061728 -38.87% -38.87% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 551239764852 138.86% 99.99% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 48839000 0.01% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 5683000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 518000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::5 149500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::6 6000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::7 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::8 9000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::9 8500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::10 44500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 396982969624 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 72067 96.03% 96.03% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2979 3.97% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 75046 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 101825 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 101825 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 104751 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 104751 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 72102 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 72102 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 173927 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 95285493 # ITB inst hits -system.cpu1.itb.inst_misses 101825 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 75046 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 75046 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 179797 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 96448537 # ITB inst hits +system.cpu1.itb.inst_misses 104751 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 1092 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 1083 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 21988 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 544 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40874 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21604 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 553 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 42139 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 205822 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 204302 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 95387318 # ITB inst accesses -system.cpu1.itb.hits 95285493 # DTB hits -system.cpu1.itb.misses 101825 # DTB misses -system.cpu1.itb.accesses 95387318 # DTB accesses -system.cpu1.numCycles 677360427 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 96553288 # ITB inst accesses +system.cpu1.itb.hits 96448537 # DTB hits +system.cpu1.itb.misses 104751 # DTB misses +system.cpu1.itb.accesses 96553288 # DTB accesses +system.cpu1.numCycles 667631540 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 248549507 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 588684684 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 132595782 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 82134204 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 389145480 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 13431349 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 2335492 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 20294 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 4597 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 5447640 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 169416 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 1942 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 95058557 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 3668998 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 40025 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 652389771 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.056521 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.304488 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 247941482 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 595071407 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 133788555 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 82940787 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 381163571 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 13497944 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 2492160 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 22589 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 3825 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 5325029 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 172051 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 1992 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 96222293 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 3665245 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 41130 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 643871402 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.082515 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.328245 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 506719262 77.67% 77.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 18449281 2.83% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 18323109 2.81% 83.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 13434339 2.06% 85.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 28729534 4.40% 89.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 8986163 1.38% 91.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 9758970 1.50% 92.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 8450464 1.30% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 39538649 6.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 496782409 77.16% 77.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 18583795 2.89% 80.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 18517016 2.88% 82.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 13597412 2.11% 85.03% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 28667245 4.45% 89.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 9152993 1.42% 90.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 9918803 1.54% 92.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 8570268 1.33% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 40081461 6.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 652389771 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.195754 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.869086 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 201147393 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 326816283 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 105097642 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 14007460 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 5318954 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 19647868 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 1416154 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 641757938 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 4369017 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 5318954 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 208911045 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 28047403 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 258823969 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 111174433 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 40111705 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 626286274 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 89729 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 2292362 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 1848085 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 19940508 # Number of times rename has blocked due to SQ full -system.cpu1.rename.FullRegisterEvents 5105 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 599962292 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 966932024 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 740689310 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 881849 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 503173353 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 96788934 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 15525446 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 13560324 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 79127309 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 101049697 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 85573282 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 13915572 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 14825014 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 593826390 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 15642550 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 594476204 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 818225 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 76136612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53142905 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 356951 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 652389771 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.911229 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.632553 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 643871402 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.200393 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.891317 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 201631753 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 315887121 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 107474204 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 13522341 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 5353840 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 20035378 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 1415024 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 649950843 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 4347472 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 5353840 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 209303047 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22542941 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 254388545 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 113174340 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 39106401 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 634340427 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 84329 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 1777036 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 1562975 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 19949989 # Number of times rename has blocked due to SQ full +system.cpu1.rename.FullRegisterEvents 3657 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 605941232 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 974899397 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 750081260 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 811718 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 508709616 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 97231611 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 15188925 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 13206274 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 75533982 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 102194667 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 87314859 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 13957552 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 14774854 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 601797044 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 15287986 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 601499543 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 865295 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 76155843 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52376442 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 362406 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 643871402 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.934192 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.656161 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 416908971 63.90% 63.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 100667120 15.43% 79.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43571359 6.68% 86.01% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 31041594 4.76% 90.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 23116047 3.54% 94.32% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 15866958 2.43% 96.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 10833871 1.66% 98.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 6331428 0.97% 99.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 4052423 0.62% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 408171960 63.39% 63.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 99067431 15.39% 78.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 44002532 6.83% 85.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 31313283 4.86% 90.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 23144485 3.59% 94.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 16264635 2.53% 96.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 11075626 1.72% 98.32% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 6519272 1.01% 99.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 4312178 0.67% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 652389771 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 643871402 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 2996828 25.66% 25.66% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 24624 0.21% 25.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 2734 0.02% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 3 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 25.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4869636 41.69% 67.58% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 3787065 32.42% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 3037678 26.20% 26.20% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 24339 0.21% 26.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 2694 0.02% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 4 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 26.43% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4607398 39.74% 66.17% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 3921783 33.83% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 402964828 67.78% 67.78% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 1445986 0.24% 68.03% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 66608 0.01% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 132 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 1 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.04% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 61370 0.01% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.05% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 107585906 18.10% 86.15% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 82351372 13.85% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 408162511 67.86% 67.86% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 1426997 0.24% 68.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 69303 0.01% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 134 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 9 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 14 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 22 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.11% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 70416 0.01% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.12% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 107729216 17.91% 86.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 84040920 13.97% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 594476204 # Type of FU issued -system.cpu1.iq.rate 0.877636 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 11680890 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.019649 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 1852781725 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 685800777 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 571863197 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 1059569 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 502092 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 457373 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 605590748 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 566345 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 4749876 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 601499543 # Type of FU issued +system.cpu1.iq.rate 0.900945 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 11593896 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.019275 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 1858238935 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 693444958 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 579923061 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 1090744 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 536293 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 488146 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 612510547 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 582891 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 4820885 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 16757289 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 22108 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 708788 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 9117452 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 16648209 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 23106 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 751890 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 9224511 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 3937125 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 8714130 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 4009170 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 7426024 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 5318954 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 15381414 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 10835277 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 609605144 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 1787029 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 101049697 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 85573282 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 13260611 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 256865 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 10466220 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 708788 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 2676587 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 2314011 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 4990598 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 587727574 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 105451218 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 5872593 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 5353840 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 14516681 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 6539646 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 617219827 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 1819635 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 102194667 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 87314859 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 12911400 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 240081 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6211315 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 751890 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 2725767 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 2332140 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 5057907 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 594561904 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 105538370 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 6033124 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 136204 # number of nop insts executed -system.cpu1.iew.exec_refs 186716455 # number of memory reference insts executed -system.cpu1.iew.exec_branches 109034476 # Number of branches executed -system.cpu1.iew.exec_stores 81265237 # Number of stores executed -system.cpu1.iew.exec_rate 0.867673 # Inst execution rate -system.cpu1.iew.wb_sent 573536970 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 572320570 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 281697554 # num instructions producing a value -system.cpu1.iew.wb_consumers 489376492 # num instructions consuming a value +system.cpu1.iew.exec_nop 134797 # number of nop insts executed +system.cpu1.iew.exec_refs 188445888 # number of memory reference insts executed +system.cpu1.iew.exec_branches 110364560 # Number of branches executed +system.cpu1.iew.exec_stores 82907518 # Number of stores executed +system.cpu1.iew.exec_rate 0.890554 # Inst execution rate +system.cpu1.iew.wb_sent 581679133 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 580411207 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 286057076 # num instructions producing a value +system.cpu1.iew.wb_consumers 496538403 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.844928 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.575625 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.869359 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.576103 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 81905872 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 15285599 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 4497270 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 638458448 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.826393 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.816586 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 81975668 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 14925580 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 4513358 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 629946041 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.849503 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.842378 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 442788562 69.35% 69.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 97620349 15.29% 84.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 33589881 5.26% 89.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 14950626 2.34% 92.25% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 10704317 1.68% 93.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 6546690 1.03% 94.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 5838446 0.91% 95.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 3972340 0.62% 96.48% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 22447237 3.52% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 433603733 68.83% 68.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 96615693 15.34% 84.17% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 33704251 5.35% 89.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 15419971 2.45% 91.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 10970958 1.74% 93.71% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 6585832 1.05% 94.75% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 6182969 0.98% 95.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 3954863 0.63% 96.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 22907771 3.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 638458448 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 448865132 # Number of instructions committed -system.cpu1.commit.committedOps 527617659 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 629946041 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 455165016 # Number of instructions committed +system.cpu1.commit.committedOps 535141123 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 160748237 # Number of memory references committed -system.cpu1.commit.loads 84292407 # Number of loads committed -system.cpu1.commit.membars 3769330 # Number of memory barriers committed -system.cpu1.commit.branches 100442689 # Number of branches committed -system.cpu1.commit.fp_insts 439800 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 484228202 # Number of committed integer instructions. -system.cpu1.commit.function_calls 13335340 # Number of function calls committed. +system.cpu1.commit.refs 163636805 # Number of memory references committed +system.cpu1.commit.loads 85546457 # Number of loads committed +system.cpu1.commit.membars 3765916 # Number of memory barriers committed +system.cpu1.commit.branches 101697828 # Number of branches committed +system.cpu1.commit.fp_insts 467953 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 491500354 # Number of committed integer instructions. +system.cpu1.commit.function_calls 13521989 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 365655543 69.30% 69.30% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 1112211 0.21% 69.51% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 49677 0.01% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.52% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 51991 0.01% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.53% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 84292407 15.98% 85.51% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 76455830 14.49% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 370285651 69.19% 69.19% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 1106053 0.21% 69.40% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 52121 0.01% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.41% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 60451 0.01% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.42% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 85546457 15.99% 85.41% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 78090348 14.59% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 527617659 # Class of committed instruction -system.cpu1.commit.bw_lim_events 22447237 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 535141123 # Class of committed instruction +system.cpu1.commit.bw_lim_events 22907771 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 1221498833 # The number of ROB reads -system.cpu1.rob.rob_writes 1232997569 # The number of ROB writes -system.cpu1.timesIdled 4096806 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 24970656 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 52437515063 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 448865132 # Number of Instructions Simulated -system.cpu1.committedOps 527617659 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 1.509051 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.509051 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.662668 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.662668 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 693047790 # number of integer regfile reads -system.cpu1.int_regfile_writes 408438474 # number of integer regfile writes -system.cpu1.fp_regfile_reads 823112 # number of floating regfile reads -system.cpu1.fp_regfile_writes 494780 # number of floating regfile writes -system.cpu1.cc_regfile_reads 126134775 # number of cc regfile reads -system.cpu1.cc_regfile_writes 127188255 # number of cc regfile writes -system.cpu1.misc_regfile_reads 2330176021 # number of misc regfile reads -system.cpu1.misc_regfile_writes 15424448 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 40375 # Transaction distribution -system.iobus.trans_dist::ReadResp 40375 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.cpu1.rob.rob_reads 1220174232 # The number of ROB reads +system.cpu1.rob.rob_writes 1248183780 # The number of ROB writes +system.cpu1.timesIdled 4134360 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 23760138 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 48765821681 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 455165016 # Number of Instructions Simulated +system.cpu1.committedOps 535141123 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 1.466790 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.466790 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.681761 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.681761 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 701277155 # number of integer regfile reads +system.cpu1.int_regfile_writes 414494210 # number of integer regfile writes +system.cpu1.fp_regfile_reads 871148 # number of floating regfile reads +system.cpu1.fp_regfile_writes 523684 # number of floating regfile writes +system.cpu1.cc_regfile_reads 126609999 # number of cc regfile reads +system.cpu1.cc_regfile_writes 127812398 # number of cc regfile writes +system.cpu1.misc_regfile_reads 2340278076 # number of misc regfile reads +system.cpu1.misc_regfile_writes 15057964 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 40297 # Transaction distribution +system.iobus.trans_dist::ReadResp 40297 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1925,13 +1888,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230946 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354216 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353736 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1946,13 +1909,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334216 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334216 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334240 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492622 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492160 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1980,71 +1943,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042399628 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607055505 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 178994733 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148389509 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115455 # number of replacements -system.iocache.tags.tagsinuse 10.429644 # Cycle average of tags in use +system.iocache.tags.replacements 115457 # number of replacements +system.iocache.tags.tagsinuse 10.425424 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115471 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115473 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13090563453000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.541528 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.888116 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.221346 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.430507 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.651853 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13090073143000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.544298 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.881126 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.221519 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.430070 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.651589 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039614 # Number of tag accesses -system.iocache.tags.data_accesses 1039614 # Number of data accesses +system.iocache.tags.tag_accesses 1039641 # Number of tag accesses +system.iocache.tags.data_accesses 1039641 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8809 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8846 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8812 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8849 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8809 # number of demand (read+write) misses -system.iocache.demand_misses::total 8849 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8812 # number of demand (read+write) misses +system.iocache.demand_misses::total 8852 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8809 # number of overall misses -system.iocache.overall_misses::total 8849 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1920259350 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1925744350 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28938987545 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28938987545 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1920259350 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1926083350 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1920259350 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1926083350 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8812 # number of overall misses +system.iocache.overall_misses::total 8852 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1661250694 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1666322694 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19868709302 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19868709302 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1661250694 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1666675194 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1661250694 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1666675194 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8809 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8846 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8812 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8849 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8809 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8849 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8812 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8852 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8809 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8849 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8812 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8852 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2058,55 +2021,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 217988.347145 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217696.625593 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271309.790979 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271309.790979 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 217988.347145 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217661.131201 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 217988.347145 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217661.131201 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 227974 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 188521.413300 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 188306.327721 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186273.806551 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186273.806551 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 188521.413300 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 188282.330999 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 188521.413300 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 188282.330999 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 113607 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27752 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16342 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.214687 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.951842 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8809 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8812 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8849 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8809 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8849 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8812 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8852 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8809 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8849 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1462065868 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1465626868 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23392010493 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23392010493 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1462065868 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1465809868 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1462065868 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1465809868 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8812 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8852 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1201855604 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1204997604 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14322073410 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14322073410 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1201855604 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1205191104 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1201855604 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1205191104 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2120,292 +2083,297 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 165974.102395 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165682.440425 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219305.581011 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219305.581011 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 165974.102395 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165646.950842 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 165974.102395 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165646.950842 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 136388.516114 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 136173.308170 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134272.795039 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134272.795039 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 136388.516114 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 136149.017623 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 136388.516114 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 136149.017623 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1414814 # number of replacements -system.l2c.tags.tagsinuse 65356.208679 # Cycle average of tags in use -system.l2c.tags.total_refs 31586438 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1477430 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.379313 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2484527000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35855.564521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 171.544585 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 252.706280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3390.645466 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 10658.750636 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 169.049447 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 250.456312 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3915.870098 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 10691.621334 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.547112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002618 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003856 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.051737 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.162640 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002579 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003822 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.059751 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.163141 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.997257 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 354 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62262 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 353 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 517 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2774 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5014 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 53845 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.005402 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.950043 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 297087469 # Number of tag accesses -system.l2c.tags.data_accesses 297087469 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 549429 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 200595 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 8013735 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3471974 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 542581 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 184113 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 8064127 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3507527 # number of ReadReq hits -system.l2c.ReadReq_hits::total 24534081 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8181117 # number of Writeback hits -system.l2c.Writeback_hits::total 8181117 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 347604 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 365500 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 713104 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4965 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5155 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 10120 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 5 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 785554 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 813200 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1598754 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 549429 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 200595 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 8013735 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4257528 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 542581 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 184113 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 8064127 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4320727 # number of demand (read+write) hits -system.l2c.demand_hits::total 26132835 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 549429 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 200595 # number of overall hits -system.l2c.overall_hits::cpu0.inst 8013735 # number of overall hits -system.l2c.overall_hits::cpu0.data 4257528 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 542581 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 184113 # number of overall hits -system.l2c.overall_hits::cpu1.inst 8064127 # number of overall hits -system.l2c.overall_hits::cpu1.data 4320727 # number of overall hits -system.l2c.overall_hits::total 26132835 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2620 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2398 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 49272 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 160159 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 2534 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2288 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 47310 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 159515 # number of ReadReq misses -system.l2c.ReadReq_misses::total 426096 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 279272 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 241385 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 520657 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 18107 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18517 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 36624 # number of UpgradeReq misses +system.l2c.tags.replacements 1412518 # number of replacements +system.l2c.tags.tagsinuse 65354.490513 # Cycle average of tags in use +system.l2c.tags.total_refs 31645259 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1474766 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.457817 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2643820000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 35783.123237 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 158.967100 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 249.670952 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3744.975731 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 12205.230455 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 164.981843 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 255.022053 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3435.700252 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9356.818889 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.546007 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002426 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003810 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.057144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.186237 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002517 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.052425 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.142774 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997230 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 337 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 61911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 333 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 503 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2841 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5066 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53373 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.005142 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.944687 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 297548374 # Number of tag accesses +system.l2c.tags.data_accesses 297548374 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 541623 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 186900 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7965775 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3551683 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 548604 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 190887 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 8107304 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3470388 # number of ReadReq hits +system.l2c.ReadReq_hits::total 24563164 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8209351 # number of Writeback hits +system.l2c.Writeback_hits::total 8209351 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 352587 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 361830 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 714417 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 4898 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5089 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9987 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 8 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 2 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 814701 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 785760 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1600461 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 541623 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 186900 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7965775 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4366384 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 548604 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 190887 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 8107304 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4256148 # number of demand (read+write) hits +system.l2c.demand_hits::total 26163625 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 541623 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 186900 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7965775 # number of overall hits +system.l2c.overall_hits::cpu0.data 4366384 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 548604 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 190887 # number of overall hits +system.l2c.overall_hits::cpu1.inst 8107304 # number of overall hits +system.l2c.overall_hits::cpu1.data 4256148 # number of overall hits +system.l2c.overall_hits::total 26163625 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2520 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2317 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 47910 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 162942 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2554 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2304 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 48528 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 151193 # number of ReadReq misses +system.l2c.ReadReq_misses::total 420268 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 278058 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 241626 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 519684 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 18363 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18249 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 36612 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 287058 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 276629 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 563687 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2620 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2398 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 49272 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 447217 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 2534 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2288 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 47310 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 436144 # number of demand (read+write) misses -system.l2c.demand_misses::total 989783 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2620 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2398 # number of overall misses -system.l2c.overall_misses::cpu0.inst 49272 # number of overall misses -system.l2c.overall_misses::cpu0.data 447217 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 2534 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2288 # number of overall misses -system.l2c.overall_misses::cpu1.inst 47310 # number of overall misses -system.l2c.overall_misses::cpu1.data 436144 # number of overall misses -system.l2c.overall_misses::total 989783 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 212400491 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 197330496 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 3854315483 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 13456201417 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 203909739 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 185508995 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3706975739 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 13518734147 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 35335376507 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 1493436 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 2029914 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 3523350 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 214252799 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 214249795 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 428502594 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 80500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 80500 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 27645550958 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 26547753140 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 54193304098 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 212400491 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 197330496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 3854315483 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 41101752375 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 203909739 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 185508995 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3706975739 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 40066487287 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 89528680605 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 212400491 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 197330496 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 3854315483 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 41101752375 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 203909739 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 185508995 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3706975739 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 40066487287 # number of overall miss cycles -system.l2c.overall_miss_latency::total 89528680605 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 552049 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 202993 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 8063007 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3632133 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 545115 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 186401 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 8111437 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 3667042 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 24960177 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 8181117 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 8181117 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 626876 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 606885 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1233761 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 23072 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 23672 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 46744 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 6 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 7 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1072612 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1089829 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2162441 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 552049 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 202993 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 8063007 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4704745 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 545115 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 186401 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 8111437 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 4756871 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 27122618 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 552049 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 202993 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 8063007 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 4704745 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 545115 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 186401 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 8111437 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 4756871 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 27122618 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004746 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.011813 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.006111 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.044095 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004649 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.012275 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005833 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.043500 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017071 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.445498 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.397744 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.422008 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784804 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782232 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.783502 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.166667 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.142857 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.267625 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.253828 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.260672 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004746 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.011813 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.006111 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.095057 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004649 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.012275 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005833 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.091687 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.036493 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004746 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.011813 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.006111 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.095057 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004649 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.012275 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005833 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.091687 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.036493 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 81068.889695 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82289.614679 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 78225.269585 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 84017.766201 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80469.510260 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 81079.106206 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 78355.014564 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 84748.983776 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 82928.205163 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 5.347604 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 8.409445 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 6.767123 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 11832.595074 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11570.437706 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 11700.048984 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 80500 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 80500 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96306.498889 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 95968.799873 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 96140.773333 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 81068.889695 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82289.614679 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 78225.269585 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 91905.612656 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80469.510260 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 81079.106206 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 78355.014564 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 91865.272220 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 90452.837243 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 81068.889695 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82289.614679 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 78225.269585 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 91905.612656 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80469.510260 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 81079.106206 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 78355.014564 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 91865.272220 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 90452.837243 # average overall miss latency +system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 281210 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 286240 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 567450 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2520 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2317 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 47910 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 444152 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2554 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2304 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 48528 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 437433 # number of demand (read+write) misses +system.l2c.demand_misses::total 987718 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2520 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2317 # number of overall misses +system.l2c.overall_misses::cpu0.inst 47910 # number of overall misses +system.l2c.overall_misses::cpu0.data 444152 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2554 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2304 # number of overall misses +system.l2c.overall_misses::cpu1.inst 48528 # number of overall misses +system.l2c.overall_misses::cpu1.data 437433 # number of overall misses +system.l2c.overall_misses::total 987718 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 226047513 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 206307511 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 4115303294 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 15012705040 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 228872009 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 204494263 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4127840290 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 13630721751 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 37752291671 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 2347926 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 2217929 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 4565855 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 282478467 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 293943100 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 576421567 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 81000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 81000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 162000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 28614775736 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 29088522937 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 57703298673 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 226047513 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 206307511 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 4115303294 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 43627480776 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 228872009 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 204494263 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4127840290 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 42719244688 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 95455590344 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 226047513 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 206307511 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 4115303294 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 43627480776 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 228872009 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 204494263 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4127840290 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 42719244688 # number of overall miss cycles +system.l2c.overall_miss_latency::total 95455590344 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 544143 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 189217 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 8013685 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 3714625 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 551158 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 193191 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 8155832 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 3621581 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 24983432 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 8209351 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 8209351 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 630645 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 603456 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 1234101 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 23261 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 23338 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 46599 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 12 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 1095911 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1072000 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2167911 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 544143 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 189217 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 8013685 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 4810536 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 551158 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 193191 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 8155832 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 4693581 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 27151343 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 544143 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 189217 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 8013685 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 4810536 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 551158 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 193191 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 8155832 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 4693581 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 27151343 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.004631 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012245 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.005979 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.043865 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.004634 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.011926 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.005950 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.041748 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016822 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.440910 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.400404 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.421103 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.789433 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781944 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.785682 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.111111 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.333333 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.166667 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.256599 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.267015 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.261750 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.004631 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.012245 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.005979 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.092329 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.004634 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.011926 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005950 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.093198 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.036378 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.004631 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.012245 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.005979 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.092329 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.004634 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.011926 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005950 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.093198 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.036378 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 89701.394048 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 89040.790246 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85896.541307 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 92135.269237 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89613.159358 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 88756.190538 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85061.001690 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 90154.449948 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 89829.089226 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 8.444015 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 9.179182 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 8.785829 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15383.023852 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 16107.353828 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 15744.061155 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 81000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 81000 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 81000 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 101755.896789 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 101622.844246 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 101688.780814 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 89701.394048 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 89040.790246 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 85896.541307 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 98226.464760 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89613.159358 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 88756.190538 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 85061.001690 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 97658.943628 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 96642.554195 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 89701.394048 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 89040.790246 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 85896.541307 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 98226.464760 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89613.159358 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 88756.190538 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 85061.001690 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 97658.943628 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 96642.554195 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2414,197 +2382,201 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1192634 # number of writebacks -system.l2c.writebacks::total 1192634 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 38 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 13 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 1194670 # number of writebacks +system.l2c.writebacks::total 1194670 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.dtb.walker 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.itb.walker 34 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 12 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 33 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.itb.walker 35 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.dtb.walker 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.itb.walker 38 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 13 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.dtb.walker 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.itb.walker 34 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 12 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.dtb.walker 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.itb.walker 33 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.itb.walker 35 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.dtb.walker 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.itb.walker 38 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 13 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.dtb.walker 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.itb.walker 34 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 12 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.dtb.walker 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.itb.walker 33 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.itb.walker 35 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 119 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2610 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2360 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 49271 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 160146 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2519 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2255 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 47310 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 159506 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 425977 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 279272 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 241385 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 520657 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 18107 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 18517 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 36624 # number of UpgradeReq MSHR misses +system.l2c.overall_mshr_hits::total 126 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2500 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2283 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 47910 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 162930 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2539 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2269 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 48527 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 151184 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 420142 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 278058 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 241626 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 519684 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 18363 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 18249 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 36612 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 287058 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 276629 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 563687 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2610 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2360 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 49271 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 447204 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 2519 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 2255 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 47310 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 436135 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 989664 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2610 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2360 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 49271 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 447204 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 2519 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 2255 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 47310 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 436135 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 989664 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 179134241 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 165129496 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3235930761 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 11464336939 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 171301239 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 154858995 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3112967761 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11534967229 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 30018626661 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 10593405856 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9513595958 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 20107001814 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 181345601 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 185397510 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 366743111 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 281210 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 286240 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 567450 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 2500 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2283 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 47910 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 444140 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2539 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2269 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 48527 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 437424 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 987592 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 2500 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2283 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 47910 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 444140 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2539 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2269 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 48527 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 437424 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 987592 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 175148007 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3515798206 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 12982690710 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 195905009 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 173430261 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3520714460 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 11743294499 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 32500171913 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 9375307322 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 8259706071 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 17635013393 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 326121860 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 324030745 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 650152605 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 68500 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 68500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 68500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 24068781040 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 23100678846 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 47169459886 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 179134241 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 165129496 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 3235930761 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 35533117979 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 171301239 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 154858995 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3112967761 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 34635646075 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 77188086547 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 179134241 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 165129496 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 3235930761 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 35533117979 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 171301239 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 154858995 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3112967761 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 34635646075 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 77188086547 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 654614249 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2623804750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 425309250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2653037250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6356765499 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2607030000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2564595500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5171625500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 654614249 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5230834750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 425309250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5217632750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 11528390999 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004728 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011626 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.006111 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.044091 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004621 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.012098 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005833 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.043497 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017066 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.445498 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.397744 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.422008 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.784804 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.782232 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.783502 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.166667 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.142857 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.267625 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.253828 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.260672 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004728 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011626 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.006111 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.095054 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004621 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005833 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.091685 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.036489 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004728 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011626 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.006111 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.095054 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004621 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005833 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.091685 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.036489 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 71586.782929 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72316.823373 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 70470.064489 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 37932.216105 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 39412.539959 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38618.518168 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.220688 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10012.286547 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10013.737194 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_mshr_miss_latency::total 137000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 25126437764 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 25538778563 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 50665216327 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 175148007 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 3515798206 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 38109128474 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 195905009 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 173430261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3520714460 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 37282073062 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 83165388240 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 193190761 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 175148007 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 3515798206 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 38109128474 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 195905009 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173430261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3520714460 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 37282073062 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 83165388240 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 735361248 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2566401000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 493860500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2722892250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6518514998 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2597122000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2578592496 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5175714496 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 735361248 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5163523000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 493860500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5301484746 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 11694229494 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.043862 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.041745 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016817 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.440910 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.400404 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.421103 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.789433 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781944 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.785682 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.111111 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.333333 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.166667 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.256599 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.267015 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.261750 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.092327 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.093196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036374 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.004594 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012066 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005979 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.092327 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.004607 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.011745 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005950 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.093196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036374 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 79682.628798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77675.511291 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 77355.208270 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 33717.092556 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 34183.846403 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 33934.108791 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17759.726624 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17756.082251 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17757.910111 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 68500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 68500 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 83846.404002 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 83507.798698 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 83680.233686 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 79456.172080 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 79414.965722 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 77994.234960 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68633.808812 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69970.125424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 65676.173835 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 79456.172080 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68003.667725 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68673.611973 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65799.360833 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 79414.965722 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 77994.234960 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 89351.153103 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89221.557305 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 89285.780821 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 85804.315022 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77276.304400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76718.356110 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73383.389814 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 85804.315022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77158.333596 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76434.667695 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72551.661137 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 85230.972836 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 84210.269261 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2619,57 +2591,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 489224 # Transaction distribution -system.membus.trans_dist::ReadResp 489224 # Transaction distribution -system.membus.trans_dist::WriteReq 33860 # Transaction distribution -system.membus.trans_dist::WriteResp 33860 # Transaction distribution -system.membus.trans_dist::Writeback 1299265 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 627170 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 627170 # Transaction distribution -system.membus.trans_dist::UpgradeReq 37411 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 37412 # Transaction distribution -system.membus.trans_dist::ReadExReq 563054 # Transaction distribution -system.membus.trans_dist::ReadExResp 563054 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 483310 # Transaction distribution +system.membus.trans_dist::ReadResp 483310 # Transaction distribution +system.membus.trans_dist::WriteReq 33697 # Transaction distribution +system.membus.trans_dist::WriteResp 33697 # Transaction distribution +system.membus.trans_dist::Writeback 1301300 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 626202 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 626202 # Transaction distribution +system.membus.trans_dist::UpgradeReq 37394 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.membus.trans_dist::UpgradeResp 37396 # Transaction distribution +system.membus.trans_dist::ReadExReq 566817 # Transaction distribution +system.membus.trans_dist::ReadExResp 566817 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6870 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4332246 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4462384 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 335088 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4797472 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6864 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4328173 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4457819 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335539 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335539 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4793358 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 2212 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13740 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174236076 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 174408348 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14052800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14052800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 188461148 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3233 # Total snoops (count) -system.membus.snoop_fanout::samples 2961771 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13728 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 174172012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 174343786 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14081472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14081472 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 188425258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 2786 # Total snoops (count) +system.membus.snoop_fanout::samples 2961350 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2961771 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2961350 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2961771 # Request fanout histogram -system.membus.reqLayer0.occupancy 99708500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2961350 # Request fanout histogram +system.membus.reqLayer0.occupancy 113801500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 54328 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5504999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5469002 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18802986477 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 11041524273 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 10120184001 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 6008607805 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186568267 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151555991 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2680,11 +2652,11 @@ system.realview.ethernet.descDMAReads 0 # Nu system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.totBandwidth 150 # Total Bandwidth (bits/s) +system.realview.ethernet.totBandwidth 151 # Total Bandwidth (bits/s) system.realview.ethernet.totPackets 3 # Total Packets system.realview.ethernet.totBytes 966 # Total Bytes system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) -system.realview.ethernet.txBandwidth 150 # Transmit Bandwidth (bits/s) +system.realview.ethernet.txBandwidth 151 # Transmit Bandwidth (bits/s) system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post @@ -2713,58 +2685,56 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 25574289 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 25566182 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33860 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33860 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8181117 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1340428 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1233761 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 46747 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 7 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 46754 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2162441 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2162441 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32390529 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29801361 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 923404 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2600212 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 65715506 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1036485248 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1208333724 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3115152 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8777312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2256711436 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 667123 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 37442651 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003085 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.055458 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 25599599 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 25591523 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33697 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33697 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8209351 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1340869 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1234101 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 46602 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 46614 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2167911 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2167911 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 32380531 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29914539 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 911927 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 2596271 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 65803268 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1036169984 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1212884202 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3059264 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 8762408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2260875858 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 669395 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 37310136 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003099 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.055581 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 37327135 99.69% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115516 0.31% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 37194516 99.69% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115620 0.31% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 37442651 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 56492183787 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 37310136 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 28102852815 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 3327000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1161000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 72944134855 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 43405971950 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 537017212 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 24319536063 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 15088594286 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 530670154 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1517407654 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 1505035766 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16420 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 16426 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt index b93c1aabd..943a39f7a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-timing/stats.txt @@ -1,159 +1,159 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.861398 # Number of seconds simulated -sim_ticks 51861397612000 # Number of ticks simulated -final_tick 51861397612000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.824541 # Number of seconds simulated +sim_ticks 51824540977500 # Number of ticks simulated +final_tick 51824540977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 682840 # Simulator instruction rate (inst/s) -host_op_rate 802417 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 40752483757 # Simulator tick rate (ticks/s) -host_mem_usage 728928 # Number of bytes of host memory used -host_seconds 1272.59 # Real time elapsed on the host -sim_insts 868978236 # Number of instructions simulated -sim_ops 1021151568 # Number of ops (including micro ops) simulated +host_inst_rate 650287 # Simulator instruction rate (inst/s) +host_op_rate 764161 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 37795835393 # Simulator tick rate (ticks/s) +host_mem_usage 728296 # Number of bytes of host memory used +host_seconds 1371.17 # Real time elapsed on the host +sim_insts 891654507 # Number of instructions simulated +sim_ops 1047794539 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 110912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 113344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 2519016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 22396080 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 118144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 113984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2612108 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 22226264 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 390656 # Number of bytes read from this memory -system.physmem.bytes_read::total 50600508 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 2519016 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2612108 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5131124 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 71823424 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 127104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 129344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2579072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24306544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 138752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 130240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2657396 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 26223832 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 397184 # Number of bytes read from this memory +system.physmem.bytes_read::total 56689468 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2579072 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2657396 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5236468 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77843520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 4 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 20576 # Number of bytes written to this memory -system.physmem.bytes_written::total 71844004 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 1733 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1771 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 66774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 349942 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1846 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1781 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 53807 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 347295 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6104 # Number of read requests responded to by this memory -system.physmem.num_reads::total 831053 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1122241 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77864100 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 1986 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2021 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 64583 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 379793 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 2168 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2035 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 57644 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 409757 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6206 # Number of read requests responded to by this memory +system.physmem.num_reads::total 926193 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1216305 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 1 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2572 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1124814 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 48572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 431845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 2278 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 2198 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 50367 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 428570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 975687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 48572 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 50367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 98939 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1384911 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1218878 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 49765 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 469016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 2677 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 2513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 51277 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 506012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7664 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1093873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 49765 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 51277 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101042 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1502059 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 0 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1385308 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1384911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 48572 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 431845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 2278 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 2198 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 50367 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 428967 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2360995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 831053 # Number of read requests accepted -system.physmem.writeReqs 1733697 # Number of write requests accepted -system.physmem.readBursts 831053 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1733697 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 53155264 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 32128 # Total number of bytes read from write queue -system.physmem.bytesWritten 110517504 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 50600508 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 110812516 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 502 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6857 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 35215 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 52772 # Per bank write bursts -system.physmem.perBankRdBursts::1 58055 # Per bank write bursts -system.physmem.perBankRdBursts::2 48746 # Per bank write bursts -system.physmem.perBankRdBursts::3 51625 # Per bank write bursts -system.physmem.perBankRdBursts::4 50901 # Per bank write bursts -system.physmem.perBankRdBursts::5 53731 # Per bank write bursts -system.physmem.perBankRdBursts::6 47545 # Per bank write bursts -system.physmem.perBankRdBursts::7 46576 # Per bank write bursts -system.physmem.perBankRdBursts::8 47759 # Per bank write bursts -system.physmem.perBankRdBursts::9 90120 # Per bank write bursts -system.physmem.perBankRdBursts::10 47452 # Per bank write bursts -system.physmem.perBankRdBursts::11 51057 # Per bank write bursts -system.physmem.perBankRdBursts::12 47939 # Per bank write bursts -system.physmem.perBankRdBursts::13 45720 # Per bank write bursts -system.physmem.perBankRdBursts::14 43868 # Per bank write bursts -system.physmem.perBankRdBursts::15 46685 # Per bank write bursts -system.physmem.perBankWrBursts::0 110572 # Per bank write bursts -system.physmem.perBankWrBursts::1 116599 # Per bank write bursts -system.physmem.perBankWrBursts::2 110707 # Per bank write bursts -system.physmem.perBankWrBursts::3 112437 # Per bank write bursts -system.physmem.perBankWrBursts::4 109828 # Per bank write bursts -system.physmem.perBankWrBursts::5 113045 # Per bank write bursts -system.physmem.perBankWrBursts::6 105073 # Per bank write bursts -system.physmem.perBankWrBursts::7 102356 # Per bank write bursts -system.physmem.perBankWrBursts::8 103784 # Per bank write bursts -system.physmem.perBankWrBursts::9 107644 # Per bank write bursts -system.physmem.perBankWrBursts::10 104570 # Per bank write bursts -system.physmem.perBankWrBursts::11 108123 # Per bank write bursts -system.physmem.perBankWrBursts::12 106842 # Per bank write bursts -system.physmem.perBankWrBursts::13 106503 # Per bank write bursts -system.physmem.perBankWrBursts::14 103411 # Per bank write bursts -system.physmem.perBankWrBursts::15 105342 # Per bank write bursts +system.physmem.bw_write::total 1502456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1502059 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 49765 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 469016 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 2677 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 2513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 51277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 506409 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2596329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 926193 # Number of read requests accepted +system.physmem.writeReqs 1833424 # Number of write requests accepted +system.physmem.readBursts 926193 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1833424 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59238720 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 37632 # Total number of bytes read from write queue +system.physmem.bytesWritten 114125056 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56689468 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 117195044 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 588 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50220 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36075 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 58169 # Per bank write bursts +system.physmem.perBankRdBursts::1 57047 # Per bank write bursts +system.physmem.perBankRdBursts::2 56978 # Per bank write bursts +system.physmem.perBankRdBursts::3 51307 # Per bank write bursts +system.physmem.perBankRdBursts::4 56070 # Per bank write bursts +system.physmem.perBankRdBursts::5 62899 # Per bank write bursts +system.physmem.perBankRdBursts::6 54110 # Per bank write bursts +system.physmem.perBankRdBursts::7 52791 # Per bank write bursts +system.physmem.perBankRdBursts::8 52847 # Per bank write bursts +system.physmem.perBankRdBursts::9 102886 # Per bank write bursts +system.physmem.perBankRdBursts::10 57805 # Per bank write bursts +system.physmem.perBankRdBursts::11 59371 # Per bank write bursts +system.physmem.perBankRdBursts::12 53186 # Per bank write bursts +system.physmem.perBankRdBursts::13 52009 # Per bank write bursts +system.physmem.perBankRdBursts::14 46290 # Per bank write bursts +system.physmem.perBankRdBursts::15 51840 # Per bank write bursts +system.physmem.perBankWrBursts::0 107643 # Per bank write bursts +system.physmem.perBankWrBursts::1 108842 # Per bank write bursts +system.physmem.perBankWrBursts::2 112436 # Per bank write bursts +system.physmem.perBankWrBursts::3 109534 # Per bank write bursts +system.physmem.perBankWrBursts::4 114716 # Per bank write bursts +system.physmem.perBankWrBursts::5 117944 # Per bank write bursts +system.physmem.perBankWrBursts::6 106840 # Per bank write bursts +system.physmem.perBankWrBursts::7 109826 # Per bank write bursts +system.physmem.perBankWrBursts::8 110854 # Per bank write bursts +system.physmem.perBankWrBursts::9 118905 # Per bank write bursts +system.physmem.perBankWrBursts::10 115046 # Per bank write bursts +system.physmem.perBankWrBursts::11 114249 # Per bank write bursts +system.physmem.perBankWrBursts::12 112384 # Per bank write bursts +system.physmem.perBankWrBursts::13 111972 # Per bank write bursts +system.physmem.perBankWrBursts::14 104755 # Per bank write bursts +system.physmem.perBankWrBursts::15 107258 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 51861395055500 # Total gap between requests +system.physmem.numWrRetry 141 # Number of times write queue was full causing retry +system.physmem.totGap 51824538352500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 787937 # Read request sizes (log2) +system.physmem.readPktSize::6 883077 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1731124 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 797504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 27344 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 572 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 363 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 201 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 125 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 110 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 101 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 87 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1830851 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 891893 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 27772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 466 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 447 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 101 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 98 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 85 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 64 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 48 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -165,206 +165,186 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 1646 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1562 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1480 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1409 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 57139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 70145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 93845 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 95924 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 98521 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 113672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 117695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 104272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 102286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 99994 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 96711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 93700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 91898 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 87418 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 86273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 85861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 84522 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1780 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 619 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 387 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 140 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 563789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 290.307984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 165.321614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.078407 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 235457 41.76% 41.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 139953 24.82% 66.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 46694 8.28% 74.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 25357 4.50% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 16838 2.99% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 11479 2.04% 84.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8496 1.51% 85.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7843 1.39% 87.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 71672 12.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 563789 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 84234 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 9.859653 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 88.079162 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 84229 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::0 1689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 1631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 1588 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 1570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 1550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 1532 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 1527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1502 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1472 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1463 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1457 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 57426 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 60838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 91061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 116478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 105808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 96280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 97400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 91891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 93113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 91599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 92000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 96823 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 95841 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 93430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 103137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 95750 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 92354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 90761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7464 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 7069 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5718 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 5228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5156 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3748 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 569 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 451 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 469 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 181 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 235 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 605479 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 286.324474 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.442500 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.472553 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 252649 41.73% 41.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 150060 24.78% 66.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 52055 8.60% 75.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 27939 4.61% 79.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19251 3.18% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12886 2.13% 85.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9838 1.62% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 9006 1.49% 88.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71795 11.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 605479 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 88964 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.404208 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 91.787630 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 88960 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::6144-7167 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 84234 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 84234 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.500463 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.372295 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.059087 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 108 0.13% 0.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 80 0.09% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 54 0.06% 0.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 121 0.14% 0.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 46153 54.79% 55.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 30225 35.88% 91.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2462 2.92% 94.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1364 1.62% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 933 1.11% 96.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 416 0.49% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 269 0.32% 97.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 164 0.19% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 538 0.64% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 68 0.08% 98.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 77 0.09% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 53 0.06% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 163 0.19% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 54 0.06% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 29 0.03% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 79 0.09% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 145 0.17% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 43 0.05% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 17 0.02% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 33 0.04% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 176 0.21% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 15 0.02% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 19 0.02% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 61 0.07% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 20 0.02% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 40 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 24 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 103 0.12% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 13 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.00% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 10 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 9 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 10 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 6 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 4 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 84234 # Writes before turning the bus around for reads -system.physmem.totQLat 10578626250 # Total ticks spent queuing -system.physmem.totMemAccLat 26151457500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4152755000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12736.88 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::7168-8191 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::21504-22527 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 88964 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 88964 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.044108 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.711925 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.727362 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 349 0.39% 0.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 86750 97.51% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 775 0.87% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 22 0.02% 98.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 52 0.06% 98.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 153 0.17% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 193 0.22% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 316 0.36% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 104 0.12% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 25 0.03% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 21 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 53 0.06% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 28 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 13 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.00% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 4 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 7 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 10 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 22 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 4 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 4 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 88964 # Writes before turning the bus around for reads +system.physmem.totQLat 11987590194 # Total ticks spent queuing +system.physmem.totMemAccLat 29342683944 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4628025000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12951.09 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31486.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 0.98 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31701.09 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.02 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.05 # Average write queue length when enqueuing -system.physmem.readRowHits 620179 # Number of row buffer hits during reads -system.physmem.writeRowHits 1373418 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.67 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.53 # Row buffer hit rate for writes -system.physmem.avgGap 20220838.31 # Average gap between requests -system.physmem.pageHitRate 77.95 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2224749240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1213900875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3197578800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5706398160 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3387334061280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1303736226660 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29973207455250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34676620370265 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.640359 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49862520204500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1731765880000 # Time in different power states +system.physmem.avgWrQLen 8.43 # Average write queue length when enqueuing +system.physmem.readRowHits 697250 # Number of row buffer hits during reads +system.physmem.writeRowHits 1406079 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.33 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.85 # Row buffer hit rate for writes +system.physmem.avgGap 18779612.66 # Average gap between requests +system.physmem.pageHitRate 77.65 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2300840640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1255419000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3505093800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5752820880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384927046800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1312402504095 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29943494064750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34653637789965 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.672359 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49812972038958 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730535300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 267111145000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 281033227292 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2037495600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1111728750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3280680000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5483499120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3387334061280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1287848520900 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29987144039250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34674240024900 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.594461 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49885777301500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1731765880000 # Time in different power states +system.physmem_1.actEnergy 2276580600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1242181875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3714586200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5802341040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384927046800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1307965107960 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29947386517500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34653314361975 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.666118 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49819438757970 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730535300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 243849706000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 274566508280 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -418,68 +398,64 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 125209 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 125209 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 19669 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 90325 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walks 132927 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 132927 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 20422 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 96268 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 16 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 125193 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 125193 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 125193 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 110010 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 22089.371421 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 18317.414501 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 13164.465309 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 107059 97.32% 97.32% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 2114 1.92% 99.24% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-98303 606 0.55% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 110 0.10% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 25 0.02% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 28 0.03% 99.94% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::229376-262143 18 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 7 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::294912-327679 6 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-360447 9 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::458752-491519 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 110010 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 3295703864 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.071233 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -234762296 -7.12% -7.12% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 3530466160 107.12% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 3295703864 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 90326 82.12% 82.12% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 19669 17.88% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 109995 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125209 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::samples 132911 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 132911 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 132911 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 116706 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 23749.820061 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 20399.632740 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 13626.974720 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 115779 99.21% 99.21% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 796 0.68% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 50 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 35 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 34 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 9 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 116706 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 17050777148 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.002177 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -37117796 -0.22% -0.22% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 17087894944 100.22% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 17050777148 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 96268 82.50% 82.50% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 20422 17.50% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 116690 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 132927 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125209 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 109995 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 132927 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 116690 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 109995 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 235204 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 116690 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 249617 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 81853035 # DTB read hits -system.cpu0.dtb.read_misses 95759 # DTB read misses -system.cpu0.dtb.write_hits 74321037 # DTB write hits -system.cpu0.dtb.write_misses 29450 # DTB write misses -system.cpu0.dtb.flush_tlb 51862 # Number of times complete TLB was flushed +system.cpu0.dtb.read_hits 83832092 # DTB read hits +system.cpu0.dtb.read_misses 101357 # DTB read misses +system.cpu0.dtb.write_hits 76051604 # DTB write hits +system.cpu0.dtb.write_misses 31570 # DTB write misses +system.cpu0.dtb.flush_tlb 51833 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 20132 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 528 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 71205 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 21426 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 523 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 72699 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4306 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4640 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 9531 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 81948794 # DTB read accesses -system.cpu0.dtb.write_accesses 74350487 # DTB write accesses +system.cpu0.dtb.perms_faults 9921 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 83933449 # DTB read accesses +system.cpu0.dtb.write_accesses 76083174 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 156174072 # DTB hits -system.cpu0.dtb.misses 125209 # DTB misses -system.cpu0.dtb.accesses 156299281 # DTB accesses +system.cpu0.dtb.hits 159883696 # DTB hits +system.cpu0.dtb.misses 132927 # DTB misses +system.cpu0.dtb.accesses 160016623 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -509,284 +485,286 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 77027 # Table walker walks requested -system.cpu0.itb.walker.walksLong 77027 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4349 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 67368 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 77027 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 77027 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 77027 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 71717 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 25312.366663 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 21958.347721 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 14763.140629 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-32767 66172 92.27% 92.27% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-65535 4523 6.31% 98.57% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-98303 706 0.98% 99.56% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::98304-131071 175 0.24% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-163839 37 0.05% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::163840-196607 34 0.05% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-229375 34 0.05% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-360447 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 78456 # Table walker walks requested +system.cpu0.itb.walker.walksLong 78456 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 4330 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 68323 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 78456 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 78456 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 78456 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 72653 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 26725.888828 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 23461.567658 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 16011.465624 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 35910 49.43% 49.43% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 35653 49.07% 98.50% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 362 0.50% 99.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 571 0.79% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 51 0.07% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 22 0.03% 99.90% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 28 0.04% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 22 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::360448-393215 6 0.01% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 71717 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -294463796 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -294463796 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -294463796 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 67368 93.94% 93.94% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 4349 6.06% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 71717 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 72653 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -294752296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -294752296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -294752296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 68323 94.04% 94.04% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 4330 5.96% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 72653 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 77027 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 77027 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 78456 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 78456 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 71717 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 71717 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 148744 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 434570813 # ITB inst hits -system.cpu0.itb.inst_misses 77027 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 72653 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 72653 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 151109 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 446243730 # ITB inst hits +system.cpu0.itb.inst_misses 78456 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 51862 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb 51833 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 20132 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 528 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 52030 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 21426 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 523 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 53592 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 434647840 # ITB inst accesses -system.cpu0.itb.hits 434570813 # DTB hits -system.cpu0.itb.misses 77027 # DTB misses -system.cpu0.itb.accesses 434647840 # DTB accesses -system.cpu0.numCycles 51862348340 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 446322186 # ITB inst accesses +system.cpu0.itb.hits 446243730 # DTB hits +system.cpu0.itb.misses 78456 # DTB misses +system.cpu0.itb.accesses 446322186 # DTB accesses +system.cpu0.numCycles 51824649281 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 434316413 # Number of instructions committed -system.cpu0.committedOps 510251172 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 468762245 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 455279 # Number of float alu accesses -system.cpu0.num_func_calls 25833192 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 66107864 # number of instructions that are conditional controls -system.cpu0.num_int_insts 468762245 # number of integer instructions -system.cpu0.num_fp_insts 455279 # number of float instructions -system.cpu0.num_int_register_reads 680505745 # number of times the integer registers were read -system.cpu0.num_int_register_writes 371520195 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 735714 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 382992 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 113236512 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 112912982 # number of times the CC registers were written -system.cpu0.num_mem_refs 156164016 # number of memory refs -system.cpu0.num_load_insts 81849666 # Number of load instructions -system.cpu0.num_store_insts 74314350 # Number of store instructions -system.cpu0.num_idle_cycles 50300563806.190483 # Number of idle cycles -system.cpu0.num_busy_cycles 1561784533.809517 # Number of busy cycles -system.cpu0.not_idle_fraction 0.030114 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.969886 # Percentage of idle cycles -system.cpu0.Branches 96959859 # Number of branches fetched +system.cpu0.committedInsts 445966277 # Number of instructions committed +system.cpu0.committedOps 524229812 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 481463261 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 467774 # Number of float alu accesses +system.cpu0.num_func_calls 26556698 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 68063516 # number of instructions that are conditional controls +system.cpu0.num_int_insts 481463261 # number of integer instructions +system.cpu0.num_fp_insts 467774 # number of float instructions +system.cpu0.num_int_register_reads 701970788 # number of times the integer registers were read +system.cpu0.num_int_register_writes 382111523 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 750606 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 404844 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 116882787 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 116605188 # number of times the CC registers were written +system.cpu0.num_mem_refs 159874579 # number of memory refs +system.cpu0.num_load_insts 83829017 # Number of load instructions +system.cpu0.num_store_insts 76045562 # Number of store instructions +system.cpu0.num_idle_cycles 50231597014.033707 # Number of idle cycles +system.cpu0.num_busy_cycles 1593052266.966292 # Number of busy cycles +system.cpu0.not_idle_fraction 0.030739 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.969261 # Percentage of idle cycles +system.cpu0.Branches 99615402 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 353181248 69.18% 69.18% # Class of executed instruction -system.cpu0.op_class::IntMult 1084077 0.21% 69.39% # Class of executed instruction -system.cpu0.op_class::IntDiv 49491 0.01% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 6 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 8 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 12 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 55978 0.01% 69.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu0.op_class::MemRead 81849666 16.03% 85.44% # Class of executed instruction -system.cpu0.op_class::MemWrite 74314350 14.56% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 363413760 69.28% 69.28% # Class of executed instruction +system.cpu0.op_class::IntMult 1135542 0.22% 69.50% # Class of executed instruction +system.cpu0.op_class::IntDiv 49216 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 60094 0.01% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu0.op_class::MemRead 83829017 15.98% 85.50% # Class of executed instruction +system.cpu0.op_class::MemWrite 76045562 14.50% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 510534837 # Class of executed instruction +system.cpu0.op_class::total 524533192 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 16221 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 9866178 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.969728 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 301750178 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 9866690 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 30.582716 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3092948250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 290.086465 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 221.883263 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.566575 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.433366 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 16327 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 10196087 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.965694 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 309323716 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 10196599 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 30.335969 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 3500850250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 229.651609 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 282.314085 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.448538 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.551395 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 404 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 398 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1256728908 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1256728908 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 76588751 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 76163346 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 152752097 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 70555546 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 70327464 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 140883010 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190561 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 196148 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 386709 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 172423 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 161036 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 333459 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1750003 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1777885 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 3527888 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1897893 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1924897 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 3822790 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147144297 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 146490810 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 293635107 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147334858 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 146686958 # number of overall hits -system.cpu0.dcache.overall_hits::total 294021816 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 2557843 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2571612 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 5129455 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1050273 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1078042 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2128315 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 601274 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 625393 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1226667 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 620770 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 607819 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1228589 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 148787 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 147781 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 296568 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1288720346 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1288720346 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 78289930 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 78118799 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 156408729 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 72116454 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 72389955 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 144506409 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 198225 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 194517 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 392742 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 165535 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 168546 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 334081 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1870803 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 1796237 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 3667040 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2023404 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 1945934 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 3969338 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 150406384 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 150508754 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 300915138 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 150604609 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 150703271 # number of overall hits +system.cpu0.dcache.overall_hits::total 301307880 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2655491 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2654704 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 5310195 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1102314 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1104773 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2207087 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 646482 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 651674 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1298156 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 617789 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 615381 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1233170 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153457 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 150527 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 303984 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 3608116 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 3649654 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 7257770 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 4209390 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 4275047 # number of overall misses -system.cpu0.dcache.overall_misses::total 8484437 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39628260752 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 40050042255 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 79678303007 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29258978305 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 29205004656 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 58463982961 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 13856629500 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13463537506 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 27320167006 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2109696250 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2149698750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 4259395000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 26501 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 75000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 101501 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 68887239057 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 69255046911 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 138142285968 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 68887239057 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 69255046911 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 138142285968 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 79146594 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 78734958 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 157881552 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 71605819 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 71405506 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 143011325 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 791835 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 821541 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 1613376 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 793193 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 768855 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1562048 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1898790 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1925666 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 3824456 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1897894 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1924898 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 3822792 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 150752413 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 150140464 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 300892877 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 151544248 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 150962005 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 302506253 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032318 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032662 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.032489 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014667 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015097 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.014882 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.759343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.761244 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.760311 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.782622 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.790551 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786524 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078359 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076743 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077545 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 3757805 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 3759477 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 7517282 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4404287 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 4411151 # number of overall misses +system.cpu0.dcache.overall_misses::total 8815438 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41854028250 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 42227875003 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 84081903253 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32373542448 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 33874267614 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 66247810062 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 16528493005 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu1.data 16264164501 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32792657506 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2255480492 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 2210676726 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 4466157218 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 82000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu1.data 82000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 74227570698 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 76102142617 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 150329713315 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 74227570698 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 76102142617 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 150329713315 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 80945421 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 80773503 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 161718924 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73218768 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 73494728 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 146713496 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 844707 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 846191 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 1690898 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 783324 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 783927 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1567251 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2024260 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 1946764 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 3971024 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2023405 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 1945935 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 3969340 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 154164189 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 154268231 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 308432420 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 155008896 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 155114422 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 310123318 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.032806 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.032866 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.032836 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.015055 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015032 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015044 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.765333 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.770126 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.767732 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.788676 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.784998 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786836 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075809 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.077322 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.076551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000001 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.023934 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024308 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.024121 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027777 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028319 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028047 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15492.843287 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15573.905494 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15533.483188 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 27858.450427 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27090.785569 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 27469.609978 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 22321.680332 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 22150.570328 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 22237.027196 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14179.304980 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14546.516467 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14362.287907 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26501 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 75000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 50750.500000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19092.301649 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18975.784255 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19033.709523 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16365.135817 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16199.832870 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16281.844743 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024375 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.024370 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.024373 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028413 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028438 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.028426 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15761.314292 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15906.811081 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15834.051904 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29368.712044 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 30661.744643 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30015.948652 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 26754.268860 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 26429.422587 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 26592.162886 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14697.801286 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14686.247158 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14692.079906 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 82000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu1.data 82000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19752.906470 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20242.747227 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 19997.881324 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16853.481778 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17252.218892 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 17053.005570 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -795,128 +773,128 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 7621991 # number of writebacks -system.cpu0.dcache.writebacks::total 7621991 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3442 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3110 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 6552 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 10246 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 10994 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21240 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 34818 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 35721 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 70539 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 13688 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 14104 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 27792 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 13688 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 14104 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 27792 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2554401 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2568502 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 5122903 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1040027 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1067048 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 2107075 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 601132 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 625207 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 1226339 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 620770 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 607819 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1228589 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 113969 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 112060 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 226029 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 7866652 # number of writebacks +system.cpu0.dcache.writebacks::total 7866652 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7707 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 8547 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 16254 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 10563 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 10564 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21127 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 35866 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 35610 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 71476 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 18270 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 19111 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 37381 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 18270 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 19111 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 37381 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2647784 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 2646157 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 5293941 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1091751 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 1094209 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 2185960 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 645721 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 650689 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 1296410 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 617789 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 615381 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 1233170 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117591 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 114917 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 232508 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu1.data 1 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 3594428 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 3635550 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 7229978 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 4195560 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 4260757 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 8456317 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34255815748 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 34669168995 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 68924984743 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 26736974445 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 26668792594 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 53405767039 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 8942698000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9200320250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18143018250 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 12615089500 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12247899494 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24862988994 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1372094500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1380082250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2752176750 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 24499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 73000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 97499 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60992790193 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 61337961589 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 122330751782 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 69935488193 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 70538281839 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 140473770032 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2674956999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3053270500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5728227499 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2550639000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3023463750 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5574102750 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5225595999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 6076734250 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11302330249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032274 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032622 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032448 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014524 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014943 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014734 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759163 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.761017 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.760107 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.782622 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.790551 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786524 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.060022 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.058193 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059101 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 3739535 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 3740366 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 7479901 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4385256 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 4391055 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 8776311 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37598794000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 37923223247 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 75522017247 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 30337029302 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 31768716886 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 62105746188 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 9761049258 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10401680524 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 20162729782 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 15601809495 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 15341092999 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 30942902494 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1519625500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1476118000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2995743500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 80500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 80500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 67935823302 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 69691940133 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 137627763435 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 77696872560 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 80093620657 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 157790493217 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2993163000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2758056250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5751219250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2831783000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2786803750 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5618586750 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5824946000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 5544860000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11369806000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.032711 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.032760 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.032735 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.014911 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014888 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.014900 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.764432 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.768962 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.766699 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.788676 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.784998 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786836 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058091 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.059030 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058551 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000000 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000001 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023843 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024214 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.024028 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027685 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028224 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.027954 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13410.508275 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13497.816624 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13454.282609 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 25707.961856 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24993.058039 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25345.926006 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14876.429802 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14715.638581 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14794.455897 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 20321.680332 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20150.570308 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20237.027186 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12039.190482 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12315.565322 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12176.210796 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 24499 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 73000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 48749.500000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16968.705506 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 16871.714483 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16919.934166 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16668.928151 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 16555.340246 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16611.696325 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.024257 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.024246 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.024251 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028290 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028308 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028299 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14200.098649 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14331.433565 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14265.745925 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 27787.498525 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29033.499894 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 28411.199742 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15116.512020 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15985.640642 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15552.741634 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 25254.268844 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 24929.422584 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25092.162876 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12922.974547 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12845.079492 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12884.474943 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18166.917358 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18632.385209 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18399.677139 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17717.750699 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18240.177055 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17979.136475 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -927,79 +905,79 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 13777264 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.892662 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 855737357 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 13777776 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 62.109977 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 32072682250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 274.033427 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 237.859235 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.535222 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.464569 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999790 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 13976964 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.880033 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 878227495 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 13977476 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 62.831622 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 35142475250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 257.003288 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 254.876744 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.501960 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.497806 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 228 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 209 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 213 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 883292919 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 883292919 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 427701374 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 428035983 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 855737357 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 427701374 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 428035983 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 855737357 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 427701374 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 428035983 # number of overall hits -system.cpu0.icache.overall_hits::total 855737357 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 6869439 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 6908342 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 13777781 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 6869439 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 6908342 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 13777781 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 6869439 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 6908342 # number of overall misses -system.cpu0.icache.overall_misses::total 13777781 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 91986566006 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 92647567751 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 184634133757 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 91986566006 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 92647567751 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 184634133757 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 91986566006 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 92647567751 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 184634133757 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 434570813 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 434944325 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 869515138 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 434570813 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 434944325 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 869515138 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 434570813 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 434944325 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 869515138 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015807 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015883 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.015845 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015807 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015883 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.015845 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015807 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015883 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.015845 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13390.695515 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13410.970064 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13400.861413 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13390.695515 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13410.970064 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13400.861413 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13390.695515 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13410.970064 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13400.861413 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 906182457 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 906182457 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 439239656 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 438987839 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 878227495 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 439239656 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 438987839 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 878227495 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 439239656 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 438987839 # number of overall hits +system.cpu0.icache.overall_hits::total 878227495 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7004074 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 6973407 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 13977481 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7004074 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 6973407 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 13977481 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7004074 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 6973407 # number of overall misses +system.cpu0.icache.overall_misses::total 13977481 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 93843146430 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 93562942727 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 187406089157 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 93843146430 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 93562942727 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 187406089157 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 93843146430 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 93562942727 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 187406089157 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 446243730 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 445961246 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 892204976 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 446243730 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 445961246 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 892204976 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 446243730 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 445961246 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 892204976 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.015696 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015637 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.015666 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.015696 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015637 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.015666 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.015696 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015637 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.015666 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13398.365927 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13417.106262 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13407.715536 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13398.365927 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13417.106262 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13407.715536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13398.365927 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13417.106262 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13407.715536 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1008,48 +986,48 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6869439 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6908342 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 13777781 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 6869439 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 6908342 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 13777781 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 6869439 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 6908342 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 13777781 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 78234289494 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 78816452749 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 157050742243 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 78234289494 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 78816452749 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 157050742243 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 78234289494 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 78816452749 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 157050742243 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 912090000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2831704500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1919614500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 912090000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 2831704500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015807 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015883 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015845 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015807 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015883 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.015845 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015807 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015883 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.015845 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11388.745063 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11408.881139 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11398.841529 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11388.745063 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11408.881139 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11398.841529 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11388.745063 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11408.881139 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11398.841529 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 7004074 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 6973407 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 13977481 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 7004074 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 6973407 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 13977481 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 7004074 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 6973407 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 13977481 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 83323187568 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 83088246273 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 166411433841 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 83323187568 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 83088246273 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 166411433841 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 83323187568 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 83088246273 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 166411433841 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1928508500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 1282516750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3211025250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 1928508500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu1.inst 1282516750 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 3211025250 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.015696 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.015666 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.015696 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.015666 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.015696 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015637 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.015666 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11896.388811 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11915.014608 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11905.681277 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11896.388811 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11915.014608 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11905.681277 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11896.388811 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11915.014608 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11905.681277 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1086,73 +1064,73 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 127972 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 127972 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 19780 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 92740 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 16 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 127956 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.265716 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 71.272998 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 127954 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 130358 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 130358 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 20442 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 94115 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 130351 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.276177 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 74.962722 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-2047 130349 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 127956 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 112536 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 22019.187193 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 18129.081838 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 13444.450617 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 109487 97.29% 97.29% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2144 1.91% 99.20% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 659 0.59% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 117 0.10% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 32 0.03% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 27 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 20 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 8 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 9 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 112536 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 6637919892 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 1.174468 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1158102796 -17.45% -17.45% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 7796022688 117.45% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 6637919892 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 92740 82.42% 82.42% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 19780 17.58% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 112520 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 127972 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 130351 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 114564 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 23894.842621 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 20601.133760 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13695.118153 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-32767 72946 63.67% 63.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-65535 40612 35.45% 99.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-98303 507 0.44% 99.56% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-131071 353 0.31% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::163840-196607 47 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-229375 10 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::229376-262143 28 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-294911 26 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-360447 4 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 114564 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 26318568 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 31.814872 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -811003296 -3081.49% -3081.49% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 837321864 3181.49% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 26318568 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 94116 82.16% 82.16% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 20442 17.84% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 114558 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 130358 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 127972 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 112520 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 130358 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 114558 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 112520 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 240492 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 114558 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 244916 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 81500118 # DTB read hits -system.cpu1.dtb.read_misses 97955 # DTB read misses -system.cpu1.dtb.write_hits 74126007 # DTB write hits -system.cpu1.dtb.write_misses 30017 # DTB write misses -system.cpu1.dtb.flush_tlb 51868 # Number of times complete TLB was flushed +system.cpu1.dtb.read_hits 83582440 # DTB read hits +system.cpu1.dtb.read_misses 99281 # DTB read misses +system.cpu1.dtb.write_hits 76249670 # DTB write hits +system.cpu1.dtb.write_misses 31077 # DTB write misses +system.cpu1.dtb.flush_tlb 51825 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 20724 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 72099 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 21270 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 73142 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4473 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4747 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9907 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 81598073 # DTB read accesses -system.cpu1.dtb.write_accesses 74156024 # DTB write accesses +system.cpu1.dtb.perms_faults 9967 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 83681721 # DTB read accesses +system.cpu1.dtb.write_accesses 76280747 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 155626125 # DTB hits -system.cpu1.dtb.misses 127972 # DTB misses -system.cpu1.dtb.accesses 155754097 # DTB accesses +system.cpu1.dtb.hits 159832110 # DTB hits +system.cpu1.dtb.misses 130358 # DTB misses +system.cpu1.dtb.accesses 159962468 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1182,135 +1160,136 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 77421 # Table walker walks requested -system.cpu1.itb.walker.walksLong 77421 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4271 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67596 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 77421 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 77421 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 77421 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 71867 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 24990.746796 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 21538.641816 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 14943.355403 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 66410 92.41% 92.41% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 4449 6.19% 98.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 690 0.96% 99.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 184 0.26% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 29 0.04% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 30 0.04% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 33 0.05% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 19 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 8 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 71867 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1257793296 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1257793296 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1257793296 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 67596 94.06% 94.06% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 4271 5.94% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 71867 # Table walker page sizes translated +system.cpu1.itb.walker.walks 77021 # Table walker walks requested +system.cpu1.itb.walker.walksLong 77021 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 4430 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 67244 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 77021 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 77021 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 77021 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 71674 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 27071.277590 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 23813.549051 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 16581.978010 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 34935 48.74% 48.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 35570 49.63% 98.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 418 0.58% 98.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 591 0.82% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 6 0.01% 99.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 60 0.08% 99.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 17 0.02% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 30 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 20 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 6 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::458752-491519 4 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 71674 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -853687296 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -853687296 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -853687296 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 67244 93.82% 93.82% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 4430 6.18% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 71674 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77421 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77421 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 77021 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 77021 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71867 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71867 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 149288 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 434944325 # ITB inst hits -system.cpu1.itb.inst_misses 77421 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 71674 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 71674 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 148695 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 445961246 # ITB inst hits +system.cpu1.itb.inst_misses 77021 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 51868 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb 51825 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 20724 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 513 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 53256 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 21270 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 540 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 52758 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 435021746 # ITB inst accesses -system.cpu1.itb.hits 434944325 # DTB hits -system.cpu1.itb.misses 77421 # DTB misses -system.cpu1.itb.accesses 435021746 # DTB accesses -system.cpu1.numCycles 51860446884 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 446038267 # ITB inst accesses +system.cpu1.itb.hits 445961246 # DTB hits +system.cpu1.itb.misses 77021 # DTB misses +system.cpu1.itb.accesses 446038267 # DTB accesses +system.cpu1.numCycles 51824432674 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 434661823 # Number of instructions committed -system.cpu1.committedOps 510900396 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 469262912 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 444776 # Number of float alu accesses -system.cpu1.num_func_calls 25944068 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66238146 # number of instructions that are conditional controls -system.cpu1.num_int_insts 469262912 # number of integer instructions -system.cpu1.num_fp_insts 444776 # number of float instructions -system.cpu1.num_int_register_reads 683773696 # number of times the integer registers were read -system.cpu1.num_int_register_writes 372368162 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 716331 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 377944 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 113908068 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113630972 # number of times the CC registers were written -system.cpu1.num_mem_refs 155618629 # number of memory refs -system.cpu1.num_load_insts 81496317 # Number of load instructions -system.cpu1.num_store_insts 74122312 # Number of store instructions -system.cpu1.num_idle_cycles 50297346072.144875 # Number of idle cycles -system.cpu1.num_busy_cycles 1563100811.855124 # Number of busy cycles -system.cpu1.not_idle_fraction 0.030141 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.969859 # Percentage of idle cycles -system.cpu1.Branches 97056682 # Number of branches fetched +system.cpu1.committedInsts 445688230 # Number of instructions committed +system.cpu1.committedOps 523564727 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 480567684 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 428483 # Number of float alu accesses +system.cpu1.num_func_calls 26273151 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 68126466 # number of instructions that are conditional controls +system.cpu1.num_int_insts 480567684 # number of integer instructions +system.cpu1.num_fp_insts 428483 # number of float instructions +system.cpu1.num_int_register_reads 701499135 # number of times the integer registers were read +system.cpu1.num_int_register_writes 381123451 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 693452 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 356440 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 117557193 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 117240637 # number of times the CC registers were written +system.cpu1.num_mem_refs 159825990 # number of memory refs +system.cpu1.num_load_insts 83579816 # Number of load instructions +system.cpu1.num_store_insts 76246174 # Number of store instructions +system.cpu1.num_idle_cycles 50239290608.732407 # Number of idle cycles +system.cpu1.num_busy_cycles 1585142065.267594 # Number of busy cycles +system.cpu1.not_idle_fraction 0.030587 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.969413 # Percentage of idle cycles +system.cpu1.Branches 99529261 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 354376144 69.32% 69.32% # Class of executed instruction -system.cpu1.op_class::IntMult 1097996 0.21% 69.54% # Class of executed instruction -system.cpu1.op_class::IntDiv 48675 0.01% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 2 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 5 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 9 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 55297 0.01% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu1.op_class::MemRead 81496317 15.94% 85.50% # Class of executed instruction -system.cpu1.op_class::MemWrite 74122312 14.50% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 362846766 69.26% 69.26% # Class of executed instruction +system.cpu1.op_class::IntMult 1082718 0.21% 69.47% # Class of executed instruction +system.cpu1.op_class::IntDiv 48965 0.01% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 50459 0.01% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.49% # Class of executed instruction +system.cpu1.op_class::MemRead 83579816 15.95% 85.45% # Class of executed instruction +system.cpu1.op_class::MemWrite 76246174 14.55% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 511196757 # Class of executed instruction +system.cpu1.op_class::total 523854940 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 40404 # Transaction distribution -system.iobus.trans_dist::ReadResp 40404 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40327 # Transaction distribution +system.iobus.trans_dist::ReadResp 40327 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1325,13 +1304,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231004 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231012 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231012 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354274 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353796 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1346,13 +1325,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334448 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334480 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334480 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492854 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492400 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1380,71 +1359,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042408857 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 606981976 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179045538 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148423298 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115484 # number of replacements -system.iocache.tags.tagsinuse 10.461673 # Cycle average of tags in use +system.iocache.tags.replacements 115487 # number of replacements +system.iocache.tags.tagsinuse 10.456623 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115500 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115503 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13154364038000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.508099 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.953575 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219256 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434598 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653855 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13157342382000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510546 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946077 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219409 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434130 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039875 # Number of tag accesses -system.iocache.tags.data_accesses 1039875 # Number of data accesses +system.iocache.tags.tag_accesses 1039911 # Number of tag accesses +system.iocache.tags.data_accesses 1039911 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8838 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8875 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8842 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8879 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8838 # number of demand (read+write) misses -system.iocache.demand_misses::total 8878 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8842 # number of demand (read+write) misses +system.iocache.demand_misses::total 8882 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8838 # number of overall misses -system.iocache.overall_misses::total 8878 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5485000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1903038512 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1908523512 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28811758807 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28811758807 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5824000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1903038512 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1908862512 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5824000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1903038512 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1908862512 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8842 # number of overall misses +system.iocache.overall_misses::total 8882 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1565914828 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1570986828 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19799416850 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19799416850 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1565914828 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1571339328 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1565914828 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1571339328 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8838 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8875 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8842 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8879 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8838 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8878 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8842 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8882 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8838 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8878 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8842 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8882 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1458,55 +1437,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 215324.565739 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 215044.902761 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270116.991740 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270116.991740 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 215324.565739 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 215010.420365 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 215324.565739 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 215010.420365 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 222004 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 177099.618638 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 176932.855952 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185624.173573 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185624.173573 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 177099.618638 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 176912.781806 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 177099.618638 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 176912.781806 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 107527 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27403 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16113 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.101449 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.673307 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106631 # number of writebacks -system.iocache.writebacks::total 106631 # number of writebacks +system.iocache.writebacks::writebacks 106630 # number of writebacks +system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8838 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8875 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8842 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8879 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8838 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8878 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8842 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8882 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8838 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8878 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3561000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1443371512 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1446932512 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23265154883 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23265154883 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3744000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1443371512 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1447115512 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3744000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1443371512 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1447115512 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8842 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8882 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1105053392 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1108195392 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14252856882 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14252856882 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1105053392 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1108388892 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1105053392 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1108388892 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1520,290 +1499,291 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163314.269292 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 163034.649239 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218116.279935 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218116.279935 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 163314.269292 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 163000.170309 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 163314.269292 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 163000.170309 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 124977.764307 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 124810.833652 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133623.873866 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133623.873866 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 124977.764307 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 124790.462959 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 124977.764307 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 124790.462959 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1193420 # number of replacements -system.l2c.tags.tagsinuse 65274.322363 # Cycle average of tags in use -system.l2c.tags.total_refs 27445630 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1256045 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.850833 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 6379783000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 38399.191078 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 165.877891 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 238.258282 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3135.660678 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9757.187471 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 161.764164 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 237.073896 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3594.762150 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 9584.546752 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.585925 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002531 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.003636 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.047846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.148883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002468 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.003617 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054852 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.146249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.996007 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 240 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62385 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 240 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 389 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2427 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5459 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54075 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003662 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.951920 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 260949842 # Number of tag accesses -system.l2c.tags.data_accesses 260949842 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 229115 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 164394 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 6831894 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3141009 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 232266 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 162523 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 6868394 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3173246 # number of ReadReq hits -system.l2c.ReadReq_hits::total 20802841 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 7621991 # number of Writeback hits -system.l2c.Writeback_hits::total 7621991 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 364580 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 361785 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 726365 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 4737 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 4832 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9569 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 795952 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 829496 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1625448 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 229115 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 164394 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 6831894 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 3936961 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 232266 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 162523 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 6868394 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4002742 # number of demand (read+write) hits -system.l2c.demand_hits::total 22428289 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 229115 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 164394 # number of overall hits -system.l2c.overall_hits::cpu0.inst 6831894 # number of overall hits -system.l2c.overall_hits::cpu0.data 3936961 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 232266 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 162523 # number of overall hits -system.l2c.overall_hits::cpu1.inst 6868394 # number of overall hits -system.l2c.overall_hits::cpu1.data 4002742 # number of overall hits -system.l2c.overall_hits::total 22428289 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 1733 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1771 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 37545 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 128493 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1846 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1781 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 39948 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 132523 # number of ReadReq misses -system.l2c.ReadReq_misses::total 345640 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 256190 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 246034 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 502224 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 17276 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 17378 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 34654 # number of UpgradeReq misses +system.l2c.tags.replacements 1294928 # number of replacements +system.l2c.tags.tagsinuse 65284.624377 # Cycle average of tags in use +system.l2c.tags.total_refs 28063625 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1358068 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 20.664374 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 7589253000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 38468.321907 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 163.057226 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 246.703748 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3367.231509 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9600.385059 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.839093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 239.160217 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3055.361096 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 9994.564521 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.586980 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002488 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003764 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.051380 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146490 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002286 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003649 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.046621 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.152505 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.996164 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 237 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 62903 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 236 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 413 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2457 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5430 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54571 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003616 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.959824 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 267604060 # Number of tag accesses +system.l2c.tags.data_accesses 267604060 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 246478 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 166336 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 6965395 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3278179 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 243308 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 165231 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 6932947 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3267656 # number of ReadReq hits +system.l2c.ReadReq_hits::total 21265530 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 7866652 # number of Writeback hits +system.l2c.Writeback_hits::total 7866652 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 360316 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 364967 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 725283 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 4896 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4962 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 9858 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 821407 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 805470 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1626877 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 246478 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 166336 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 6965395 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4099586 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 243308 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 165231 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 6932947 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4073126 # number of demand (read+write) hits +system.l2c.demand_hits::total 22892407 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 246478 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 166336 # number of overall hits +system.l2c.overall_hits::cpu0.inst 6965395 # number of overall hits +system.l2c.overall_hits::cpu0.data 4099586 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 243308 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 165231 # number of overall hits +system.l2c.overall_hits::cpu1.inst 6932947 # number of overall hits +system.l2c.overall_hits::cpu1.data 4073126 # number of overall hits +system.l2c.overall_hits::total 22892407 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1986 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2021 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 38679 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 132917 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 2168 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2035 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 40460 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 144107 # number of ReadReq misses +system.l2c.ReadReq_misses::total 364373 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 257472 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 250414 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 507886 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 17895 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 17622 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 35517 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu0.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 222062 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 215342 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 437404 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 1733 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1771 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 37545 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 350555 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1846 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1781 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 39948 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 347865 # number of demand (read+write) misses -system.l2c.demand_misses::total 783044 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 1733 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1771 # number of overall misses -system.l2c.overall_misses::cpu0.inst 37545 # number of overall misses -system.l2c.overall_misses::cpu0.data 350555 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1846 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1781 # number of overall misses -system.l2c.overall_misses::cpu1.inst 39948 # number of overall misses -system.l2c.overall_misses::cpu1.data 347865 # number of overall misses -system.l2c.overall_misses::total 783044 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 135529750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 141622000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 2789793743 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 9757073998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 147020500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 143375750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 2965510998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 10074405745 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 26154332484 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 117495 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 117495 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 204892196 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 203834744 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 408726940 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 23499 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 72000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 95499 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 16405067720 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 15885009720 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 32290077440 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 135529750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 141622000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 2789793743 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 26162141718 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 147020500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 143375750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 2965510998 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 25959415465 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 58444409924 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 135529750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 141622000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 2789793743 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 26162141718 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 147020500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 143375750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 2965510998 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 25959415465 # number of overall miss cycles -system.l2c.overall_miss_latency::total 58444409924 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 230848 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 166165 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 6869439 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3269502 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 234112 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 164304 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 6908342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 3305769 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 21148481 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 7621991 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 7621991 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 620770 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 607819 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1228589 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 22013 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 22210 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 44223 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses::cpu0.data 247554 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 266155 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 513709 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1986 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2021 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 38679 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 380471 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 2168 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2035 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 40460 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 410262 # number of demand (read+write) misses +system.l2c.demand_misses::total 878082 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1986 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2021 # number of overall misses +system.l2c.overall_misses::cpu0.inst 38679 # number of overall misses +system.l2c.overall_misses::cpu0.data 380471 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 2168 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2035 # number of overall misses +system.l2c.overall_misses::cpu1.inst 40460 # number of overall misses +system.l2c.overall_misses::cpu1.data 410262 # number of overall misses +system.l2c.overall_misses::total 878082 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 170354500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 177467000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 3182312556 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 11047112258 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 186335000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 177844750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3318730008 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 12078497021 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 30338653093 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 123996 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 123996 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 276678088 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 272829710 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 549507798 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 79500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 79500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 20013735944 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 21618082257 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 41631818201 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 170354500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 177467000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 3182312556 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 31060848202 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 186335000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 177844750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3318730008 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 33696579278 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 71970471294 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 170354500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 177467000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 3182312556 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 31060848202 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 186335000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 177844750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3318730008 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 33696579278 # number of overall miss cycles +system.l2c.overall_miss_latency::total 71970471294 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 248464 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 168357 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 7004074 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 3411096 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 245476 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 167266 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 6973407 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 3411763 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 21629903 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 7866652 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 7866652 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 617788 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 615381 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 1233169 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 22791 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 22584 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 45375 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1018014 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1044838 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2062852 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 230848 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 166165 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 6869439 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 4287516 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 234112 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 164304 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 6908342 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 4350607 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 23211333 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 230848 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 166165 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 6869439 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 4287516 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 234112 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 164304 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 6908342 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 4350607 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 23211333 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.007507 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.010658 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.005466 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.039300 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.007885 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.010840 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.005783 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.040088 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016343 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.412697 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.404782 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.408781 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784809 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782440 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.783619 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 1068961 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1071625 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2140586 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 248464 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 168357 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 7004074 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 4480057 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 245476 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 167266 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 6973407 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 4483388 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 23770489 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 248464 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 168357 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 7004074 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 4480057 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 245476 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 167266 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 6973407 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 4483388 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 23770489 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.007993 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012004 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.005522 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038966 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.008832 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.012166 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.005802 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.042238 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016846 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.416764 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.406925 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.411854 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.785178 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.780287 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.782744 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.218133 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.206101 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.212038 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.007507 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.010658 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.005466 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.081762 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.007885 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.010840 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.005783 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.079958 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.033735 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.007507 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.010658 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.005466 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.081762 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.007885 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.010840 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.005783 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.079958 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.033735 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78205.279862 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 79967.250141 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 74305.333413 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 75934.673469 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 79642.741062 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 80502.947782 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 74234.279513 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 76020.054972 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 75669.287363 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 0.477556 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 0.233949 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 11859.932623 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 11729.470825 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 11794.509725 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 23499 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 72000 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 47749.500000 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73876.069386 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73766.426057 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73822.089967 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78205.279862 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 79967.250141 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 74305.333413 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 74630.633475 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 79642.741062 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 80502.947782 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74234.279513 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74624.970793 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 74637.453226 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78205.279862 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 79967.250141 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 74305.333413 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 74630.633475 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 79642.741062 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 80502.947782 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74234.279513 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74624.970793 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 74637.453226 # average overall miss latency +system.l2c.ReadExReq_miss_rate::cpu0.data 0.231584 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.248366 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.239985 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.007993 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.012004 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.005522 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.084925 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.008832 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.012166 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.005802 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.091507 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.036940 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.007993 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.012004 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.005522 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.084925 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.008832 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.012166 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.005802 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.091507 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.036940 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 85777.693857 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 87811.479466 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82274.943923 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 83112.861846 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 85947.878229 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87392.997543 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82024.963124 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 83816.171463 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 83262.626740 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 0.481590 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 0.244141 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 15461.195194 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15482.335149 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 15471.683926 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 79500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 79500 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 80845.940457 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81223.656354 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 81041.636804 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 85777.693857 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87811.479466 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82274.943923 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 81637.886204 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85947.878229 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87392.997543 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82024.963124 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 82134.292910 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 81963.269141 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 85777.693857 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87811.479466 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82274.943923 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 81637.886204 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85947.878229 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87392.997543 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82024.963124 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 82134.292910 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 81963.269141 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1812,177 +1792,177 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1015610 # number of writebacks -system.l2c.writebacks::total 1015610 # number of writebacks -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1733 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1771 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 37545 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 128493 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1846 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1781 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 39948 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 132523 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 345640 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 256190 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 246034 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 502224 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 17276 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 17378 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 34654 # number of UpgradeReq MSHR misses +system.l2c.writebacks::writebacks 1109675 # number of writebacks +system.l2c.writebacks::total 1109675 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1986 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2021 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 38679 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 132917 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2168 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2035 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 40460 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 144107 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 364373 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 257472 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 250414 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 507886 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 17895 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 17622 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 35517 # number of UpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 222062 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 215342 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 437404 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 1733 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1771 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 37545 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 350555 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1846 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1781 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 39948 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 347865 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 783044 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 1733 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1771 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 37545 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 350555 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1846 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1781 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 39948 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 347865 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 783044 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 113876750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 119482500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2314108757 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 8139874502 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 123968000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 121118750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2459268502 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 8407004255 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 21798702016 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 5528504500 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 5313983006 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 10842487506 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 172842275 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 173897376 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 346739651 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 10001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 60000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 70001 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 13562638280 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 13132691780 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 26695330060 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 113876750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 119482500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2314108757 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 21702512782 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 123968000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 121118750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2459268502 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 21539696035 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 48494032076 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 113876750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 119482500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2314108757 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 21702512782 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 123968000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 121118750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2459268502 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 21539696035 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 48494032076 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1524532500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2469002751 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 724437500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2819508250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7537481001 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2376122500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2790457500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5166580000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1524532500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4845125251 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 724437500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5609965750 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12704061001 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007507 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010658 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.005466 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.039300 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.007885 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.010840 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005783 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.040088 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016343 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.412697 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.404782 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.408781 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.784809 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.782440 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.783619 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_misses::cpu0.data 247554 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 266155 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 513709 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 1986 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2021 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 38679 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 380471 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 2168 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2035 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 40460 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 410262 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 878082 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 1986 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2021 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 38679 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 380471 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 2168 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2035 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 40460 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 410262 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 878082 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 145388500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152020000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2697284444 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 9381927242 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 159094500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 152239750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2811418492 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 10272794479 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 25772167407 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 8111001504 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7888588001 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 15999589505 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 313790893 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 308995621 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 622786514 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 67500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 67500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 16917537056 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 18290027743 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 35207564799 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 145388500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 152020000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 2697284444 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 26299464298 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 159094500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 152239750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 2811418492 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 28562822222 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 60979732206 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 145388500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 152020000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 2697284444 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 26299464298 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 159094500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 152239750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 2811418492 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 28562822222 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 60979732206 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1552554500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2745071250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 1033159250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2534045000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7864830000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2622187500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2557908500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5180096000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1552554500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5367258750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1033159250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5091953500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13044926000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007993 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012004 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.005522 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.038966 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.008832 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.012166 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.005802 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.042238 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016846 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.416764 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.406925 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.411854 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.785178 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.780287 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.782744 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.218133 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.206101 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.212038 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007507 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010658 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005466 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.081762 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007885 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.010840 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005783 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.079958 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.033735 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007507 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010658 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005466 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.081762 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007885 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.010840 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005783 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.079958 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.033735 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63348.777770 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63438.076824 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63067.648467 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 21579.704516 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 21598.571767 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21588.947374 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10004.762387 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10006.754287 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10005.761269 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 60000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 35000.500000 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61075.907990 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60985.278209 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61031.289289 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61909.009377 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61919.698834 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61930.149616 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65710.761685 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67466.120836 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61635.604128 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61909.009377 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67154.929577 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 68006.035935 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 61561.742816 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61919.698834 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61930.149616 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.231584 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.248366 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.239985 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.007993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.012004 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.005522 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.084925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.008832 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.012166 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.005802 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.091507 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.036940 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.007993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.012004 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.005522 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.084925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.008832 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.012166 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.005802 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.091507 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.036940 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69735.113214 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70584.855526 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 71285.881179 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 70730.178710 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31502.460477 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31502.184387 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 31502.324350 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17535.115563 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17534.651061 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17534.885097 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 67500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68338.774797 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68719.459499 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 68536.009295 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69735.113214 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69123.439889 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69620.930581 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 69446.512064 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73206.696878 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 75220.188026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69735.113214 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69123.439889 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73383.071956 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 74810.687961 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69486.369056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69620.930581 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 69446.512064 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1997,57 +1977,57 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 431429 # Transaction distribution -system.membus.trans_dist::ReadResp 431429 # Transaction distribution -system.membus.trans_dist::WriteReq 33873 # Transaction distribution -system.membus.trans_dist::WriteResp 33873 # Transaction distribution -system.membus.trans_dist::Writeback 1122241 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 608883 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 608883 # Transaction distribution -system.membus.trans_dist::UpgradeReq 35220 # Transaction distribution +system.membus.trans_dist::ReadReq 450083 # Transaction distribution +system.membus.trans_dist::ReadResp 450083 # Transaction distribution +system.membus.trans_dist::WriteReq 33710 # Transaction distribution +system.membus.trans_dist::WriteResp 33710 # Transaction distribution +system.membus.trans_dist::Writeback 1216305 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 614546 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 614546 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36081 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 35222 # Transaction distribution -system.membus.trans_dist::ReadExReq 436846 # Transaction distribution -system.membus.trans_dist::ReadExResp 436846 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 36083 # Transaction distribution +system.membus.trans_dist::ReadExReq 513152 # Transaction distribution +system.membus.trans_dist::ReadExResp 513152 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6948 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3746179 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 3876375 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 334941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4211316 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4043368 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4173072 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335046 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4508118 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 147371488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 147541836 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14041536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14041536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 161583372 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3431 # Total snoops (count) -system.membus.snoop_fanout::samples 2557707 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159836512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 160006362 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14048000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14048000 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 174054362 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3335 # Total snoops (count) +system.membus.snoop_fanout::samples 2753479 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2557707 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2753479 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2557707 # Request fanout histogram -system.membus.reqLayer0.occupancy 107352000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2753479 # Request fanout histogram +system.membus.reqLayer0.occupancy 107121000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5560499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5172000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 16960886493 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10421674858 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 8211852015 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5445003775 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186625462 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151621202 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -2091,55 +2071,53 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 21612149 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 21604161 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33873 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33873 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 7621991 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1335253 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1228589 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 44226 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 22091229 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 22083154 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 7866652 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1339933 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1233169 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 45378 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 44228 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2062852 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2062852 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 27641812 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 27580079 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 784917 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1183820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 57190628 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 881950484 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1119524728 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2643752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3719680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2007838644 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 494311 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 32599559 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003544 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.059428 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 45380 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2140586 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2140586 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28041212 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 28486273 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 793018 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1241724 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 58562227 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 894731284 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1156290950 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2684984 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3951520 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2057658738 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 492069 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 33406949 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003462 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.058735 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 32484017 99.65% 99.65% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 33291303 99.65% 99.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115646 0.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 32599559 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 51716744749 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 3993000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 33406949 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 25817690750 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 1207500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 62067119757 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 39696027226 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 454863250 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 21033645158 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 14294630789 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 457872249 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 719296500 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 748277250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt index 2fadfdb24..daa556624 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt @@ -1,132 +1,132 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.121937 # Number of seconds simulated -sim_ticks 5121937205500 # Number of ticks simulated -final_tick 5121937205500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.154240 # Number of seconds simulated +sim_ticks 5154239928000 # Number of ticks simulated +final_tick 5154239928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 250170 # Simulator instruction rate (inst/s) -host_op_rate 494496 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3139783576 # Simulator tick rate (ticks/s) -host_mem_usage 754660 # Number of bytes of host memory used -host_seconds 1631.30 # Real time elapsed on the host -sim_insts 408103625 # Number of instructions simulated -sim_ops 806672783 # Number of ops (including micro ops) simulated +host_inst_rate 177928 # Simulator instruction rate (inst/s) +host_op_rate 351699 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2247974259 # Simulator tick rate (ticks/s) +host_mem_usage 809460 # Number of bytes of host memory used +host_seconds 2292.84 # Real time elapsed on the host +sim_insts 407959851 # Number of instructions simulated +sim_ops 806389826 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1046784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10762752 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 4224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1048832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10760128 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11842240 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1046784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1046784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9571648 # Number of bytes written to this memory -system.physmem.bytes_written::total 9571648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 16356 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 168168 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11841856 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1048832 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1048832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9579968 # Number of bytes written to this memory +system.physmem.bytes_written::total 9579968 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 66 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 16388 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 168127 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 185035 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 149557 # Number of write requests responded to by this memory -system.physmem.num_writes::total 149557 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 204373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2101305 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5535 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2312063 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 204373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 204373 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1868755 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1868755 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1868755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 204373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2101305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5535 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4180818 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 185035 # Number of read requests accepted -system.physmem.writeReqs 196277 # Number of write requests accepted -system.physmem.readBursts 185035 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 196277 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11833600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue -system.physmem.bytesWritten 12404928 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11842240 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12561728 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2419 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1772 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11869 # Per bank write bursts -system.physmem.perBankRdBursts::1 11279 # Per bank write bursts -system.physmem.perBankRdBursts::2 11900 # Per bank write bursts -system.physmem.perBankRdBursts::3 11555 # Per bank write bursts -system.physmem.perBankRdBursts::4 12140 # Per bank write bursts -system.physmem.perBankRdBursts::5 11427 # Per bank write bursts -system.physmem.perBankRdBursts::6 11446 # Per bank write bursts -system.physmem.perBankRdBursts::7 11418 # Per bank write bursts -system.physmem.perBankRdBursts::8 11156 # Per bank write bursts -system.physmem.perBankRdBursts::9 11288 # Per bank write bursts -system.physmem.perBankRdBursts::10 11167 # Per bank write bursts -system.physmem.perBankRdBursts::11 11604 # Per bank write bursts -system.physmem.perBankRdBursts::12 11474 # Per bank write bursts -system.physmem.perBankRdBursts::13 12255 # Per bank write bursts -system.physmem.perBankRdBursts::14 11757 # Per bank write bursts -system.physmem.perBankRdBursts::15 11165 # Per bank write bursts -system.physmem.perBankWrBursts::0 12900 # Per bank write bursts -system.physmem.perBankWrBursts::1 13064 # Per bank write bursts -system.physmem.perBankWrBursts::2 11983 # Per bank write bursts -system.physmem.perBankWrBursts::3 10698 # Per bank write bursts -system.physmem.perBankWrBursts::4 10899 # Per bank write bursts -system.physmem.perBankWrBursts::5 11057 # Per bank write bursts -system.physmem.perBankWrBursts::6 11263 # Per bank write bursts -system.physmem.perBankWrBursts::7 11237 # Per bank write bursts -system.physmem.perBankWrBursts::8 11985 # Per bank write bursts -system.physmem.perBankWrBursts::9 12151 # Per bank write bursts -system.physmem.perBankWrBursts::10 12710 # Per bank write bursts -system.physmem.perBankWrBursts::11 12714 # Per bank write bursts -system.physmem.perBankWrBursts::12 13328 # Per bank write bursts -system.physmem.perBankWrBursts::13 13119 # Per bank write bursts -system.physmem.perBankWrBursts::14 12767 # Per bank write bursts -system.physmem.perBankWrBursts::15 11952 # Per bank write bursts +system.physmem.num_reads::total 185029 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 149687 # Number of write requests responded to by this memory +system.physmem.num_writes::total 149687 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 820 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 203489 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2087627 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5501 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2297498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 203489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 203489 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1858658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1858658 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1858658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 820 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 203489 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2087627 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5501 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4156156 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 185029 # Number of read requests accepted +system.physmem.writeReqs 196407 # Number of write requests accepted +system.physmem.readBursts 185029 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 196407 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11835328 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6528 # Total number of bytes read from write queue +system.physmem.bytesWritten 10911872 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11841856 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 12570048 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 102 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25884 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1735 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11576 # Per bank write bursts +system.physmem.perBankRdBursts::1 11057 # Per bank write bursts +system.physmem.perBankRdBursts::2 12153 # Per bank write bursts +system.physmem.perBankRdBursts::3 11198 # Per bank write bursts +system.physmem.perBankRdBursts::4 11802 # Per bank write bursts +system.physmem.perBankRdBursts::5 11348 # Per bank write bursts +system.physmem.perBankRdBursts::6 11143 # Per bank write bursts +system.physmem.perBankRdBursts::7 11153 # Per bank write bursts +system.physmem.perBankRdBursts::8 11425 # Per bank write bursts +system.physmem.perBankRdBursts::9 11213 # Per bank write bursts +system.physmem.perBankRdBursts::10 11332 # Per bank write bursts +system.physmem.perBankRdBursts::11 11504 # Per bank write bursts +system.physmem.perBankRdBursts::12 11762 # Per bank write bursts +system.physmem.perBankRdBursts::13 12902 # Per bank write bursts +system.physmem.perBankRdBursts::14 11974 # Per bank write bursts +system.physmem.perBankRdBursts::15 11385 # Per bank write bursts +system.physmem.perBankWrBursts::0 11439 # Per bank write bursts +system.physmem.perBankWrBursts::1 10429 # Per bank write bursts +system.physmem.perBankWrBursts::2 10485 # Per bank write bursts +system.physmem.perBankWrBursts::3 9453 # Per bank write bursts +system.physmem.perBankWrBursts::4 11713 # Per bank write bursts +system.physmem.perBankWrBursts::5 11103 # Per bank write bursts +system.physmem.perBankWrBursts::6 10277 # Per bank write bursts +system.physmem.perBankWrBursts::7 10587 # Per bank write bursts +system.physmem.perBankWrBursts::8 10639 # Per bank write bursts +system.physmem.perBankWrBursts::9 10347 # Per bank write bursts +system.physmem.perBankWrBursts::10 10880 # Per bank write bursts +system.physmem.perBankWrBursts::11 10311 # Per bank write bursts +system.physmem.perBankWrBursts::12 10712 # Per bank write bursts +system.physmem.perBankWrBursts::13 11096 # Per bank write bursts +system.physmem.perBankWrBursts::14 11110 # Per bank write bursts +system.physmem.perBankWrBursts::15 9917 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5121937091000 # Total gap between requests +system.physmem.numWrRetry 48 # Number of times write queue was full causing retry +system.physmem.totGap 5154239876000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 185035 # Read request sizes (log2) +system.physmem.readPktSize::6 185029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 196277 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 170268 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 11906 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2015 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 55 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 27 # What read queue length does an incoming req see +system.physmem.writePktSize::6 196407 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 170541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 11600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1966 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -156,436 +156,415 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 9714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 12594 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 13080 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 14093 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 13730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 13174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 12623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 11181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8308 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 209 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 32 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74867 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.753643 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 187.995922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 341.769329 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 27720 37.03% 37.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17254 23.05% 60.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7564 10.10% 70.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4205 5.62% 75.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3013 4.02% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2021 2.70% 82.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1360 1.82% 84.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1151 1.54% 85.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10579 14.13% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74867 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7807 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.681312 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 544.837786 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7806 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1636 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1926 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6237 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6870 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7894 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9954 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8496 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8567 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1459 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2521 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2901 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 57 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 73580 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 309.148356 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.632665 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.613307 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 27722 37.68% 37.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17426 23.68% 61.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7585 10.31% 71.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4195 5.70% 77.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2982 4.05% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2040 2.77% 84.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1416 1.92% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1303 1.77% 87.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8911 12.11% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 73580 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6767 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.326437 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 584.974446 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6766 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7807 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.827334 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.378246 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.718812 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6359 81.45% 81.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 60 0.77% 82.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 16 0.20% 82.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 274 3.51% 85.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 187 2.40% 88.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 50 0.64% 88.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 34 0.44% 89.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 41 0.53% 89.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 177 2.27% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 17 0.22% 92.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 12 0.15% 92.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.17% 92.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 35 0.45% 93.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 16 0.20% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.10% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 51 0.65% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 104 1.33% 95.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 7 0.09% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 10 0.13% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 27 0.35% 96.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 148 1.90% 97.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 8 0.10% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 6 0.08% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 33 0.42% 98.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 2 0.03% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 12 0.15% 98.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.36% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 4 0.05% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.08% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.15% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.04% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 7 0.09% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.10% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.04% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.05% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 4 0.05% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::244-247 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7807 # Writes before turning the bus around for reads -system.physmem.totQLat 1977045500 # Total ticks spent queuing -system.physmem.totMemAccLat 5443920500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 924500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10692.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6767 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6767 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 25.195508 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.700984 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 42.210035 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6335 93.62% 93.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 84 1.24% 94.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.25% 95.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 17 0.25% 95.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 19 0.28% 95.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 20 0.30% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 33 0.49% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 32 0.47% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 26 0.38% 97.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 8 0.12% 97.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 61 0.90% 98.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 50 0.74% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.18% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 1 0.01% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.04% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.03% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.03% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 4 0.06% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 9 0.13% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 14 0.21% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.09% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.04% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6767 # Writes before turning the bus around for reads +system.physmem.totQLat 2002245948 # Total ticks spent queuing +system.physmem.totMemAccLat 5469627198 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 924635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10827.22 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29442.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.31 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.45 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29577.22 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.30 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.04 # Data bus utilization in percentage +system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing -system.physmem.readRowHits 151994 # Number of row buffer hits during reads -system.physmem.writeRowHits 151865 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.34 # Row buffer hit rate for writes -system.physmem.avgGap 13432404.67 # Average gap between requests -system.physmem.pageHitRate 80.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 281753640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 153734625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 725665200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 603294480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 129490880310 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2959572897750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3425368148085 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.764386 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4923440733500 # Time in different power states -system.physmem_0.memoryStateTime::REF 171032680000 # Time in different power states +system.physmem.avgWrQLen 23.30 # Average write queue length when enqueuing +system.physmem.readRowHits 151945 # Number of row buffer hits during reads +system.physmem.writeRowHits 129899 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.16 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.18 # Row buffer hit rate for writes +system.physmem.avgGap 13512725.27 # Average gap between requests +system.physmem.pageHitRate 79.29 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 271547640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 148165875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 713146200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 553949280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 130302295830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2978239548750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3446878082535 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.747042 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4954509635136 # Time in different power states +system.physmem_0.memoryStateTime::REF 172111160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27462249000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27619022864 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 284240880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 155091750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 716547000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 652704480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 334539922080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 129160456155 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2959862743500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3425371705845 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.765080 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4923925616750 # Time in different power states -system.physmem_1.memoryStateTime::REF 171032680000 # Time in different power states +system.physmem_1.actEnergy 284717160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 155351625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 729276600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 550877760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 336649428960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 130834885590 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2977772364750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3446976902445 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.766215 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4953723422640 # Time in different power states +system.physmem_1.memoryStateTime::REF 172111160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26978805250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28398444860 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 86925803 # Number of BP lookups -system.cpu.branchPred.condPredicted 86925803 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 896443 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 80098191 # Number of BTB lookups -system.cpu.branchPred.BTBHits 78212465 # Number of BTB hits +system.cpu.branchPred.lookups 86886659 # Number of BP lookups +system.cpu.branchPred.condPredicted 86886659 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 896606 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 80012064 # Number of BTB lookups +system.cpu.branchPred.BTBHits 78173158 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.645732 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1561001 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 180305 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.701714 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1555790 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 180979 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 449601109 # number of cpu cycles simulated +system.cpu.numCycles 452015949 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27685322 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 429319828 # Number of instructions fetch has processed -system.cpu.fetch.Branches 86925803 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 79773466 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 418005810 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1881156 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 145066 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 56340 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 216419 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 69 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 534 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 9181154 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 448969 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 4854 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 447050138 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.894862 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.052352 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 27708415 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 429123541 # Number of instructions fetch has processed +system.cpu.fetch.Branches 86886659 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 79728948 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 420284778 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1879978 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 144708 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 58405 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 207121 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 57 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 651 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 9181144 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 450119 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5089 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 449344124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.884391 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.047300 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 281515886 62.97% 62.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2210439 0.49% 63.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 72204596 16.15% 79.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1602689 0.36% 79.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2146844 0.48% 80.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 2305649 0.52% 80.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1524322 0.34% 81.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1908424 0.43% 81.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 81631289 18.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 283935319 63.19% 63.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2153229 0.48% 63.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 72170843 16.06% 79.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1584001 0.35% 80.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2141625 0.48% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 2336888 0.52% 81.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1524270 0.34% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1887238 0.42% 81.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 81610711 18.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 447050138 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.193340 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.954891 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 23043701 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 264854286 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 150758526 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 7453047 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 940578 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 838760021 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 940578 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 25901615 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 223330945 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13194802 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 154665359 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 29016839 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 835288144 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 480498 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 12432167 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 195018 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 13714744 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 997792221 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1814468169 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1115407405 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 373 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 964705167 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 33087052 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 465878 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 469687 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 39083891 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 17351329 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10177979 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1302580 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1089364 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 829800190 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1202669 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 824540368 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 243435 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 23398238 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 36211142 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 151712 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 447050138 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.844402 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.418243 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 449344124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.192220 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.949355 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 23005123 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 267198709 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 150742142 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 7458161 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 939989 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 838443104 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 939989 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 25847202 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 224345308 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 13466568 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 154654216 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 30090841 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 834933758 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 459142 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 12335285 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 199811 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 14823013 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 997303578 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1813575837 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1114848675 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 334 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 964352232 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 32951344 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 467055 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 470880 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 38821668 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 17323479 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10180206 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1295686 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1069829 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 829469634 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1196558 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 824230120 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 243416 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 23349289 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 36028466 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 151024 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 449344124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.834296 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.415438 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 262726585 58.77% 58.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13876357 3.10% 61.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 10104726 2.26% 64.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 6925504 1.55% 65.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 74353941 16.63% 82.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4450821 1.00% 83.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 72845421 16.29% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1198612 0.27% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 568171 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 265024726 58.98% 58.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 14037592 3.12% 62.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 9914300 2.21% 64.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7059540 1.57% 65.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 74309398 16.54% 82.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4399488 0.98% 83.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 72817937 16.21% 99.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1206490 0.27% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 574653 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 447050138 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 449344124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 1991949 71.90% 71.90% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 123 0.00% 71.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 1473 0.05% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 71.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 615411 22.21% 94.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 161409 5.83% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1987162 71.98% 71.98% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 137 0.00% 71.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 645 0.02% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 72.01% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 611861 22.16% 94.18% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 160804 5.82% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 289852 0.04% 0.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 796144481 96.56% 96.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 150888 0.02% 96.61% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 125650 0.02% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 123 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 18436778 2.24% 98.86% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 9392596 1.14% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 290308 0.04% 0.04% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 795868269 96.56% 96.59% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 150766 0.02% 96.61% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 125160 0.02% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 92 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 18401922 2.23% 98.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 9393603 1.14% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 824540368 # Type of FU issued -system.cpu.iq.rate 1.833938 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2770367 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.003360 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2099144137 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 854413357 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 819991210 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 538 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 510 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 185 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 827020625 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 258 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1864655 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 824230120 # Type of FU issued +system.cpu.iq.rate 1.823454 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2760609 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.003349 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2100807897 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 854027763 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 819692227 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 491 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 488 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 172 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 826700185 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 236 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1868049 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 3351077 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13836 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 14513 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1751193 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 3330814 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14803 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 14207 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1754572 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2224299 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 72996 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2207477 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 74768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 940578 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 205605732 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9422457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 831002859 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 153624 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 17351329 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 10177979 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 705669 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 415252 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 8108448 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 14513 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 513988 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 533382 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1047370 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 822936172 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 18038480 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1469642 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 939989 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 205903045 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10169335 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 830666192 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152285 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 17323479 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 10180206 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 703380 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 416558 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 8857895 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 14207 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 510302 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 537060 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1047362 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 822616274 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 18004247 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1478799 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 27207078 # number of memory reference insts executed -system.cpu.iew.exec_branches 83328554 # Number of branches executed -system.cpu.iew.exec_stores 9168598 # Number of stores executed -system.cpu.iew.exec_rate 1.830370 # Inst execution rate -system.cpu.iew.wb_sent 822433213 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 819991395 # cumulative count of insts written-back -system.cpu.iew.wb_producers 641244168 # num instructions producing a value -system.cpu.iew.wb_consumers 1050921658 # num instructions consuming a value +system.cpu.iew.exec_refs 27174393 # number of memory reference insts executed +system.cpu.iew.exec_branches 83301836 # Number of branches executed +system.cpu.iew.exec_stores 9170146 # Number of stores executed +system.cpu.iew.exec_rate 1.819883 # Inst execution rate +system.cpu.iew.wb_sent 822114086 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 819692399 # cumulative count of insts written-back +system.cpu.iew.wb_producers 640992347 # num instructions producing a value +system.cpu.iew.wb_consumers 1050518142 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.823820 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.610173 # average fanout of values written-back +system.cpu.iew.wb_rate 1.813415 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.610168 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 24200169 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1050957 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 908606 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 443415424 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.819226 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.675431 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 24149765 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1045534 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 907960 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 445713409 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.809212 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.671420 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 272547704 61.47% 61.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 11191107 2.52% 63.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3581688 0.81% 64.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 74592593 16.82% 81.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 2424395 0.55% 82.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1607477 0.36% 82.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 945915 0.21% 82.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 71066294 16.03% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5458251 1.23% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 274913705 61.68% 61.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 11179565 2.51% 64.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3571950 0.80% 64.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 74564778 16.73% 81.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 2421074 0.54% 82.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1628213 0.37% 82.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 937027 0.21% 82.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71052272 15.94% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5444825 1.22% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 443415424 # Number of insts commited each cycle -system.cpu.commit.committedInsts 408103625 # Number of instructions committed -system.cpu.commit.committedOps 806672783 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 445713409 # Number of insts commited each cycle +system.cpu.commit.committedInsts 407959851 # Number of instructions committed +system.cpu.commit.committedOps 806389826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 22427037 # Number of memory references committed -system.cpu.commit.loads 14000251 # Number of loads committed -system.cpu.commit.membars 475479 # Number of memory barriers committed -system.cpu.commit.branches 82225235 # Number of branches committed +system.cpu.commit.refs 22418298 # Number of memory references committed +system.cpu.commit.loads 13992664 # Number of loads committed +system.cpu.commit.membars 471797 # Number of memory barriers committed +system.cpu.commit.branches 82198639 # Number of branches committed system.cpu.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu.commit.int_insts 735463006 # Number of committed integer instructions. -system.cpu.commit.function_calls 1156113 # Number of function calls committed. -system.cpu.commit.op_class_0::No_OpClass 171674 0.02% 0.02% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 783810008 97.17% 97.19% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 145072 0.02% 97.21% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 121556 0.02% 97.22% # Class of committed instruction +system.cpu.commit.int_insts 735203522 # Number of committed integer instructions. +system.cpu.commit.function_calls 1155963 # Number of function calls committed. +system.cpu.commit.op_class_0::No_OpClass 171777 0.02% 0.02% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 783535872 97.17% 97.19% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 144976 0.02% 97.21% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 121468 0.02% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 16 0.00% 97.22% # Class of committed instruction @@ -612,167 +591,167 @@ system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 97.22% # system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 97.22% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 97.22% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 13997671 1.74% 98.96% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 8426786 1.04% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 13990083 1.73% 98.96% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 8425634 1.04% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 806672783 # Class of committed instruction -system.cpu.commit.bw_lim_events 5458251 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 806389826 # Class of committed instruction +system.cpu.commit.bw_lim_events 5444825 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1268751952 # The number of ROB reads -system.cpu.rob.rob_writes 1665400460 # The number of ROB writes -system.cpu.timesIdled 293768 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 2550971 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 9794270972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 408103625 # Number of Instructions Simulated -system.cpu.committedOps 806672783 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.101684 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.101684 # CPI: Total CPI of All Threads -system.cpu.ipc 0.907702 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.907702 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1092990942 # number of integer regfile reads -system.cpu.int_regfile_writes 656343554 # number of integer regfile writes -system.cpu.fp_regfile_reads 191 # number of floating regfile reads -system.cpu.cc_regfile_reads 416454943 # number of cc regfile reads -system.cpu.cc_regfile_writes 322187827 # number of cc regfile writes -system.cpu.misc_regfile_reads 265705543 # number of misc regfile reads -system.cpu.misc_regfile_writes 400219 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1658771 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.995092 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 19161993 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1659283 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.548357 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 37454250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.995092 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999990 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999990 # Average percentage of cache occupancy +system.cpu.rob.rob_reads 1270729806 # The number of ROB reads +system.cpu.rob.rob_writes 1664729387 # The number of ROB writes +system.cpu.timesIdled 294275 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 2671825 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 9856461520 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 407959851 # Number of Instructions Simulated +system.cpu.committedOps 806389826 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 1.107991 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.107991 # CPI: Total CPI of All Threads +system.cpu.ipc 0.902534 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.902534 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1092541258 # number of integer regfile reads +system.cpu.int_regfile_writes 656084038 # number of integer regfile writes +system.cpu.fp_regfile_reads 176 # number of floating regfile reads +system.cpu.cc_regfile_reads 416293281 # number of cc regfile reads +system.cpu.cc_regfile_writes 322054452 # number of cc regfile writes +system.cpu.misc_regfile_reads 265591845 # number of misc regfile reads +system.cpu.misc_regfile_writes 400328 # number of misc regfile writes +system.cpu.dcache.tags.replacements 1659836 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.989699 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 19130413 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1660348 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.521930 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 41264250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.989699 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999980 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999980 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 294 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88441081 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88441081 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 11011311 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 11011311 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8082990 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8082990 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 64916 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 64916 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 19094301 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 19094301 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 19159217 # number of overall hits -system.cpu.dcache.overall_hits::total 19159217 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1795762 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1795762 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 334107 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 334107 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 406359 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 406359 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 2129869 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2129869 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2536228 # number of overall misses -system.cpu.dcache.overall_misses::total 2536228 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26474085005 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26474085005 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12834716256 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12834716256 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39308801261 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39308801261 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39308801261 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39308801261 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12807073 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12807073 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8417097 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8417097 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 471275 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 471275 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21224170 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21224170 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21695445 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21695445 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.140216 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.140216 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039694 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.039694 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.862255 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.862255 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.100351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.100351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.116901 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.116901 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14742.535484 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14742.535484 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38414.987582 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38414.987582 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18455.971358 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18455.971358 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 15498.922518 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 15498.922518 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 371080 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39978 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.282105 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.tags.tag_accesses 88364873 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88364873 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 10981747 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 10981747 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8081553 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8081553 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 64328 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 64328 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 19063300 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 19063300 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 19127628 # number of overall hits +system.cpu.dcache.overall_hits::total 19127628 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1807734 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1807734 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 334390 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 334390 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 406367 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 406367 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 2142124 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2142124 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2548491 # number of overall misses +system.cpu.dcache.overall_misses::total 2548491 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27237843437 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27237843437 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 13894605384 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 13894605384 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 41132448821 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 41132448821 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 41132448821 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 41132448821 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12789481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12789481 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8415943 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8415943 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 470695 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 470695 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21205424 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21205424 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21676119 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21676119 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.141345 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.141345 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.039733 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.039733 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.863334 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.863334 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.101018 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.101018 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117571 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117571 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15067.395666 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15067.395666 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41552.096008 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41552.096008 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19201.712329 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19201.712329 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 16139.923124 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 16139.923124 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 413510 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 44186 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.358394 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1560107 # number of writebacks -system.cpu.dcache.writebacks::total 1560107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 826960 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 826960 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44237 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 44237 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 871197 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 871197 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 871197 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 871197 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 968802 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 968802 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289870 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 289870 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402896 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402896 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1258672 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1258672 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1661568 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1661568 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12247021519 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 12247021519 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11168468751 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11168468751 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5577776251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5577776251 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23415490270 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23415490270 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993266521 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28993266521 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97397501000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97397501000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2571147000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2571147000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 99968648000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 99968648000 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075646 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075646 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034438 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034438 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.854906 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.854906 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059304 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059304 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076586 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076586 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12641.408171 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12641.408171 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38529.232935 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38529.232935 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13844.208558 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13844.208558 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18603.329755 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18603.329755 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17449.340936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17449.340936 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 1561658 # number of writebacks +system.cpu.dcache.writebacks::total 1561658 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 837908 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 837908 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 44444 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 44444 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 882352 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 882352 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 882352 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 882352 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969826 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 969826 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 289946 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 289946 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402900 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 402900 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1259772 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1259772 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1662672 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1662672 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12862571524 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 12862571524 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12285238213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12285238213 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5938147500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5938147500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25147809737 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25147809737 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31085957237 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31085957237 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 97453049000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 97453049000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2592894500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2592894500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 100045943500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 100045943500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075830 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075830 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.034452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.034452 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.855968 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.855968 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059408 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059408 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076705 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076705 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13262.762108 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13262.762108 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42370.780121 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42370.780121 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14738.514520 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14738.514520 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19962.191362 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 19962.191362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18696.385840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 18696.385840 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -780,58 +759,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 75411 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 15.808771 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 114018 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 75427 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.511634 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 193713357500 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.808771 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988048 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988048 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.replacements 73822 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 15.784353 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 116295 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 73836 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.575045 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 194860088500 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.784353 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.986522 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.986522 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 14 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 457557 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 457557 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 114018 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 114018 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 114018 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 114018 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 114018 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 114018 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 76507 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 76507 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 76507 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 76507 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 76507 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 76507 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 935770691 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 935770691 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 935770691 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 935770691 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 935770691 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 935770691 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 190525 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 190525 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 190525 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 190525 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 190525 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 190525 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.401559 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.401559 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.401559 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.401559 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.401559 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.401559 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12231.177422 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12231.177422 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12231.177422 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12231.177422 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12231.177422 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12231.177422 # average overall miss latency +system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.875000 # Percentage of cache occupancy per task id +system.cpu.dtb_walker_cache.tags.tag_accesses 457427 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 457427 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116311 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 116311 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116311 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 116311 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116311 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 116311 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 74935 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 74935 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 74935 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 74935 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 74935 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 74935 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 914897711 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 914897711 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 914897711 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 914897711 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 914897711 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 914897711 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 191246 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 191246 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 191246 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 191246 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 191246 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 191246 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.391825 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.391825 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.391825 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.391825 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.391825 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.391825 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12209.217468 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12209.217468 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12209.217468 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12209.217468 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12209.217468 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -840,180 +819,180 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 22022 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 22022 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 76507 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 76507 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 76507 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 76507 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 76507 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 76507 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 782624451 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 782624451 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 782624451 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 782624451 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 782624451 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 782624451 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.401559 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.401559 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.401559 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.401559 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10229.448952 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10229.448952 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10229.448952 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10229.448952 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 20337 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 20337 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 74935 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 74935 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 74935 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 74935 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 74935 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 74935 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 802357975 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 802357975 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 802357975 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 802357975 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 802357975 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 802357975 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.391825 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.391825 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.391825 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.391825 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10707.386068 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10707.386068 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10707.386068 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1000352 # number of replacements -system.cpu.icache.tags.tagsinuse 509.220531 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 8118136 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1000864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 8.111128 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 147684343000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 509.220531 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.994571 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.994571 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1000631 # number of replacements +system.cpu.icache.tags.tagsinuse 508.729229 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 8114183 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1001143 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 8.104919 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 148026169000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.729229 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.993612 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.993612 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 170 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 233 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 172 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 10182088 # Number of tag accesses -system.cpu.icache.tags.data_accesses 10182088 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 8118136 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 8118136 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 8118136 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 8118136 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 8118136 # number of overall hits -system.cpu.icache.overall_hits::total 8118136 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1063017 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1063017 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1063017 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1063017 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1063017 # number of overall misses -system.cpu.icache.overall_misses::total 1063017 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14764552848 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14764552848 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14764552848 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14764552848 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14764552848 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14764552848 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 9181153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 9181153 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 9181153 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 9181153 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 9181153 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 9181153 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115783 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.115783 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.115783 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.115783 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.115783 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.115783 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13889.291374 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13889.291374 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13889.291374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13889.291374 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13889.291374 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7778 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 8 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 283 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 27.484099 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 8 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 10182374 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10182374 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 8114183 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 8114183 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 8114183 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 8114183 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 8114183 # number of overall hits +system.cpu.icache.overall_hits::total 8114183 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1066954 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1066954 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1066954 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1066954 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1066954 # number of overall misses +system.cpu.icache.overall_misses::total 1066954 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14925731792 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14925731792 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14925731792 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14925731792 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14925731792 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14925731792 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 9181137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 9181137 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 9181137 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 9181137 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 9181137 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 9181137 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.116212 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.116212 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.116212 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.116212 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.116212 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.116212 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13989.105240 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13989.105240 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13989.105240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13989.105240 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13989.105240 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 10002 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 328 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 30.493902 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62082 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 62082 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 62082 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 62082 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 62082 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 62082 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1000935 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1000935 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1000935 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1000935 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1000935 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1000935 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12121618509 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12121618509 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12121618509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12121618509 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12121618509 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12121618509 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109021 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.109021 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109021 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.109021 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12110.295383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12110.295383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12110.295383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12110.295383 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65717 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 65717 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 65717 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 65717 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 65717 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 65717 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1001237 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1001237 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1001237 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1001237 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1001237 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1001237 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12740674547 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12740674547 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12740674547 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12740674547 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12740674547 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12740674547 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109054 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109054 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109054 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109054 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12724.933804 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12724.933804 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12724.933804 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12724.933804 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 14419 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 6.299272 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 25752 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 14435 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 1.783997 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5101096739000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.299272 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.393704 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.393704 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 16 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 14933 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 6.063651 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 25583 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 14948 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.711466 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5108134601500 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.063651 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.378978 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.378978 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 97449 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 97449 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25750 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 25750 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 98613 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 98613 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 25588 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 25588 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25752 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 25752 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25752 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 25752 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15315 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 15315 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15315 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 15315 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15315 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 15315 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 177860992 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 177860992 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 177860992 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 177860992 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 177860992 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 177860992 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41065 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 41065 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 25590 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 25590 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 25590 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 25590 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 15811 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 15811 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 15811 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 15811 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 15811 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 15811 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 183242996 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 183242996 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 183242996 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 183242996 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 183242996 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 183242996 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41399 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 41399 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41067 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 41067 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41067 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 41067 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.372945 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.372945 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.372927 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.372927 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.372927 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.372927 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11613.515638 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11613.515638 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11613.515638 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11613.515638 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11613.515638 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11613.515638 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41401 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 41401 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41401 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 41401 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.381917 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.381917 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.381899 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.381899 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.381899 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.381899 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11589.589273 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11589.589273 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11589.589273 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11589.589273 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11589.589273 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1022,177 +1001,177 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 3318 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 3318 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15315 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15315 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15315 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 15315 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15315 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 15315 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 147213024 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 147213024 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 147213024 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 147213024 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 147213024 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 147213024 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.372945 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.372945 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.372927 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.372927 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.372927 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9612.342409 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9612.342409 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9612.342409 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9612.342409 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 3310 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 3310 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 15811 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 15811 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 15811 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 15811 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 15811 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 15811 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 159511522 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 159511522 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 159511522 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 159511522 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 159511522 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 159511522 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.381917 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.381917 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.381899 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.381899 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.381899 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10088.642211 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 10088.642211 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 10088.642211 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 112445 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64830.405135 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3843138 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 176455 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 21.779706 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 112684 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64825.802499 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3846196 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 176714 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 21.765089 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50339.203670 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 14.644782 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.444532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3208.377327 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11267.734824 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768115 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000223 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048956 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.171932 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.989233 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64010 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 596 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3348 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7208 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 52806 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.976715 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 35103909 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 35103909 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 69111 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12768 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 984459 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1335184 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2401522 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1585447 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1585447 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 154410 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 154410 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 69111 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12768 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 984459 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1489594 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2555932 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 69111 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12768 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 984459 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1489594 # number of overall hits -system.cpu.l2cache.overall_hits::total 2555932 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 62 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 6 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 16359 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 35824 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 52251 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1504 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1504 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133327 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133327 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 62 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 6 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 16359 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 169151 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 185578 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 62 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 6 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 16359 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 169151 # number of overall misses -system.cpu.l2cache.overall_misses::total 185578 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 5303750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 467500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1250815250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2830285496 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 4086871996 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 17716796 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 17716796 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9290586712 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9290586712 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 5303750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 467500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1250815250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12120872208 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13377458708 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 5303750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 467500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1250815250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12120872208 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13377458708 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 69173 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12774 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1000818 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1371008 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2453773 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1585447 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1585447 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1813 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1813 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 287737 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 287737 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 69173 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12774 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1000818 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1658745 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2741510 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 69173 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12774 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1000818 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1658745 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2741510 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000896 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000470 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016346 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026130 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021294 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.829564 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.829564 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463364 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.463364 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000896 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000470 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016346 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.101975 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.067692 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000896 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000470 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016346 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.101975 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.067692 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 85544.354839 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77916.666667 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76460.373495 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79005.289638 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 78216.148897 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11779.784574 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11779.784574 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69682.710269 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69682.710269 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 85544.354839 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77916.666667 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76460.373495 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71657.112332 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72085.369537 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 85544.354839 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77916.666667 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76460.373495 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71657.112332 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72085.369537 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 50361.141250 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 15.517179 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.137228 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3161.997282 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11287.009561 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.768450 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000237 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.048248 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.172226 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.989163 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64030 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 558 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3484 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5616 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54343 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.977020 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 35101682 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 35101682 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 67331 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 13137 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 984666 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1336353 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2401487 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1585305 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1585305 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 326 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 326 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 154346 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 154346 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 67331 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 13137 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 984666 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1490699 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2555833 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 67331 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 13137 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 984666 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1490699 # number of overall hits +system.cpu.l2cache.overall_hits::total 2555833 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 66 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 16391 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 35623 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 52085 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1473 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1473 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133459 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133459 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 66 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 16391 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 169082 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 185544 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 66 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 16391 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 169082 # number of overall misses +system.cpu.l2cache.overall_misses::total 185544 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 6193250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 446000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1375483774 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3059797000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 4441920024 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22673320 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 22673320 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10319199473 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10319199473 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 6193250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 446000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1375483774 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 13378996473 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14761119497 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 6193250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 446000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1375483774 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 13378996473 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14761119497 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 67397 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 13142 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1001057 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1371976 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2453572 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1585305 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1585305 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1799 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1799 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 287805 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 287805 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 67397 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 13142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1001057 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1659781 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2741377 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 67397 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 13142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1001057 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1659781 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2741377 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000979 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000380 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016374 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025965 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.021228 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.818788 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.463713 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.463713 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000979 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000380 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016374 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.101870 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.067683 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000979 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000380 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016374 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.101870 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.067683 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93837.121212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 89200 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83917.013849 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85893.860708 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 85282.135432 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15392.613714 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15392.613714 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77321.120891 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77321.120891 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79555.897776 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93837.121212 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 89200 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83917.013849 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79127.266492 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79555.897776 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1201,99 +1180,99 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 102890 # number of writebacks -system.cpu.l2cache.writebacks::total 102890 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 103019 # number of writebacks +system.cpu.l2cache.writebacks::total 103019 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 3 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 62 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 6 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16356 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35821 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 52245 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1504 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1504 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133327 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133327 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 62 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 6 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 16356 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 169148 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 185572 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 62 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 6 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 16356 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 169148 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 185572 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 4538750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 391500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1045537500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2387984748 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3438452498 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 15960982 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 15960982 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7616458286 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7616458286 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 4538750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 391500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1045537500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10004443034 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11054910784 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 4538750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 391500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1045537500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10004443034 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11054910784 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 89282348000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 89282348000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2403570000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2403570000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91685918000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91685918000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026127 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021292 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.829564 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.829564 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463364 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463364 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.067690 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000896 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000470 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016343 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101973 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.067690 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63923.789435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66664.379777 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65814.001302 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10612.355053 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10612.355053 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57126.150637 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57126.150637 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73205.645161 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63923.789435 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59146.091198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59572.084064 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_hits::cpu.data 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 66 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 16388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 35622 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 52081 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1473 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1473 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133459 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133459 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 66 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 16388 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 169081 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 185540 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 66 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 16388 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 169081 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 185540 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5361750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 383000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1170197226 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2615090750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3791032726 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27003455 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27003455 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8650755527 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8650755527 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 5361750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 383000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1170197226 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11265846277 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12441788253 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 5361750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 383000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1170197226 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11265846277 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12441788253 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 88987317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 88987317500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2410942500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2410942500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 91398260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 91398260000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025964 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021227 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.818788 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.818788 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.463713 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.463713 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.067681 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000979 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000380 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016371 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.101869 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.067681 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 76600 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 71405.737491 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73412.238224 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72791.089380 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18332.284453 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18332.284453 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64819.574004 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64819.574004 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 81238.636364 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 76600 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71405.737491 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66629.877260 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67057.175019 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1301,69 +1280,69 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3074706 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3074138 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3070183 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3069642 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 13919 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 13919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1585447 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2253 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 287746 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 287746 # Transaction distribution -system.cpu.toL2Bus.trans_dist::BadAddressError 27 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2001753 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6129358 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 31407 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 167702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8330220 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64052352 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207821235 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1029888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5836480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 278739955 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 59032 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4387424 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.010858 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.103635 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::Writeback 1585305 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46754 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2280 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 287814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 287814 # Transaction distribution +system.cpu.toL2Bus.trans_dist::BadAddressError 8 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2002294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6123530 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 32263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 162669 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8320756 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 64067648 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207974818 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1052928 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5614976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 278710370 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 59545 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4387643 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.010865 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.103666 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4339785 98.91% 98.91% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47639 1.09% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4339973 98.91% 98.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47670 1.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4387424 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4074051871 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4387643 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4071571970 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 574500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1505430236 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1506228195 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3141534733 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3139390437 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 22981484 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 23723987 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 114826620 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 112471118 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 225722 # Transaction distribution -system.iobus.trans_dist::ReadResp 225722 # Transaction distribution -system.iobus.trans_dist::WriteReq 57753 # Transaction distribution -system.iobus.trans_dist::WriteResp 11033 # Transaction distribution +system.iobus.trans_dist::ReadReq 223900 # Transaction distribution +system.iobus.trans_dist::ReadResp 223900 # Transaction distribution +system.iobus.trans_dist::WriteReq 57738 # Transaction distribution +system.iobus.trans_dist::WriteResp 11018 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1643 # Transaction distribution -system.iobus.trans_dist::MessageResp 1643 # Transaction distribution +system.iobus.trans_dist::MessageReq 1650 # Transaction distribution +system.iobus.trans_dist::MessageResp 1650 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 423734 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1373,21 +1352,21 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 471672 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95278 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95278 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3286 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 570236 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 468004 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95272 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3300 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3300 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 566576 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 211867 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1397,19 +1376,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 242122 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027896 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3276590 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3915016 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 240285 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027872 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3274757 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3933000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 8851000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1421,7 +1400,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 211868000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1439,54 +1418,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448363457 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 257352407 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 460639000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 456986000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52378260 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50389253 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1643000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1650000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47584 # number of replacements -system.iocache.tags.tagsinuse 0.079092 # Cycle average of tags in use +system.iocache.tags.replacements 47582 # number of replacements +system.iocache.tags.tagsinuse 0.177916 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47600 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47598 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 4992999647000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.079092 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.004943 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.004943 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 4993302485000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.177916 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.011120 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.011120 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428751 # Number of tag accesses -system.iocache.tags.data_accesses 428751 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 919 # number of ReadReq misses -system.iocache.ReadReq_misses::total 919 # number of ReadReq misses +system.iocache.tags.tag_accesses 428724 # Number of tag accesses +system.iocache.tags.data_accesses 428724 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 916 # number of ReadReq misses +system.iocache.ReadReq_misses::total 916 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 919 # number of demand (read+write) misses -system.iocache.demand_misses::total 919 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 919 # number of overall misses -system.iocache.overall_misses::total 919 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 149123196 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 149123196 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12357582001 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12357582001 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 149123196 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 149123196 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 149123196 # number of overall miss cycles -system.iocache.overall_miss_latency::total 149123196 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 919 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 919 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 916 # number of demand (read+write) misses +system.iocache.demand_misses::total 916 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 916 # number of overall misses +system.iocache.overall_misses::total 916 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144791938 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 144791938 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8565273216 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8565273216 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 144791938 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 144791938 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 144791938 # number of overall miss cycles +system.iocache.overall_miss_latency::total 144791938 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 916 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 916 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 919 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 919 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 919 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 919 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 916 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 916 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 916 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 916 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1495,40 +1474,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 162266.807399 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264503.039405 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264503.039405 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 162266.807399 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 162266.807399 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 162266.807399 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70647 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158069.801310 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183332.046575 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183332.046575 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 158069.801310 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158069.801310 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 158069.801310 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 29224 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9165 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4409 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.708347 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.628260 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 46667 # number of writebacks -system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 919 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 919 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 46668 # number of writebacks +system.iocache.writebacks::total 46668 # number of writebacks +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 916 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 916 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 919 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 919 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 919 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 919 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 101309696 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9928122021 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9928122021 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 101309696 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 101309696 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 101309696 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 916 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 916 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 916 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 916 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 96734432 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6135821228 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6135821228 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 96734432 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 96734432 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 96734432 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1537,79 +1516,79 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 110239.059848 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212502.611751 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212502.611751 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 110239.059848 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 110239.059848 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105605.275109 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131331.789983 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131331.789983 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105605.275109 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 105605.275109 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 662612 # Transaction distribution -system.membus.trans_dist::ReadResp 662585 # Transaction distribution +system.membus.trans_dist::ReadReq 657690 # Transaction distribution +system.membus.trans_dist::ReadResp 657682 # Transaction distribution system.membus.trans_dist::WriteReq 13919 # Transaction distribution system.membus.trans_dist::WriteResp 13919 # Transaction distribution -system.membus.trans_dist::Writeback 149557 # Transaction distribution +system.membus.trans_dist::Writeback 149687 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2230 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1790 # Transaction distribution -system.membus.trans_dist::ReadExReq 133043 # Transaction distribution -system.membus.trans_dist::ReadExResp 133041 # Transaction distribution -system.membus.trans_dist::MessageReq 1643 # Transaction distribution -system.membus.trans_dist::MessageResp 1643 # Transaction distribution -system.membus.trans_dist::BadAddressError 27 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3286 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471672 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775062 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476745 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 54 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1723533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141469 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141469 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1868288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6572 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242122 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550121 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18398848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20191091 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26202783 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1603 # Total snoops (count) -system.membus.snoop_fanout::samples 384714 # Request fanout histogram +system.membus.trans_dist::UpgradeReq 2233 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1752 # Transaction distribution +system.membus.trans_dist::ReadExReq 133182 # Transaction distribution +system.membus.trans_dist::ReadExResp 133180 # Transaction distribution +system.membus.trans_dist::MessageReq 1650 # Transaction distribution +system.membus.trans_dist::MessageResp 1650 # Transaction distribution +system.membus.trans_dist::BadAddressError 8 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 468004 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 769220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 476828 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 16 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1714068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141467 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1858835 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6600 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 240285 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1538437 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18406720 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20185442 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6005184 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26197226 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1640 # Total snoops (count) +system.membus.snoop_fanout::samples 384867 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 384714 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 384867 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 384714 # Request fanout histogram -system.membus.reqLayer0.occupancy 251770499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 384867 # Request fanout histogram +system.membus.reqLayer0.occupancy 357799000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 583267500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 388520500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3286000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3300000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1992294999 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1203232654 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 33000 # Layer occupancy (ticks) +system.membus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1643000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1650000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 3156735730 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 55013740 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2208381292 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 51518747 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). -system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD). +system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD). system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions. diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt index 79cf4b255..fa561f06e 100644 --- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/stats.txt @@ -1,154 +1,150 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.144107 # Number of seconds simulated -sim_ticks 5144107123500 # Number of ticks simulated -final_tick 5144107123500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.134221 # Number of seconds simulated +sim_ticks 5134220888000 # Number of ticks simulated +final_tick 5134220888000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 387693 # Simulator instruction rate (inst/s) -host_op_rate 770744 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 8185899527 # Simulator tick rate (ticks/s) -host_mem_usage 958064 # Number of bytes of host memory used -host_seconds 628.41 # Real time elapsed on the host -sim_insts 243630211 # Number of instructions simulated -sim_ops 484343866 # Number of ops (including micro ops) simulated +host_inst_rate 274165 # Simulator instruction rate (inst/s) +host_op_rate 545049 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5772363280 # Simulator tick rate (ticks/s) +host_mem_usage 1013712 # Number of bytes of host memory used +host_seconds 889.45 # Real time elapsed on the host +sim_insts 243855553 # Number of instructions simulated +sim_ops 484792888 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 435328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 5271168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 167488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 2239424 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 2304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 369088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2863936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 442496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 5387840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 144896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1908224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 377856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 3143424 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 11377408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 435328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 167488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 369088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 971904 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9177088 # Number of bytes written to this memory -system.physmem.bytes_written::total 9177088 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 82362 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2617 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 34991 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 36 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 44749 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 11436096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 442496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 144896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 377856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 965248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9176704 # Number of bytes written to this memory +system.physmem.bytes_written::total 9176704 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6914 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 84185 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2264 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 29816 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5904 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 49116 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 177772 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 143392 # Number of write requests responded to by this memory -system.physmem.num_writes::total 143392 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 84627 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1024700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 12 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 32559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 435338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 448 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 71750 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 556741 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5512 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2211736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 84627 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 32559 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 71750 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 188935 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1784000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1784000 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1784000 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 84627 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1024700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 12 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 32559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 435338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 448 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 71750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 556741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5512 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3995736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 88604 # Number of read requests accepted -system.physmem.writeReqs 101715 # Number of write requests accepted -system.physmem.readBursts 88604 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 101715 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 5666496 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 4160 # Total number of bytes read from write queue -system.physmem.bytesWritten 6448384 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 5670656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6509760 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 65 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 959 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 894 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 5172 # Per bank write bursts -system.physmem.perBankRdBursts::1 4675 # Per bank write bursts -system.physmem.perBankRdBursts::2 4614 # Per bank write bursts -system.physmem.perBankRdBursts::3 5517 # Per bank write bursts -system.physmem.perBankRdBursts::4 6171 # Per bank write bursts -system.physmem.perBankRdBursts::5 5192 # Per bank write bursts -system.physmem.perBankRdBursts::6 5194 # Per bank write bursts -system.physmem.perBankRdBursts::7 5097 # Per bank write bursts -system.physmem.perBankRdBursts::8 5481 # Per bank write bursts -system.physmem.perBankRdBursts::9 5563 # Per bank write bursts -system.physmem.perBankRdBursts::10 5214 # Per bank write bursts -system.physmem.perBankRdBursts::11 5694 # Per bank write bursts -system.physmem.perBankRdBursts::12 5834 # Per bank write bursts -system.physmem.perBankRdBursts::13 6887 # Per bank write bursts -system.physmem.perBankRdBursts::14 6277 # Per bank write bursts -system.physmem.perBankRdBursts::15 5957 # Per bank write bursts -system.physmem.perBankWrBursts::0 6561 # Per bank write bursts -system.physmem.perBankWrBursts::1 6098 # Per bank write bursts -system.physmem.perBankWrBursts::2 5964 # Per bank write bursts -system.physmem.perBankWrBursts::3 5948 # Per bank write bursts -system.physmem.perBankWrBursts::4 7233 # Per bank write bursts -system.physmem.perBankWrBursts::5 6043 # Per bank write bursts -system.physmem.perBankWrBursts::6 6495 # Per bank write bursts -system.physmem.perBankWrBursts::7 6502 # Per bank write bursts -system.physmem.perBankWrBursts::8 5629 # Per bank write bursts -system.physmem.perBankWrBursts::9 6174 # Per bank write bursts -system.physmem.perBankWrBursts::10 5473 # Per bank write bursts -system.physmem.perBankWrBursts::11 6467 # Per bank write bursts -system.physmem.perBankWrBursts::12 6126 # Per bank write bursts -system.physmem.perBankWrBursts::13 6747 # Per bank write bursts -system.physmem.perBankWrBursts::14 6614 # Per bank write bursts -system.physmem.perBankWrBursts::15 6682 # Per bank write bursts +system.physmem.num_reads::total 178689 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 143386 # Number of write requests responded to by this memory +system.physmem.num_writes::total 143386 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.itb.walker 62 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 86186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1049398 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 28222 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 371668 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 524 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 612249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2227426 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 86186 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 28222 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73596 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 188003 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1787361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1787361 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1787361 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 86186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1049398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 28222 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 371668 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 524 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 612249 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5522 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4014786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 87585 # Number of read requests accepted +system.physmem.writeReqs 96690 # Number of write requests accepted +system.physmem.readBursts 87585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96690 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 5601728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 3712 # Total number of bytes read from write queue +system.physmem.bytesWritten 5458112 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 5605440 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6188160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 58 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11390 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 914 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 5700 # Per bank write bursts +system.physmem.perBankRdBursts::1 5150 # Per bank write bursts +system.physmem.perBankRdBursts::2 4887 # Per bank write bursts +system.physmem.perBankRdBursts::3 5253 # Per bank write bursts +system.physmem.perBankRdBursts::4 5094 # Per bank write bursts +system.physmem.perBankRdBursts::5 4483 # Per bank write bursts +system.physmem.perBankRdBursts::6 5146 # Per bank write bursts +system.physmem.perBankRdBursts::7 4650 # Per bank write bursts +system.physmem.perBankRdBursts::8 5914 # Per bank write bursts +system.physmem.perBankRdBursts::9 5792 # Per bank write bursts +system.physmem.perBankRdBursts::10 5352 # Per bank write bursts +system.physmem.perBankRdBursts::11 5127 # Per bank write bursts +system.physmem.perBankRdBursts::12 5714 # Per bank write bursts +system.physmem.perBankRdBursts::13 6636 # Per bank write bursts +system.physmem.perBankRdBursts::14 6391 # Per bank write bursts +system.physmem.perBankRdBursts::15 6238 # Per bank write bursts +system.physmem.perBankWrBursts::0 5924 # Per bank write bursts +system.physmem.perBankWrBursts::1 5309 # Per bank write bursts +system.physmem.perBankWrBursts::2 4960 # Per bank write bursts +system.physmem.perBankWrBursts::3 5064 # Per bank write bursts +system.physmem.perBankWrBursts::4 5666 # Per bank write bursts +system.physmem.perBankWrBursts::5 4857 # Per bank write bursts +system.physmem.perBankWrBursts::6 5361 # Per bank write bursts +system.physmem.perBankWrBursts::7 4594 # Per bank write bursts +system.physmem.perBankWrBursts::8 5275 # Per bank write bursts +system.physmem.perBankWrBursts::9 5755 # Per bank write bursts +system.physmem.perBankWrBursts::10 5195 # Per bank write bursts +system.physmem.perBankWrBursts::11 4824 # Per bank write bursts +system.physmem.perBankWrBursts::12 5173 # Per bank write bursts +system.physmem.perBankWrBursts::13 6061 # Per bank write bursts +system.physmem.perBankWrBursts::14 5642 # Per bank write bursts +system.physmem.perBankWrBursts::15 5623 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5140299284500 # Total gap between requests +system.physmem.numWrRetry 29 # Number of times write queue was full causing retry +system.physmem.totGap 5133220754000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 88604 # Read request sizes (log2) +system.physmem.readPktSize::6 87585 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 101715 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 3378 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96690 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 81722 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4619 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 680 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 44 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -165,455 +161,450 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6371 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6627 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 6534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4632 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 40184 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 301.485168 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 176.308895 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.181387 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15726 39.13% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9443 23.50% 62.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4063 10.11% 72.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2232 5.55% 78.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1531 3.81% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1042 2.59% 84.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 702 1.75% 86.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 613 1.53% 87.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4832 12.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 40184 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4135 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.412092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 185.359125 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 4132 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1535 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5632-6143 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9728-10239 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4135 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4135 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.366626 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.429404 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 24.022185 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-7 69 1.67% 1.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-15 9 0.22% 1.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 3347 80.94% 82.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 165 3.99% 86.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 114 2.76% 89.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 31 0.75% 90.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 101 2.44% 92.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 11 0.27% 93.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 26 0.63% 93.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 40 0.97% 94.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 54 1.31% 95.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 10 0.24% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 75 1.81% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 8 0.19% 98.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 18 0.44% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 7 0.17% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 15 0.36% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 4 0.10% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 12 0.29% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 5 0.12% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 2 0.05% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 2 0.05% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 1 0.02% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 4 0.10% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.05% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4135 # Writes before turning the bus around for reads -system.physmem.totQLat 956383499 # Total ticks spent queuing -system.physmem.totMemAccLat 2616489749 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 442695000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10801.83 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::0 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 3794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 3928 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 3751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 759 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1374 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1059 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1078 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 775 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 674 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 568 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 55 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 67 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 38708 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 285.721608 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 170.408148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 310.834116 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15365 39.69% 39.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9282 23.98% 63.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4036 10.43% 74.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2303 5.95% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1514 3.91% 83.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1118 2.89% 86.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 653 1.69% 88.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 582 1.50% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3855 9.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38708 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3628 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.124587 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 196.006736 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 3625 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1535 1 0.03% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-6655 1 0.03% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::9728-10239 1 0.03% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 3628 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3628 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.506891 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.576033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 38.070070 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-15 79 2.18% 2.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 3330 91.79% 93.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 63 1.74% 95.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 14 0.39% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 6 0.17% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 13 0.36% 96.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 6 0.17% 96.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 13 0.36% 97.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 16 0.44% 97.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 18 0.50% 98.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.08% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 8 0.22% 98.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.91% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 3 0.08% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 1 0.03% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.06% 99.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 2 0.06% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.08% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 1 0.03% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.19% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.08% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 1 0.03% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3628 # Writes before turning the bus around for reads +system.physmem.totQLat 973946232 # Total ticks spent queuing +system.physmem.totMemAccLat 2615077482 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 437635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11127.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29551.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.25 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.10 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.27 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29877.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.09 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.06 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.21 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.42 # Average write queue length when enqueuing -system.physmem.readRowHits 70796 # Number of row buffer hits during reads -system.physmem.writeRowHits 78315 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.96 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 77.73 # Row buffer hit rate for writes -system.physmem.avgGap 27008860.31 # Average gap between requests -system.physmem.pageHitRate 78.77 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 147178080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 80086875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 324729600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 329469120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 94792163085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2243751115500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 2589991237140 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.838461 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 3691094925500 # Time in different power states -system.physmem_0.memoryStateTime::REF 128101480000 # Time in different power states +system.physmem.avgWrQLen 10.98 # Average write queue length when enqueuing +system.physmem.readRowHits 70024 # Number of row buffer hits during reads +system.physmem.writeRowHits 64077 # Number of row buffer hits during writes +system.physmem.readRowHitRate 80.00 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.12 # Row buffer hit rate for writes +system.physmem.avgGap 27856305.81 # Average gap between requests +system.physmem.pageHitRate 77.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 138605040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 75351375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 314831400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 270442800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 94326783165 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2239415376750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 2584559149170 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.799253 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 3683386249962 # Time in different power states +system.physmem_0.memoryStateTime::REF 127820940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 17513749500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 17097201288 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 156612960 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 85300875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 365874600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 323429760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 250566494880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 95660983305 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2237004864750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 2584163561130 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.053818 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 3689804823000 # Time in different power states -system.physmem_1.memoryStateTime::REF 128101480000 # Time in different power states +system.physmem_1.actEnergy 154027440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 83877750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 367863600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 282191040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 250017758640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 95207179230 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2235926942250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 2582039839950 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.929569 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 3682087997664 # Time in different power states +system.physmem_1.memoryStateTime::REF 127820940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 18778765250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 18395204336 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu0.numCycles 906748886 # number of cpu cycles simulated +system.cpu0.numCycles 861071319 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 71802590 # Number of instructions committed -system.cpu0.committedOps 146381299 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 134255761 # Number of integer alu accesses +system.cpu0.committedInsts 71289400 # Number of instructions committed +system.cpu0.committedOps 145467698 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 133359316 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 943296 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 14239563 # number of instructions that are conditional controls -system.cpu0.num_int_insts 134255761 # number of integer instructions +system.cpu0.num_func_calls 922812 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14140303 # number of instructions that are conditional controls +system.cpu0.num_int_insts 133359316 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 246209877 # number of times the integer registers were read -system.cpu0.num_int_register_writes 115427878 # number of times the integer registers were written +system.cpu0.num_int_register_reads 244470794 # number of times the integer registers were read +system.cpu0.num_int_register_writes 114705006 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 83592437 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 55838323 # number of times the CC registers were written -system.cpu0.num_mem_refs 13658115 # number of memory refs -system.cpu0.num_load_insts 10127652 # Number of load instructions -system.cpu0.num_store_insts 3530463 # Number of store instructions -system.cpu0.num_idle_cycles 859556134.264708 # Number of idle cycles -system.cpu0.num_busy_cycles 47192751.735292 # Number of busy cycles -system.cpu0.not_idle_fraction 0.052046 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.947954 # Percentage of idle cycles -system.cpu0.Branches 15533640 # Number of branches fetched -system.cpu0.op_class::No_OpClass 89870 0.06% 0.06% # Class of executed instruction -system.cpu0.op_class::IntAlu 132527069 90.54% 90.60% # Class of executed instruction -system.cpu0.op_class::IntMult 58535 0.04% 90.64% # Class of executed instruction -system.cpu0.op_class::IntDiv 49919 0.03% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.67% # Class of executed instruction -system.cpu0.op_class::MemRead 10125945 6.92% 97.59% # Class of executed instruction -system.cpu0.op_class::MemWrite 3530463 2.41% 100.00% # Class of executed instruction +system.cpu0.num_cc_register_reads 82965986 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 55469495 # number of times the CC registers were written +system.cpu0.num_mem_refs 13497529 # number of memory refs +system.cpu0.num_load_insts 10019587 # Number of load instructions +system.cpu0.num_store_insts 3477942 # Number of store instructions +system.cpu0.num_idle_cycles 817633663.650796 # Number of idle cycles +system.cpu0.num_busy_cycles 43437655.349204 # Number of busy cycles +system.cpu0.not_idle_fraction 0.050446 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.949554 # Percentage of idle cycles +system.cpu0.Branches 15408320 # Number of branches fetched +system.cpu0.op_class::No_OpClass 89223 0.06% 0.06% # Class of executed instruction +system.cpu0.op_class::IntAlu 131776877 90.59% 90.65% # Class of executed instruction +system.cpu0.op_class::IntMult 58105 0.04% 90.69% # Class of executed instruction +system.cpu0.op_class::IntDiv 48148 0.03% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 90.72% # Class of executed instruction +system.cpu0.op_class::MemRead 10017918 6.89% 97.61% # Class of executed instruction +system.cpu0.op_class::MemWrite 3477942 2.39% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 146381801 # Class of executed instruction +system.cpu0.op_class::total 145468213 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 1639020 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999449 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 19713831 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1639532 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 12.024060 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 1637783 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999406 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 19710876 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1638295 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 12.031335 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 7549500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 129.995226 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 275.897813 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 106.106411 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.253897 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.538863 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.207239 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.289579 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 344.626695 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 23.083132 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.281816 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.673099 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.045084 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 235 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 219 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 88616075 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 88616075 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 4923544 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 2619910 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4021776 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 11565230 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3397085 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1858074 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2831900 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 8087059 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19915 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10654 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29231 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 59800 # number of SoftPFReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8320629 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 4477984 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6853676 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 19652289 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8340544 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 4488638 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6882907 # number of overall hits -system.cpu0.dcache.overall_hits::total 19712089 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 358740 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 166586 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 774812 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1300138 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 129303 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 72150 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 124071 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 325524 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 150487 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 66279 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 189615 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 406381 # number of SoftPFReq misses -system.cpu0.dcache.demand_misses::cpu0.data 488043 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 238736 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 898883 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1625662 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 638530 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 305015 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 1088498 # number of overall misses -system.cpu0.dcache.overall_misses::total 2032043 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2329828500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11922594046 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 14252422546 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2798605810 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 3955887575 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6754493385 # number of WriteReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 5128434310 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 15878481621 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 21006915931 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 5128434310 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 15878481621 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 21006915931 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5282284 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 2786496 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4796588 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 12865368 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3526388 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1930224 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2955971 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 8412583 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 170402 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 76933 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 218846 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 466181 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 8808672 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 4716720 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7752559 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 21277951 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 8979074 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 4793653 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7971405 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 21744132 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067914 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.059783 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.161534 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.101057 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036667 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.037379 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.041973 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.038695 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.883129 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.861516 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.866431 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871724 # miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055405 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050615 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115947 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.076401 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.071113 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.063629 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.136550 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.093452 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13985.740098 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15387.725082 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 10962.238275 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38788.715315 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 31884.062956 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20749.601827 # average WriteReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21481.612786 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17664.681189 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 12922.068629 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16813.711817 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14587.515660 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 10337.830415 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 128988 # number of cycles access was blocked +system.cpu0.dcache.tags.tag_accesses 88682212 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88682212 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 4830179 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 2466757 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4264396 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 11561332 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3346491 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1735459 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 3006073 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 8088023 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 19837 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 10092 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu2.data 29821 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 59750 # number of SoftPFReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8176670 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 4202216 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 7270469 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 19649355 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8196507 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 4212308 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 7300290 # number of overall hits +system.cpu0.dcache.overall_hits::total 19709105 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 348359 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 159608 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 811619 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1319586 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 127641 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 64125 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 133967 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 325733 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 145510 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 64697 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu2.data 196344 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 406551 # number of SoftPFReq misses +system.cpu0.dcache.demand_misses::cpu0.data 476000 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 223733 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 945586 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1645319 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 621510 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 288430 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 1141930 # number of overall misses +system.cpu0.dcache.overall_misses::total 2051870 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 2193925000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 11673600356 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13867525356 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 2608735779 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 4432412697 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7041148476 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 4802660779 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 16106013053 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 20908673832 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 4802660779 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 16106013053 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 20908673832 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5178538 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 2626365 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 5076015 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 12880918 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3474132 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1799584 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 3140040 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 8413756 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 165347 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 74789 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 226165 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 466301 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 8652670 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 4425949 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 8216055 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 21294674 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 8818017 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 4500738 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 8442220 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 21760975 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.067270 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.060771 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.159893 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.102445 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.036740 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.035633 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.042664 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.038714 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.880028 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.865060 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.868145 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.871864 # miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.055012 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.050550 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115090 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.077264 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.070482 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.064085 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.135264 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.094291 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13745.708235 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14383.103841 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10508.997031 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 40682.039439 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 33085.854703 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21616.319120 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 21466.036655 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 17032.837894 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 12707.975676 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16651.044548 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 14104.203456 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 10190.057768 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 161116 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27777 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19020 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 4.643698 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.470873 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1548363 # number of writebacks -system.cpu0.dcache.writebacks::total 1548363 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 50 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 354752 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 354802 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1695 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 30847 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 32542 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu1.data 1745 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 385599 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 387344 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 1745 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 385599 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 387344 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 166536 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 420060 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 586596 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 70455 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 93224 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 163679 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 66278 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 186071 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 252349 # number of SoftPFReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 236991 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 513284 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 750275 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 303269 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 699355 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1002624 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1995417000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5681817065 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7677234065 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2564306918 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3209237662 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5773544580 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 908338500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2750087755 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3658426255 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4559723918 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 8891054727 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13450778645 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5468062418 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 11641142482 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 17109204900 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30379634500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33000290500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63379925000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 574626500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 695015500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1269642000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30954261000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33695306000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64649567000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.059765 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.087575 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.045595 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036501 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.031538 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019456 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.861503 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.850237 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.541311 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050245 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.066208 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.035261 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063265 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.087733 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.046110 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11981.895806 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13526.203554 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13087.770910 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36396.379505 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34425.015683 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35273.581706 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13704.977519 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14779.776295 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14497.486636 # average SoftPFReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19240.072062 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17321.901183 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17927.798001 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18030.403431 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16645.541223 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17064.427841 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1546722 # number of writebacks +system.cpu0.dcache.writebacks::total 1546722 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 49 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 374785 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 374834 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 1569 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 32139 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 33708 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 1618 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 406924 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 408542 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 1618 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 406924 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 408542 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 159559 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 436834 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 596393 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 62556 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 101828 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 164384 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 64697 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 192960 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 257657 # number of SoftPFReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 222115 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 538662 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 760777 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 286812 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 731622 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1018434 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1953809500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5644023259 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7597832759 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 2418621221 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 3692192265 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6110813486 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 904952750 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2733042751 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 3637995501 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 4372430721 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 9336215524 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13708646245 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 5277383471 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 12069258275 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 17346641746 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30408890000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 33050179000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 63459069000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 531811000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 800665000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1332476000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 30940701000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 33850844000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 64791545000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.060753 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.086058 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.046301 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034761 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.032429 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019538 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.865060 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.853182 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.552555 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.050185 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.065562 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.035726 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.063726 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.086662 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.046801 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.059821 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12920.292969 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12739.641074 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 38663.297222 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 36259.106189 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37174.016242 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 13987.553519 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14163.778768 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14119.529068 # average SoftPFReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 19685.436468 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17332.233430 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18019.270095 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18400.148777 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16496.576477 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17032.661661 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -624,521 +615,521 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 869493 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.803035 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 129984824 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 870005 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 149.406985 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 149054236250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 146.476673 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 257.387173 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 106.939188 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.286087 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.502709 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.208866 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997662 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 877463 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.822061 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 128690361 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 877975 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 146.576339 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 150549344000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 275.387940 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 146.288168 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 89.145952 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.537867 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.285719 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.174113 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997699 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 281 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 131747901 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 131747901 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 87329682 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 39588904 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3066238 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 129984824 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 87329682 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 39588904 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3066238 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 129984824 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 87329682 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 39588904 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3066238 # number of overall hits -system.cpu0.icache.overall_hits::total 129984824 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 312920 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 172473 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 407665 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 893058 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 312920 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 172473 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 407665 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 893058 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 312920 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 172473 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 407665 # number of overall misses -system.cpu0.icache.overall_misses::total 893058 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2415923500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 5732417941 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 8148341441 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 2415923500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 5732417941 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 8148341441 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 2415923500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 5732417941 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 8148341441 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 87642602 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 39761377 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 3473903 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 130877882 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 87642602 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 39761377 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 3473903 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 130877882 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 87642602 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 39761377 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 3473903 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 130877882 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003570 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004338 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.117351 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.006824 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003570 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004338 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.117351 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.006824 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003570 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004338 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.117351 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.006824 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 14007.546109 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 14061.589641 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9124.089859 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 14007.546109 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 14061.589641 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9124.089859 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 14007.546109 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 14061.589641 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9124.089859 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 4572 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 6 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 130472306 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 130472306 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 86685680 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 38800184 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3204497 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 128690361 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 86685680 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 38800184 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3204497 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 128690361 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 86685680 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 38800184 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3204497 # number of overall hits +system.cpu0.icache.overall_hits::total 128690361 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 302042 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 162655 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 439255 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 903952 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 302042 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 162655 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 439255 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 903952 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 302042 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 162655 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 439255 # number of overall misses +system.cpu0.icache.overall_misses::total 903952 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2276697249 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6082026148 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 8358723397 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 2276697249 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 6082026148 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 8358723397 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 2276697249 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 6082026148 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 8358723397 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 86987722 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 38962839 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3643752 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 129594313 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 86987722 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 38962839 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3643752 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 129594313 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 86987722 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 38962839 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3643752 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 129594313 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003472 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.004175 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.120550 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.006975 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003472 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.004175 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.120550 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.006975 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003472 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.004175 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.120550 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.006975 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13997.093535 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13846.230886 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9246.866423 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13997.093535 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13846.230886 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9246.866423 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13997.093535 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13846.230886 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9246.866423 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5936 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 21 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 289 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.970954 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 6 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.539792 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 21 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23039 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23039 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23039 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23039 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23039 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23039 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 172473 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 384626 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 557099 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 172473 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 384626 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 557099 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 172473 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 384626 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 557099 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2070011500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 4726513433 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 6796524933 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2070011500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 4726513433 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 6796524933 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2070011500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 4726513433 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 6796524933 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004257 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.004257 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004338 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.110719 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.004257 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12199.851253 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12001.945232 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12288.595761 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12199.851253 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 25959 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 25959 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 25959 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 25959 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 25959 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 25959 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 162655 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 413296 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 575951 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 162655 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 413296 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 575951 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 162655 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 413296 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 575951 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2031893251 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 5207377551 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 7239270802 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2031893251 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 5207377551 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 7239270802 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2031893251 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 5207377551 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 7239270802 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.004444 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.004444 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.004175 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.113426 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.004444 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12569.247735 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12492.042981 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12599.632106 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12569.247735 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 2608020264 # number of cpu cycles simulated +system.cpu1.numCycles 2606018109 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 35983855 # Number of instructions committed -system.cpu1.committedOps 69821911 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 64889046 # Number of integer alu accesses +system.cpu1.committedInsts 35373738 # Number of instructions committed +system.cpu1.committedOps 68746890 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 63819737 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 503439 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 6569343 # number of instructions that are conditional controls -system.cpu1.num_int_insts 64889046 # number of integer instructions +system.cpu1.num_func_calls 481772 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 6496386 # number of instructions that are conditional controls +system.cpu1.num_int_insts 63819737 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 120388172 # number of times the integer registers were read -system.cpu1.num_int_register_writes 55814326 # number of times the integer registers were written +system.cpu1.num_int_register_reads 118130559 # number of times the integer registers were read +system.cpu1.num_int_register_writes 54973369 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 36581725 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 27247591 # number of times the CC registers were written -system.cpu1.num_mem_refs 4980693 # number of memory refs -system.cpu1.num_load_insts 3049501 # Number of load instructions -system.cpu1.num_store_insts 1931192 # Number of store instructions -system.cpu1.num_idle_cycles 2477411639.002949 # Number of idle cycles -system.cpu1.num_busy_cycles 130608624.997051 # Number of busy cycles -system.cpu1.not_idle_fraction 0.050080 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.949920 # Percentage of idle cycles -system.cpu1.Branches 7257729 # Number of branches fetched -system.cpu1.op_class::No_OpClass 34768 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 64752658 92.74% 92.79% # Class of executed instruction -system.cpu1.op_class::IntMult 32117 0.05% 92.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 23661 0.03% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 92.87% # Class of executed instruction -system.cpu1.op_class::MemRead 3047883 4.37% 97.23% # Class of executed instruction -system.cpu1.op_class::MemWrite 1931192 2.77% 100.00% # Class of executed instruction +system.cpu1.num_cc_register_reads 36098608 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 26881383 # number of times the CC registers were written +system.cpu1.num_mem_refs 4684980 # number of memory refs +system.cpu1.num_load_insts 2884758 # Number of load instructions +system.cpu1.num_store_insts 1800222 # Number of store instructions +system.cpu1.num_idle_cycles 2483538175.555252 # Number of idle cycles +system.cpu1.num_busy_cycles 122479933.444748 # Number of busy cycles +system.cpu1.not_idle_fraction 0.046999 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.953001 # Percentage of idle cycles +system.cpu1.Branches 7152522 # Number of branches fetched +system.cpu1.op_class::No_OpClass 34380 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 63978277 93.06% 93.11% # Class of executed instruction +system.cpu1.op_class::IntMult 29063 0.04% 93.16% # Class of executed instruction +system.cpu1.op_class::IntDiv 22112 0.03% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 93.19% # Class of executed instruction +system.cpu1.op_class::MemRead 2883100 4.19% 97.38% # Class of executed instruction +system.cpu1.op_class::MemWrite 1800222 2.62% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 69822279 # Class of executed instruction +system.cpu1.op_class::total 68747154 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 29145274 # Number of BP lookups -system.cpu2.branchPred.condPredicted 29145274 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 322260 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 26440523 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 25789579 # Number of BTB hits +system.cpu2.branchPred.lookups 29503892 # Number of BP lookups +system.cpu2.branchPred.condPredicted 29503892 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 342810 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 26694805 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 25976378 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.538082 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 584080 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 63924 # Number of incorrect RAS predictions. -system.cpu2.numCycles 153878746 # number of cpu cycles simulated +system.cpu2.branchPred.BTBHitPct 97.308739 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 611666 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 68809 # Number of incorrect RAS predictions. +system.cpu2.numCycles 155682865 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 10764874 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 143615831 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 29145274 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 26373659 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 141609884 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 675175 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 95795 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.MiscStallCycles 6373 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 7380 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 61565 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 20 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 458 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 3473911 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 167436 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 3564 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 152883285 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.850280 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 3.030640 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 11322292 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 145393707 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 29503892 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 26588044 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 142785185 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 717310 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 102884 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.MiscStallCycles 9783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 8624 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 60469 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 854 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3643758 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 177822 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 3817 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 154648109 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.849994 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 3.031354 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 97765346 63.95% 63.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 837203 0.55% 64.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 23601513 15.44% 79.93% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 591420 0.39% 80.32% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 819374 0.54% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 838216 0.55% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 577391 0.38% 81.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 693159 0.45% 82.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 27159663 17.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 98977108 64.00% 64.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 881864 0.57% 64.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 23689941 15.32% 79.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 607646 0.39% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 853753 0.55% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 859687 0.56% 81.39% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 584791 0.38% 81.77% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 755278 0.49% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 27438041 17.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 152883285 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.189404 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.933305 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9834703 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 93251994 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 21466938 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 4884733 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 338239 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 279965546 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 338239 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 11923429 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 75993663 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 4610925 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 24032799 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 12877614 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 278749384 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 221936 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 5866894 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 51314 # Number of times rename has blocked due to LQ full -system.cpu2.rename.SQFullEvents 4911660 # Number of times rename has blocked due to SQ full -system.cpu2.rename.RenamedOperands 333127303 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 607942521 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 373256279 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 196 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 320819170 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12308133 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 159156 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 160655 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 23900033 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6505190 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3599973 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 377004 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 316512 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 276808275 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 423236 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 274695170 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 101004 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 8754938 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 13676659 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 65243 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 152883285 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.796764 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 2.395757 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 154648109 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.189513 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.933910 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10277895 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 94004330 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 21519674 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4891128 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 359306 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 283040141 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 359306 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 12341484 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 77022094 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 4867618 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 24062417 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12399480 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 281740718 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 206678 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 5855345 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 68061 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 4394741 # Number of times rename has blocked due to SQ full +system.cpu2.rename.RenamedOperands 336544944 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 615400877 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 377780143 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 207 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 323636169 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12908773 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 167322 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 168903 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 23920372 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6854331 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3831116 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 436605 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 369940 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 279698877 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 432383 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 277466645 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 109952 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 9178493 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 14257252 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 68980 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 154648109 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.794181 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.395462 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 90394017 59.13% 59.13% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 5385946 3.52% 62.65% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 3961954 2.59% 65.24% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 3603407 2.36% 67.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 22510778 14.72% 82.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 2513602 1.64% 83.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 23841558 15.59% 99.56% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 461559 0.30% 99.86% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 210464 0.14% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 91599661 59.23% 59.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 5400101 3.49% 62.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 3869243 2.50% 65.22% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 3752650 2.43% 67.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 22658386 14.65% 82.30% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 2693281 1.74% 84.04% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 23975807 15.50% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 476523 0.31% 99.86% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 222457 0.14% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 152883285 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 154648109 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 1679391 85.86% 85.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 6 0.00% 85.86% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 133 0.01% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.87% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 216471 11.07% 96.93% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 59961 3.07% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 1665704 85.56% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 85.56% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 217161 11.15% 96.71% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 64057 3.29% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 81534 0.03% 0.03% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 264357889 96.24% 96.27% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 55368 0.02% 96.29% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 50253 0.02% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 68 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.30% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 6828846 2.49% 98.79% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3321212 1.21% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 83075 0.03% 0.03% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 266581381 96.08% 96.11% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 59040 0.02% 96.13% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 53621 0.02% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 87 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.15% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 7156038 2.58% 98.73% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3533403 1.27% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 274695170 # Type of FU issued -system.cpu2.iq.rate 1.785140 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1955962 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.007120 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 704330322 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 285990572 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 273107568 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 269 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 242 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 106 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 276569466 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 132 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 697735 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 277466645 # Type of FU issued +system.cpu2.iq.rate 1.782256 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1946922 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.007017 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 711637991 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 289314219 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 275821613 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 281 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 236 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 279330355 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 137 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 727263 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1221587 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 6074 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 4844 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 639616 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1301667 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 5946 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 5330 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 686178 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 755983 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 21219 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 750303 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 28695 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 338239 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 70808815 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 1780684 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 277231511 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 42116 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6505190 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3599973 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 246009 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 189602 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 1292389 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 4844 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 181953 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 192646 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 374599 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 274123146 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 6692505 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 521898 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 359306 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 71000950 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 2910946 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 280131260 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 44826 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6854348 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3831116 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 254274 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 173954 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2389293 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 5330 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 193600 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 205490 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 399090 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 276846611 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 7005762 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 563321 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 0 # number of nop insts executed -system.cpu2.iew.exec_refs 9929733 # number of memory reference insts executed -system.cpu2.iew.exec_branches 27833627 # Number of branches executed -system.cpu2.iew.exec_stores 3237228 # Number of stores executed -system.cpu2.iew.exec_rate 1.781423 # Inst execution rate -system.cpu2.iew.wb_sent 273932637 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 273107674 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 213006118 # num instructions producing a value -system.cpu2.iew.wb_consumers 349346589 # num instructions consuming a value +system.cpu2.iew.exec_refs 10447548 # number of memory reference insts executed +system.cpu2.iew.exec_branches 28131020 # Number of branches executed +system.cpu2.iew.exec_stores 3441786 # Number of stores executed +system.cpu2.iew.exec_rate 1.778273 # Inst execution rate +system.cpu2.iew.wb_sent 276647008 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 275821721 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 215019240 # num instructions producing a value +system.cpu2.iew.wb_consumers 352722264 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.774824 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.609727 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.771690 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.609599 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 9088854 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357993 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 325291 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 151524726 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.769617 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.649272 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 9550045 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 363403 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 345846 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 153217834 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.765971 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.651639 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 94238602 62.19% 62.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4221946 2.79% 64.98% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1274040 0.84% 65.82% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 24556134 16.21% 82.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1017367 0.67% 82.70% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 681486 0.45% 83.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 477034 0.31% 83.46% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 23101810 15.25% 98.71% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1956307 1.29% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 95448328 62.30% 62.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4376826 2.86% 65.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1280143 0.84% 65.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 24626260 16.07% 82.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 968124 0.63% 82.69% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 723433 0.47% 83.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 420249 0.27% 83.44% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 23244515 15.17% 98.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 2129956 1.39% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 151524726 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 135843766 # Number of instructions committed -system.cpu2.commit.committedOps 268140656 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 153217834 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 137192415 # Number of instructions committed +system.cpu2.commit.committedOps 270578300 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8243960 # Number of memory references committed -system.cpu2.commit.loads 5283603 # Number of loads committed -system.cpu2.commit.membars 162116 # Number of memory barriers committed -system.cpu2.commit.branches 27422801 # Number of branches committed +system.cpu2.commit.refs 8697618 # Number of memory references committed +system.cpu2.commit.loads 5552680 # Number of loads committed +system.cpu2.commit.membars 162630 # Number of memory barriers committed +system.cpu2.commit.branches 27696347 # Number of branches committed system.cpu2.commit.fp_insts 48 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 244944567 # Number of committed integer instructions. -system.cpu2.commit.function_calls 433353 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 47848 0.02% 0.02% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 259747107 96.87% 96.89% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 53065 0.02% 96.91% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 48699 0.02% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.93% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5283564 1.97% 98.90% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 2960357 1.10% 100.00% # Class of committed instruction +system.cpu2.commit.int_insts 247309305 # Number of committed integer instructions. +system.cpu2.commit.function_calls 454335 # Number of function calls committed. +system.cpu2.commit.op_class_0::No_OpClass 48751 0.02% 0.02% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 261723532 96.73% 96.75% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 56607 0.02% 96.77% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 51834 0.02% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 16 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 96.79% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5552622 2.05% 98.84% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3144938 1.16% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 268140656 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1956307 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 270578300 # Class of committed instruction +system.cpu2.commit.bw_lim_events 2129956 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 426769551 # The number of ROB reads -system.cpu2.rob.rob_writes 555823820 # The number of ROB writes -system.cpu2.timesIdled 116899 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 995461 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 4917307163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 135843766 # Number of Instructions Simulated -system.cpu2.committedOps 268140656 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 1.132763 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 1.132763 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.882797 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.882797 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 364780652 # number of integer regfile reads -system.cpu2.int_regfile_writes 218921020 # number of integer regfile writes -system.cpu2.fp_regfile_reads 73130 # number of floating regfile reads -system.cpu2.fp_regfile_writes 73024 # number of floating regfile writes -system.cpu2.cc_regfile_reads 139296056 # number of cc regfile reads -system.cpu2.cc_regfile_writes 107100465 # number of cc regfile writes -system.cpu2.misc_regfile_reads 89036481 # number of misc regfile reads -system.cpu2.misc_regfile_writes 137201 # number of misc regfile writes -system.iobus.trans_dist::ReadReq 3554570 # Transaction distribution -system.iobus.trans_dist::ReadResp 3554570 # Transaction distribution +system.cpu2.rob.rob_reads 431186663 # The number of ROB reads +system.cpu2.rob.rob_writes 561693850 # The number of ROB writes +system.cpu2.timesIdled 124283 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1034756 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 4900728082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 137192415 # Number of Instructions Simulated +system.cpu2.committedOps 270578300 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 1.134777 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 1.134777 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.881230 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.881230 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 368834984 # number of integer regfile reads +system.cpu2.int_regfile_writes 221067360 # number of integer regfile writes +system.cpu2.fp_regfile_reads 73020 # number of floating regfile reads +system.cpu2.fp_regfile_writes 72968 # number of floating regfile writes +system.cpu2.cc_regfile_reads 140711927 # number of cc regfile reads +system.cpu2.cc_regfile_writes 108060819 # number of cc regfile writes +system.cpu2.misc_regfile_reads 90227595 # number of misc regfile reads +system.cpu2.misc_regfile_writes 143035 # number of misc regfile writes +system.iobus.trans_dist::ReadReq 3553360 # Transaction distribution +system.iobus.trans_dist::ReadResp 3553360 # Transaction distribution system.iobus.trans_dist::WriteReq 57725 # Transaction distribution system.iobus.trans_dist::WriteResp 11005 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1681 # Transaction distribution -system.iobus.trans_dist::MessageResp 1681 # Transaction distribution +system.iobus.trans_dist::MessageReq 1679 # Transaction distribution +system.iobus.trans_dist::MessageResp 1679 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11134 # Packet count per connected master and slave (bytes) @@ -1147,7 +1138,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7085054 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 7082618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1154 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1157,12 +1148,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 7129348 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95242 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3362 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 7227952 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 7126912 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95258 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3358 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 7225528 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6712 # Cumulative packet size per connected master and slave (bytes) @@ -1171,7 +1162,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3542527 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 3541309 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2308 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1181,19 +1172,19 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 3570873 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027752 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6724 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6724 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 6605349 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 2588568 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 3569655 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027816 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6716 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6716 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 6604187 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 2698688 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 27000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 21000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 4563000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 5333000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1201,70 +1192,68 @@ system.iobus.reqLayer5.occupancy 758000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 15000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 142528000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 141310000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 404000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 414000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 134000 # Layer occupancy (ticks) +system.iobus.reqLayer11.occupancy 78000 # Layer occupancy (ticks) system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10340000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10425000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 9000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 4000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 221126240 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 116029251 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1032000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 302697000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 300958000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 28304753 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 24266250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1088000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1136000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47566 # number of replacements -system.iocache.tags.tagsinuse 0.112009 # Cycle average of tags in use +system.iocache.tags.replacements 47574 # number of replacements +system.iocache.tags.tagsinuse 0.081409 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47582 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47590 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5000571390009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.112009 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.007001 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.007001 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5000597695009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.081409 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005088 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005088 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428589 # Number of tag accesses -system.iocache.tags.data_accesses 428589 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 901 # number of ReadReq misses -system.iocache.ReadReq_misses::total 901 # number of ReadReq misses +system.iocache.tags.tag_accesses 428661 # Number of tag accesses +system.iocache.tags.data_accesses 428661 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 909 # number of ReadReq misses +system.iocache.ReadReq_misses::total 909 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 901 # number of demand (read+write) misses -system.iocache.demand_misses::total 901 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 901 # number of overall misses -system.iocache.overall_misses::total 901 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132764027 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 132764027 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 6059046460 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6059046460 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 132764027 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 132764027 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 132764027 # number of overall miss cycles -system.iocache.overall_miss_latency::total 132764027 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 901 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 901 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 909 # number of demand (read+write) misses +system.iocache.demand_misses::total 909 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 909 # number of overall misses +system.iocache.overall_misses::total 909 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 125652013 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 125652013 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 3845868988 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 3845868988 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 125652013 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 125652013 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 125652013 # number of overall miss cycles +system.iocache.overall_miss_latency::total 125652013 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 909 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 901 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 901 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 901 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 901 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 909 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 909 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 909 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 909 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1273,325 +1262,311 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 147351.861265 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 129688.494435 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 129688.494435 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 147351.861265 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 147351.861265 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 147351.861265 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 34598 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 138231.037404 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 82317.401284 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 82317.401284 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 138231.037404 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 138231.037404 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 138231.037404 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 13512 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 4497 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2030 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.693573 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.656158 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 738 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 738 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 23008 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 23008 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 738 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 738 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 738 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 738 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 94361527 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 4862624466 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4862624466 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 94361527 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 94361527 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 94361527 # number of overall MSHR miss cycles -system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total 0.819090 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.492466 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.492466 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total 0.819090 # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819090 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total 0.819090 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 127861.147696 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 211344.943759 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 211344.943759 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 127861.147696 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 127861.147696 # average overall mshr miss latency +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 745 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 745 # number of ReadReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 21024 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 21024 # number of WriteInvalidateReq MSHR misses +system.iocache.demand_mshr_misses::pc.south_bridge.ide 745 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 745 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 745 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 745 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 86664503 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2752610998 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2752610998 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 86664503 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 86664503 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 86664503 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 0.819582 # mshr miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 0.450000 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_mshr_miss_rate::total 0.450000 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 0.819582 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 0.819582 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 0.819582 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 116328.191946 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 130927.083238 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 130927.083238 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 116328.191946 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 116328.191946 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 104970 # number of replacements -system.l2c.tags.tagsinuse 64826.298792 # Cycle average of tags in use -system.l2c.tags.total_refs 3700737 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 169148 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 21.878692 # Average number of references to valid blocks. +system.l2c.tags.replacements 105420 # number of replacements +system.l2c.tags.tagsinuse 64829.150073 # Cycle average of tags in use +system.l2c.tags.total_refs 3714265 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 169452 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 21.919275 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 51221.575879 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.131319 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 1714.525389 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 5051.845543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.003637 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 364.783966 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1988.075845 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.500719 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 853.175626 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 3622.680869 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.781579 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 51423.363344 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.134649 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 1822.192254 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5065.443853 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 236.253380 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1546.126379 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 11.729356 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 913.877634 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 3810.029226 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.784658 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000002 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.026162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.077085 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.005566 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.030336 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000145 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.013018 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.055278 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.989171 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 64178 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 278 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2747 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54646 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.979279 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 33928519 # Number of tag accesses -system.l2c.tags.data_accesses 33928519 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 20269 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 10932 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 306104 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 491683 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 12164 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6423 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 169856 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 227750 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 59393 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 13568 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 378835 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 595825 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2292802 # number of ReadReq hits +system.l2c.tags.occ_percent::cpu0.inst 0.027804 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.077293 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.003605 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023592 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000179 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.013945 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.058136 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.989214 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 64032 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 535 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 7219 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 53036 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.977051 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 34034094 # Number of tag accesses +system.l2c.tags.data_accesses 34034094 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 19379 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 10642 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 295114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 477769 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 12495 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 7386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 160391 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 220397 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 66650 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 14282 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 407368 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 616656 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2308529 # number of ReadReq hits system.l2c.WriteReq_hits::cpu0.itb.walker 2 # number of WriteReq hits system.l2c.WriteReq_hits::total 2 # number of WriteReq hits -system.l2c.Writeback_hits::writebacks 1548363 # number of Writeback hits -system.l2c.Writeback_hits::total 1548363 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 100 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 71 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 101 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 272 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 63359 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 39945 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 57961 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 161265 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 20269 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 10934 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 306104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 555042 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 12164 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6423 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 169856 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 267695 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 59393 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 13568 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 378835 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 653786 # number of demand (read+write) hits -system.l2c.demand_hits::total 2454069 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 20269 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 10934 # number of overall hits -system.l2c.overall_hits::cpu0.inst 306104 # number of overall hits -system.l2c.overall_hits::cpu0.data 555042 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 12164 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6423 # number of overall hits -system.l2c.overall_hits::cpu1.inst 169856 # number of overall hits -system.l2c.overall_hits::cpu1.data 267695 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 59393 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 13568 # number of overall hits -system.l2c.overall_hits::cpu2.inst 378835 # number of overall hits -system.l2c.overall_hits::cpu2.data 653786 # number of overall hits -system.l2c.overall_hits::total 2454069 # number of overall hits -system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6803 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 17544 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2617 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 5064 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 36 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 5767 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 10237 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48073 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 615 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 285 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 446 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 1346 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 65229 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 30166 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 34786 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 130181 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6803 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 82773 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2617 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 35230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 36 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 5767 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 45023 # number of demand (read+write) misses -system.l2c.demand_misses::total 178254 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6803 # number of overall misses -system.l2c.overall_misses::cpu0.data 82773 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2617 # number of overall misses -system.l2c.overall_misses::cpu1.data 35230 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 36 # number of overall misses -system.l2c.overall_misses::cpu2.inst 5767 # number of overall misses -system.l2c.overall_misses::cpu2.data 45023 # number of overall misses -system.l2c.overall_misses::total 178254 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 74500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 190653500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 384787000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2953999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 449712500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 795071749 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1823253248 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 3961367 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 5247781 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 9209148 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 2078566202 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 2496913123 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 4575479325 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 74500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 190653500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 2463353202 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 2953999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 449712500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 3291984872 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 6398732573 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 74500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 190653500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 2463353202 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 2953999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 449712500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 3291984872 # number of overall miss cycles -system.l2c.overall_miss_latency::total 6398732573 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 20269 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 10936 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 312907 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 509227 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 12164 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6424 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 172473 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 232814 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 59429 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 13568 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 384602 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 606062 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2340875 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_hits::writebacks 1546722 # number of Writeback hits +system.l2c.Writeback_hits::total 1546722 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 113 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 56 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 89 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 258 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 58538 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 36097 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 64817 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 159452 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 19379 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 10644 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 295114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 536307 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 12495 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 7386 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 160391 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256494 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 66650 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 14282 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 407368 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 681473 # number of demand (read+write) hits +system.l2c.demand_hits::total 2467983 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 19379 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 10644 # number of overall hits +system.l2c.overall_hits::cpu0.inst 295114 # number of overall hits +system.l2c.overall_hits::cpu0.data 536307 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 12495 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 7386 # number of overall hits +system.l2c.overall_hits::cpu1.inst 160391 # number of overall hits +system.l2c.overall_hits::cpu1.data 256494 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 66650 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 14282 # number of overall hits +system.l2c.overall_hits::cpu2.inst 407368 # number of overall hits +system.l2c.overall_hits::cpu2.data 681473 # number of overall hits +system.l2c.overall_hits::total 2467983 # number of overall hits +system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6915 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 16100 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2264 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3859 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 42 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 5904 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 13093 # number of ReadReq misses +system.l2c.ReadReq_misses::total 48182 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 632 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 257 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 496 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 1385 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 68358 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 26158 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 36472 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 130988 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6915 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 84458 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2264 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 30017 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 42 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 5904 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 49565 # number of demand (read+write) misses +system.l2c.demand_misses::total 179170 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6915 # number of overall misses +system.l2c.overall_misses::cpu0.data 84458 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2264 # number of overall misses +system.l2c.overall_misses::cpu1.data 30017 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 42 # number of overall misses +system.l2c.overall_misses::cpu2.inst 5904 # number of overall misses +system.l2c.overall_misses::cpu2.data 49565 # number of overall misses +system.l2c.overall_misses::total 179170 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.inst 185117250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 320324250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 3767000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 506409000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 1123352250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 2138969750 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 5734849 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 6109808 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11844657 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1967190465 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 2891355862 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 4858546327 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.inst 185117250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 2287514715 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 3767000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 506409000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 4014708112 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 6997516077 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.inst 185117250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 2287514715 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 3767000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 506409000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 4014708112 # number of overall miss cycles +system.l2c.overall_miss_latency::total 6997516077 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 19379 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 10647 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 302029 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 493869 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 12495 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7386 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 162655 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 224256 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 66692 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 14282 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 413272 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 629749 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2356711 # number of ReadReq accesses(hits+misses) system.l2c.WriteReq_accesses::cpu0.itb.walker 2 # number of WriteReq accesses(hits+misses) system.l2c.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1548363 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1548363 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 715 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 356 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 547 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 1618 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 128588 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 70111 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 92747 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 291446 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 20269 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 10938 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 312907 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 637815 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 12164 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6424 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 172473 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 302925 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 59429 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 13568 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 384602 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 698809 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2632323 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 20269 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 10938 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 312907 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 637815 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 12164 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6424 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 172473 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 302925 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 59429 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 13568 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 384602 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 698809 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2632323 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000366 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.021741 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.034452 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000156 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.015173 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021751 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000606 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.014995 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.016891 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.020536 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.860140 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800562 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.815356 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.831891 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.507271 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.430261 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.375063 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.446673 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000366 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.021741 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.129776 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000156 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.015173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.116299 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000606 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.014995 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.064428 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.067717 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000366 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.021741 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.129776 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000156 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.015173 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.116299 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000606 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.014995 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.064428 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.067717 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 74500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72851.929690 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75984.794629 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 82055.527778 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 77980.319057 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 77666.479340 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 37926.762382 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 13899.533333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 11766.325112 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 6841.863299 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 68904.269774 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 71779.253809 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 35147.059287 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72851.929690 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 69922.032416 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 82055.527778 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 77980.319057 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 73117.848033 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 35896.712405 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 74500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72851.929690 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 69922.032416 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 82055.527778 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 77980.319057 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 73117.848033 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 35896.712405 # average overall miss latency +system.l2c.Writeback_accesses::writebacks 1546722 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1546722 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 745 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 313 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 585 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 1643 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 126896 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 62255 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 101289 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 290440 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 19379 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 10649 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 302029 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 620765 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 12495 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7386 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 162655 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 286511 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 66692 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 14282 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 413272 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 731038 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2647153 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 19379 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 10649 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 302029 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 620765 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 12495 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7386 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 162655 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 286511 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 66692 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 14282 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 413272 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 731038 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2647153 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000470 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.022895 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.032600 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.013919 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017208 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.014286 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.020791 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.020445 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.848322 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.821086 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.847863 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.842970 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.538693 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.420175 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.360079 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.450998 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000470 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.022895 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.136055 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.013919 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.104767 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.014286 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.067801 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.067684 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000470 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.022895 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.136055 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.013919 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.104767 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000630 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.014286 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.067801 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.067684 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81765.569788 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 83007.061415 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 85773.882114 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 85797.926373 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 44393.544270 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 22314.587549 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 12318.161290 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 8552.098917 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75204.161824 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79276.043595 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 37091.537599 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81765.569788 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 76207.306360 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 85773.882114 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 80998.852255 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 39055.177078 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81765.569788 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 76207.306360 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 89690.476190 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 85773.882114 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 80998.852255 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 39055.177078 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1600,131 +1575,113 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 96725 # number of writebacks -system.l2c.writebacks::total 96725 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2617 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 5064 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 36 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 5767 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 10236 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 23721 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 285 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 446 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 731 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 30166 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 34786 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 64952 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2617 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 35230 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 36 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 5767 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 45022 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 88673 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2617 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 35230 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 36 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 5767 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 45022 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 88673 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 157432500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 321524500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2508499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 377524500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 667618251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1526670750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3450773 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 4577444 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 8028217 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1690819298 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2050981877 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 3741801175 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 157432500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 2012343798 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2508499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 377524500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 2718600128 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 5268471925 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 157432500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 2012343798 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2508499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 377524500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 2718600128 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 5268471925 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27931457000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30246385500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 58177842500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 534826000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 653150000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1187976000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28466283000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30899535500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 59365818500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000156 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.015173 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.021751 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000606 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014995 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.016889 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.010133 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.800562 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.815356 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.451792 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.430261 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.375063 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.222861 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000156 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.015173 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.116299 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000606 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014995 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.064427 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.033686 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000156 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.015173 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.116299 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000606 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014995 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.064427 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.033686 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60157.623233 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63492.199842 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 65462.892318 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65222.572392 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 64359.459972 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 12107.975439 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10263.327354 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10982.512996 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 56050.497182 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 58959.980366 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 57608.713742 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60157.623233 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57120.175930 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 65462.892318 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 60383.815201 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59414.612396 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60157.623233 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57120.175930 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 69680.527778 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 65462.892318 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 60383.815201 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59414.612396 # average overall mshr miss latency +system.l2c.writebacks::writebacks 96719 # number of writebacks +system.l2c.writebacks::total 96719 # number of writebacks +system.l2c.ReadReq_mshr_misses::cpu1.inst 2264 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 3859 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 42 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 5904 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 13093 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25162 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 257 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 496 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 753 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 26158 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 36472 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 62630 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2264 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 30017 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 42 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 5904 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 49565 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 87792 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2264 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 30017 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 42 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 5904 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 49565 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 87792 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 156732750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 272024750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 432457000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 959731250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1824184750 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5165744 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 8859994 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14025738 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 1640131535 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2435332138 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4075463673 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 156732750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1912156285 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 432457000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 3395063388 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 5899648423 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 156732750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1912156285 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 3239000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 432457000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 3395063388 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 5899648423 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 27747826000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 30174191500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 57922017500 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 492354000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 747099000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1239453000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 28240180000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 30921290500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59161470500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017208 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.020791 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.010677 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.821086 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.847863 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.458308 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420175 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.360079 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.215638 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.033165 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.013919 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.104767 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000630 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.067801 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.033165 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70490.995076 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 73301.096005 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 72497.605516 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20100.171206 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17862.891129 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 18626.478088 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62700.953246 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66772.651294 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 65072.068865 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69228.246466 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63702.444781 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 77119.047619 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73248.136856 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68497.193342 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 67200.296417 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1735,66 +1692,66 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 5122083 # Transaction distribution -system.membus.trans_dist::ReadResp 5122081 # Transaction distribution -system.membus.trans_dist::WriteReq 13936 # Transaction distribution -system.membus.trans_dist::WriteResp 13936 # Transaction distribution -system.membus.trans_dist::Writeback 143392 # Transaction distribution +system.membus.trans_dist::ReadReq 5119167 # Transaction distribution +system.membus.trans_dist::ReadResp 5119165 # Transaction distribution +system.membus.trans_dist::WriteReq 13931 # Transaction distribution +system.membus.trans_dist::WriteResp 13931 # Transaction distribution +system.membus.trans_dist::Writeback 143386 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 1613 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1613 # Transaction distribution -system.membus.trans_dist::ReadExReq 129914 # Transaction distribution -system.membus.trans_dist::ReadExResp 129914 # Transaction distribution -system.membus.trans_dist::MessageReq 1681 # Transaction distribution -system.membus.trans_dist::MessageResp 1681 # Transaction distribution +system.membus.trans_dist::UpgradeReq 1652 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution +system.membus.trans_dist::ReadExReq 130721 # Transaction distribution +system.membus.trans_dist::ReadExResp 130721 # Transaction distribution +system.membus.trans_dist::MessageReq 1679 # Transaction distribution +system.membus.trans_dist::MessageResp 1679 # Transaction distribution system.membus.trans_dist::BadAddressError 2 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3362 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7129348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3044744 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 455572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::system.cpu0.interrupts.int_slave 3358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3358 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 7126912 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.cpu0.interrupts.pio 3041102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 457338 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.membus.badaddr_responder.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 10629668 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141614 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141614 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10774644 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6724 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3570873 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6089485 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17560128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 27220486 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 6015552 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 33242762 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 642 # Total snoops (count) -system.membus.snoop_fanout::samples 370612 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::total 10625356 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141623 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10770337 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu0.interrupts.int_slave 6716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6716 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 3569655 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.cpu0.interrupts.pio 6082201 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17609408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 27261264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6015616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 6015616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 33283596 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 789 # Total snoops (count) +system.membus.snoop_fanout::samples 371599 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 370612 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 371599 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 370612 # Request fanout histogram -system.membus.reqLayer0.occupancy 162893500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 371599 # Request fanout histogram +system.membus.reqLayer0.occupancy 233199000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 314579500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 303775500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 2176000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 2272000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1055146498 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 587213160 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 2500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1088000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1136000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1708813357 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1313776839 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer4.occupancy 29666247 # Layer occupancy (ticks) +system.membus.respLayer4.occupancy 24877750 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). @@ -1808,52 +1765,52 @@ system.pc.south_bridge.ide.disks1.dma_read_txs 0 system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes. system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes. system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 7441673 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 7441143 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 13938 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 13938 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1548363 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 23008 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1618 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1618 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 291446 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 291446 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 7456393 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 7455858 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 13933 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 13933 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1546722 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 21038 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1643 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1643 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 290440 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 290440 # Transaction distribution system.toL2Bus.trans_dist::BadAddressError 2 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1740014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 15004999 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 72834 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 207249 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 17025096 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 55679680 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213700038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 269360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 773664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 270422742 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 67345 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4256875 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.011187 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.105175 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1755962 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14994862 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 74580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.port::system.l2c.cpu_side 223072 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 17048476 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 56190016 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 213507600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 279632 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823928 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 270801176 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 69805 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 4272022 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011152 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.105014 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 4209254 98.88% 98.88% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 47621 1.12% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 4224379 98.88% 98.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 47643 1.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4256875 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 5306709352 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 945000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 4272022 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2506180983 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 318000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2510055059 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 865936683 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 4923615960 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 25531897 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1938409360 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 26348986 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 85751327 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 96467647 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed diff --git a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt index 4f1cfb81e..2c11d0b34 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061494 # Number of seconds simulated -sim_ticks 61493732000 # Number of ticks simulated -final_tick 61493732000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.061593 # Number of seconds simulated +sim_ticks 61592600500 # Number of ticks simulated +final_tick 61592600500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 144123 # Simulator instruction rate (inst/s) -host_op_rate 144840 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 97818525 # Simulator tick rate (ticks/s) -host_mem_usage 433504 # Number of bytes of host memory used -host_seconds 628.65 # Real time elapsed on the host +host_inst_rate 271325 # Simulator instruction rate (inst/s) +host_op_rate 272676 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 184448880 # Simulator tick rate (ticks/s) +host_mem_usage 445184 # Number of bytes of host memory used +host_seconds 333.93 # Real time elapsed on the host sim_insts 90602849 # Number of instructions simulated sim_ops 91054080 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 49600 # Nu system.physmem.num_reads::cpu.inst 775 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 14800 # Number of read requests responded to by this memory system.physmem.num_reads::total 15575 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 806586 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 15403196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 16209782 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 806586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 806586 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 806586 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 15403196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 16209782 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 805292 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 15378471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 16183762 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 805292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 805292 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 805292 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 15378471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 16183762 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15575 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 15575 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61493643500 # Total gap between requests +system.physmem.totGap 61592506000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 15453 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 112 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 15454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,29 +186,29 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1534 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 648.594524 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 444.741065 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 399.329877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 241 15.71% 15.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 178 11.60% 27.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 90 5.87% 33.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 4.11% 37.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 79 5.15% 42.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 102 6.65% 49.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 37 2.41% 51.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 39 2.54% 54.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 705 45.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1534 # Bytes accessed per row activation -system.physmem.totQLat 73247750 # Total ticks spent queuing -system.physmem.totMemAccLat 365279000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1549 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 642.644287 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 437.986910 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 400.933627 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 248 16.01% 16.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 186 12.01% 28.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 90 5.81% 33.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 71 4.58% 38.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 77 4.97% 43.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 93 6.00% 49.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 43 2.78% 52.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 36 2.32% 54.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 705 45.51% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1549 # Bytes accessed per row activation +system.physmem.totQLat 77242000 # Total ticks spent queuing +system.physmem.totMemAccLat 369273250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 77875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4702.91 # Average queueing delay per DRAM burst +system.physmem.avgQLat 4959.36 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23452.91 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 16.21 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 23709.36 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 16.18 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 16.21 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 16.18 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.13 # Data bus utilization in percentage @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.13 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 14031 # Number of row buffer hits during reads +system.physmem.readRowHits 14018 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 90.00 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 3948227.51 # Average gap between requests -system.physmem.pageHitRate 90.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6320160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3448500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 63663600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 3954575.02 # Average gap between requests +system.physmem.pageHitRate 90.00 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6373080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3477375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 63718200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2490640650 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34708185000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41288356230 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.483541 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57732029500 # Time in different power states -system.physmem_0.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_0.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2539008855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34726497750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41361784860 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.572046 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57760380750 # Time in different power states +system.physmem_0.memoryStateTime::REF 2056600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1704707500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1772530500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5261760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2871000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 57462600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5329800 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2908125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 57478200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4016098320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2514095865 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34687610250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41283399795 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.402933 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57698939250 # Time in different power states -system.physmem_1.memoryStateTime::REF 2053220000 # Time in different power states +system.physmem_1.refreshEnergy 4022709600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2571546735 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34697955750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41357928210 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.509428 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57713961000 # Time in different power states +system.physmem_1.memoryStateTime::REF 2056600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1738589750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1819631500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 20789429 # Number of BP lookups -system.cpu.branchPred.condPredicted 17091399 # Number of conditional branches predicted +system.cpu.branchPred.lookups 20789446 # Number of BP lookups +system.cpu.branchPred.condPredicted 17091418 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 765966 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8973618 # Number of BTB lookups -system.cpu.branchPred.BTBHits 8867020 # Number of BTB hits +system.cpu.branchPred.BTBLookups 8973614 # Number of BTB lookups +system.cpu.branchPred.BTBHits 8867024 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.812096 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 62716 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 98.812184 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 62715 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,89 +377,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 122987464 # number of cpu cycles simulated +system.cpu.numCycles 123185201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90602849 # Number of instructions committed system.cpu.committedOps 91054080 # Number of ops (including micro ops) committed -system.cpu.discardedOps 2068195 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 2068247 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.357435 # CPI: cycles per instruction -system.cpu.ipc 0.736684 # IPC: instructions per cycle -system.cpu.tickCycles 109826570 # Number of cycles that the object actually ticked -system.cpu.idleCycles 13160894 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.359617 # CPI: cycles per instruction +system.cpu.ipc 0.735501 # IPC: instructions per cycle +system.cpu.tickCycles 109827605 # Number of cycles that the object actually ticked +system.cpu.idleCycles 13357596 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 946107 # number of replacements -system.cpu.dcache.tags.tagsinuse 3616.604238 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26267660 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3616.143974 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26267423 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 950203 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 27.644261 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 20617906250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3616.604238 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.882960 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.882960 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 27.644012 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 20661192250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3616.143974 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.882848 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.882848 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 262 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2249 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1585 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2247 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1597 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 55463255 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 55463255 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21598813 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21598813 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4661073 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4661073 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 55463259 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 55463259 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21598839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21598839 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4660810 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4660810 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 26259886 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26259886 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26259886 # number of overall hits -system.cpu.dcache.overall_hits::total 26259886 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 914958 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 914958 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73908 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73908 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 988866 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 988866 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 988866 # number of overall misses -system.cpu.dcache.overall_misses::total 988866 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11910296994 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11910296994 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2345727500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2345727500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 14256024494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 14256024494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 14256024494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 14256024494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22513771 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22513771 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 26259649 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26259649 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26259649 # number of overall hits +system.cpu.dcache.overall_hits::total 26259649 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 914934 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 914934 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 74171 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 74171 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 989105 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 989105 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 989105 # number of overall misses +system.cpu.dcache.overall_misses::total 989105 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11918412494 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11918412494 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2568231500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2568231500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14486643994 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14486643994 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14486643994 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14486643994 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22513773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22513773 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 27248752 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 27248752 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 27248752 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 27248752 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040640 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015609 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015609 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.036290 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.036290 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.036290 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.036290 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13017.315542 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13017.315542 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31738.478920 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31738.478920 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14416.538231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14416.538231 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14416.538231 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 27248754 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 27248754 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 27248754 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 27248754 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040639 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040639 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015664 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015664 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.036299 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.036299 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.036299 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.036299 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13026.527043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13026.527043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34625.817368 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 34625.817368 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 14646.214501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14646.214501 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14646.214501 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -470,14 +470,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 943286 # number of writebacks system.cpu.dcache.writebacks::total 943286 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11523 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 11523 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27140 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 27140 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38663 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38663 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38663 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38663 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 11499 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 11499 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 27403 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 27403 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38902 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38902 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38902 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38902 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 903435 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 903435 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46768 # number of WriteReq MSHR misses @@ -486,14 +486,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 950203 system.cpu.dcache.demand_mshr_misses::total 950203 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 950203 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 950203 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9958855506 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9958855506 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1333449750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1333449750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11292305256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11292305256 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11292305256 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11292305256 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10413322256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10413322256 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1464464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1464464500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11877786756 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11877786756 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11877786756 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11877786756 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040128 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009877 # mshr miss rate for WriteReq accesses @@ -502,67 +502,67 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034871 system.cpu.dcache.demand_mshr_miss_rate::total 0.034871 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034871 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034871 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11023.322659 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11023.322659 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28512.011418 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28512.011418 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11884.097668 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11884.097668 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11526.365766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11526.365766 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31313.387359 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31313.387359 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12500.262319 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12500.262319 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 5 # number of replacements -system.cpu.icache.tags.tagsinuse 690.411182 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27857009 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 690.370829 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27857028 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 803 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 34691.169365 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 34691.193026 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 690.411182 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.337115 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.337115 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 690.370829 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.337095 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.337095 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 741 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.389648 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55716427 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55716427 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27857009 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27857009 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27857009 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27857009 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27857009 # number of overall hits -system.cpu.icache.overall_hits::total 27857009 # number of overall hits +system.cpu.icache.tags.tag_accesses 55716465 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55716465 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27857028 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27857028 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27857028 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27857028 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27857028 # number of overall hits +system.cpu.icache.overall_hits::total 27857028 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 803 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 803 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 803 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 803 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.icache.overall_misses::total 803 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55346748 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55346748 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55346748 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55346748 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55346748 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55346748 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27857812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27857812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27857812 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27857812 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27857812 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27857812 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 61138997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 61138997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 61138997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 61138997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 61138997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 61138997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27857831 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27857831 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27857831 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27857831 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27857831 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27857831 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000029 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000029 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000029 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000029 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000029 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68924.966376 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68924.966376 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68924.966376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68924.966376 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68924.966376 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76138.227895 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76138.227895 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76138.227895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76138.227895 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76138.227895 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -577,38 +577,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 803 system.cpu.icache.demand_mshr_misses::total 803 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 803 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 53408252 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 53408252 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 53408252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 53408252 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 53408252 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 53408252 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 59598503 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 59598503 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 59598503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 59598503 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 59598503 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 59598503 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000029 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000029 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000029 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000029 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66510.899128 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66510.899128 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66510.899128 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66510.899128 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74219.804483 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74219.804483 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74219.804483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74219.804483 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 10247.121902 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1831334 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 10238.643668 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1831333 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15558 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 117.710117 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 117.710053 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 9356.236608 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.415381 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 215.469913 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.285530 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020612 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.006576 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.312717 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 9347.860585 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 675.375683 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 215.407400 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.285274 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020611 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.006574 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.312459 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15558 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id @@ -618,41 +618,41 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13878 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.474792 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15216662 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15216662 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 26 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 25 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 903173 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 903199 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 903198 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 943286 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 943286 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32224 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32224 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 26 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 25 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 935397 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 935423 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 26 # number of overall hits +system.cpu.l2cache.demand_hits::total 935422 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 25 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 935397 # number of overall hits -system.cpu.l2cache.overall_hits::total 935423 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 777 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 935422 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 778 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 262 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1039 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1040 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14544 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14544 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 777 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 778 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 14806 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 15583 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 777 # number of overall misses +system.cpu.l2cache.demand_misses::total 15584 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 778 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14806 # number of overall misses -system.cpu.l2cache.overall_misses::total 15583 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 52344250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19360000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 71704250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 958084250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 958084250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 52344250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 977444250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1029788500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 52344250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 977444250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1029788500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::total 15584 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 58533000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22267750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 80800750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1073909000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1073909000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 58533000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1096176750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1154709750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 58533000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1096176750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1154709750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 803 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 903435 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 904238 # number of ReadReq accesses(hits+misses) @@ -666,28 +666,28 @@ system.cpu.l2cache.demand_accesses::total 951006 # n system.cpu.l2cache.overall_accesses::cpu.inst 803 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 950203 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 951006 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.967621 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.968867 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000290 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001149 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001150 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.310982 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.310982 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.967621 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.968867 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.015582 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.016386 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.967621 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.016387 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.968867 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015582 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.016386 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67367.117117 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73893.129771 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69012.752647 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65874.879675 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65874.879675 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66084.098056 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67367.117117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66016.766851 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66084.098056 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.016387 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75235.218509 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84991.412214 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77693.028846 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73838.627613 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73838.627613 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74095.851514 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75235.218509 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74035.982034 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74095.851514 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -696,15 +696,15 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 256 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 1031 # number of ReadReq MSHR misses @@ -716,17 +716,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15575 system.cpu.l2cache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14800 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15575 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42469000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15862000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58331000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 774515250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 774515250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42469000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 790377250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 832846250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42469000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 790377250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 832846250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 48659000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18669250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 67328250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 892098500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 892098500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 48659000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 910767750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 959426750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 48659000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 910767750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 959426750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000283 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001140 # mshr miss rate for ReadReq accesses @@ -738,17 +738,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016377 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965131 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015576 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016377 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54798.709677 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61960.937500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56577.109602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 53253.248762 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 53253.248762 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54798.709677 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53403.868243 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53473.274478 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62785.806452 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72926.757812 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65303.831232 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61337.905666 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61337.905666 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62785.806452 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61538.361486 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61600.433387 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 904238 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 904238 # Transaction distribution @@ -763,25 +763,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 121234688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1894292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1894292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1894292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1894292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1890432000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1370748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1372497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1428672244 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1428682244 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) system.membus.trans_dist::ReadReq 1031 # Transaction distribution system.membus.trans_dist::ReadResp 1031 # Transaction distribution @@ -802,9 +800,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15575 # Request fanout histogram -system.membus.reqLayer0.occupancy 17956500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 21632500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 146201750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 82148250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt index ea993d96c..8fe6f61b1 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt @@ -1,117 +1,117 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057719 # Number of seconds simulated -sim_ticks 57719377000 # Number of ticks simulated -final_tick 57719377000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058203 # Number of seconds simulated +sim_ticks 58202727500 # Number of ticks simulated +final_tick 58202727500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 125223 # Simulator instruction rate (inst/s) -host_op_rate 125847 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 79786059 # Simulator tick rate (ticks/s) -host_mem_usage 443544 # Number of bytes of host memory used -host_seconds 723.43 # Real time elapsed on the host +host_inst_rate 129726 # Simulator instruction rate (inst/s) +host_op_rate 130372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 83346935 # Simulator tick rate (ticks/s) +host_mem_usage 443628 # Number of bytes of host memory used +host_seconds 698.32 # Real time elapsed on the host sim_insts 90589798 # Number of instructions simulated sim_ops 91041029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 44416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 43648 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 927744 # Number of bytes read from this memory -system.physmem.bytes_read::total 1015808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 44416 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 19776 # Number of bytes written to this memory -system.physmem.bytes_written::total 19776 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 694 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 682 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 14496 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15872 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 309 # Number of write requests responded to by this memory -system.physmem.num_writes::total 309 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 769516 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 756211 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 16073354 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 17599081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 769516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 769516 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 342623 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 342623 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 342623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 769516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 756211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 16073354 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17941704 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15872 # Number of read requests accepted -system.physmem.writeReqs 309 # Number of write requests accepted -system.physmem.readBursts 15872 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 309 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1006016 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9792 # Total number of bytes read from write queue -system.physmem.bytesWritten 18432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1015808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 19776 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 153 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 44480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 45376 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 930112 # Number of bytes read from this memory +system.physmem.bytes_read::total 1019968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 44480 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 22912 # Number of bytes written to this memory +system.physmem.bytes_written::total 22912 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 695 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 709 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 14533 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15937 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 358 # Number of write requests responded to by this memory +system.physmem.num_writes::total 358 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 764225 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 779620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 15980557 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 17524402 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 764225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 764225 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 393659 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 393659 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 393659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 764225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 779620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 15980557 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17918061 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15937 # Number of read requests accepted +system.physmem.writeReqs 358 # Number of write requests accepted +system.physmem.readBursts 15937 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 358 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1010432 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue +system.physmem.bytesWritten 21184 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1019968 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 22912 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 2 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 999 # Per bank write bursts +system.physmem.perBankRdBursts::0 1009 # Per bank write bursts system.physmem.perBankRdBursts::1 876 # Per bank write bursts -system.physmem.perBankRdBursts::2 956 # Per bank write bursts -system.physmem.perBankRdBursts::3 1023 # Per bank write bursts +system.physmem.perBankRdBursts::2 958 # Per bank write bursts +system.physmem.perBankRdBursts::3 1024 # Per bank write bursts system.physmem.perBankRdBursts::4 1064 # Per bank write bursts -system.physmem.perBankRdBursts::5 1127 # Per bank write bursts -system.physmem.perBankRdBursts::6 1115 # Per bank write bursts -system.physmem.perBankRdBursts::7 1101 # Per bank write bursts -system.physmem.perBankRdBursts::8 1033 # Per bank write bursts +system.physmem.perBankRdBursts::5 1132 # Per bank write bursts +system.physmem.perBankRdBursts::6 1124 # Per bank write bursts +system.physmem.perBankRdBursts::7 1103 # Per bank write bursts +system.physmem.perBankRdBursts::8 1046 # Per bank write bursts system.physmem.perBankRdBursts::9 962 # Per bank write bursts system.physmem.perBankRdBursts::10 937 # Per bank write bursts system.physmem.perBankRdBursts::11 899 # Per bank write bursts -system.physmem.perBankRdBursts::12 910 # Per bank write bursts -system.physmem.perBankRdBursts::13 886 # Per bank write bursts -system.physmem.perBankRdBursts::14 919 # Per bank write bursts -system.physmem.perBankRdBursts::15 912 # Per bank write bursts -system.physmem.perBankWrBursts::0 23 # Per bank write bursts +system.physmem.perBankRdBursts::12 909 # Per bank write bursts +system.physmem.perBankRdBursts::13 889 # Per bank write bursts +system.physmem.perBankRdBursts::14 926 # Per bank write bursts +system.physmem.perBankRdBursts::15 930 # Per bank write bursts +system.physmem.perBankWrBursts::0 30 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 4 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 9 # Per bank write bursts +system.physmem.perBankWrBursts::2 8 # Per bank write bursts +system.physmem.perBankWrBursts::3 1 # Per bank write bursts +system.physmem.perBankWrBursts::4 10 # Per bank write bursts system.physmem.perBankWrBursts::5 29 # Per bank write bursts -system.physmem.perBankWrBursts::6 62 # Per bank write bursts -system.physmem.perBankWrBursts::7 30 # Per bank write bursts -system.physmem.perBankWrBursts::8 15 # Per bank write bursts +system.physmem.perBankWrBursts::6 69 # Per bank write bursts +system.physmem.perBankWrBursts::7 31 # Per bank write bursts +system.physmem.perBankWrBursts::8 36 # Per bank write bursts system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 10 # Per bank write bursts -system.physmem.perBankWrBursts::11 1 # Per bank write bursts -system.physmem.perBankWrBursts::12 9 # Per bank write bursts +system.physmem.perBankWrBursts::10 7 # Per bank write bursts +system.physmem.perBankWrBursts::11 0 # Per bank write bursts +system.physmem.perBankWrBursts::12 7 # Per bank write bursts system.physmem.perBankWrBursts::13 27 # Per bank write bursts -system.physmem.perBankWrBursts::14 48 # Per bank write bursts -system.physmem.perBankWrBursts::15 21 # Per bank write bursts +system.physmem.perBankWrBursts::14 45 # Per bank write bursts +system.physmem.perBankWrBursts::15 31 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57719226000 # Total gap between requests +system.physmem.totGap 58202569500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 15872 # Read request sizes (log2) +system.physmem.readPktSize::6 15937 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 309 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 10641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 489 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 352 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 358 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 10945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 522 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 349 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 297 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 305 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 289 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 62 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -148,24 +148,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 18 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -197,95 +197,94 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1739 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 588.402530 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 354.168959 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 429.121053 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 443 25.47% 25.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 194 11.16% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 91 5.23% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 64 3.68% 45.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 57 3.28% 48.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 2.47% 51.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 46 2.65% 53.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 54 3.11% 57.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 747 42.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1739 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 16 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 981 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 40.634826 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 3762.941438 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 15 93.75% 93.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14848-15359 1 6.25% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 16 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 16 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.975187 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.966092 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 12.50% 12.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 11 68.75% 81.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 2 12.50% 93.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 1 6.25% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 16 # Writes before turning the bus around for reads -system.physmem.totQLat 179464908 # Total ticks spent queuing -system.physmem.totMemAccLat 474196158 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 78595000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11417.07 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1871 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 551.268840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 315.885566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 433.770323 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 552 29.50% 29.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 218 11.65% 41.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 92 4.92% 46.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 57 3.05% 49.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 63 3.37% 52.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 44 2.35% 54.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 55 2.94% 57.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 42 2.24% 60.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 748 39.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1871 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 18 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 874.777778 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 39.760140 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3541.219224 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17 94.44% 94.44% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14848-15359 1 5.56% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 18 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.388889 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.356746 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.195033 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 15 83.33% 83.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 2 11.11% 94.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 1 5.56% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 18 # Writes before turning the bus around for reads +system.physmem.totQLat 172783990 # Total ticks spent queuing +system.physmem.totMemAccLat 468808990 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 78940000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10944.01 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30167.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 17.43 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 17.60 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29694.01 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 17.36 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 17.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.14 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.97 # Average write queue length when enqueuing -system.physmem.readRowHits 14166 # Number of row buffer hits during reads -system.physmem.writeRowHits 92 # Number of row buffer hits during writes -system.physmem.readRowHitRate 90.12 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 29.97 # Row buffer hit rate for writes -system.physmem.avgGap 3567098.82 # Average gap between requests -system.physmem.pageHitRate 88.97 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7053480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3848625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 64162800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 959040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2338304445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32576022750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 38759797860 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.607894 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 54183699610 # Time in different power states -system.physmem_0.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem.avgRdQLen 1.11 # Average read queue length when enqueuing +system.physmem.avgWrQLen 16.15 # Average write queue length when enqueuing +system.physmem.readRowHits 14154 # Number of row buffer hits during reads +system.physmem.writeRowHits 93 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.65 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 26.20 # Row buffer hit rate for writes +system.physmem.avgGap 3571805.43 # Average gap between requests +system.physmem.pageHitRate 88.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7658280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 4178625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 64638600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 1153440 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2451888630 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32770707750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 39101711325 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.822097 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 54506616189 # Time in different power states +system.physmem_0.memoryStateTime::REF 1943500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1601139140 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1752376311 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6002640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3275250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 58133400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 803520 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3769446720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2319744105 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32592295500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 38749701135 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.433104 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 54217128450 # Time in different power states -system.physmem_1.memoryStateTime::REF 1927120000 # Time in different power states +system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 58484400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 991440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3801486000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2431326735 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32788744500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 39091058805 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.639072 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 54537138662 # Time in different power states +system.physmem_1.memoryStateTime::REF 1943500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1573598050 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1721853838 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 28271166 # Number of BP lookups -system.cpu.branchPred.condPredicted 23289258 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 837919 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 11857915 # Number of BTB lookups -system.cpu.branchPred.BTBHits 11789421 # Number of BTB hits +system.cpu.branchPred.lookups 28259323 # Number of BP lookups +system.cpu.branchPred.condPredicted 23281308 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 837964 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 11850778 # Number of BTB lookups +system.cpu.branchPred.BTBHits 11785443 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.422377 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 75707 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 88 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.448686 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 75758 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 89 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -404,83 +403,83 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 115438755 # number of cpu cycles simulated +system.cpu.numCycles 116405456 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 750677 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 135029605 # Number of instructions fetch has processed -system.cpu.fetch.Branches 28271166 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 11865128 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 113801477 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1679415 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 715 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 32315558 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 576 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 115393730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.175455 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.320715 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 749294 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 134993998 # Number of instructions fetch has processed +system.cpu.fetch.Branches 28259323 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 11861201 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 114761716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1679249 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1000 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 840 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 32304088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 579 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 116352474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.165469 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.319047 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 57838402 50.12% 50.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 13925125 12.07% 62.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9175651 7.95% 70.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 34454552 29.86% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58780581 50.52% 50.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 13944559 11.98% 62.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9221403 7.93% 70.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 34405931 29.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 115393730 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.244902 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.169708 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8870766 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63114849 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 33033969 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9546674 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 827472 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 4101024 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12335 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 114392732 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1987220 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 827472 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15224664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 49207626 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 108919 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 35472493 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 14552556 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 110856042 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 1413744 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 11047079 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1056491 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1457150 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 456315 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 129915292 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 483076638 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 119437218 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 420 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 116352474 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.242766 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.159688 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8844184 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 64087377 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 33032699 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9560836 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 827378 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 4101289 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12349 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 114434840 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1995518 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 827378 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15306554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 49837632 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 110028 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 35408205 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 14862677 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 110902804 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 1415247 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 11133046 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1143083 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1515709 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 570063 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 129962368 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 483290389 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 119478713 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 424 # Number of floating rename lookups system.cpu.rename.CommittedMaps 107312919 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 22602373 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 22649449 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 4363 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 4358 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 21217869 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26815015 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 5348915 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 559856 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 297304 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 109685726 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 8247 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 101429576 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1059441 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18455382 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 41507392 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 29 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 115393730 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.878987 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.999963 # Number of insts issued each cycle +system.cpu.rename.skidInsts 21572068 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26814283 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 5349560 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 615072 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 351208 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 109694902 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 8246 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 101389982 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1073881 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18465721 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 41703174 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 116352474 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.871404 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.988585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 54518642 47.25% 47.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 30124755 26.11% 73.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22142664 19.19% 92.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 7411500 6.42% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1195852 1.04% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 54656656 46.98% 46.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 31447896 27.03% 74.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 21997479 18.91% 92.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 7054961 6.06% 98.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1195165 1.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 317 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -488,149 +487,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 115393730 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 116352474 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9750384 48.86% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 50 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 13 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.86% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9494227 47.58% 96.44% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 710033 3.56% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9796147 48.71% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 50 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 12 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 48.71% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9605529 47.77% 96.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 708223 3.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 71988081 70.97% 70.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 10708 0.01% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 55 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 125 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24381590 24.04% 95.02% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 5049013 4.98% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 71985557 71.00% 71.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 10710 0.01% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 123 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24344215 24.01% 95.02% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 5049315 4.98% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 101429576 # Type of FU issued -system.cpu.iq.rate 0.878644 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19954707 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.196735 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 339266571 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 128150140 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 99658235 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 101389982 # Type of FU issued +system.cpu.iq.rate 0.871007 # Inst issue rate +system.cpu.iq.fu_busy_cnt 20109961 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.198343 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 340315821 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 128169527 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 99626078 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 459 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 607 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 119 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 121384044 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_writes 609 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 115 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 121499704 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 239 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 285219 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 282708 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4339104 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1483 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 1422 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 604071 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4338372 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1511 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 1302 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 604716 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 7565 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 130466 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 7561 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 130367 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 827472 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 8003638 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 730506 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 109706640 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 827378 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 8117043 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 661508 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 109715814 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26815015 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 5348915 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 4359 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 187146 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 360894 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 1422 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 436340 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412872 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 849212 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 100146798 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23824665 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1282778 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26814283 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 5349560 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 4358 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 178487 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 319637 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 1302 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 436579 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 412967 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 849546 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 100128293 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23807365 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1261689 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 12667 # number of nop insts executed -system.cpu.iew.exec_refs 28743608 # number of memory reference insts executed -system.cpu.iew.exec_branches 20629236 # Number of branches executed -system.cpu.iew.exec_stores 4918943 # Number of stores executed -system.cpu.iew.exec_rate 0.867532 # Inst execution rate -system.cpu.iew.wb_sent 99756620 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 99658354 # cumulative count of insts written-back -system.cpu.iew.wb_producers 59706662 # num instructions producing a value -system.cpu.iew.wb_consumers 95558908 # num instructions consuming a value +system.cpu.iew.exec_nop 12666 # number of nop insts executed +system.cpu.iew.exec_refs 28725194 # number of memory reference insts executed +system.cpu.iew.exec_branches 20624883 # Number of branches executed +system.cpu.iew.exec_stores 4917829 # Number of stores executed +system.cpu.iew.exec_rate 0.860168 # Inst execution rate +system.cpu.iew.wb_sent 99711182 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 99626193 # cumulative count of insts written-back +system.cpu.iew.wb_producers 59706016 # num instructions producing a value +system.cpu.iew.wb_consumers 95562461 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.863301 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.624815 # average fanout of values written-back +system.cpu.iew.wb_rate 0.855855 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.624785 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 17391201 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 17390136 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 8218 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 825684 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 112699801 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.807931 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.745752 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 825718 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 113659456 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.801109 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.737097 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 76441556 67.83% 67.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18447200 16.37% 84.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 7119761 6.32% 90.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 3375676 3.00% 93.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1760831 1.56% 95.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 536786 0.48% 95.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 726119 0.64% 96.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 179056 0.16% 96.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 4112816 3.65% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 77211009 67.93% 67.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18641585 16.40% 84.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 7152887 6.29% 90.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 3463018 3.05% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1652627 1.45% 95.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 524640 0.46% 95.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 723684 0.64% 96.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 178635 0.16% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 4111371 3.62% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 112699801 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 113659456 # Number of insts commited each cycle system.cpu.commit.committedInsts 90602407 # Number of instructions committed system.cpu.commit.committedOps 91053638 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -676,383 +675,383 @@ system.cpu.commit.op_class_0::MemWrite 4744844 5.21% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91053638 # Class of committed instruction -system.cpu.commit.bw_lim_events 4112816 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 4111371 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 217026090 # The number of ROB reads -system.cpu.rob.rob_writes 219584249 # The number of ROB writes -system.cpu.timesIdled 586 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 45025 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 217986125 # The number of ROB reads +system.cpu.rob.rob_writes 219581178 # The number of ROB writes +system.cpu.timesIdled 584 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 52982 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 90589798 # Number of Instructions Simulated system.cpu.committedOps 91041029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.274302 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.274302 # CPI: Total CPI of All Threads -system.cpu.ipc 0.784743 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.784743 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 108125012 # number of integer regfile reads -system.cpu.int_regfile_writes 58739124 # number of integer regfile writes +system.cpu.cpi 1.284973 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.284973 # CPI: Total CPI of All Threads +system.cpu.ipc 0.778226 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.778226 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 108112973 # number of integer regfile reads +system.cpu.int_regfile_writes 58701982 # number of integer regfile writes system.cpu.fp_regfile_reads 58 # number of floating regfile reads -system.cpu.fp_regfile_writes 99 # number of floating regfile writes -system.cpu.cc_regfile_reads 369256929 # number of cc regfile reads -system.cpu.cc_regfile_writes 58699332 # number of cc regfile writes -system.cpu.misc_regfile_reads 28460693 # number of misc regfile reads +system.cpu.fp_regfile_writes 95 # number of floating regfile writes +system.cpu.cc_regfile_reads 369069288 # number of cc regfile reads +system.cpu.cc_regfile_writes 58692619 # number of cc regfile writes +system.cpu.misc_regfile_reads 28415446 # number of misc regfile reads system.cpu.misc_regfile_writes 7784 # number of misc regfile writes -system.cpu.dcache.tags.replacements 5486247 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.800439 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 18271247 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 5486759 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 3.330062 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 33236000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.800439 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999610 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999610 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 5469543 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.788616 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 18297454 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 5470055 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 3.345022 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 35157000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.788616 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999587 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999587 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 370 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 61970439 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 61970439 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 13905626 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13905626 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 4357324 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4357324 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 61924995 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 61924995 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13934183 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13934183 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 4354974 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4354974 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 522 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 522 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 3872 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 3872 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 18262950 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 18262950 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 18263472 # number of overall hits -system.cpu.dcache.overall_hits::total 18263472 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 9592929 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 9592929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 377657 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 377657 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 8 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 8 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 18289157 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 18289157 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 18289679 # number of overall hits +system.cpu.dcache.overall_hits::total 18289679 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 9550003 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 9550003 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 380007 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 380007 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 7 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 7 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 15 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 15 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9970586 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9970586 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9970594 # number of overall misses -system.cpu.dcache.overall_misses::total 9970594 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 87008583027 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 87008583027 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3975903343 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3975903343 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 269500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 269500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 90984486370 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 90984486370 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 90984486370 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 90984486370 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23498555 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23498555 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9930010 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9930010 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9930017 # number of overall misses +system.cpu.dcache.overall_misses::total 9930017 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88443276736 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88443276736 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3962066244 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3962066244 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 297000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 92405342980 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 92405342980 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 92405342980 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 92405342980 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23484186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23484186 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 4734981 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 530 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 530 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 529 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 529 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 3887 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 3887 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28233536 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28233536 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28234066 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28234066 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.408235 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.408235 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.015094 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.015094 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 28219167 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28219167 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28219696 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28219696 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.406657 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.406657 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.080255 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.080255 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.013233 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.013233 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003859 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003859 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.353147 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.353147 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.353141 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.353141 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9070.074742 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9070.074742 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10527.815830 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 10527.815830 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17966.666667 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 17966.666667 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9125.289764 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9125.289764 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9125.282443 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9125.282443 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 301798 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 69284 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 120550 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 12191 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.503509 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.683209 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.351889 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.351889 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.351882 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.351882 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9261.073189 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9261.073189 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10426.298052 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10426.298052 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 19800 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 19800 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9305.664645 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9305.664645 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9305.658085 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9305.658085 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 306020 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 36082 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 120709 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 2278 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.535188 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 15.839333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 5460017 # number of writebacks -system.cpu.dcache.writebacks::total 5460017 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4328962 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4328962 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 154868 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 154868 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 5439051 # number of writebacks +system.cpu.dcache.writebacks::total 5439051 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4313021 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 4313021 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 146936 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 146936 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 15 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 15 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4483830 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4483830 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4483830 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4483830 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5263967 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5263967 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222789 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 222789 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 5 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 5 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 5486756 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 5486756 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 5486761 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 5486761 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38199288241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 38199288241 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2164503781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2164503781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 250500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 250500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40363792022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 40363792022 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40364042522 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 40364042522 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.224012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.224012 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047052 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047052 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.009434 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.009434 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.194335 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.194335 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.194331 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.194331 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7256.749186 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7256.749186 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9715.487663 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9715.487663 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 50100 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 50100 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7356.585936 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7356.585936 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7356.624887 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7356.624887 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 4459957 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4459957 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4459957 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4459957 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5236982 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5236982 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 233071 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 233071 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 4 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 5470053 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 5470053 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 5470057 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 5470057 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 40519086258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 40519086258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2295163471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2295163471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 213000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 213000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42814249729 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 42814249729 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42814462729 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 42814462729 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.223000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.223000 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049223 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.007561 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.007561 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.193842 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.193842 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.193838 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.193838 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7737.106268 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7737.106268 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9847.486264 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9847.486264 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53250 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53250 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7827.026489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7827.026489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7827.059705 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7827.059705 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 447 # number of replacements -system.cpu.icache.tags.tagsinuse 428.924531 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 32314402 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 906 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 35667.110375 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 451 # number of replacements +system.cpu.icache.tags.tagsinuse 428.263511 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 32302915 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 910 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 35497.708791 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 428.924531 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.837743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.837743 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 428.263511 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.836452 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.836452 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 459 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 21 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 332 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.896484 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 64631998 # Number of tag accesses -system.cpu.icache.tags.data_accesses 64631998 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 32314402 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 32314402 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 32314402 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 32314402 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 32314402 # number of overall hits -system.cpu.icache.overall_hits::total 32314402 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1144 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1144 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1144 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1144 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1144 # number of overall misses -system.cpu.icache.overall_misses::total 1144 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 55657984 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 55657984 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 55657984 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 55657984 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 55657984 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 55657984 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 32315546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 32315546 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 32315546 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 32315546 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 32315546 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 32315546 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000035 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000035 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000035 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000035 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000035 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000035 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48652.083916 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48652.083916 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48652.083916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48652.083916 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48652.083916 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 17056 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 75 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 223 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 76.484305 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 25 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 64609056 # Number of tag accesses +system.cpu.icache.tags.data_accesses 64609056 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 32302915 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 32302915 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 32302915 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 32302915 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 32302915 # number of overall hits +system.cpu.icache.overall_hits::total 32302915 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses +system.cpu.icache.overall_misses::total 1158 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 62669987 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 62669987 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 62669987 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 62669987 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 62669987 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 62669987 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 32304073 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 32304073 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 32304073 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 32304073 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 32304073 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 32304073 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000036 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000036 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000036 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000036 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000036 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000036 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54119.159758 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54119.159758 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54119.159758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54119.159758 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54119.159758 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 19414 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 134 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 238 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 81.571429 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 26.800000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 238 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 238 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 238 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 238 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 238 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 238 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 906 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 906 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 906 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 906 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 906 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 906 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44276742 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 44276742 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44276742 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 44276742 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44276742 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 44276742 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 248 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 248 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 248 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 248 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 248 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 910 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50368733 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 50368733 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50368733 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 50368733 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50368733 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 50368733 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000028 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000028 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000028 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48870.576159 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48870.576159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48870.576159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48870.576159 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 55350.256044 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 55350.256044 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 55350.256044 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 55350.256044 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 4494242 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 5296949 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 693182 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 4495585 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 5292074 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 687825 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 14114027 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 432 # number of replacements -system.cpu.l2cache.tags.tagsinuse 12071.451375 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 10694296 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 15874 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 673.698879 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 14072766 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 493 # number of replacements +system.cpu.l2cache.tags.tagsinuse 12074.856330 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 10653372 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 15934 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 668.593699 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 11103.819168 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 569.155490 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 195.974498 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 202.502218 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.677723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034738 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011961 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.012360 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.736783 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 240 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15202 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 11119.543661 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 571.365929 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 202.646634 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 181.300106 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.678683 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.034873 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.012369 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.011066 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.736991 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 216 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15225 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 12 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 973 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1059 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13108 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.014648 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927856 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 175404109 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 175404109 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 211 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 5261084 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 5261295 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 5460017 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 5460017 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 224780 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 224780 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 211 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 5485864 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 5486075 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 211 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 5485864 # number of overall hits -system.cpu.l2cache.overall_hits::total 5486075 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 695 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 386 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1081 # number of ReadReq misses +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 13 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 3 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 191 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 974 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1048 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13130 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.013184 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.929260 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 174809424 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 174809424 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 213 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 5236439 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 5236652 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 5439051 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 5439051 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 232688 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 232688 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 213 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 5469127 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 5469340 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 213 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 5469127 # number of overall hits +system.cpu.l2cache.overall_hits::total 5469340 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 697 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 416 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1113 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 509 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 509 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 695 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 895 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1590 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 695 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 895 # number of overall misses -system.cpu.l2cache.overall_misses::total 1590 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42529250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21068985 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 63598235 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 30498 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 30498 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 34497490 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 34497490 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 42529250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 55566475 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 98095725 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 42529250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 55566475 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 98095725 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 906 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 5261470 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5262376 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 5460017 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 5460017 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 512 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 512 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 697 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 928 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1625 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 697 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 928 # number of overall misses +system.cpu.l2cache.overall_misses::total 1625 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 48506493 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26932750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 75439243 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 46498 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 46498 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 37042063 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 37042063 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 48506493 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 63974813 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 112481306 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 48506493 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 63974813 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 112481306 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 910 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 5236855 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5237765 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 5439051 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 5439051 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 225289 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 225289 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 906 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 5486759 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 5487665 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 906 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 5486759 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 5487665 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.767108 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000073 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000205 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 233200 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 233200 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 910 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 5470055 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 5470965 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 910 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 5470055 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 5470965 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.765934 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000079 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000212 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002259 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.002259 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.767108 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.000163 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.000290 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.767108 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.000163 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.000290 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61193.165468 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54582.862694 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 58832.779833 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15249 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15249 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67775.029470 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67775.029470 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61695.424528 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61193.165468 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 62085.446927 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61695.424528 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.002196 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.002196 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.765934 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.000170 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.000297 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.765934 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.000170 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.000297 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69593.246772 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64742.187500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67780.092543 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23249 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23249 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72347.779297 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72347.779297 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69219.265231 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69593.246772 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68938.376078 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69219.265231 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1061,148 +1060,146 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 309 # number of writebacks -system.cpu.l2cache.writebacks::total 309 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 168 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 168 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 213 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 213 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 214 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 694 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 341 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1035 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20230 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 20230 # number of HardPFReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 358 # number of writebacks +system.cpu.l2cache.writebacks::total 358 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 48 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 171 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 171 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 221 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 695 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 368 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1063 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 20246 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 20246 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 341 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 341 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 694 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 682 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1376 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 694 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 682 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20230 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 21606 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 36534500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16113750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52648250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 777111161 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 22591778 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 22591778 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36534500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 38705528 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 75240028 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36534500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 38705528 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 777111161 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 852351189 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000065 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000197 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 695 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 709 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1404 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 695 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 709 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 20246 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 21650 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 42518507 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 21103750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63622257 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 830590289 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 25988008 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 25988008 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 42518507 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 47091758 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 89610265 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 42518507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 47091758 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 830590289 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 920200554 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000070 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000203 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001514 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.000251 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.766004 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000124 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001462 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001462 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.000257 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.763736 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.000130 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.003937 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52643.371758 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47254.398827 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 50867.874396 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 38413.799357 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66251.548387 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66251.548387 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54680.252907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52643.371758 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56752.973607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 38413.799357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39449.744932 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.003957 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61177.707914 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57347.146739 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59851.605833 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 41024.908081 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76211.167155 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76211.167155 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63824.975071 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61177.707914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66419.968970 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 41024.908081 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.489792 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5262376 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5262376 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 5460017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 22339 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5237765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5237765 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 5439051 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 22132 # Transaction distribution system.cpu.toL2Bus.trans_dist::HardPFResp 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 225289 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 225289 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1812 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16433541 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16435353 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 57984 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 700593792 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 700651776 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 22341 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10970023 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.002036 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.045080 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 233200 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 233200 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1820 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 16379167 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16380987 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698182912 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 698241152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 22134 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10932150 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.002024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.044949 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 10947684 99.80% 99.80% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 22339 0.20% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10910018 99.80% 99.80% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 22132 0.20% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10970023 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10933859000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 18.9 # Layer utilization (%) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 10932150 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10894060998 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 3000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1479748 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1497004 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 8230187517 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 14.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 15531 # Transaction distribution -system.membus.trans_dist::ReadResp 15531 # Transaction distribution -system.membus.trans_dist::Writeback 309 # Transaction distribution +system.cpu.toL2Bus.respLayer1.occupancy 8205133181 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 15596 # Transaction distribution +system.membus.trans_dist::ReadResp 15596 # Transaction distribution +system.membus.trans_dist::Writeback 358 # Transaction distribution system.membus.trans_dist::UpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution system.membus.trans_dist::ReadExReq 341 # Transaction distribution system.membus.trans_dist::ReadExResp 341 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32057 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 32057 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1035584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1035584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 32236 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 32236 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1042880 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1042880 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 16183 # Request fanout histogram +system.membus.snoop_fanout::samples 16297 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 16183 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 16297 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 16183 # Request fanout histogram -system.membus.reqLayer0.occupancy 28002068 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 16297 # Request fanout histogram +system.membus.reqLayer0.occupancy 26854780 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 149256371 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 83365318 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index 16d507b60..b143a6790 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.054141 # Nu sim_ticks 54141000000 # Number of ticks simulated final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1669323 # Simulator instruction rate (inst/s) -host_op_rate 1677636 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 997531404 # Simulator tick rate (ticks/s) -host_mem_usage 433488 # Number of bytes of host memory used -host_seconds 54.28 # Real time elapsed on the host +host_inst_rate 1893120 # Simulator instruction rate (inst/s) +host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1131265211 # Simulator tick rate (ticks/s) +host_mem_usage 433636 # Number of bytes of host memory used +host_seconds 47.86 # Real time elapsed on the host sim_insts 90602407 # Number of instructions simulated sim_ops 91053638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 135031170 # Request fanout histogram -system.membus.snoop_fanout::mean 4.798562 # Request fanout histogram +system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::5 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram +system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 135031170 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 3f9742fb4..7176a8af9 100644 --- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041218000 # Number of ticks simulated -final_tick 147041218000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 147041218500 # Number of ticks simulated +final_tick 147041218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1114927 # Simulator instruction rate (inst/s) -host_op_rate 1120467 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1809956176 # Simulator tick rate (ticks/s) -host_mem_usage 442716 # Number of bytes of host memory used -host_seconds 81.24 # Real time elapsed on the host +host_inst_rate 937429 # Simulator instruction rate (inst/s) +host_op_rate 942087 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1521808702 # Simulator tick rate (ticks/s) +host_mem_usage 442868 # Number of bytes of host memory used +host_seconds 96.62 # Real time elapsed on the host sim_insts 90576861 # Number of instructions simulated sim_ops 91026990 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082436 # number of cpu cycles simulated +system.cpu.numCycles 294082437 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 90576861 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 27220755 # nu system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082435.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294082436.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 18732304 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91054080 # Class of executed instruction system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593965 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.593939 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410413000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593965 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 54410414000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593939 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9910952000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1123965500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 117000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11034917500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11035034500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11035034500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361045000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361045000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11508315000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508433500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11508433500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11009.893511 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24114.773971 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11655.022999 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11655.022999 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11655.109643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11655.109643 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.893511 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.022999 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.022999 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.109643 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.109643 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120575 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 510.120572 # Cycle average of tags in use system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120575 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120572 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id @@ -374,12 +374,12 @@ system.cpu.icache.demand_misses::cpu.inst 599 # n system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32073500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32073500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32073500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32073500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32073500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32073500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32074000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32074000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32074000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32074000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32074000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32074000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses @@ -392,12 +392,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.075125 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53545.075125 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53545.075125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.075125 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53545.075125 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.909850 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53545.909850 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53545.909850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53545.909850 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,34 +412,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 30875500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 30875500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30875500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 30875500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30875500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 30875500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31175500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31175500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31175500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31175500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31175500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31175500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51545.075125 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51545.075125 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51545.075125 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51545.075125 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52045.909850 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52045.909850 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.852615 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9567.852421 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446533 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172981 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233101 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446344 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172977 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233100 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy @@ -477,17 +477,17 @@ system.cpu.l2cache.demand_misses::total 15340 # nu system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30066500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11130000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 41196500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 756746500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 756746500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 30066500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 767876500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 797943000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 30066500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 767876500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 797943000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30356000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11237000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 41593000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764020500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 764020500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30356000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 775257500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 805613500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30356000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 775257500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 805613500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 900788 # number of ReadReq accesses(hits+misses) @@ -512,17 +512,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016192 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52018.166090 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52009.345794 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52015.782828 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52017.218862 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52017.218862 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52017.144720 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52018.166090 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52017.104728 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52017.144720 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.031142 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.345794 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -542,17 +542,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15340 system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8560000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 31680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 581920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 581920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 613600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 613600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23409000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32076000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589194000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589194000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23409000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597861000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 621270000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23409000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597861000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 621270000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses @@ -564,17 +564,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 900788 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 900788 # Transaction distribution @@ -589,19 +589,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1889731 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) @@ -628,9 +626,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 15340 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 138323000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 76963500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt index 86f47af4e..b81c12b39 100644 --- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.361489 # Number of seconds simulated -sim_ticks 361488530000 # Number of ticks simulated -final_tick 361488530000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 361488530500 # Number of ticks simulated +final_tick 361488530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1379749 # Simulator instruction rate (inst/s) -host_op_rate 1379806 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2045576865 # Simulator tick rate (ticks/s) -host_mem_usage 421936 # Number of bytes of host memory used -host_seconds 176.72 # Real time elapsed on the host +host_inst_rate 1163469 # Simulator instruction rate (inst/s) +host_op_rate 1163517 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1724927568 # Simulator tick rate (ticks/s) +host_mem_usage 425840 # Number of bytes of host memory used +host_seconds 209.57 # Real time elapsed on the host sim_insts 243825150 # Number of instructions simulated sim_ops 243835265 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,32 +29,9 @@ system.physmem.bw_inst_read::total 155623 # In system.physmem.bw_total::cpu.inst 155623 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 2606821 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2762444 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1036 # Transaction distribution -system.membus.trans_dist::ReadResp 1036 # Transaction distribution -system.membus.trans_dist::ReadExReq 14567 # Transaction distribution -system.membus.trans_dist::ReadExResp 14567 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 15603 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 15603 # Request fanout histogram -system.membus.reqLayer0.occupancy 15603000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 140427000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 443 # Number of system calls -system.cpu.numCycles 722977060 # number of cpu cycles simulated +system.cpu.numCycles 722977061 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 243825150 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 105711441 # nu system.cpu.num_load_insts 82803521 # Number of load instructions system.cpu.num_store_insts 22907920 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 722977059.998000 # Number of busy cycles +system.cpu.num_busy_cycles 722977060.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29302884 # Number of branches fetched @@ -112,13 +89,141 @@ system.cpu.op_class::MemWrite 22907920 9.37% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 244431613 # Class of executed instruction +system.cpu.dcache.tags.replacements 935475 # number of replacements +system.cpu.dcache.tags.tagsinuse 3562.469045 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 134366266000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469045 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits +system.cpu.dcache.overall_hits::total 104182817 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses +system.cpu.dcache.overall_misses::total 939567 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks +system.cpu.dcache.writebacks::total 935266 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10274449500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10274449500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1148937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1148937000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 88000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 88000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11423386500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11423386500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11423386500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11423386500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11507.385281 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11507.385281 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24597.238279 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24597.238279 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 22000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 22000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12158.139334 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12158.139334 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 25 # number of replacements -system.cpu.icache.tags.tagsinuse 725.412977 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 725.412975 # Cycle average of tags in use system.cpu.icache.tags.total_refs 244420617 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 882 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 277120.880952 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 725.412977 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 725.412975 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.354206 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 857 # Occupied blocks per task id @@ -141,12 +246,12 @@ system.cpu.icache.demand_misses::cpu.inst 882 # n system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses system.cpu.icache.overall_misses::total 882 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 48384000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 48384000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 48384000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 48384000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 48384000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 48384500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 48384500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 48384500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 48384500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 48384500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 48384500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 244421499 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 244421499 # number of demand (read+write) accesses @@ -159,12 +264,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54857.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54857.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54857.142857 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54857.709751 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54857.709751 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54857.709751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54857.709751 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54857.709751 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -179,33 +284,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 882 system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 47061500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 47061500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 47061500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 47061500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 47061500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 47061500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52857.142857 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52857.142857 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53357.709751 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53357.709751 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53357.709751 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53357.709751 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9730.625290 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9730.625210 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1813290 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15586 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 116.340947 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670241 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635592 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8847.670164 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 738.635590 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 144.319456 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270009 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.022541 # Average percentage of cache occupancy @@ -244,17 +349,17 @@ system.cpu.l2cache.demand_misses::total 15603 # nu system.cpu.l2cache.overall_misses::cpu.inst 879 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 14724 # number of overall misses system.cpu.l2cache.overall_misses::total 15603 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 45708000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8164000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 53872000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 757484000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 757484000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 45708000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 765648000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 811356000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 45708000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 765648000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 811356000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46148000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8242500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 54390500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764767500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 764767500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 46148000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 773010000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 819158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 46148000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 773010000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 819158000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 882 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 892857 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 893739 # number of ReadReq accesses(hits+misses) @@ -279,17 +384,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.016591 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996599 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.015671 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016591 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.568828 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.482625 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.032045 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.568828 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.032045 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -309,17 +414,17 @@ system.cpu.l2cache.demand_mshr_misses::total 15603 system.cpu.l2cache.overall_mshr_misses::cpu.inst 879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 14724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 582680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 582680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 588960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 624120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 588960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 624120000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 35599500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6358500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41958000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589963500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35599500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 596322000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 631921500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35599500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 596322000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 631921500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000176 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001159 # mshr miss rate for ReadReq accesses @@ -331,146 +436,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.016591 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015671 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016591 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 935475 # number of replacements -system.cpu.dcache.tags.tagsinuse 3562.469056 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 104186699 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 939571 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 110.887521 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 134366265000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3562.469056 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.869743 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1418 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2513 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 211192111 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 211192111 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 81327576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 81327576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 104182817 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 104182817 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 104182817 # number of overall hits -system.cpu.dcache.overall_hits::total 104182817 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 892857 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 892857 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 46710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 46710 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 4 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 4 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 939567 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 939567 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 939567 # number of overall misses -system.cpu.dcache.overall_misses::total 939567 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11613735000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1219002000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 94000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 94000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12832737000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12832737000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12832737000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 82220433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22901951 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 3886 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 105122384 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 105122384 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 105122384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 105122384 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010859 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.001029 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008938 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008938 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008938 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008938 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13007.385281 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13007.385281 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26097.238279 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26097.238279 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 23500 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 23500 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13658.139334 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13658.139334 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 935266 # number of writebacks -system.cpu.dcache.writebacks::total 935266 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 892857 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 892857 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46710 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 46710 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 4 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 939567 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 939567 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 939567 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9828021000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9828021000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1125582000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1125582000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 86000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10953603000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10953603000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10953603000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10953603000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.010859 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.001029 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.008938 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.008938 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11007.385281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24097.238279 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 21500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 21500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11658.139334 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11658.139334 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 893739 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 935266 # Transaction distribution @@ -500,5 +477,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 1323000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1409356500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1036 # Transaction distribution +system.membus.trans_dist::ReadResp 1036 # Transaction distribution +system.membus.trans_dist::ReadExReq 14567 # Transaction distribution +system.membus.trans_dist::ReadExResp 14567 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 31206 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 998592 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 15603 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 15603 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 15603 # Request fanout histogram +system.membus.reqLayer0.occupancy 15603500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 78015500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt index a20619a99..22cc57507 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt @@ -1,76 +1,76 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.061857 # Number of seconds simulated -sim_ticks 61857343500 # Number of ticks simulated -final_tick 61857343500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.062113 # Number of seconds simulated +sim_ticks 62113055500 # Number of ticks simulated +final_tick 62113055500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113051 # Simulator instruction rate (inst/s) -host_op_rate 199065 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 44263102 # Simulator tick rate (ticks/s) -host_mem_usage 453712 # Number of bytes of host memory used -host_seconds 1397.49 # Real time elapsed on the host +host_inst_rate 113198 # Simulator instruction rate (inst/s) +host_op_rate 199324 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44503726 # Simulator tick rate (ticks/s) +host_mem_usage 454072 # Number of bytes of host memory used +host_seconds 1395.68 # Real time elapsed on the host sim_insts 157988547 # Number of instructions simulated sim_ops 278192464 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 64640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 1884928 # Number of bytes read from this memory -system.physmem.bytes_read::total 1949568 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 64640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 64640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 12608 # Number of bytes written to this memory -system.physmem.bytes_written::total 12608 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 29452 # Number of read requests responded to by this memory -system.physmem.num_reads::total 30462 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 197 # Number of write requests responded to by this memory -system.physmem.num_writes::total 197 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 1044985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 30472178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 31517163 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1044985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1044985 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 203824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 203824 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 203824 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1044985 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 30472178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 31720987 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 30463 # Number of read requests accepted -system.physmem.writeReqs 197 # Number of write requests accepted -system.physmem.readBursts 30463 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 197 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 1943744 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 5888 # Total number of bytes read from write queue -system.physmem.bytesWritten 11328 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 1949632 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 12608 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 92 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 64896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 1883008 # Number of bytes read from this memory +system.physmem.bytes_read::total 1947904 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 64896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 64896 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 10624 # Number of bytes written to this memory +system.physmem.bytes_written::total 10624 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1014 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 29422 # Number of read requests responded to by this memory +system.physmem.num_reads::total 30436 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 166 # Number of write requests responded to by this memory +system.physmem.num_writes::total 166 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1044805 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 30315817 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 31360621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1044805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1044805 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 171043 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 171043 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 171043 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1044805 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 30315817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 31531664 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 30436 # Number of read requests accepted +system.physmem.writeReqs 166 # Number of write requests accepted +system.physmem.readBursts 30436 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 166 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 1943680 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 4224 # Total number of bytes read from write queue +system.physmem.bytesWritten 9216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 1947904 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10624 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 66 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 1927 # Per bank write bursts -system.physmem.perBankRdBursts::1 2067 # Per bank write bursts -system.physmem.perBankRdBursts::2 2027 # Per bank write bursts -system.physmem.perBankRdBursts::3 1932 # Per bank write bursts +system.physmem.perBankRdBursts::0 1923 # Per bank write bursts +system.physmem.perBankRdBursts::1 2063 # Per bank write bursts +system.physmem.perBankRdBursts::2 2030 # Per bank write bursts +system.physmem.perBankRdBursts::3 1928 # Per bank write bursts system.physmem.perBankRdBursts::4 2026 # Per bank write bursts system.physmem.perBankRdBursts::5 1903 # Per bank write bursts system.physmem.perBankRdBursts::6 1964 # Per bank write bursts -system.physmem.perBankRdBursts::7 1863 # Per bank write bursts -system.physmem.perBankRdBursts::8 1937 # Per bank write bursts -system.physmem.perBankRdBursts::9 1937 # Per bank write bursts -system.physmem.perBankRdBursts::10 1804 # Per bank write bursts -system.physmem.perBankRdBursts::11 1796 # Per bank write bursts +system.physmem.perBankRdBursts::7 1866 # Per bank write bursts +system.physmem.perBankRdBursts::8 1938 # Per bank write bursts +system.physmem.perBankRdBursts::9 1940 # Per bank write bursts +system.physmem.perBankRdBursts::10 1805 # Per bank write bursts +system.physmem.perBankRdBursts::11 1795 # Per bank write bursts system.physmem.perBankRdBursts::12 1792 # Per bank write bursts system.physmem.perBankRdBursts::13 1800 # Per bank write bursts system.physmem.perBankRdBursts::14 1818 # Per bank write bursts -system.physmem.perBankRdBursts::15 1778 # Per bank write bursts +system.physmem.perBankRdBursts::15 1779 # Per bank write bursts system.physmem.perBankWrBursts::0 15 # Per bank write bursts -system.physmem.perBankWrBursts::1 94 # Per bank write bursts -system.physmem.perBankWrBursts::2 13 # Per bank write bursts -system.physmem.perBankWrBursts::3 21 # Per bank write bursts +system.physmem.perBankWrBursts::1 80 # Per bank write bursts +system.physmem.perBankWrBursts::2 11 # Per bank write bursts +system.physmem.perBankWrBursts::3 10 # Per bank write bursts system.physmem.perBankWrBursts::4 7 # Per bank write bursts -system.physmem.perBankWrBursts::5 7 # Per bank write bursts -system.physmem.perBankWrBursts::6 12 # Per bank write bursts +system.physmem.perBankWrBursts::5 0 # Per bank write bursts +system.physmem.perBankWrBursts::6 13 # Per bank write bursts system.physmem.perBankWrBursts::7 0 # Per bank write bursts system.physmem.perBankWrBursts::8 0 # Per bank write bursts system.physmem.perBankWrBursts::9 5 # Per bank write bursts @@ -82,27 +82,27 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 61857329000 # Total gap between requests +system.physmem.totGap 62113012500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 30463 # Read request sizes (log2) +system.physmem.readPktSize::6 30436 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 197 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 29883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 166 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 29887 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 372 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 84 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -146,22 +146,22 @@ system.physmem.wrQLenPdf::13 1 # Wh system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,327 +193,324 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 2724 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 716.922173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 515.538805 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 389.679049 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 350 12.85% 12.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 254 9.32% 22.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 128 4.70% 26.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 108 3.96% 30.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 103 3.78% 34.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 103 3.78% 38.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 111 4.07% 42.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 70 2.57% 45.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 1497 54.96% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 2724 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 10 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 3031.200000 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 22.218074 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 9548.252985 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 9 90.00% 90.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::29696-30719 1 10.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 10 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 10 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.700000 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.676249 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.948683 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2 20.00% 20.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 7 70.00% 90.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 10.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 10 # Writes before turning the bus around for reads -system.physmem.totQLat 130999000 # Total ticks spent queuing -system.physmem.totMemAccLat 700455250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 151855000 # Total ticks spent in databus transfers -system.physmem.avgQLat 4313.29 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 2732 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 714.471449 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 512.855124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 389.294613 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 368 13.47% 13.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 227 8.31% 21.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 131 4.80% 26.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 130 4.76% 31.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 109 3.99% 35.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 99 3.62% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 107 3.92% 42.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 79 2.89% 45.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 1482 54.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 2732 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 8 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 3788.500000 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.757307 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 10676.303052 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7 87.50% 87.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::29696-30719 1 12.50% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 8 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 8 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.000000 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 8 100.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 8 # Writes before turning the bus around for reads +system.physmem.totQLat 135350500 # Total ticks spent queuing +system.physmem.totMemAccLat 704788000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 151850000 # Total ticks spent in databus transfers +system.physmem.avgQLat 4456.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 23063.29 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 31.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 31.52 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.20 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23206.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 31.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 0.15 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 31.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 0.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.25 # Data bus utilization in percentage -system.physmem.busUtilRead 0.25 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.24 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.62 # Average write queue length when enqueuing -system.physmem.readRowHits 27696 # Number of row buffer hits during reads -system.physmem.writeRowHits 119 # Number of row buffer hits during writes -system.physmem.readRowHitRate 91.19 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.41 # Row buffer hit rate for writes -system.physmem.avgGap 2017525.41 # Average gap between requests -system.physmem.pageHitRate 90.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 10939320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 5968875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 122226000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 1095120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2776043070 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34677412500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41633685525 # Total energy per rank (pJ) -system.physmem_0.averagePower 673.093587 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57673269750 # Time in different power states -system.physmem_0.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 11.89 # Average write queue length when enqueuing +system.physmem.readRowHits 27681 # Number of row buffer hits during reads +system.physmem.writeRowHits 96 # Number of row buffer hits during writes +system.physmem.readRowHitRate 91.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.83 # Row buffer hit rate for writes +system.physmem.avgGap 2029704.35 # Average gap between requests +system.physmem.pageHitRate 90.96 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 10931760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 5964750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 122311800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 881280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2875200840 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 34744599750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41816673300 # Total energy per rank (pJ) +system.physmem_0.averagePower 673.255215 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 57785258250 # Time in different power states +system.physmem_0.memoryStateTime::REF 2074020000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 2115534000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 2252296250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 9623880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 5251125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 114246600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 9714600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 5300625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 114332400 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 51840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4040000640 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2977027920 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 34501101750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41647303755 # Total energy per rank (pJ) -system.physmem_1.averagePower 673.313903 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57380456750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2065440000 # Time in different power states +system.physmem_1.refreshEnergy 4056783120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3044489985 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 34596104250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41826776820 # Total energy per rank (pJ) +system.physmem_1.averagePower 673.417815 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57536988500 # Time in different power states +system.physmem_1.memoryStateTime::REF 2074020000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 2409426750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 2500187750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37414357 # Number of BP lookups -system.cpu.branchPred.condPredicted 37414357 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 797165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 21409472 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21302649 # Number of BTB hits +system.cpu.branchPred.lookups 37409115 # Number of BP lookups +system.cpu.branchPred.condPredicted 37409115 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 796961 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 21404292 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21297612 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 99.501048 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 5521067 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5418 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 99.501595 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 5520840 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 5370 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 123714688 # number of cpu cycles simulated +system.cpu.numCycles 124226112 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 28240185 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 201519425 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37414357 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 26823716 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 94568946 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1664995 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 796 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13919 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 14 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 16 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 27849620 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 205824 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 123656373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.872113 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.370891 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 28235935 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 201516528 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37409115 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 26818452 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 95078093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1665601 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 765 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13635 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 38 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 27845177 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 203940 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 124161279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.860308 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.369086 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 62738354 50.74% 50.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3652838 2.95% 53.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 3508504 2.84% 56.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5967471 4.83% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 7654257 6.19% 67.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5436238 4.40% 71.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 3366087 2.72% 74.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 2072932 1.68% 76.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 29259692 23.66% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 63245394 50.94% 50.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3661074 2.95% 53.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 3505984 2.82% 56.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5966145 4.81% 61.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 7636259 6.15% 67.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5451035 4.39% 72.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 3359633 2.71% 74.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 2076013 1.67% 76.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 29259742 23.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 123656373 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.302425 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.628905 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13285381 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 63221156 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 36527318 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 9790021 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 832497 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 334996459 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 832497 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 18592314 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8932600 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 16230 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 40801194 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 54481538 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 328650401 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 2309 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 768646 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 48119117 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4597217 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 330628900 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 873052183 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 537682976 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 692 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 124161279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.301137 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.622175 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13292806 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63720296 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 36521548 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 9793829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 832800 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 335002829 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 832800 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 18597256 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8862328 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 16249 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 40799373 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 55053273 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 328652486 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 2589 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 765140 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 48300530 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 4998296 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 330629230 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 873051813 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 537695602 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 524 # Number of floating rename lookups system.cpu.rename.CommittedMaps 279212747 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 51416153 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 475 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 476 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 66201491 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106325920 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 36528653 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 49813174 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 8481864 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 325481116 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 307976733 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 54133 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 46686820 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 68916320 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1850 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 123656373 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.490585 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.124426 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 51416483 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 478 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 478 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 66182076 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106321382 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 36530805 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 49812358 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 8510426 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 325477303 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2126 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 307989355 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 51384 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 46683880 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 68913858 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1681 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 124161279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.480559 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.127626 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 30107102 24.35% 24.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19550071 15.81% 40.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 16727632 13.53% 53.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 17064547 13.80% 67.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16031841 12.96% 80.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 12684150 10.26% 90.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 5762404 4.66% 95.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 4173789 3.38% 98.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 1554837 1.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 30601082 24.65% 24.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19574247 15.77% 40.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 16779908 13.51% 53.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 17045625 13.73% 67.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 15969415 12.86% 80.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 12663210 10.20% 90.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 5764205 4.64% 95.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 4169219 3.36% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 1594368 1.28% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 123656373 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 124161279 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 316999 7.53% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 3711822 88.14% 95.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 182351 4.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 316891 7.52% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.52% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 3711549 88.13% 95.66% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 182770 4.34% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33338 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 175394846 56.95% 56.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 11227 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 339 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 53 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 98503391 31.98% 88.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 34033539 11.05% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 175395413 56.95% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 11214 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 334 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 40 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 98514236 31.99% 88.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 34034780 11.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 307976733 # Type of FU issued -system.cpu.iq.rate 2.489411 # Inst issue rate -system.cpu.iq.fu_busy_cnt 4211172 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013674 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 743874545 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 372209729 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 305990656 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 599 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1009 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 208 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 312154274 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 58255905 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 307989355 # Type of FU issued +system.cpu.iq.rate 2.479264 # Inst issue rate +system.cpu.iq.fu_busy_cnt 4211210 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013673 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 744402178 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 372203676 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 305987015 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 405 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 719 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 146 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 312167028 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 199 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 58260510 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 15546535 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 56855 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 41794 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 5088901 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 15541997 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 57887 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42363 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 5091053 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3643 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 105171 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3649 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 124471 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 832497 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5705091 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 3134574 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 325483411 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 125197 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106325920 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 36528653 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 468 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2776 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3138754 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 41794 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 401755 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 445201 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 846956 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 306897357 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 98135370 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1079376 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 832800 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5705086 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 3056605 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 325479429 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 124396 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106321382 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 36530805 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2770 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3059848 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42363 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 401945 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 444615 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 846560 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 306916313 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 98157297 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1073042 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 131959976 # number of memory reference insts executed -system.cpu.iew.exec_branches 31536734 # Number of branches executed -system.cpu.iew.exec_stores 33824606 # Number of stores executed -system.cpu.iew.exec_rate 2.480687 # Inst execution rate -system.cpu.iew.wb_sent 306320115 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 305990864 # cumulative count of insts written-back -system.cpu.iew.wb_producers 231632886 # num instructions producing a value -system.cpu.iew.wb_consumers 336126880 # num instructions consuming a value +system.cpu.iew.exec_refs 131977680 # number of memory reference insts executed +system.cpu.iew.exec_branches 31536553 # Number of branches executed +system.cpu.iew.exec_stores 33820383 # Number of stores executed +system.cpu.iew.exec_rate 2.470626 # Inst execution rate +system.cpu.iew.wb_sent 306317735 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 305987161 # cumulative count of insts written-back +system.cpu.iew.wb_producers 231581512 # num instructions producing a value +system.cpu.iew.wb_consumers 336076811 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.473359 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.689123 # average fanout of values written-back +system.cpu.iew.wb_rate 2.463147 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.689073 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 47392313 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 47389031 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 445 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 797958 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 117208008 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.373494 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.089570 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 797726 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 117712955 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.363312 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.086758 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 52857679 45.10% 45.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 15964987 13.62% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 10970811 9.36% 68.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8748487 7.46% 75.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1925592 1.64% 77.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1731776 1.48% 78.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 850158 0.73% 79.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 689946 0.59% 79.98% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 23468572 20.02% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 53359699 45.33% 45.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 15949045 13.55% 58.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 10998829 9.34% 68.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8750765 7.43% 75.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1918688 1.63% 77.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1725778 1.47% 78.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 854994 0.73% 79.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 681396 0.58% 80.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 23473761 19.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 117208008 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 117712955 # Number of insts commited each cycle system.cpu.commit.committedInsts 157988547 # Number of instructions committed system.cpu.commit.committedOps 278192464 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -559,325 +556,325 @@ system.cpu.commit.op_class_0::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 278192464 # Class of committed instruction -system.cpu.commit.bw_lim_events 23468572 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 23473761 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 419324213 # The number of ROB reads -system.cpu.rob.rob_writes 657627213 # The number of ROB writes -system.cpu.timesIdled 611 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 58315 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 419820689 # The number of ROB reads +system.cpu.rob.rob_writes 657620446 # The number of ROB writes +system.cpu.timesIdled 598 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 64833 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 157988547 # Number of Instructions Simulated system.cpu.committedOps 278192464 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.783061 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.783061 # CPI: Total CPI of All Threads -system.cpu.ipc 1.277040 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.277040 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 493625454 # number of integer regfile reads -system.cpu.int_regfile_writes 240898259 # number of integer regfile writes -system.cpu.fp_regfile_reads 178 # number of floating regfile reads -system.cpu.fp_regfile_writes 135 # number of floating regfile writes -system.cpu.cc_regfile_reads 107699117 # number of cc regfile reads -system.cpu.cc_regfile_writes 64568807 # number of cc regfile writes -system.cpu.misc_regfile_reads 196282104 # number of misc regfile reads +system.cpu.cpi 0.786298 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.786298 # CPI: Total CPI of All Threads +system.cpu.ipc 1.271782 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.271782 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 493661924 # number of integer regfile reads +system.cpu.int_regfile_writes 240899982 # number of integer regfile writes +system.cpu.fp_regfile_reads 121 # number of floating regfile reads +system.cpu.fp_regfile_writes 99 # number of floating regfile writes +system.cpu.cc_regfile_reads 107697498 # number of cc regfile reads +system.cpu.cc_regfile_writes 64570083 # number of cc regfile writes +system.cpu.misc_regfile_reads 196298941 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2072433 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.938050 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 68459745 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2076529 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 32.968355 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 19695463250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.938050 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993393 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993393 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2072451 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.920590 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 68431233 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2076547 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 32.954339 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 19749732250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.920590 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993145 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993145 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 636 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 3333 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 585 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 3383 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 144502465 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 144502465 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37113882 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37113882 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31345863 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31345863 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 68459745 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 68459745 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 68459745 # number of overall hits -system.cpu.dcache.overall_hits::total 68459745 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2659334 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2659334 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 93889 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 93889 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2753223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2753223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2753223 # number of overall misses -system.cpu.dcache.overall_misses::total 2753223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 31861027000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 31861027000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2765155494 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2765155494 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34626182494 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34626182494 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34626182494 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34626182494 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 39773216 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 39773216 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 144497109 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 144497109 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37085404 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37085404 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31345829 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31345829 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 68431233 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 68431233 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 68431233 # number of overall hits +system.cpu.dcache.overall_hits::total 68431233 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2685125 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2685125 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 93923 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 93923 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2779048 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2779048 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2779048 # number of overall misses +system.cpu.dcache.overall_misses::total 2779048 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 32124036248 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 32124036248 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2977938994 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2977938994 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35101975242 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35101975242 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35101975242 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35101975242 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 39770529 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 39770529 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 71212968 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 71212968 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 71212968 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 71212968 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.066862 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.002986 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.038662 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.038662 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038662 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038662 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11980.829411 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11980.829411 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29451.325437 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29451.325437 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 12576.599314 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 12576.599314 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 12576.599314 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 182189 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 71210281 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 71210281 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 71210281 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 71210281 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067515 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.067515 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.002987 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.002987 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.039026 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.039026 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.039026 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.039026 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11963.702341 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11963.702341 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31706.174143 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31706.174143 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 12630.935213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 12630.935213 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 12630.935213 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 199096 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 39926 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 39942 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.563167 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 4.984628 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2066654 # number of writebacks -system.cpu.dcache.writebacks::total 2066654 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 664835 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 664835 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 11856 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 676691 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 676691 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 676691 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1994499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82033 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 82033 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2076532 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2076532 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2076532 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22009124500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22009124500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2514972744 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2514972744 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24524097244 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 24524097244 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24524097244 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 24524097244 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050147 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050147 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 2066749 # number of writebacks +system.cpu.dcache.writebacks::total 2066749 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 690617 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 690617 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 11883 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 11883 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 702500 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 702500 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 702500 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 702500 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1994508 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1994508 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82040 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82040 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2076548 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2076548 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2076548 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2076548 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23032838251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23032838251 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2765865745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2765865745 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 25798703996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 25798703996 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 25798703996 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 25798703996 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050150 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050150 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002609 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002609 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.029159 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.029159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11034.913780 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11034.913780 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30658.061317 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30658.061317 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11810.122475 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11810.122475 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.029161 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.029161 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11548.130291 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11548.130291 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33713.624391 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33713.624391 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12423.841874 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12423.841874 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 62 # number of replacements -system.cpu.icache.tags.tagsinuse 827.714171 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 27848273 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1026 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 27142.566277 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 58 # number of replacements +system.cpu.icache.tags.tagsinuse 832.593358 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 27843840 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1028 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 27085.447471 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 827.714171 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.404157 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.404157 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 964 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.470703 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 55700266 # Number of tag accesses -system.cpu.icache.tags.data_accesses 55700266 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 27848273 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 27848273 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 27848273 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 27848273 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 27848273 # number of overall hits -system.cpu.icache.overall_hits::total 27848273 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1347 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1347 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1347 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1347 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1347 # number of overall misses -system.cpu.icache.overall_misses::total 1347 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 92877749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 92877749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 92877749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 92877749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 92877749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 92877749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 27849620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 27849620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 27849620 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 27849620 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 27849620 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 27849620 # number of overall (read+write) accesses +system.cpu.icache.tags.occ_blocks::cpu.inst 832.593358 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.406540 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.406540 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 970 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 23 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 12 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 880 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.473633 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 55691382 # Number of tag accesses +system.cpu.icache.tags.data_accesses 55691382 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 27843840 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 27843840 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 27843840 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 27843840 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 27843840 # number of overall hits +system.cpu.icache.overall_hits::total 27843840 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1337 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1337 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1337 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1337 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1337 # number of overall misses +system.cpu.icache.overall_misses::total 1337 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 100311747 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 100311747 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 100311747 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 100311747 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 100311747 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 100311747 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 27845177 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 27845177 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 27845177 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 27845177 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 27845177 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 27845177 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000048 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000048 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000048 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000048 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000048 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000048 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68951.558278 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68951.558278 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68951.558278 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68951.558278 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68951.558278 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68951.558278 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 850 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75027.484667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75027.484667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75027.484667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75027.484667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75027.484667 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 601 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 141.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 100.166667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 321 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 321 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 321 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 321 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 321 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 321 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1026 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1026 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1026 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1026 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1026 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72330999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 72330999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72330999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 72330999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72330999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 72330999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 309 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 309 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 309 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 309 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 309 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 309 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1028 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1028 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1028 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1028 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1028 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1028 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79616501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 79616501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79616501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 79616501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79616501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 79616501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000037 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000037 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000037 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000037 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70498.049708 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70498.049708 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70498.049708 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70498.049708 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70498.049708 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70498.049708 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77447.958171 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77447.958171 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77447.958171 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77447.958171 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 515 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20693.420547 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4029533 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 30444 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 132.358856 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 480 # number of replacements +system.cpu.l2cache.tags.tagsinuse 20677.307711 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4029650 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 30419 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 132.471482 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19762.319882 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 681.987127 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 249.113538 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.603098 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020813 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.007602 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.631513 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29929 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 784 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27627 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913361 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 33266205 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 33266205 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1994012 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1994028 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2066654 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2066654 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 53067 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 53067 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2047079 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2047095 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2047079 # number of overall hits -system.cpu.l2cache.overall_hits::total 2047095 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1010 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 455 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1465 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 28998 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 28998 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1010 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 29453 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 30463 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1010 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 29453 # number of overall misses -system.cpu.l2cache.overall_misses::total 30463 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71135750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 31674000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 102809750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1901914750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1901914750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 71135750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1933588750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 2004724500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 71135750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1933588750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 2004724500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1026 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1994467 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1995493 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2066654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2066654 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 82065 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 82065 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1026 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2076532 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2077558 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1026 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2076532 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2077558 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.984405 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000228 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.000734 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353354 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.353354 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.984405 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.014184 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014663 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.984405 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.014184 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014663 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70431.435644 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69613.186813 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70177.303754 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65587.790537 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65587.790537 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70431.435644 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65649.976233 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 65808.505400 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70431.435644 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65649.976233 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 65808.505400 # average overall miss latency +system.cpu.l2cache.tags.occ_blocks::writebacks 19740.626067 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 685.734645 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 250.946999 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.602436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.020927 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.007658 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.631021 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29939 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 761 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1395 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27655 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.913666 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 33267098 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 33267098 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 14 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1994043 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1994057 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2066749 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2066749 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 53083 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 53083 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 14 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2047126 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2047140 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 14 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2047126 # number of overall hits +system.cpu.l2cache.overall_hits::total 2047140 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1014 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 426 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1440 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 28996 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 28996 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1014 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 29422 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 30436 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1014 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 29422 # number of overall misses +system.cpu.l2cache.overall_misses::total 30436 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 78434000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32404750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 110838750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2126346500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2126346500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 78434000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2158751250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 2237185250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 78434000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2158751250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 2237185250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1028 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1994469 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1995497 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2066749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2066749 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 82079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 82079 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1028 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2076548 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2077576 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1028 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2076548 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2077576 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.986381 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000214 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000722 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.353269 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.353269 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.986381 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.014169 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014650 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.986381 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.014169 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014650 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77351.084813 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76067.488263 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76971.354167 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73332.407918 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73332.407918 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73504.575174 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77351.084813 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73372.009041 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73504.575174 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -886,109 +883,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 197 # number of writebacks -system.cpu.l2cache.writebacks::total 197 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1010 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 455 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1465 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 28998 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1010 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 29453 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 30463 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1010 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 29453 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 30463 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58476750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 26090500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84567250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1530042250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1530042250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58476750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1556132750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1614609500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58476750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1556132750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1614609500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000228 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000734 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353354 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014663 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.984405 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014184 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.014663 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57897.772277 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57341.758242 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57725.085324 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52763.716463 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52763.716463 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57897.772277 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52834.439616 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53002.314283 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 166 # number of writebacks +system.cpu.l2cache.writebacks::total 166 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1014 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 426 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1440 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 28996 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1014 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 29422 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 30436 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1014 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 29422 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 30436 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 65771000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27116250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92887250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1763882000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1763882000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 65771000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1790998250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1856769250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 65771000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1790998250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1856769250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000214 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000722 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.353269 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.353269 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014650 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.986381 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014169 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.014650 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64862.919132 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63653.169014 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64505.034722 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60831.907849 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60831.907849 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64862.919132 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60872.756781 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61005.692272 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1995493 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1995490 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2066654 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 82065 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 82065 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2052 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219715 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6221767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265163712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 265229376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1995497 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1995496 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2066749 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 82079 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 82079 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2056 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6219844 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6221900 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 65792 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 265170944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 265236736 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4144212 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4144325 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 4144212 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4144325 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4144212 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4138760000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4144325 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4138911500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1710750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1734248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3121417250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3121601499 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 5.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1465 # Transaction distribution -system.membus.trans_dist::ReadResp 1462 # Transaction distribution -system.membus.trans_dist::Writeback 197 # Transaction distribution -system.membus.trans_dist::ReadExReq 28998 # Transaction distribution -system.membus.trans_dist::ReadExResp 28998 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 61120 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1962048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1962048 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1440 # Transaction distribution +system.membus.trans_dist::ReadResp 1439 # Transaction distribution +system.membus.trans_dist::Writeback 166 # Transaction distribution +system.membus.trans_dist::ReadExReq 28996 # Transaction distribution +system.membus.trans_dist::ReadExResp 28996 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 61037 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 61037 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 61037 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1958464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1958464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1958464 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30660 # Request fanout histogram +system.membus.snoop_fanout::samples 30602 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30660 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 30602 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30660 # Request fanout histogram -system.membus.reqLayer0.occupancy 43499500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 30602 # Request fanout histogram +system.membus.reqLayer0.occupancy 42540000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 291787500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 160392250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt index f80736ade..05a346173 100644 --- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.365989 # Number of seconds simulated -sim_ticks 365989065000 # Number of ticks simulated -final_tick 365989065000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 365989065500 # Number of ticks simulated +final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 756908 # Simulator instruction rate (inst/s) -host_op_rate 1332794 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1753418925 # Simulator tick rate (ticks/s) -host_mem_usage 446124 # Number of bytes of host memory used -host_seconds 208.73 # Real time elapsed on the host +host_inst_rate 638452 # Simulator instruction rate (inst/s) +host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1479007835 # Simulator tick rate (ticks/s) +host_mem_usage 450980 # Number of bytes of host memory used +host_seconds 247.46 # Real time elapsed on the host sim_insts 157988548 # Number of instructions simulated sim_ops 278192465 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,36 +36,10 @@ system.physmem.bw_total::writebacks 17487 # To system.physmem.bw_total::cpu.inst 140419 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 5114207 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 5272114 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1025 # Transaction distribution -system.membus.trans_dist::ReadResp 1025 # Transaction distribution -system.membus.trans_dist::Writeback 100 # Transaction distribution -system.membus.trans_dist::ReadExReq 29024 # Transaction distribution -system.membus.trans_dist::ReadExResp 29024 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 30149 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 30149 # Request fanout histogram -system.membus.reqLayer0.occupancy 30980000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 270472000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 444 # Number of system calls -system.cpu.numCycles 731978130 # number of cpu cycles simulated +system.cpu.numCycles 731978131 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 157988548 # Number of instructions committed @@ -86,7 +60,7 @@ system.cpu.num_mem_refs 122219137 # nu system.cpu.num_load_insts 90779385 # Number of load instructions system.cpu.num_store_insts 31439752 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 731978129.998000 # Number of busy cycles +system.cpu.num_busy_cycles 731978130.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 29309705 # Number of branches fetched @@ -125,13 +99,121 @@ system.cpu.op_class::MemWrite 31439752 11.30% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 278192465 # Class of executed instruction +system.cpu.dcache.tags.replacements 2062733 # number of replacements +system.cpu.dcache.tags.tagsinuse 4076.488607 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 126079702000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488607 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits +system.cpu.dcache.overall_hits::total 120152370 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses +system.cpu.dcache.overall_misses::total 2066829 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks +system.cpu.dcache.writebacks::total 2062484 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22557604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 22557604000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2439292500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2439292500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24996896500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 24996896500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24996896500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 24996896500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11504.755396 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11504.755396 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22988.554223 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22988.554223 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12094.322510 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12094.322510 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 24 # number of replacements -system.cpu.icache.tags.tagsinuse 665.632508 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 665.632506 # Cycle average of tags in use system.cpu.icache.tags.total_refs 217695356 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 808 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 269424.945545 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 665.632508 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 665.632506 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.325016 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id @@ -153,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 808 # n system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses system.cpu.icache.overall_misses::total 808 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44230000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44230000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44230000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44230000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44230000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44230500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44230500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44230500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44230500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44230500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44230500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 217696164 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 217696164 # number of demand (read+write) accesses @@ -171,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.099010 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54740.099010 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54740.099010 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.099010 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54740.099010 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54740.717822 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54740.717822 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54740.717822 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54740.717822 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54740.717822 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -191,33 +273,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 808 system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42614000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42614000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42614000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42614000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42614000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42614000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 43018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 43018500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 43018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 43018500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 43018500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 43018500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52740.099010 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52740.099010 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52740.099010 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52740.099010 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53240.717822 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53240.717822 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53240.717822 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53240.717822 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 318 # number of replacements -system.cpu.l2cache.tags.tagsinuse 20041.899765 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 20041.899592 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3992419 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 30026 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 132.965397 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 19330.353164 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646382 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 19330.352993 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 557.646380 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.data 153.900219 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.589916 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.017018 # Average percentage of cache occupancy @@ -256,17 +338,17 @@ system.cpu.l2cache.demand_misses::total 30049 # nu system.cpu.l2cache.overall_misses::cpu.inst 803 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 29246 # number of overall misses system.cpu.l2cache.overall_misses::total 30049 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11544000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 53300000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1509279000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1509279000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41756000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 1520823000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 1562579000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41756000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 1520823000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 1562579000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42158000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11655000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 53813000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1523791000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1523791000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42158000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 1535446000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 1577604000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42158000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 1535446000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 1577604000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 808 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1960720 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1961528 # number of ReadReq accesses(hits+misses) @@ -291,17 +373,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.014533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993812 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.014150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.014533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.068082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.068082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.031648 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.059974 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.031648 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.622665 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.487805 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52501.068082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52501.068082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.048288 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.622665 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.059974 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.048288 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,17 +405,17 @@ system.cpu.l2cache.demand_mshr_misses::total 30049 system.cpu.l2cache.overall_mshr_misses::cpu.inst 803 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 29246 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 30049 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1160960000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1160960000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1169840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 1201960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1169840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 1201960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32521500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8991000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41512500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1175472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1175472000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32521500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 1184463000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 1216984500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32521500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1184463000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 1216984500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000113 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000523 # mshr miss rate for ReadReq accesses @@ -345,126 +427,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.014533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993812 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.014150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.014533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2062733 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.488619 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 120152370 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2066829 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 58.133677 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 126079701000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.488619 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995236 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1796 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2178 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 6 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 246505227 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 246505227 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 88818727 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 88818727 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 31333643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 31333643 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 120152370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 120152370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 120152370 # number of overall hits -system.cpu.dcache.overall_hits::total 120152370 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1960720 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1960720 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 106109 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 106109 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2066829 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2066829 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2066829 # number of overall misses -system.cpu.dcache.overall_misses::total 2066829 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 25498684000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2598456000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 28097140000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 28097140000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 28097140000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 90779447 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 31439752 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 122219199 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 122219199 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 122219199 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 122219199 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.021599 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.003375 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016911 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016911 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.016911 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.016911 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13004.755396 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13004.755396 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24488.554223 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24488.554223 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13594.322510 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13594.322510 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2062484 # number of writebacks -system.cpu.dcache.writebacks::total 2062484 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1960720 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 106109 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 106109 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2066829 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2066829 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2066829 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21577244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21577244000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2386238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2386238000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23963482000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 23963482000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23963482000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 23963482000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.021599 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.003375 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016911 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016911 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11004.755396 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11004.755396 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22488.554223 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22488.554223 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11594.322510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 11594.322510 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1961528 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2062484 # Transaction distribution @@ -496,5 +470,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 1212000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3100243500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1025 # Transaction distribution +system.membus.trans_dist::ReadResp 1025 # Transaction distribution +system.membus.trans_dist::Writeback 100 # Transaction distribution +system.membus.trans_dist::ReadExReq 29024 # Transaction distribution +system.membus.trans_dist::ReadExResp 29024 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 60198 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1929536 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 30149 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 30149 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 30149 # Request fanout histogram +system.membus.reqLayer0.occupancy 30585000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 150276500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt index 9abbba24f..af9445aa2 100644 --- a/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.410940 # Number of seconds simulated -sim_ticks 410940483000 # Number of ticks simulated -final_tick 410940483000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.413669 # Number of seconds simulated +sim_ticks 413668621500 # Number of ticks simulated +final_tick 413668621500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207244 # Simulator instruction rate (inst/s) -host_op_rate 207244 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 139181064 # Simulator tick rate (ticks/s) -host_mem_usage 283892 # Number of bytes of host memory used -host_seconds 2952.56 # Real time elapsed on the host +host_inst_rate 330001 # Simulator instruction rate (inst/s) +host_op_rate 330001 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 223093103 # Simulator tick rate (ticks/s) +host_mem_usage 297764 # Number of bytes of host memory used +host_seconds 1854.24 # Real time elapsed on the host sim_insts 611901617 # Number of instructions simulated sim_ops 611901617 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 171008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24149568 # Number of bytes read from this memory -system.physmem.bytes_read::total 24320576 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 171008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 171008 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18724416 # Number of bytes written to this memory -system.physmem.bytes_written::total 18724416 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2672 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 377337 # Number of read requests responded to by this memory -system.physmem.num_reads::total 380009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292569 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292569 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 416138 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 58766583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 59182721 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 416138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 416138 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 45564788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 45564788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 45564788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 416138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 58766583 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 104747509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 380009 # Number of read requests accepted -system.physmem.writeReqs 292569 # Number of write requests accepted -system.physmem.readBursts 380009 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292569 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24297024 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 23552 # Total number of bytes read from write queue +system.physmem.bytes_read::cpu.inst 170880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24149824 # Number of bytes read from this memory +system.physmem.bytes_read::total 24320704 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 170880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 170880 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18724288 # Number of bytes written to this memory +system.physmem.bytes_written::total 18724288 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 2670 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 377341 # Number of read requests responded to by this memory +system.physmem.num_reads::total 380011 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292567 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292567 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 413084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 58379637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 58792721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 413084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 413084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 45263979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 45263979 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 45263979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 413084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 58379637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 104056701 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 380011 # Number of read requests accepted +system.physmem.writeReqs 292567 # Number of write requests accepted +system.physmem.readBursts 380011 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292567 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24296448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 24256 # Total number of bytes read from write queue system.physmem.bytesWritten 18722752 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24320576 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18724416 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 368 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesReadSys 24320704 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18724288 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 379 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 23736 # Per bank write bursts -system.physmem.perBankRdBursts::1 23216 # Per bank write bursts -system.physmem.perBankRdBursts::2 23510 # Per bank write bursts -system.physmem.perBankRdBursts::3 24529 # Per bank write bursts -system.physmem.perBankRdBursts::4 25457 # Per bank write bursts -system.physmem.perBankRdBursts::5 23594 # Per bank write bursts -system.physmem.perBankRdBursts::6 23677 # Per bank write bursts -system.physmem.perBankRdBursts::7 23981 # Per bank write bursts -system.physmem.perBankRdBursts::8 23173 # Per bank write bursts -system.physmem.perBankRdBursts::9 23945 # Per bank write bursts -system.physmem.perBankRdBursts::10 24675 # Per bank write bursts -system.physmem.perBankRdBursts::11 22741 # Per bank write bursts -system.physmem.perBankRdBursts::12 23723 # Per bank write bursts -system.physmem.perBankRdBursts::13 24409 # Per bank write bursts -system.physmem.perBankRdBursts::14 22807 # Per bank write bursts -system.physmem.perBankRdBursts::15 22468 # Per bank write bursts +system.physmem.perBankRdBursts::0 23738 # Per bank write bursts +system.physmem.perBankRdBursts::1 23215 # Per bank write bursts +system.physmem.perBankRdBursts::2 23512 # Per bank write bursts +system.physmem.perBankRdBursts::3 24525 # Per bank write bursts +system.physmem.perBankRdBursts::4 25461 # Per bank write bursts +system.physmem.perBankRdBursts::5 23591 # Per bank write bursts +system.physmem.perBankRdBursts::6 23667 # Per bank write bursts +system.physmem.perBankRdBursts::7 23972 # Per bank write bursts +system.physmem.perBankRdBursts::8 23176 # Per bank write bursts +system.physmem.perBankRdBursts::9 23948 # Per bank write bursts +system.physmem.perBankRdBursts::10 24672 # Per bank write bursts +system.physmem.perBankRdBursts::11 22745 # Per bank write bursts +system.physmem.perBankRdBursts::12 23724 # Per bank write bursts +system.physmem.perBankRdBursts::13 24415 # Per bank write bursts +system.physmem.perBankRdBursts::14 22805 # Per bank write bursts +system.physmem.perBankRdBursts::15 22466 # Per bank write bursts system.physmem.perBankWrBursts::0 17754 # Per bank write bursts -system.physmem.perBankWrBursts::1 17431 # Per bank write bursts -system.physmem.perBankWrBursts::2 17901 # Per bank write bursts -system.physmem.perBankWrBursts::3 18773 # Per bank write bursts +system.physmem.perBankWrBursts::1 17430 # Per bank write bursts +system.physmem.perBankWrBursts::2 17902 # Per bank write bursts +system.physmem.perBankWrBursts::3 18771 # Per bank write bursts system.physmem.perBankWrBursts::4 19442 # Per bank write bursts system.physmem.perBankWrBursts::5 18543 # Per bank write bursts -system.physmem.perBankWrBursts::6 18677 # Per bank write bursts -system.physmem.perBankWrBursts::7 18574 # Per bank write bursts -system.physmem.perBankWrBursts::8 18352 # Per bank write bursts +system.physmem.perBankWrBursts::6 18683 # Per bank write bursts +system.physmem.perBankWrBursts::7 18577 # Per bank write bursts +system.physmem.perBankWrBursts::8 18350 # Per bank write bursts system.physmem.perBankWrBursts::9 18833 # Per bank write bursts -system.physmem.perBankWrBursts::10 19127 # Per bank write bursts -system.physmem.perBankWrBursts::11 17966 # Per bank write bursts -system.physmem.perBankWrBursts::12 18224 # Per bank write bursts -system.physmem.perBankWrBursts::13 18695 # Per bank write bursts -system.physmem.perBankWrBursts::14 17148 # Per bank write bursts +system.physmem.perBankWrBursts::10 19129 # Per bank write bursts +system.physmem.perBankWrBursts::11 17963 # Per bank write bursts +system.physmem.perBankWrBursts::12 18222 # Per bank write bursts +system.physmem.perBankWrBursts::13 18694 # Per bank write bursts +system.physmem.perBankWrBursts::14 17147 # Per bank write bursts system.physmem.perBankWrBursts::15 17103 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 410940401000 # Total gap between requests +system.physmem.totGap 413668533000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 380009 # Read request sizes (log2) +system.physmem.readPktSize::6 380011 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292569 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 378252 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1375 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292567 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 378248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,40 +144,40 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 7441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17416 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17420 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17410 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17492 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17454 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 20 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 7429 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17382 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17407 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17276 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 12 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see @@ -193,126 +193,128 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142331 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 302.240383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.797095 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 325.472154 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 51326 36.06% 36.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38738 27.22% 63.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13057 9.17% 72.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7891 5.54% 78.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5698 4.00% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3672 2.58% 84.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3107 2.18% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2648 1.86% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16194 11.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142331 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17261 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 21.992932 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 228.052387 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17249 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 142473 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 301.943638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 179.238649 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.808189 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 51183 35.92% 35.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 38564 27.07% 62.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13147 9.23% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 8365 5.87% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5777 4.05% 82.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3877 2.72% 84.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2993 2.10% 86.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2580 1.81% 88.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 15987 11.22% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 142473 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17260 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 21.993917 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 228.515702 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17249 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 2 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17261 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17261 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.948207 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.879580 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.601828 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17058 98.82% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 154 0.89% 99.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.14% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 10 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17260 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17260 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.949189 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.879017 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.574623 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17060 98.84% 98.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 147 0.85% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 31 0.18% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 6 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 3 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 2 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 1 0.01% 99.96% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::60-63 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::120-123 2 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17261 # Writes before turning the bus around for reads -system.physmem.totQLat 4019056000 # Total ticks spent queuing -system.physmem.totMemAccLat 11137324750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1898205000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10586.46 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::216-219 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 17260 # Writes before turning the bus around for reads +system.physmem.totQLat 4063422250 # Total ticks spent queuing +system.physmem.totMemAccLat 11181522250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1898160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10703.58 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29336.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 59.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 45.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 59.18 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 45.56 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29453.58 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 58.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 45.26 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 58.79 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 45.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.82 # Data bus utilization in percentage +system.physmem.busUtil 0.81 # Data bus utilization in percentage system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.36 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.74 # Average write queue length when enqueuing -system.physmem.readRowHits 314673 # Number of row buffer hits during reads -system.physmem.writeRowHits 215171 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.89 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.55 # Row buffer hit rate for writes -system.physmem.avgGap 610992.93 # Average gap between requests -system.physmem.pageHitRate 78.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 547495200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 298732500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1495119600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 953078400 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 61546767165 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 192572713500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 284254177485 # Total energy per rank (pJ) -system.physmem_0.averagePower 691.725104 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 319820574750 # Time in different power states -system.physmem_0.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem.avgWrQLen 20.80 # Average write queue length when enqueuing +system.physmem.readRowHits 314502 # Number of row buffer hits during reads +system.physmem.writeRowHits 215198 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.84 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.56 # Row buffer hit rate for writes +system.physmem.avgGap 615049.16 # Average gap between requests +system.physmem.pageHitRate 78.80 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 548387280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 299219250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1495111800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 953220960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 27018775680 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 62462923605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 193408851750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 286186490325 # Total energy per rank (pJ) +system.physmem_0.averagePower 691.826263 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 321201361250 # Time in different power states +system.physmem_0.memoryStateTime::REF 13813280000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 77392866750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 78653522500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 528262560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 288238500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1465495200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 942392880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26840271120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 58539586815 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 195210595500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 283814842575 # Total energy per rank (pJ) -system.physmem_1.averagePower 690.655981 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 324225356250 # Time in different power states -system.physmem_1.memoryStateTime::REF 13722020000 # Time in different power states +system.physmem_1.actEnergy 528708600 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 288481875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1465971000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 942457680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 27018775680 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 59403829365 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 196092272250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 285740496450 # Total energy per rank (pJ) +system.physmem_1.averagePower 690.748106 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 325682433750 # Time in different power states +system.physmem_1.memoryStateTime::REF 13813280000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 72987820500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 74172457500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 124267347 # Number of BP lookups -system.cpu.branchPred.condPredicted 87926966 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6405633 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 71910290 # Number of BTB lookups -system.cpu.branchPred.BTBHits 67438494 # Number of BTB hits +system.cpu.branchPred.lookups 124268150 # Number of BP lookups +system.cpu.branchPred.condPredicted 87927054 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6406473 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 71778224 # Number of BTB lookups +system.cpu.branchPred.BTBHits 67442624 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.781424 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15062581 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1126311 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.959728 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15063408 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1126260 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 149395037 # DTB read hits -system.cpu.dtb.read_misses 569044 # DTB read misses +system.cpu.dtb.read_hits 149394774 # DTB read hits +system.cpu.dtb.read_misses 568338 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 149964081 # DTB read accesses -system.cpu.dtb.write_hits 57322306 # DTB write hits -system.cpu.dtb.write_misses 67257 # DTB write misses +system.cpu.dtb.read_accesses 149963112 # DTB read accesses +system.cpu.dtb.write_hits 57322660 # DTB write hits +system.cpu.dtb.write_misses 67060 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 57389563 # DTB write accesses -system.cpu.dtb.data_hits 206717343 # DTB hits -system.cpu.dtb.data_misses 636301 # DTB misses +system.cpu.dtb.write_accesses 57389720 # DTB write accesses +system.cpu.dtb.data_hits 206717434 # DTB hits +system.cpu.dtb.data_misses 635398 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 207353644 # DTB accesses -system.cpu.itb.fetch_hits 226796884 # ITB hits +system.cpu.dtb.data_accesses 207352832 # DTB accesses +system.cpu.itb.fetch_hits 226805869 # ITB hits system.cpu.itb.fetch_misses 48 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 226796932 # ITB accesses +system.cpu.itb.fetch_accesses 226805917 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -326,66 +328,66 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 485 # Number of system calls -system.cpu.numCycles 821880966 # number of cpu cycles simulated +system.cpu.numCycles 827337243 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 611901617 # Number of instructions committed system.cpu.committedOps 611901617 # Number of ops (including micro ops) committed -system.cpu.discardedOps 12979255 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 12980749 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.343159 # CPI: cycles per instruction -system.cpu.ipc 0.744514 # IPC: instructions per cycle -system.cpu.tickCycles 741712966 # Number of cycles that the object actually ticked -system.cpu.idleCycles 80168000 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 2535450 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.778260 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 202631199 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2539546 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 79.790324 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1608227250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.778260 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997993 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997993 # Average percentage of cache occupancy +system.cpu.cpi 1.352076 # CPI: cycles per instruction +system.cpu.ipc 0.739604 # IPC: instructions per cycle +system.cpu.tickCycles 741744427 # Number of cycles that the object actually ticked +system.cpu.idleCycles 85592816 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 2535433 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.647440 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 202630848 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2539529 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 79.790720 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1642835250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647440 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 829 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3145 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 830 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3144 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 414706244 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 414706244 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 146964985 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 146964985 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 55666214 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 55666214 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 202631199 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 202631199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 202631199 # number of overall hits -system.cpu.dcache.overall_hits::total 202631199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1908330 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1908330 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1543820 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1543820 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3452150 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3452150 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3452150 # number of overall misses -system.cpu.dcache.overall_misses::total 3452150 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 36414832750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 36414832750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 44905898000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 44905898000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 81320730750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 81320730750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 81320730750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 81320730750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 148873315 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 148873315 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 414705331 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 414705331 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 146964653 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 146964653 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 55666195 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 55666195 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 202630848 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 202630848 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 202630848 # number of overall hits +system.cpu.dcache.overall_hits::total 202630848 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1908214 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1908214 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1543839 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1543839 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3452053 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3452053 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3452053 # number of overall misses +system.cpu.dcache.overall_misses::total 3452053 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 37787863500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 37787863500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48074024750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48074024750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 85861888250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 85861888250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 85861888250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 85861888250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 148872867 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 148872867 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 57210034 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 57210034 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 206083349 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 206083349 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 206083349 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 206083349 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 206082901 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 206082901 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 206082901 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 206082901 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012818 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026985 # miss rate for WriteReq accesses @@ -394,14 +396,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.016751 system.cpu.dcache.demand_miss_rate::total 0.016751 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.016751 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.016751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19082.041759 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19082.041759 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29087.521861 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29087.521861 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 23556.546138 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 23556.546138 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 23556.546138 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19802.738844 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19802.738844 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31139.273428 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31139.273428 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24872.702780 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24872.702780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24872.702780 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24872.702780 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -410,32 +412,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2340060 # number of writebacks -system.cpu.dcache.writebacks::total 2340060 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143560 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 143560 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769044 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 769044 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 912604 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 912604 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 912604 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 912604 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764770 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1764770 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774776 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 774776 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2539546 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2539546 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2539546 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2539546 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30222614500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30222614500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 21167535500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 21167535500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 51390150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 51390150000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 51390150000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 51390150000 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 2340050 # number of writebacks +system.cpu.dcache.writebacks::total 2340050 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 143464 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 143464 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 769060 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 769060 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 912524 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 912524 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 912524 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 912524 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1764750 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1764750 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 774779 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 774779 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2539529 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2539529 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2539529 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2539529 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32323432750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32323432750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 23036899500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 23036899500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 55360332250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 55360332250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 55360332250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 55360332250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.011854 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.013543 # mshr miss rate for WriteReq accesses @@ -444,69 +446,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012323 system.cpu.dcache.demand_mshr_miss_rate::total 0.012323 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012323 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.012323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17125.525989 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17125.525989 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27320.845638 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27320.845638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20235.959498 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20235.959498 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18316.153988 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18316.153988 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 29733.510459 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 29733.510459 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21799.448736 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21799.448736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21799.448736 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21799.448736 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 3192 # number of replacements -system.cpu.icache.tags.tagsinuse 1117.017357 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 226791863 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5021 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 45168.664210 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 3160 # number of replacements +system.cpu.icache.tags.tagsinuse 1117.931154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 226800880 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4989 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 45460.188415 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1117.017357 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.545419 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.545419 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1117.931154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.545865 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.545865 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1590 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 70 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 77 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 453598789 # Number of tag accesses -system.cpu.icache.tags.data_accesses 453598789 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 226791863 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 226791863 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 226791863 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 226791863 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 226791863 # number of overall hits -system.cpu.icache.overall_hits::total 226791863 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5021 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5021 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5021 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5021 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5021 # number of overall misses -system.cpu.icache.overall_misses::total 5021 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 229227250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 229227250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 229227250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 229227250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 229227250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 229227250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 226796884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 226796884 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 226796884 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 226796884 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 226796884 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 226796884 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 453616727 # Number of tag accesses +system.cpu.icache.tags.data_accesses 453616727 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 226800880 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 226800880 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 226800880 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 226800880 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 226800880 # number of overall hits +system.cpu.icache.overall_hits::total 226800880 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4989 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4989 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4989 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4989 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4989 # number of overall misses +system.cpu.icache.overall_misses::total 4989 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 247276500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 247276500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 247276500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 247276500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 247276500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 247276500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 226805869 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 226805869 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 226805869 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 226805869 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 226805869 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 226805869 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000022 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45653.704441 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 45653.704441 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 45653.704441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 45653.704441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 45653.704441 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49564.341551 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49564.341551 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49564.341551 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49564.341551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49564.341551 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49564.341551 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,123 +517,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5021 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5021 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5021 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5021 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5021 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5021 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 218087750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 218087750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 218087750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 218087750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 218087750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 218087750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4989 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4989 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4989 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4989 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4989 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4989 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 238690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 238690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 238690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 238690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 238690000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 238690000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 43435.122486 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 43435.122486 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 43435.122486 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 43435.122486 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 43435.122486 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 43435.122486 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47843.255161 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47843.255161 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47843.255161 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47843.255161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47843.255161 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47843.255161 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 347298 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29498.877271 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3711146 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 379722 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.773324 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 188676425000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21419.098483 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 178.648433 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7901.130355 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.653659 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005452 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.241123 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.900234 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 347300 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29504.344374 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3711084 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 379724 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.773109 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 189731783500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21417.549269 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 178.140463 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7908.654642 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.653612 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005436 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.241353 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.900401 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32424 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13171 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18831 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13175 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 18827 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.989502 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 40234870 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 40234870 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2349 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1590703 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1593052 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2340060 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2340060 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 571506 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 571506 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2349 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2162209 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2164558 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2349 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2162209 # number of overall hits -system.cpu.l2cache.overall_hits::total 2164558 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2672 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 170711 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 173383 # number of ReadReq misses +system.cpu.l2cache.tags.tag_accesses 40234408 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 40234408 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2319 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1590674 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1592993 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2340050 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2340050 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 571514 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 571514 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2319 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2162188 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2164507 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2319 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2162188 # number of overall hits +system.cpu.l2cache.overall_hits::total 2164507 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2670 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 170715 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 173385 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 206626 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 206626 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2672 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 377337 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 380009 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2672 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 377337 # number of overall misses -system.cpu.l2cache.overall_misses::total 380009 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 189570250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12482834000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12672404250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14718134000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14718134000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 189570250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27200968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 27390538250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 189570250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27200968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 27390538250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5021 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1761414 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1766435 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2340060 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2340060 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 778132 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 778132 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5021 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2539546 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2544567 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5021 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2539546 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2544567 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.532165 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.096917 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.098154 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265541 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.265541 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.532165 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.148584 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.149341 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.532165 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.148584 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.149341 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70946.949850 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73122.610728 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73089.081686 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71230.793801 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71230.793801 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70946.949850 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72086.670536 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72078.656690 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70946.949850 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72086.670536 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72078.656690 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 2670 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 377341 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 380011 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2670 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 377341 # number of overall misses +system.cpu.l2cache.overall_misses::total 380011 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 209339000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13791460250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14000799250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16303609000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16303609000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 209339000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30095069250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30304408250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 209339000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30095069250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30304408250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4989 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1761389 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1766378 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2340050 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2340050 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 778140 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 778140 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4989 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2539529 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2544518 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4989 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2539529 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2544518 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.535177 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.096921 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.098158 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.265538 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.265538 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.535177 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.148587 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.149345 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.535177 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.148587 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.149345 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78404.119850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80786.458425 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80749.772183 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78903.956908 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78903.956908 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78404.119850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79755.630186 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79746.134322 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78404.119850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79755.630186 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79746.134322 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,89 +642,89 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292569 # number of writebacks -system.cpu.l2cache.writebacks::total 292569 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2672 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 170711 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 173383 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 292567 # number of writebacks +system.cpu.l2cache.writebacks::total 292567 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2670 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 170715 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 173385 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 206626 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 206626 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2672 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 377337 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 380009 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2672 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 377337 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 380009 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 155967750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10304871500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10460839250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12089060000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12089060000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 155967750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22393931500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22549899250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 155967750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22393931500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22549899250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096917 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098154 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265541 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148584 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.149341 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.532165 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148584 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.149341 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58371.163922 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60364.425843 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60333.707745 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58506.964274 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58506.964274 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58371.163922 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59347.298304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59340.434700 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2670 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 377341 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380011 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2670 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 377341 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 380011 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175922000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11655046250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11830968250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13719523500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13719523500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175922000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25374569750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25550491750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175922000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25374569750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25550491750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.096921 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.098158 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.265538 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.265538 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.148587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.149345 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.535177 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.148587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.149345 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65888.389513 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68271.951791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68235.246705 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66397.856514 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66397.856514 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65888.389513 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67245.726677 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67236.189873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65888.389513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67245.726677 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67236.189873 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1766435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1766435 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2340060 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 778132 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 778132 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10042 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419152 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7429194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 321344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312294784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312616128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 1766378 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1766378 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2340050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 778140 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 778140 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9978 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7419108 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7429086 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 319296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312293056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312612352 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4884627 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 4884568 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 4884627 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 4884568 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4884627 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4782373500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4884568 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4782334000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8080250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8035000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3891629500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3891583750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 173383 # Transaction distribution -system.membus.trans_dist::ReadResp 173383 # Transaction distribution -system.membus.trans_dist::Writeback 292569 # Transaction distribution +system.membus.trans_dist::ReadReq 173385 # Transaction distribution +system.membus.trans_dist::ReadResp 173385 # Transaction distribution +system.membus.trans_dist::Writeback 292567 # Transaction distribution system.membus.trans_dist::ReadExReq 206626 # Transaction distribution system.membus.trans_dist::ReadExResp 206626 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052587 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1052587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1052589 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1052589 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43044992 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 43044992 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) @@ -736,9 +738,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 672578 # Request fanout histogram -system.membus.reqLayer0.occupancy 3222626500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3617752750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 1986204500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2010997250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt index 441853c88..8128561b2 100644 --- a/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.365317 # Number of seconds simulated -sim_ticks 365317233000 # Number of ticks simulated -final_tick 365317233000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.366359 # Number of seconds simulated +sim_ticks 366358704500 # Number of ticks simulated +final_tick 366358704500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 157262 # Simulator instruction rate (inst/s) -host_op_rate 170335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 113407877 # Simulator tick rate (ticks/s) -host_mem_usage 304680 # Number of bytes of host memory used -host_seconds 3221.27 # Real time elapsed on the host +host_inst_rate 242855 # Simulator instruction rate (inst/s) +host_op_rate 263044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 175631724 # Simulator tick rate (ticks/s) +host_mem_usage 316616 # Number of bytes of host memory used +host_seconds 2085.95 # Real time elapsed on the host sim_insts 506582155 # Number of instructions simulated sim_ops 548695378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 222144 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9003904 # Number of bytes read from this memory -system.physmem.bytes_read::total 9226048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 222144 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 222144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6179904 # Number of bytes written to this memory -system.physmem.bytes_written::total 6179904 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3471 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140686 # Number of read requests responded to by this memory -system.physmem.num_reads::total 144157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 96561 # Number of write requests responded to by this memory -system.physmem.num_writes::total 96561 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 608085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 24646809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 25254894 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 608085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 608085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 16916541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 16916541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 16916541 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 608085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 24646809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42171435 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 144157 # Number of read requests accepted -system.physmem.writeReqs 96561 # Number of write requests accepted -system.physmem.readBursts 144157 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 96561 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9219904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 6178688 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9226048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6179904 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 221696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9006016 # Number of bytes read from this memory +system.physmem.bytes_read::total 9227712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221696 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6179648 # Number of bytes written to this memory +system.physmem.bytes_written::total 6179648 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3464 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140719 # Number of read requests responded to by this memory +system.physmem.num_reads::total 144183 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 96557 # Number of write requests responded to by this memory +system.physmem.num_writes::total 96557 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 605134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 24582509 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 25187642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 605134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605134 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 16867753 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 16867753 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 16867753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 605134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 24582509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 42055395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 144183 # Number of read requests accepted +system.physmem.writeReqs 96557 # Number of write requests accepted +system.physmem.readBursts 144183 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 96557 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9220288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7424 # Total number of bytes read from write queue +system.physmem.bytesWritten 6178496 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9227712 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6179648 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 116 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 9347 # Per bank write bursts -system.physmem.perBankRdBursts::1 8970 # Per bank write bursts -system.physmem.perBankRdBursts::2 8998 # Per bank write bursts -system.physmem.perBankRdBursts::3 8695 # Per bank write bursts +system.physmem.perBankRdBursts::1 9007 # Per bank write bursts +system.physmem.perBankRdBursts::2 8992 # Per bank write bursts +system.physmem.perBankRdBursts::3 8698 # Per bank write bursts system.physmem.perBankRdBursts::4 9455 # Per bank write bursts system.physmem.perBankRdBursts::5 9342 # Per bank write bursts -system.physmem.perBankRdBursts::6 8947 # Per bank write bursts -system.physmem.perBankRdBursts::7 8101 # Per bank write bursts -system.physmem.perBankRdBursts::8 8578 # Per bank write bursts +system.physmem.perBankRdBursts::6 8946 # Per bank write bursts +system.physmem.perBankRdBursts::7 8102 # Per bank write bursts +system.physmem.perBankRdBursts::8 8570 # Per bank write bursts system.physmem.perBankRdBursts::9 8679 # Per bank write bursts -system.physmem.perBankRdBursts::10 8774 # Per bank write bursts -system.physmem.perBankRdBursts::11 9477 # Per bank write bursts +system.physmem.perBankRdBursts::10 8773 # Per bank write bursts +system.physmem.perBankRdBursts::11 9476 # Per bank write bursts system.physmem.perBankRdBursts::12 9374 # Per bank write bursts -system.physmem.perBankRdBursts::13 9525 # Per bank write bursts +system.physmem.perBankRdBursts::13 9521 # Per bank write bursts system.physmem.perBankRdBursts::14 8712 # Per bank write bursts -system.physmem.perBankRdBursts::15 9087 # Per bank write bursts -system.physmem.perBankWrBursts::0 6196 # Per bank write bursts -system.physmem.perBankWrBursts::1 6092 # Per bank write bursts -system.physmem.perBankWrBursts::2 6006 # Per bank write bursts -system.physmem.perBankWrBursts::3 5813 # Per bank write bursts +system.physmem.perBankRdBursts::15 9073 # Per bank write bursts +system.physmem.perBankWrBursts::0 6191 # Per bank write bursts +system.physmem.perBankWrBursts::1 6098 # Per bank write bursts +system.physmem.perBankWrBursts::2 6005 # Per bank write bursts +system.physmem.perBankWrBursts::3 5815 # Per bank write bursts system.physmem.perBankWrBursts::4 6163 # Per bank write bursts -system.physmem.perBankWrBursts::5 6172 # Per bank write bursts +system.physmem.perBankWrBursts::5 6174 # Per bank write bursts system.physmem.perBankWrBursts::6 6014 # Per bank write bursts -system.physmem.perBankWrBursts::7 5493 # Per bank write bursts -system.physmem.perBankWrBursts::8 5728 # Per bank write bursts -system.physmem.perBankWrBursts::9 5823 # Per bank write bursts -system.physmem.perBankWrBursts::10 5962 # Per bank write bursts +system.physmem.perBankWrBursts::7 5494 # Per bank write bursts +system.physmem.perBankWrBursts::8 5727 # Per bank write bursts +system.physmem.perBankWrBursts::9 5822 # Per bank write bursts +system.physmem.perBankWrBursts::10 5961 # Per bank write bursts system.physmem.perBankWrBursts::11 6445 # Per bank write bursts system.physmem.perBankWrBursts::12 6308 # Per bank write bursts -system.physmem.perBankWrBursts::13 6282 # Per bank write bursts -system.physmem.perBankWrBursts::14 5997 # Per bank write bursts -system.physmem.perBankWrBursts::15 6048 # Per bank write bursts +system.physmem.perBankWrBursts::13 6277 # Per bank write bursts +system.physmem.perBankWrBursts::14 5998 # Per bank write bursts +system.physmem.perBankWrBursts::15 6047 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 365317203500 # Total gap between requests +system.physmem.totGap 366358675500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 144157 # Read request sizes (log2) +system.physmem.readPktSize::6 144183 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 96561 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 143694 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 347 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see +system.physmem.writePktSize::6 96557 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 143693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 352 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,37 +144,37 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2930 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 3119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5664 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5666 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5692 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5643 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5596 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5533 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5657 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5587 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see @@ -193,110 +193,112 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 65080 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 236.601352 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 156.588709 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 242.751381 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24737 38.01% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18138 27.87% 65.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6930 10.65% 76.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7871 12.09% 88.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2125 3.27% 91.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1134 1.74% 93.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 708 1.09% 94.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 644 0.99% 95.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 2793 4.29% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 65080 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5572 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.854092 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 382.114973 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5569 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 65205 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 236.159558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 156.546491 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 241.906067 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24752 37.96% 37.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18185 27.89% 65.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7019 10.76% 76.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7903 12.12% 88.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2061 3.16% 91.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1167 1.79% 93.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 745 1.14% 94.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 604 0.93% 95.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 2769 4.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65205 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5568 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.873563 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 382.195910 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5565 99.95% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 2 0.04% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5572 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5572 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.326274 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.230410 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.286782 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-17 2628 47.16% 47.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18-19 2789 50.05% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-21 53 0.95% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22-23 30 0.54% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-25 23 0.41% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26-27 9 0.16% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-29 9 0.16% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30-31 6 0.11% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-33 7 0.13% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34-35 3 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-37 1 0.02% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::38-39 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-41 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::42-43 2 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-45 2 0.04% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::46-47 2 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::54-55 1 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::70-71 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 5568 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5568 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.338182 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.234627 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.449204 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-17 2631 47.25% 47.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18-19 2778 49.89% 97.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-21 61 1.10% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22-23 29 0.52% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-25 20 0.36% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26-27 10 0.18% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-29 6 0.11% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30-31 7 0.13% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-33 5 0.09% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34-35 2 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-37 5 0.09% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38-39 2 0.04% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-41 2 0.04% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42-43 2 0.04% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46-47 1 0.02% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-53 2 0.04% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-57 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::58-59 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-61 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-73 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::78-79 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5572 # Writes before turning the bus around for reads -system.physmem.totQLat 1534207250 # Total ticks spent queuing -system.physmem.totMemAccLat 4235351000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 720305000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10649.71 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 5568 # Writes before turning the bus around for reads +system.physmem.totQLat 1536843000 # Total ticks spent queuing +system.physmem.totMemAccLat 4238099250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 720335000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10667.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29399.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 25.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 16.91 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 25.25 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 16.92 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29417.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 25.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 16.86 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 25.19 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 16.87 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.20 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.13 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 20.29 # Average write queue length when enqueuing -system.physmem.readRowHits 111019 # Number of row buffer hits during reads -system.physmem.writeRowHits 64498 # Number of row buffer hits during writes -system.physmem.readRowHitRate 77.06 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.80 # Row buffer hit rate for writes -system.physmem.avgGap 1517614.82 # Average gap between requests -system.physmem.pageHitRate 72.94 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 247892400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 135258750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 560445600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 310566960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 47138982615 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 177839337750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 250093102155 # Total energy per rank (pJ) -system.physmem_0.averagePower 684.594758 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 295545266000 # Time in different power states -system.physmem_0.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 20.79 # Average write queue length when enqueuing +system.physmem.readRowHits 110982 # Number of row buffer hits during reads +system.physmem.writeRowHits 64419 # Number of row buffer hits during writes +system.physmem.readRowHitRate 77.03 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 66.72 # Row buffer hit rate for writes +system.physmem.avgGap 1521802.26 # Average gap between requests +system.physmem.pageHitRate 72.89 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 248111640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 135378375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 560734200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 310741920 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 47516601060 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 178134108000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 250834440315 # Total energy per rank (pJ) +system.physmem_0.averagePower 684.668623 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 296034178750 # Time in different power states +system.physmem_0.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 57571800000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 58091210000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 244014120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 133142625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 563058600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 314817840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 23860618080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 46734210225 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 178194401250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 250044262740 # Total energy per rank (pJ) -system.physmem_1.averagePower 684.461067 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 296138902500 # Time in different power states -system.physmem_1.memoryStateTime::REF 12198680000 # Time in different power states +system.physmem_1.actEnergy 244838160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 133592250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 562988400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 314830800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 23928765120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 46994125095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 178592423250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 250771563075 # Total energy per rank (pJ) +system.physmem_1.averagePower 684.496987 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 296797282750 # Time in different power states +system.physmem_1.memoryStateTime::REF 12233260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 56977968750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 57328110000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 132578917 # Number of BP lookups -system.cpu.branchPred.condPredicted 98507789 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6555100 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 69037584 # Number of BTB lookups -system.cpu.branchPred.BTBHits 64855119 # Number of BTB hits +system.cpu.branchPred.lookups 132587783 # Number of BP lookups +system.cpu.branchPred.condPredicted 98513206 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6558220 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 68845364 # Number of BTB lookups +system.cpu.branchPred.BTBHits 64852055 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.941756 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 10014942 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 17500 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 94.199596 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 10016928 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17846 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -415,74 +417,74 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 730634466 # number of cpu cycles simulated +system.cpu.numCycles 732717409 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 506582155 # Number of instructions committed system.cpu.committedOps 548695378 # Number of ops (including micro ops) committed -system.cpu.discardedOps 13461155 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 13466110 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.442282 # CPI: cycles per instruction -system.cpu.ipc 0.693346 # IPC: instructions per cycle -system.cpu.tickCycles 695780172 # Number of cycles that the object actually ticked -system.cpu.idleCycles 34854294 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 1139812 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.074819 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 171281876 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1143908 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 149.733961 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 4867376000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.074819 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993915 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993915 # Average percentage of cache occupancy +system.cpu.cpi 1.446394 # CPI: cycles per instruction +system.cpu.ipc 0.691375 # IPC: instructions per cycle +system.cpu.tickCycles 695820940 # Number of cycles that the object actually ticked +system.cpu.idleCycles 36896469 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 1139887 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.954708 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 171283476 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1143983 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 149.725543 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 4900143250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.954708 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993885 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993885 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 545 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3506 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 346818362 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 346818362 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114766084 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114766084 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 53538710 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 53538710 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 346821767 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 346821767 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114767712 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114767712 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 53538682 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 53538682 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488541 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 1488541 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168304794 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168304794 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168304794 # number of overall hits -system.cpu.dcache.overall_hits::total 168304794 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 854755 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 854755 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 700596 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 700596 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1555351 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1555351 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1555351 # number of overall misses -system.cpu.dcache.overall_misses::total 1555351 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 13707430482 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 13707430482 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20521575250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20521575250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34229005732 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34229005732 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34229005732 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34229005732 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 115620839 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 115620839 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168306394 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168306394 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168306394 # number of overall hits +system.cpu.dcache.overall_hits::total 168306394 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 854792 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 854792 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700624 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700624 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1555416 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1555416 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1555416 # number of overall misses +system.cpu.dcache.overall_misses::total 1555416 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 14024046732 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 14024046732 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22031424000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22031424000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36055470732 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36055470732 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36055470732 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36055470732 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 115622504 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 115622504 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 1488541 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 169860145 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 169860145 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 169860145 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 169860145 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 169861810 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 169861810 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 169861810 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 169861810 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.007393 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012917 # miss rate for WriteReq accesses @@ -491,14 +493,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.009157 system.cpu.dcache.demand_miss_rate::total 0.009157 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.009157 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.009157 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16036.677740 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 16036.677740 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29291.596369 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 29291.596369 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22007.254782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22007.254782 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22007.254782 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16406.385100 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16406.385100 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31445.431501 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31445.431501 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 23180.596530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 23180.596530 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 23180.596530 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -507,103 +509,103 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1068525 # number of writebacks -system.cpu.dcache.writebacks::total 1068525 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66991 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66991 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344452 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 344452 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 411443 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 411443 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 411443 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 411443 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787764 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 787764 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356144 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 356144 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1143908 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1143908 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1143908 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1143908 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11252029015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 11252029015 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10073374750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10073374750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21325403765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21325403765 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21325403765 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 21325403765 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006813 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006813 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 1068568 # number of writebacks +system.cpu.dcache.writebacks::total 1068568 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66956 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66956 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 344477 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 344477 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 411433 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 411433 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 411433 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 411433 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 787836 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 787836 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 356147 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 356147 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1143983 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1143983 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1143983 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1143983 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11930645015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11930645015 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10967643750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10967643750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22898288765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22898288765 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 22898288765 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 22898288765 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006814 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006814 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006566 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006566 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006734 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006734 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14283.502439 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14283.502439 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28284.555545 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28284.555545 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18642.586436 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 18642.586436 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006735 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006735 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006735 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15143.564162 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15143.564162 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30795.272037 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30795.272037 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20016.284127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20016.284127 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 17690 # number of replacements -system.cpu.icache.tags.tagsinuse 1190.635807 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 200942292 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 19563 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10271.547922 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 17670 # number of replacements +system.cpu.icache.tags.tagsinuse 1190.214047 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 200949213 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 19542 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 10282.939975 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1190.635807 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.581365 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.581365 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1873 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1190.214047 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.581159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.581159 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1872 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1406 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.914551 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 401943273 # Number of tag accesses -system.cpu.icache.tags.data_accesses 401943273 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 200942292 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 200942292 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 200942292 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 200942292 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 200942292 # number of overall hits -system.cpu.icache.overall_hits::total 200942292 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 19563 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 19563 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 19563 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 19563 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 19563 # number of overall misses -system.cpu.icache.overall_misses::total 19563 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 469537995 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 469537995 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 469537995 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 469537995 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 469537995 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 469537995 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 200961855 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 200961855 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 200961855 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 200961855 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 200961855 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 200961855 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 303 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.914062 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 401957052 # Number of tag accesses +system.cpu.icache.tags.data_accesses 401957052 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 200949213 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 200949213 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 200949213 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 200949213 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 200949213 # number of overall hits +system.cpu.icache.overall_hits::total 200949213 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 19542 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 19542 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 19542 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 19542 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 19542 # number of overall misses +system.cpu.icache.overall_misses::total 19542 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 494400997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 494400997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 494400997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 494400997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 494400997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 494400997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 200968755 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 200968755 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 200968755 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 200968755 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 200968755 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 200968755 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000097 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000097 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000097 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000097 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000097 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000097 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24001.328784 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24001.328784 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24001.328784 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24001.328784 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24001.328784 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24001.328784 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25299.406253 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25299.406253 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25299.406253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25299.406253 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25299.406253 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -612,122 +614,122 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19563 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 19563 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 19563 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 19563 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 19563 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 19563 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 429024005 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 429024005 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 429024005 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 429024005 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 429024005 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 429024005 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 19542 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 19542 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 19542 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 19542 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 19542 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 19542 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 463701003 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 463701003 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 463701003 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 463701003 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 463701003 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 463701003 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000097 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000097 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000097 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000097 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21930.379032 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21930.379032 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21930.379032 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21930.379032 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23728.431225 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23728.431225 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23728.431225 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23728.431225 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23728.431225 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23728.431225 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 111403 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27648.458293 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1684717 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 142590 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 11.815113 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 163177408500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23523.224801 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 389.561382 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3735.672111 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.717872 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011888 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.114004 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.843764 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31187 # Occupied blocks per task id +system.cpu.l2cache.tags.replacements 111429 # number of replacements +system.cpu.l2cache.tags.tagsinuse 27648.762381 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 1684764 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 142617 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 11.813206 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 163811788500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23520.899956 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 390.576322 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3737.286102 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.717801 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.011919 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.114053 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.843773 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31188 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 323 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4940 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25856 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951752 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 18354956 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 18354956 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 16090 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 747677 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 763767 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1068525 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1068525 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 255530 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 255530 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 16090 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1003207 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1019297 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 16090 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1003207 # number of overall hits -system.cpu.l2cache.overall_hits::total 1019297 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3473 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 39833 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 43306 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 100868 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 100868 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3473 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 140701 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 144174 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3473 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 140701 # number of overall misses -system.cpu.l2cache.overall_misses::total 144174 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 248520000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2980751000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3229271000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7164307250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7164307250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 248520000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10145058250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10393578250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 248520000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10145058250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10393578250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 19563 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 787510 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 807073 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1068525 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1068525 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 356398 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 356398 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 19563 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1143908 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1163471 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 19563 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1143908 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1163471 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177529 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050581 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.053658 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283021 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.283021 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177529 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.123000 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.123917 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177529 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.123000 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.123917 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71557.731068 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74831.195240 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74568.674087 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71026.561942 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71026.561942 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72103.668417 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72090.517361 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71557.731068 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72103.668417 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72090.517361 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 321 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4941 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 25858 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.951782 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 18355761 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 18355761 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 16076 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 747713 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 763789 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1068568 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1068568 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 255536 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 255536 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 16076 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1003249 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1019325 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 16076 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1003249 # number of overall hits +system.cpu.l2cache.overall_hits::total 1019325 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3466 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 39870 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 43336 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 100864 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 100864 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3466 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 140734 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 144200 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3466 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 140734 # number of overall misses +system.cpu.l2cache.overall_misses::total 144200 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 275297000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3285022000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3560319000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7930866750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 7930866750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 275297000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11215888750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 11491185750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 275297000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11215888750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 11491185750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 19542 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 787583 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 807125 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1068568 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1068568 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 356400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 356400 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 19542 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1143983 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1163525 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 19542 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1143983 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1163525 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.177362 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.050623 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.053692 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.283008 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.283008 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.177362 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.123021 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.123934 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.177362 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.123021 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.123934 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79427.870744 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82393.328317 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82156.151929 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78629.310259 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78629.310259 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79689.221567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79427.870744 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79695.658121 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79689.221567 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -736,8 +738,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 96561 # number of writebacks -system.cpu.l2cache.writebacks::total 96561 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 96557 # number of writebacks +system.cpu.l2cache.writebacks::total 96557 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 15 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits @@ -747,107 +749,105 @@ system.cpu.l2cache.demand_mshr_hits::total 17 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 15 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3471 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39818 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 43289 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100868 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 100868 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3471 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 140686 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 144157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3471 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 140686 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 144157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 204743500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2475547000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2680290500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5883442250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5883442250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 204743500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8358989250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8563732750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 204743500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8358989250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8563732750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050562 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053637 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283021 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283021 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.123903 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177427 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122987 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.123903 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58986.891386 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62171.555578 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61916.202730 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58328.134294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58328.134294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58986.891386 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59415.928024 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59405.597716 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3464 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 39855 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 43319 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 100864 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 100864 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3464 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 140719 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 144183 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3464 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 140719 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 144183 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 231582500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2784547250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3016129750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6669444250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6669444250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 231582500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9453991500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9685574000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 231582500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9453991500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9685574000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.050604 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.053671 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.283008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.283008 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.123919 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.177259 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.123008 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.123919 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66854.070439 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69866.948940 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69626.024377 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66123.138583 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66123.138583 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66854.070439 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67183.475579 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67175.561613 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 807073 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 807073 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1068525 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 356398 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 356398 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39126 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356341 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 3395467 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1252032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141595712 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 142847744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 807125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 807125 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1068568 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 356400 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 356400 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 39084 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3356534 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 3395618 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1250688 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 141603264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 142853952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 2231996 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 2232093 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2231996 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 2232093 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 2231996 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2184523000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 2232093 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2184614500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 30038495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 30006497 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1744651235 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1744748235 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.membus.trans_dist::ReadReq 43289 # Transaction distribution -system.membus.trans_dist::ReadResp 43289 # Transaction distribution -system.membus.trans_dist::Writeback 96561 # Transaction distribution -system.membus.trans_dist::ReadExReq 100868 # Transaction distribution -system.membus.trans_dist::ReadExResp 100868 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384875 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 384875 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15405952 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15405952 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 43319 # Transaction distribution +system.membus.trans_dist::ReadResp 43319 # Transaction distribution +system.membus.trans_dist::Writeback 96557 # Transaction distribution +system.membus.trans_dist::ReadExReq 100864 # Transaction distribution +system.membus.trans_dist::ReadExResp 100864 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 384923 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 384923 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15407360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15407360 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 240718 # Request fanout histogram +system.membus.snoop_fanout::samples 240740 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 240718 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 240740 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 240718 # Request fanout histogram -system.membus.reqLayer0.occupancy 1081999000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1366864750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.4 # Layer utilization (%) +system.membus.snoop_fanout::total 240740 # Request fanout histogram +system.membus.reqLayer0.occupancy 679202000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 765364000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt index e36a9b419..17deb175b 100644 --- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.232212 # Number of seconds simulated -sim_ticks 232211555000 # Number of ticks simulated -final_tick 232211555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.233382 # Number of seconds simulated +sim_ticks 233381523500 # Number of ticks simulated +final_tick 233381523500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 135087 # Simulator instruction rate (inst/s) -host_op_rate 146347 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 62087234 # Simulator tick rate (ticks/s) -host_mem_usage 317808 # Number of bytes of host memory used -host_seconds 3740.09 # Real time elapsed on the host +host_inst_rate 139639 # Simulator instruction rate (inst/s) +host_op_rate 151279 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 64502789 # Simulator tick rate (ticks/s) +host_mem_usage 317896 # Number of bytes of host memory used +host_seconds 3618.16 # Real time elapsed on the host sim_insts 505237723 # Number of instructions simulated sim_ops 547350944 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 681088 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9254400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 16474624 # Number of bytes read from this memory -system.physmem.bytes_read::total 26410112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 681088 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 681088 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18728832 # Number of bytes written to this memory -system.physmem.bytes_written::total 18728832 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 10642 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 144600 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 257416 # Number of read requests responded to by this memory -system.physmem.num_reads::total 412658 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 292638 # Number of write requests responded to by this memory -system.physmem.num_writes::total 292638 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2933050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 39853314 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 70946616 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 113732979 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2933050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2933050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 80654178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 80654178 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 80654178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2933050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 39853314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 70946616 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 194387157 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 412658 # Number of read requests accepted -system.physmem.writeReqs 292638 # Number of write requests accepted -system.physmem.readBursts 412658 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 292638 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26271168 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 138944 # Total number of bytes read from write queue -system.physmem.bytesWritten 18727424 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26410112 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18728832 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 2171 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 689856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9181056 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 16498240 # Number of bytes read from this memory +system.physmem.bytes_read::total 26369152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 689856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 689856 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18710272 # Number of bytes written to this memory +system.physmem.bytes_written::total 18710272 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 10779 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143454 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 257785 # Number of read requests responded to by this memory +system.physmem.num_reads::total 412018 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 292348 # Number of write requests responded to by this memory +system.physmem.num_writes::total 292348 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2955915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 39339258 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 70692143 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 112987316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2955915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2955915 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 80170322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 80170322 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 80170322 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2955915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 39339258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 70692143 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 193157639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 412018 # Number of read requests accepted +system.physmem.writeReqs 292348 # Number of write requests accepted +system.physmem.readBursts 412018 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 292348 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26233536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 135616 # Total number of bytes read from write queue +system.physmem.bytesWritten 18708736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26369152 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18710272 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2119 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 4 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 3 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 26576 # Per bank write bursts -system.physmem.perBankRdBursts::1 25575 # Per bank write bursts -system.physmem.perBankRdBursts::2 25174 # Per bank write bursts -system.physmem.perBankRdBursts::3 24876 # Per bank write bursts -system.physmem.perBankRdBursts::4 27202 # Per bank write bursts -system.physmem.perBankRdBursts::5 26589 # Per bank write bursts -system.physmem.perBankRdBursts::6 25428 # Per bank write bursts -system.physmem.perBankRdBursts::7 24234 # Per bank write bursts -system.physmem.perBankRdBursts::8 25846 # Per bank write bursts -system.physmem.perBankRdBursts::9 24812 # Per bank write bursts -system.physmem.perBankRdBursts::10 25055 # Per bank write bursts -system.physmem.perBankRdBursts::11 26081 # Per bank write bursts -system.physmem.perBankRdBursts::12 26502 # Per bank write bursts -system.physmem.perBankRdBursts::13 25872 # Per bank write bursts -system.physmem.perBankRdBursts::14 25198 # Per bank write bursts -system.physmem.perBankRdBursts::15 25467 # Per bank write bursts -system.physmem.perBankWrBursts::0 18795 # Per bank write bursts -system.physmem.perBankWrBursts::1 18343 # Per bank write bursts -system.physmem.perBankWrBursts::2 17877 # Per bank write bursts -system.physmem.perBankWrBursts::3 18076 # Per bank write bursts -system.physmem.perBankWrBursts::4 18802 # Per bank write bursts -system.physmem.perBankWrBursts::5 18306 # Per bank write bursts -system.physmem.perBankWrBursts::6 18071 # Per bank write bursts -system.physmem.perBankWrBursts::7 17638 # Per bank write bursts -system.physmem.perBankWrBursts::8 18138 # Per bank write bursts -system.physmem.perBankWrBursts::9 17849 # Per bank write bursts -system.physmem.perBankWrBursts::10 18079 # Per bank write bursts -system.physmem.perBankWrBursts::11 18708 # Per bank write bursts -system.physmem.perBankWrBursts::12 18879 # Per bank write bursts -system.physmem.perBankWrBursts::13 18261 # Per bank write bursts -system.physmem.perBankWrBursts::14 18465 # Per bank write bursts -system.physmem.perBankWrBursts::15 18329 # Per bank write bursts +system.physmem.perBankRdBursts::0 26413 # Per bank write bursts +system.physmem.perBankRdBursts::1 25441 # Per bank write bursts +system.physmem.perBankRdBursts::2 25280 # Per bank write bursts +system.physmem.perBankRdBursts::3 24861 # Per bank write bursts +system.physmem.perBankRdBursts::4 26943 # Per bank write bursts +system.physmem.perBankRdBursts::5 26409 # Per bank write bursts +system.physmem.perBankRdBursts::6 25350 # Per bank write bursts +system.physmem.perBankRdBursts::7 24226 # Per bank write bursts +system.physmem.perBankRdBursts::8 25719 # Per bank write bursts +system.physmem.perBankRdBursts::9 24800 # Per bank write bursts +system.physmem.perBankRdBursts::10 25359 # Per bank write bursts +system.physmem.perBankRdBursts::11 26216 # Per bank write bursts +system.physmem.perBankRdBursts::12 26433 # Per bank write bursts +system.physmem.perBankRdBursts::13 25856 # Per bank write bursts +system.physmem.perBankRdBursts::14 25009 # Per bank write bursts +system.physmem.perBankRdBursts::15 25584 # Per bank write bursts +system.physmem.perBankWrBursts::0 18684 # Per bank write bursts +system.physmem.perBankWrBursts::1 18331 # Per bank write bursts +system.physmem.perBankWrBursts::2 18001 # Per bank write bursts +system.physmem.perBankWrBursts::3 18053 # Per bank write bursts +system.physmem.perBankWrBursts::4 18581 # Per bank write bursts +system.physmem.perBankWrBursts::5 18287 # Per bank write bursts +system.physmem.perBankWrBursts::6 18028 # Per bank write bursts +system.physmem.perBankWrBursts::7 17667 # Per bank write bursts +system.physmem.perBankWrBursts::8 18026 # Per bank write bursts +system.physmem.perBankWrBursts::9 17689 # Per bank write bursts +system.physmem.perBankWrBursts::10 18246 # Per bank write bursts +system.physmem.perBankWrBursts::11 18799 # Per bank write bursts +system.physmem.perBankWrBursts::12 18831 # Per bank write bursts +system.physmem.perBankWrBursts::13 18312 # Per bank write bursts +system.physmem.perBankWrBursts::14 18349 # Per bank write bursts +system.physmem.perBankWrBursts::15 18440 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 232211534500 # Total gap between requests +system.physmem.totGap 233381437000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 412658 # Read request sizes (log2) +system.physmem.readPktSize::6 412018 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 292638 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 311514 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 49355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13370 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7406 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6188 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4451 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 292348 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 312437 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5333 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -148,30 +148,30 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6468 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 13583 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 15531 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 16421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 16883 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 17608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 18103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 18634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 19068 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 19781 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 18496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 18131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 13233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 15344 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 16357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 16904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17394 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 17602 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18396 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18527 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 19969 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 18456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see @@ -197,102 +197,103 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 307877 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 146.155822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 102.817953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 181.897933 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 185209 60.16% 60.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 81919 26.61% 86.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 16650 5.41% 92.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7285 2.37% 94.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4666 1.52% 96.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2373 0.77% 96.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1833 0.60% 97.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1570 0.51% 97.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6372 2.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 307877 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17388 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.607430 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 116.348412 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 17387 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 307121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 146.330964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 102.916756 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 182.072957 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 184589 60.10% 60.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 81854 26.65% 86.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16654 5.42% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7226 2.35% 94.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4782 1.56% 96.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2270 0.74% 96.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1753 0.57% 97.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1588 0.52% 97.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6405 2.09% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 307121 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17353 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.620930 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 116.705820 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 17352 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14848-15359 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17388 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17388 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.828617 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.789393 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.188635 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 10816 62.20% 62.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 278 1.60% 63.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 5484 31.54% 95.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 506 2.91% 98.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 126 0.72% 98.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 66 0.38% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 41 0.24% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 33 0.19% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 20 0.12% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 12 0.07% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 5 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17353 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17353 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.845733 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.805125 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.212117 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 10719 61.77% 61.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 285 1.64% 63.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 5449 31.40% 94.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 585 3.37% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 128 0.74% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 65 0.37% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 37 0.21% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 35 0.20% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 29 0.17% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 15 0.09% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 4 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::31 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17388 # Writes before turning the bus around for reads -system.physmem.totQLat 9526506707 # Total ticks spent queuing -system.physmem.totMemAccLat 17223137957 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2052435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 23207.82 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17353 # Writes before turning the bus around for reads +system.physmem.totQLat 9387910450 # Total ticks spent queuing +system.physmem.totMemAccLat 17073516700 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2049495000 # Total ticks spent in databus transfers +system.physmem.avgQLat 22902.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 41957.82 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 113.13 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 80.65 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 113.73 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 80.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 41652.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 112.41 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 80.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 112.99 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 80.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.51 # Data bus utilization in percentage +system.physmem.busUtil 1.50 # Data bus utilization in percentage system.physmem.busUtilRead 0.88 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.63 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.62 # Average write queue length when enqueuing -system.physmem.readRowHits 299737 # Number of row buffer hits during reads -system.physmem.writeRowHits 95481 # Number of row buffer hits during writes -system.physmem.readRowHitRate 73.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 32.63 # Row buffer hit rate for writes -system.physmem.avgGap 329239.83 # Average gap between requests -system.physmem.pageHitRate 56.21 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 1161435240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 633719625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1603960800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 945386640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 74505009510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 73970535750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 167986832445 # Total energy per rank (pJ) -system.physmem_0.averagePower 723.427350 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 122529683190 # Time in different power states -system.physmem_0.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem.avgWrQLen 21.73 # Average write queue length when enqueuing +system.physmem.readRowHits 299659 # Number of row buffer hits during reads +system.physmem.writeRowHits 95432 # Number of row buffer hits during writes +system.physmem.readRowHitRate 73.11 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 32.64 # Row buffer hit rate for writes +system.physmem.avgGap 331335.47 # Average gap between requests +system.physmem.pageHitRate 56.26 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 1156453200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 631001250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1598134200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 943500960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 74948893020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 74281875750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 168802927260 # Total energy per rank (pJ) +system.physmem_0.averagePower 723.304109 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 123045424463 # Time in different power states +system.physmem_0.memoryStateTime::REF 7792980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 101926029060 # Time in different power states +system.physmem_0.memoryStateTime::ACT 102539140537 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 1165888080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 636149250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1597541400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 950557680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 15166784880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 73837287855 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 74556205500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 167910414645 # Total energy per rank (pJ) -system.physmem_1.averagePower 723.098525 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 123510236330 # Time in different power states -system.physmem_1.memoryStateTime::REF 7753980000 # Time in different power states +system.physmem_1.actEnergy 1165048920 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 635691375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1598610000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 950447520 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 15243068880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74482095510 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 74691339000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 168766301205 # Total energy per rank (pJ) +system.physmem_1.averagePower 723.147212 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 123736015873 # Time in different power states +system.physmem_1.memoryStateTime::REF 7792980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 100945998170 # Time in different power states +system.physmem_1.memoryStateTime::ACT 101848756127 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 175052211 # Number of BP lookups -system.cpu.branchPred.condPredicted 131310953 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 7443013 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 90523756 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83852008 # Number of BTB hits +system.cpu.branchPred.lookups 175093442 # Number of BP lookups +system.cpu.branchPred.condPredicted 131339013 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 7445255 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90524838 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83882931 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.629837 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 12106573 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104182 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.662890 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 12110656 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104163 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,129 +412,129 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 464423111 # number of cpu cycles simulated +system.cpu.numCycles 466763048 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7829450 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 731665108 # Number of instructions fetch has processed -system.cpu.fetch.Branches 175052211 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 95958581 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 448342475 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 14938309 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 5167 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 75 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 11385 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 236661621 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 34410 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 463657706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.708988 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.176697 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7833738 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 731827371 # Number of instructions fetch has processed +system.cpu.fetch.Branches 175093442 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 95993587 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 450556948 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 14942959 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 6375 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 162 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 12684 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 236728618 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 34396 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 465881386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.701216 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.179605 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 91809808 19.80% 19.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 132662466 28.61% 48.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 57833448 12.47% 60.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 181351984 39.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 93942381 20.16% 20.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 132696529 28.48% 48.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 57859169 12.42% 61.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 181383307 38.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 463657706 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.376924 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.575428 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 32373161 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 115247897 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 287024980 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 22030943 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 6980725 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 24047273 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 496181 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 715717692 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 29980742 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 6980725 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 63423134 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 52089726 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 40328416 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 276637091 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 24198614 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 686503661 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13339375 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 9395545 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2450716 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1889859 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1786281 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 830901474 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 3018793647 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 723833359 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 465881386 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.375123 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.567878 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 32362328 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 117422213 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 287082190 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 22031979 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 6982676 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 24051776 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 496598 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 715820836 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 30011268 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 6982676 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 63423410 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 54356901 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 40333857 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 276674345 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 24110197 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 686603373 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13342977 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 9430232 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2385222 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1668168 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1866322 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 831029947 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 3019214336 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 723928049 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 416 # Number of floating rename lookups system.cpu.rename.CommittedMaps 654123751 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 176777723 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 1544705 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 1534955 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 42254952 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 143502988 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 67972899 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12881093 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11309167 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 668070815 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2978330 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 610220228 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5852709 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 122637533 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 318907162 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 698 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 463657706 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.316101 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101419 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 176906196 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 1544708 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 1534779 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 42310456 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 143529227 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 67980457 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12876117 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11223865 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 668168633 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2978333 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 610244720 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5860928 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 122748160 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 319249921 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 701 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 465881386 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.309871 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.101485 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 147083310 31.72% 31.72% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 100037180 21.58% 53.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 146356248 31.57% 84.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 63253795 13.64% 98.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 6926698 1.49% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 475 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 148726725 31.92% 31.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 101219272 21.73% 53.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 145704053 31.27% 84.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 63308472 13.59% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 6922394 1.49% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 470 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 463657706 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 465881386 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 71297182 52.75% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 31 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.75% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 44549866 32.96% 85.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19309097 14.29% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 71926892 52.97% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 30 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 52.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 44548808 32.81% 85.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19308609 14.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 413143881 67.70% 67.70% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 351753 0.06% 67.76% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 413151205 67.70% 67.70% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 351762 0.06% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued @@ -561,84 +562,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.00% 67.76% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 134202503 21.99% 89.75% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 62522088 10.25% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 134213175 21.99% 89.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 62528575 10.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 610220228 # Type of FU issued -system.cpu.iq.rate 1.313932 # Inst issue rate -system.cpu.iq.fu_busy_cnt 135156176 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.221488 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 1825106754 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 793714763 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 594959628 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 610244720 # Type of FU issued +system.cpu.iq.rate 1.307397 # Inst issue rate +system.cpu.iq.fu_busy_cnt 135784339 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.222508 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 1828015800 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 793923222 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 594984495 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 293 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 316 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 745376227 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 746028882 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 177 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 7281483 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 7272735 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 27618232 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 25000 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 28827 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11112422 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 27644471 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 25523 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 28862 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11119980 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 224691 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 19267 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 225173 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 19543 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 6980725 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 22383279 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 635884 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 672535669 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 6982676 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 23041794 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 922625 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 672634659 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 143502988 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 67972899 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1489788 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 251092 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 252064 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 28827 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3821462 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3734064 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 7555526 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 599376603 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 129568443 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 10843625 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 143529227 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 67980457 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1489791 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 257738 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 528673 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 28862 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3822612 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3731799 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 7554411 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 599400407 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 129575642 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 10844313 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1486524 # number of nop insts executed -system.cpu.iew.exec_refs 190520911 # number of memory reference insts executed -system.cpu.iew.exec_branches 131371292 # Number of branches executed -system.cpu.iew.exec_stores 60952468 # Number of stores executed -system.cpu.iew.exec_rate 1.290583 # Inst execution rate -system.cpu.iew.wb_sent 596255942 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 594959644 # cumulative count of insts written-back -system.cpu.iew.wb_producers 349870966 # num instructions producing a value -system.cpu.iew.wb_consumers 570295631 # num instructions consuming a value +system.cpu.iew.exec_nop 1487693 # number of nop insts executed +system.cpu.iew.exec_refs 190530493 # number of memory reference insts executed +system.cpu.iew.exec_branches 131374378 # Number of branches executed +system.cpu.iew.exec_stores 60954851 # Number of stores executed +system.cpu.iew.exec_rate 1.284164 # Inst execution rate +system.cpu.iew.wb_sent 596279757 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 594984511 # cumulative count of insts written-back +system.cpu.iew.wb_producers 349915362 # num instructions producing a value +system.cpu.iew.wb_consumers 570660996 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.281072 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.613491 # average fanout of values written-back +system.cpu.iew.wb_rate 1.274704 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.613176 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 109920418 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 110032490 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 2977632 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 6954584 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 446560356 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.228714 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.894004 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 6956452 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 448764802 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.222678 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.888107 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 218012124 48.82% 48.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 116021741 25.98% 74.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 43540177 9.75% 84.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 23444560 5.25% 89.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 10920781 2.45% 92.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 8059552 1.80% 94.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 8487825 1.90% 95.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 4237549 0.95% 96.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 13836047 3.10% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 219732753 48.96% 48.96% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 116339584 25.92% 74.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 43745322 9.75% 84.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 23276938 5.19% 89.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 11568250 2.58% 92.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 7761637 1.73% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 8261110 1.84% 95.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 4247723 0.95% 96.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 13831485 3.08% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 446560356 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 448764802 # Number of insts commited each cycle system.cpu.commit.committedInsts 506581607 # Number of instructions committed system.cpu.commit.committedOps 548694828 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,380 +685,381 @@ system.cpu.commit.op_class_0::MemWrite 56860477 10.36% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 548694828 # Class of committed instruction -system.cpu.commit.bw_lim_events 13836047 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 13831485 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1091332417 # The number of ROB reads -system.cpu.rob.rob_writes 1334357175 # The number of ROB writes -system.cpu.timesIdled 13678 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 765405 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1093653497 # The number of ROB reads +system.cpu.rob.rob_writes 1334601058 # The number of ROB writes +system.cpu.timesIdled 13925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 881662 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 505237723 # Number of Instructions Simulated system.cpu.committedOps 547350944 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.919217 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.919217 # CPI: Total CPI of All Threads -system.cpu.ipc 1.087882 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.087882 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 611063177 # number of integer regfile reads -system.cpu.int_regfile_writes 328106532 # number of integer regfile writes +system.cpu.cpi 0.923848 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.923848 # CPI: Total CPI of All Threads +system.cpu.ipc 1.082429 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.082429 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 611089137 # number of integer regfile reads +system.cpu.int_regfile_writes 328121807 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 2170100255 # number of cc regfile reads -system.cpu.cc_regfile_writes 376532879 # number of cc regfile writes -system.cpu.misc_regfile_reads 217961412 # number of misc regfile reads +system.cpu.cc_regfile_reads 2170187431 # number of cc regfile reads +system.cpu.cc_regfile_writes 376547848 # number of cc regfile writes +system.cpu.misc_regfile_reads 217970630 # number of misc regfile reads system.cpu.misc_regfile_writes 2977084 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2823114 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.633158 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 169651956 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2823626 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 60.083012 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 496259500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.633158 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999284 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999284 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2821443 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.630682 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 169417803 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2821955 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 60.035615 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 498977500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.630682 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999279 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999279 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 274 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 164 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 281 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 356228622 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 356228622 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 114681272 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 114681272 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 51990753 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 51990753 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 2786 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 2786 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488557 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 1488557 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 356251797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 356251797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 114676407 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 114676407 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 51761464 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 51761464 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 2782 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 2782 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 1488559 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 1488559 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 1488541 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 1488541 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 166672025 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 166672025 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 166674811 # number of overall hits -system.cpu.dcache.overall_hits::total 166674811 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 4801959 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 4801959 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2248553 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2248553 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 11 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 11 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 166437871 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 166437871 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 166440653 # number of overall hits +system.cpu.dcache.overall_hits::total 166440653 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 4819248 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 4819248 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2477842 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2477842 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 12 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 12 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 66 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 66 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 7050512 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7050512 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7050523 # number of overall misses -system.cpu.dcache.overall_misses::total 7050523 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 53499385357 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 53499385357 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 17165986851 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 17165986851 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1002500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 1002500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 70665372208 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 70665372208 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 70665372208 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 70665372208 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 119483231 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 119483231 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 7297090 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7297090 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7297102 # number of overall misses +system.cpu.dcache.overall_misses::total 7297102 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 56184151983 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 56184151983 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18816988488 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18816988488 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 1349500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 1349500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75001140471 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75001140471 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75001140471 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75001140471 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 119495655 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 119495655 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 54239306 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2797 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488623 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 1488623 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2794 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2794 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 1488625 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 1488625 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 1488541 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 1488541 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 173722537 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 173722537 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 173725334 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 173725334 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040189 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040189 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.041456 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.041456 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.003933 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.003933 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 173734961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 173734961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 173737755 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 173737755 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040330 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.040330 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.045684 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.045684 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.004295 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.004295 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000044 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000044 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.040585 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.040585 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.040584 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.040584 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11141.158297 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11141.158297 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7634.237152 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7634.237152 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 15189.393939 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 15189.393939 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10022.729159 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10022.729159 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10022.713522 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10022.713522 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 56 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 454984 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 10035 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 45.339711 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.042001 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.042001 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.042001 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.042001 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11658.281952 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11658.281952 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7594.103453 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 7594.103453 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20446.969697 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20446.969697 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 10278.226042 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 10278.226042 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 10278.209140 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 10278.209140 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 705176 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 220270 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 3.201416 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2354028 # number of writebacks -system.cpu.dcache.writebacks::total 2354028 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2498261 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2498261 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1728610 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1728610 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 2356074 # number of writebacks +system.cpu.dcache.writebacks::total 2356074 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2516883 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2516883 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1958234 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1958234 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 66 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 66 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4226871 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4226871 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4226871 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4226871 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2303698 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2303698 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519943 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 519943 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4475117 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4475117 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4475117 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4475117 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2302365 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2302365 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 519608 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 519608 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 10 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 10 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2823641 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2823641 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2823651 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2823651 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 25499562714 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 25499562714 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4017408221 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4017408221 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 706750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 706750 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29516970935 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 29516970935 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29517677685 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 29517677685 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019281 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019281 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009586 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003575 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003575 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016254 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016254 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.016254 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11068.969420 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11068.969420 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7726.631998 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7726.631998 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70675 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70675 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10453.514075 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 10453.514075 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10453.727350 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 10453.727350 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 2821973 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2821973 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2821983 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2821983 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27555148045 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27555148045 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4324407514 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4324407514 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 652250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 652250 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31879555559 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31879555559 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31880207809 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31880207809 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019267 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009580 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009580 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.003579 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.003579 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016243 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.016243 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.016243 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11968.192726 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11968.192726 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8322.442137 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8322.442137 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 65225 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 65225 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11296.903110 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11296.903110 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11297.094210 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 11297.094210 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 73454 # number of replacements -system.cpu.icache.tags.tagsinuse 465.665769 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 236580046 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 73966 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3198.497228 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 114499459250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 465.665769 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.909503 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.909503 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 73466 # number of replacements +system.cpu.icache.tags.tagsinuse 466.200525 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 236646541 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 73978 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3198.877247 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 115003506250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 466.200525 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.910548 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.910548 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 119 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 19 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 16 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 20 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 15 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 473397028 # Number of tag accesses -system.cpu.icache.tags.data_accesses 473397028 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 236580046 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 236580046 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 236580046 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 236580046 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 236580046 # number of overall hits -system.cpu.icache.overall_hits::total 236580046 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 81472 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 81472 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 81472 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 81472 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 81472 # number of overall misses -system.cpu.icache.overall_misses::total 81472 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1465585914 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1465585914 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1465585914 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1465585914 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1465585914 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1465585914 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 236661518 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 236661518 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 236661518 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 236661518 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 236661518 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 236661518 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000344 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000344 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000344 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000344 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000344 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000344 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17988.829463 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 17988.829463 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 17988.829463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 17988.829463 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 17988.829463 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 164374 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 692 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 6271 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.211768 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 138.400000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 473531001 # Number of tag accesses +system.cpu.icache.tags.data_accesses 473531001 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 236646541 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 236646541 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 236646541 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 236646541 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 236646541 # number of overall hits +system.cpu.icache.overall_hits::total 236646541 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 81956 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 81956 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 81956 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 81956 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 81956 # number of overall misses +system.cpu.icache.overall_misses::total 81956 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1579166787 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1579166787 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1579166787 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1579166787 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1579166787 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1579166787 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 236728497 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 236728497 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 236728497 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 236728497 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 236728497 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 236728497 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000346 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000346 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000346 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000346 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000346 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19268.470728 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19268.470728 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19268.470728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19268.470728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19268.470728 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 192617 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 91 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6539 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.456645 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 22.750000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7479 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 7479 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 7479 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 7479 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 7479 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 7479 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 73993 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 73993 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 73993 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 73993 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 73993 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 73993 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1129183847 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1129183847 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1129183847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1129183847 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1129183847 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1129183847 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 7948 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 7948 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 7948 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 7948 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 7948 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 7948 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 74008 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 74008 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 74008 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 74008 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 74008 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 74008 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1251050514 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1251050514 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1251050514 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1251050514 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1251050514 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1251050514 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000313 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000313 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000313 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000313 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15260.684754 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15260.684754 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15260.684754 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 15260.684754 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16904.260539 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16904.260539 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16904.260539 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 16904.260539 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 8509131 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 8512942 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 2237 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 8510841 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 8513336 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 1033 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 743602 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 401614 # number of replacements -system.cpu.l2cache.tags.tagsinuse 15413.386139 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4559849 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 417953 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 10.909956 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 34584601500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8474.787715 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 477.139723 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4908.892257 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1552.566443 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.517260 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.029122 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.299615 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.094761 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.940758 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 1129 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15210 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 49 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 259 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 821 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 147 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1536 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10030 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3283 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.068909 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.928345 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 84965966 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 84965966 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 63311 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 2156931 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2220242 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2354028 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2354028 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 516650 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 516650 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 63311 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2673581 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2736892 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 63311 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2673581 # number of overall hits -system.cpu.l2cache.overall_hits::total 2736892 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 10651 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 144961 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 155612 # number of ReadReq misses +system.cpu.l2cache.prefetcher.pfSpanPage 743496 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 401010 # number of replacements +system.cpu.l2cache.tags.tagsinuse 15417.841274 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4560227 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 417347 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 10.926704 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 34597011000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 8457.509015 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 475.097428 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4918.264697 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 1566.970133 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.516205 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.028998 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.300187 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.095640 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.941030 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 1096 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15241 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 810 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1567 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9927 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3395 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.066895 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.930237 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 84971798 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 84971798 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 63191 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 2156048 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2219239 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2356074 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2356074 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 516713 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 516713 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 63191 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2672761 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2735952 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 63191 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2672761 # number of overall hits +system.cpu.l2cache.overall_hits::total 2735952 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 10784 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 143994 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 154778 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 5084 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 5084 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 10651 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 150045 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 160696 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 10651 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 150045 # number of overall misses -system.cpu.l2cache.overall_misses::total 160696 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 711026986 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 10160623428 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 10871650414 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 411274728 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 411274728 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 711026986 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10571898156 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11282925142 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 711026986 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10571898156 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11282925142 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 73962 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 2301892 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2375854 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2354028 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2354028 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 25 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 521734 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 521734 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 73962 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2823626 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2897588 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 73962 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2823626 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2897588 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.144006 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062975 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.065497 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.080000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.080000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009744 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.009744 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.144006 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.053139 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.055459 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.144006 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.053139 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.055459 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66756.829030 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70092.117383 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69863.830643 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80895.894571 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80895.894571 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66756.829030 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70458.183585 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70212.856213 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66756.829030 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70458.183585 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70212.856213 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 5200 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 5200 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 10784 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 149194 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 159978 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 10784 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 149194 # number of overall misses +system.cpu.l2cache.overall_misses::total 159978 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 802172675 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11140653266 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11942825941 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 468295272 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 468295272 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 802172675 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11608948538 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12411121213 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 802172675 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11608948538 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12411121213 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 73975 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 2300042 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2374017 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2356074 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2356074 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 28 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 521913 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 521913 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 73975 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2821955 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2895930 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 73975 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2821955 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2895930 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.145779 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.062605 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.065197 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.071429 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.071429 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.009963 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.009963 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.145779 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.052869 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.055242 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.145779 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.052869 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.055242 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74385.448349 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77368.871384 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.004413 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90056.783077 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90056.783077 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74385.448349 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77811.095205 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77580.174855 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74385.448349 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77811.095205 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77580.174855 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1066,145 +1068,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 292638 # number of writebacks -system.cpu.l2cache.writebacks::total 292638 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4068 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 4076 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1399 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1399 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5467 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5475 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5467 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5475 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10643 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 140893 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 151536 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275229 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 275229 # number of HardPFReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 292348 # number of writebacks +system.cpu.l2cache.writebacks::total 292348 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4205 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4209 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1534 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1534 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 5739 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 5743 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 5739 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 5743 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10780 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 139789 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 150569 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 275622 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 275622 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 2 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3685 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 3685 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 10643 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 144578 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 155221 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 10643 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 144578 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275229 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 430450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 619626514 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8627975760 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9247602274 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18094630257 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 12002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 12002 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 229963510 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 229963510 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 619626514 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8857939270 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9477565784 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 619626514 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8857939270 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18094630257 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27572196041 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.061207 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063782 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3666 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 3666 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 10780 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143455 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154235 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 10780 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143455 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 275622 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 429857 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 710057825 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 9596193047 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10306250872 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18910984010 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27502 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 283384780 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 283384780 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 710057825 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9879577827 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10589635652 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 710057825 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9879577827 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18910984010 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29500619662 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.060777 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.063424 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.080000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.080000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007063 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.053569 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.143898 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.051203 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.071429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.071429 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.007024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.007024 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.053259 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.145725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.050835 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.148555 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58219.159448 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61237.788677 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61025.777861 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 65743.908734 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62405.294437 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62405.294437 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61058.528060 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58219.159448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61267.546031 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 65743.908734 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64054.352517 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.148435 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65868.072820 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68647.697938 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68448.690448 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 68612.026652 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13751 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77300.812875 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77300.812875 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68659.095873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65868.072820 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68868.828741 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 68612.026652 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68628.915342 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2375885 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2375884 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2354028 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 335698 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 25 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 521734 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 521734 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8001330 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8149284 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4733504 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331369856 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 336103360 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 335729 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5587370 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.060082 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.237638 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2374050 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2374049 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2356074 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 317604 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 28 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 521913 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 521913 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 147982 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8000040 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8148022 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4734336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 331393856 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 336128192 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 317637 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5569669 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.057024 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.231888 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 5251672 93.99% 93.99% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 335698 6.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5252065 94.30% 94.30% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 317604 5.70% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5587370 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4979864499 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 5569669 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4982106500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 112728958 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 112829788 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4257992809 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4256050685 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 408974 # Transaction distribution -system.membus.trans_dist::ReadResp 408974 # Transaction distribution -system.membus.trans_dist::Writeback 292638 # Transaction distribution +system.membus.trans_dist::ReadReq 408353 # Transaction distribution +system.membus.trans_dist::ReadResp 408353 # Transaction distribution +system.membus.trans_dist::Writeback 292348 # Transaction distribution system.membus.trans_dist::UpgradeReq 3 # Transaction distribution system.membus.trans_dist::UpgradeResp 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 3684 # Transaction distribution -system.membus.trans_dist::ReadExResp 3684 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1117960 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1117960 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45138944 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 45138944 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 3665 # Transaction distribution +system.membus.trans_dist::ReadExResp 3665 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1116390 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1116390 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 45079424 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 45079424 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 705299 # Request fanout histogram +system.membus.snoop_fanout::samples 704369 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 705299 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 704369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 705299 # Request fanout histogram -system.membus.reqLayer0.occupancy 3281426491 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3862639706 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.7 # Layer utilization (%) +system.membus.snoop_fanout::total 704369 # Request fanout histogram +system.membus.reqLayer0.occupancy 2100254662 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2178151058 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt index 29aebf258..ac9d5a522 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.279362 # Nu sim_ticks 279362297500 # Number of ticks simulated final_tick 279362297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1700410 # Simulator instruction rate (inst/s) -host_op_rate 1841769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 937717572 # Simulator tick rate (ticks/s) -host_mem_usage 304668 # Number of bytes of host memory used -host_seconds 297.92 # Real time elapsed on the host +host_inst_rate 1941586 # Simulator instruction rate (inst/s) +host_op_rate 2102994 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1070717412 # Simulator tick rate (ticks/s) +host_mem_usage 304560 # Number of bytes of host memory used +host_seconds 260.91 # Real time elapsed on the host sim_insts 506581607 # Number of instructions simulated sim_ops 548694828 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 638920325 system.membus.pkt_size::total 2705365825 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 687930749 # Request fanout histogram -system.membus.snoop_fanout::mean 4.750964 # Request fanout histogram +system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 171319374 24.90% 24.90% # Request fanout histogram -system.membus.snoop_fanout::5 516611375 75.10% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram +system.membus.snoop_fanout::3 516611375 75.10% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 687930749 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt index efad42105..f53112701 100644 --- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.707539 # Number of seconds simulated -sim_ticks 707539023000 # Number of ticks simulated -final_tick 707539023000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.707538 # Number of seconds simulated +sim_ticks 707538046500 # Number of ticks simulated +final_tick 707538046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1166033 # Simulator instruction rate (inst/s) -host_op_rate 1262762 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1633733414 # Simulator tick rate (ticks/s) -host_mem_usage 312880 # Number of bytes of host memory used -host_seconds 433.08 # Real time elapsed on the host +host_inst_rate 1058036 # Simulator instruction rate (inst/s) +host_op_rate 1145805 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1482416058 # Simulator tick rate (ticks/s) +host_mem_usage 313032 # Number of bytes of host memory used +host_seconds 477.29 # Real time elapsed on the host sim_insts 504986853 # Number of instructions simulated sim_ops 546878104 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 142649 # Nu system.physmem.num_writes::writebacks 95953 # Number of write requests responded to by this memory system.physmem.num_writes::total 95953 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 250559 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12652667 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 12903226 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12652685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 12903244 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 250559 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 250559 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 8679369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 8679369 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 8679369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 8679381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 8679381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 8679381 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 250559 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12652667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 21582595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12652685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 21582625 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 548 # Number of system calls -system.cpu.numCycles 1415078046 # number of cpu cycles simulated +system.cpu.numCycles 1415076093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 504986853 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 172745235 # nu system.cpu.num_load_insts 115884756 # Number of load instructions system.cpu.num_store_insts 56860479 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1415078045.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1415076092.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 121548301 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 548695378 # Class of executed instruction system.cpu.dcache.tags.replacements 1134822 # number of replacements -system.cpu.dcache.tags.tagsinuse 4065.318438 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4065.318390 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 170180456 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1138918 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 149.422922 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 11716392000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318438 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 11716393000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4065.318390 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.992509 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -256,14 +256,14 @@ system.cpu.dcache.demand_misses::cpu.data 1138917 # n system.cpu.dcache.demand_misses::total 1138917 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1138918 # number of overall misses system.cpu.dcache.overall_misses::total 1138918 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11819576500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8868781000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 20688357500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 20688357500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 20688357500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11818657500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11818657500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8868772000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8868772000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20687429500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20687429500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20687429500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20687429500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 114100415 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 54239306 # number of WriteReq accesses(hits+misses) @@ -288,14 +288,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_miss_rate::total 0.006766 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.006765 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.006765 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15101.860074 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15101.860074 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.125077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.125077 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.938709 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 18164.938709 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.922760 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 18164.922760 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15100.685869 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15100.685869 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24894.099815 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 24894.099815 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 18164.123900 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 18164.123900 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 18164.107952 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 18164.107952 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1138917 system.cpu.dcache.demand_mshr_misses::total 1138917 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1138918 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1138918 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10254262500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8156261000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18410523500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18410576500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18410576500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10644672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10644672000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8334382000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8334382000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18979054000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18979054000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18979107500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18979107500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.006859 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006568 # mshr miss rate for WriteReq accesses @@ -336,24 +336,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006766 system.cpu.dcache.demand_mshr_miss_rate::total 0.006766 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006765 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.006765 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13101.860074 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22894.125077 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16164.938709 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 16164.938709 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16164.971051 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16164.971051 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13600.685869 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13600.685869 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23394.099815 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23394.099815 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16664.123900 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 16664.123900 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16664.156243 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 16664.156243 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 9788 # number of replacements -system.cpu.icache.tags.tagsinuse 983.372001 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 983.372132 # Cycle average of tags in use system.cpu.icache.tags.total_refs 516599855 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 11521 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 44839.845066 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 983.372001 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 983.372132 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.480162 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1733 # Occupied blocks per task id @@ -377,12 +377,12 @@ system.cpu.icache.demand_misses::cpu.inst 11521 # n system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses system.cpu.icache.overall_misses::total 11521 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 266342000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 266342000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 266342000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 266342000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 266342000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 266342000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 266293500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 266293500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 266293500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 266293500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 266293500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 266293500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 516611376 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 516611376 # number of demand (read+write) accesses @@ -395,12 +395,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000022 system.cpu.icache.demand_miss_rate::total 0.000022 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000022 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000022 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23117.958511 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 23117.958511 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 23117.958511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 23117.958511 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 23117.958511 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23113.748807 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 23113.748807 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 23113.748807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 23113.748807 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 23113.748807 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -415,38 +415,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 11521 system.cpu.icache.demand_mshr_misses::total 11521 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 11521 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 11521 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243300000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 243300000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243300000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 243300000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243300000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 243300000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 249012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 249012000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 249012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 249012000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 249012000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 249012000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000022 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000022 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000022 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21117.958511 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21117.958511 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21117.958511 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 21117.958511 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21613.748807 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21613.748807 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21613.748807 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 21613.748807 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 109895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 27249.394273 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 27249.388139 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1668833 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 141072 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 11.829654 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 338494923500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 23386.993586 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904756 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.495930 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 338494304500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 23386.989190 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 287.904965 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 3574.493984 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.713714 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008786 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.109085 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.831586 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.831585 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31177 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id @@ -479,17 +479,17 @@ system.cpu.l2cache.demand_misses::total 142649 # nu system.cpu.l2cache.overall_misses::cpu.inst 2770 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 139879 # number of overall misses system.cpu.l2cache.overall_misses::total 142649 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 144269000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2035873000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2180142000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5245341000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5245341000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 144269000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7281214000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7425483000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 144269000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7281214000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7425483000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145605500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2054496500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2200102000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5295729000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5295729000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 145605500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7350225500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7495831000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 145605500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7350225500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7495831000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses) @@ -514,17 +514,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.123995 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.240431 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.122817 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.123995 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52082.671480 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52088.345913 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52087.970374 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52040.210727 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52040.210727 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52054.224004 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52082.671480 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52053.660664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52054.224004 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52565.162455 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52564.833056 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52564.854856 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52540.121436 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52540.121436 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52547.378531 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52565.162455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52547.026358 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52547.378531 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -546,17 +546,17 @@ system.cpu.l2cache.demand_mshr_misses::total 142649 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 139879 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 142649 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 110883500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1564721500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1675605000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4031776000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4031776000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 110883500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5596497500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5707381000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 110883500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5596497500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5707381000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 112218500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1583343000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1695561500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4082164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4082164000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 112218500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5665507000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5777725500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 112218500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5665507000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5777725500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.049939 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.052702 # mshr miss rate for ReadReq accesses @@ -568,17 +568,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.123995 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.240431 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.122817 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.123995 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40030.144404 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40033.810925 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40033.568271 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.158740 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.158740 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40030.144404 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40009.561836 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40009.961514 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40512.093863 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40510.246898 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40510.369132 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.069449 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.069449 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40512.093863 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40502.913232 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.091504 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 794179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 794179 # Transaction distribution @@ -593,19 +593,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 2215344 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) @@ -633,9 +631,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 238603 # Request fanout histogram -system.membus.reqLayer0.occupancy 1018523828 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 638238328 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 1290155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 719562500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt index be422e790..a1911a66a 100644 --- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt @@ -1,108 +1,108 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.451526 # Number of seconds simulated -sim_ticks 451526391500 # Number of ticks simulated -final_tick 451526391500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.455304 # Number of seconds simulated +sim_ticks 455304035500 # Number of ticks simulated +final_tick 455304035500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 97078 # Simulator instruction rate (inst/s) -host_op_rate 179507 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 53010367 # Simulator tick rate (ticks/s) -host_mem_usage 427448 # Number of bytes of host memory used -host_seconds 8517.70 # Real time elapsed on the host +host_inst_rate 97470 # Simulator instruction rate (inst/s) +host_op_rate 180233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 53670129 # Simulator tick rate (ticks/s) +host_mem_usage 427808 # Number of bytes of host memory used +host_seconds 8483.38 # Real time elapsed on the host sim_insts 826877109 # Number of instructions simulated sim_ops 1528988701 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24535168 # Number of bytes read from this memory -system.physmem.bytes_read::total 24760128 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224960 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 18817920 # Number of bytes written to this memory -system.physmem.bytes_written::total 18817920 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3515 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 383362 # Number of read requests responded to by this memory -system.physmem.num_reads::total 386877 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 294030 # Number of write requests responded to by this memory -system.physmem.num_writes::total 294030 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 498221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 54338281 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54836502 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 498221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 498221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 41676235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 41676235 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 41676235 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 498221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 54338281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 96512737 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 386877 # Number of read requests accepted -system.physmem.writeReqs 294030 # Number of write requests accepted -system.physmem.readBursts 386877 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 294030 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 24738496 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21632 # Total number of bytes read from write queue -system.physmem.bytesWritten 18816576 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 24760128 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 18817920 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 338 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24524608 # Number of bytes read from this memory +system.physmem.bytes_read::total 24749952 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 18812544 # Number of bytes written to this memory +system.physmem.bytes_written::total 18812544 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 383197 # Number of read requests responded to by this memory +system.physmem.num_reads::total 386718 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 293946 # Number of write requests responded to by this memory +system.physmem.num_writes::total 293946 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 494931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53864245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54359176 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 494931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 494931 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 41318641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 41318641 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 41318641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 494931 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53864245 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 95677817 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 386718 # Number of read requests accepted +system.physmem.writeReqs 293946 # Number of write requests accepted +system.physmem.readBursts 386718 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 293946 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 24728064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 21888 # Total number of bytes read from write queue +system.physmem.bytesWritten 18810880 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 24749952 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 18812544 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 342 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 180174 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24137 # Per bank write bursts -system.physmem.perBankRdBursts::1 26529 # Per bank write bursts -system.physmem.perBankRdBursts::2 24699 # Per bank write bursts -system.physmem.perBankRdBursts::3 24593 # Per bank write bursts -system.physmem.perBankRdBursts::4 23302 # Per bank write bursts -system.physmem.perBankRdBursts::5 23749 # Per bank write bursts -system.physmem.perBankRdBursts::6 24449 # Per bank write bursts -system.physmem.perBankRdBursts::7 24297 # Per bank write bursts -system.physmem.perBankRdBursts::8 23610 # Per bank write bursts -system.physmem.perBankRdBursts::9 23919 # Per bank write bursts -system.physmem.perBankRdBursts::10 24817 # Per bank write bursts -system.physmem.perBankRdBursts::11 24050 # Per bank write bursts -system.physmem.perBankRdBursts::12 23346 # Per bank write bursts -system.physmem.perBankRdBursts::13 22971 # Per bank write bursts -system.physmem.perBankRdBursts::14 24088 # Per bank write bursts -system.physmem.perBankRdBursts::15 23983 # Per bank write bursts -system.physmem.perBankWrBursts::0 18558 # Per bank write bursts -system.physmem.perBankWrBursts::1 19844 # Per bank write bursts -system.physmem.perBankWrBursts::2 18955 # Per bank write bursts -system.physmem.perBankWrBursts::3 18948 # Per bank write bursts -system.physmem.perBankWrBursts::4 18040 # Per bank write bursts -system.physmem.perBankWrBursts::5 18446 # Per bank write bursts -system.physmem.perBankWrBursts::6 18985 # Per bank write bursts -system.physmem.perBankWrBursts::7 18975 # Per bank write bursts -system.physmem.perBankWrBursts::8 18547 # Per bank write bursts -system.physmem.perBankWrBursts::9 18155 # Per bank write bursts -system.physmem.perBankWrBursts::10 18842 # Per bank write bursts -system.physmem.perBankWrBursts::11 17721 # Per bank write bursts -system.physmem.perBankWrBursts::12 17374 # Per bank write bursts -system.physmem.perBankWrBursts::13 16974 # Per bank write bursts -system.physmem.perBankWrBursts::14 17821 # Per bank write bursts -system.physmem.perBankWrBursts::15 17824 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 191861 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 24073 # Per bank write bursts +system.physmem.perBankRdBursts::1 26434 # Per bank write bursts +system.physmem.perBankRdBursts::2 24630 # Per bank write bursts +system.physmem.perBankRdBursts::3 24561 # Per bank write bursts +system.physmem.perBankRdBursts::4 23290 # Per bank write bursts +system.physmem.perBankRdBursts::5 23730 # Per bank write bursts +system.physmem.perBankRdBursts::6 24498 # Per bank write bursts +system.physmem.perBankRdBursts::7 24639 # Per bank write bursts +system.physmem.perBankRdBursts::8 23691 # Per bank write bursts +system.physmem.perBankRdBursts::9 23546 # Per bank write bursts +system.physmem.perBankRdBursts::10 24793 # Per bank write bursts +system.physmem.perBankRdBursts::11 24069 # Per bank write bursts +system.physmem.perBankRdBursts::12 23353 # Per bank write bursts +system.physmem.perBankRdBursts::13 23015 # Per bank write bursts +system.physmem.perBankRdBursts::14 24077 # Per bank write bursts +system.physmem.perBankRdBursts::15 23977 # Per bank write bursts +system.physmem.perBankWrBursts::0 18554 # Per bank write bursts +system.physmem.perBankWrBursts::1 19855 # Per bank write bursts +system.physmem.perBankWrBursts::2 18927 # Per bank write bursts +system.physmem.perBankWrBursts::3 18928 # Per bank write bursts +system.physmem.perBankWrBursts::4 18036 # Per bank write bursts +system.physmem.perBankWrBursts::5 18437 # Per bank write bursts +system.physmem.perBankWrBursts::6 18989 # Per bank write bursts +system.physmem.perBankWrBursts::7 19175 # Per bank write bursts +system.physmem.perBankWrBursts::8 18571 # Per bank write bursts +system.physmem.perBankWrBursts::9 17897 # Per bank write bursts +system.physmem.perBankWrBursts::10 18838 # Per bank write bursts +system.physmem.perBankWrBursts::11 17731 # Per bank write bursts +system.physmem.perBankWrBursts::12 17375 # Per bank write bursts +system.physmem.perBankWrBursts::13 16985 # Per bank write bursts +system.physmem.perBankWrBursts::14 17811 # Per bank write bursts +system.physmem.perBankWrBursts::15 17811 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 451526286000 # Total gap between requests +system.physmem.totGap 455304010000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 386877 # Read request sizes (log2) +system.physmem.readPktSize::6 386718 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 294030 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 381438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 4703 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 355 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.writePktSize::6 293946 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 381427 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 4550 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 37 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -144,395 +144,395 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 6185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 6621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 16894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17467 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 6166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 6575 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 16890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17473 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17565 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17592 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 17612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 17623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 17621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 17592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 17724 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 17701 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 17610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 17799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 17543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 17462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 17616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 17654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 17597 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 17680 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 17600 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17861 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 17481 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 18 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 147686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 294.912829 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.000830 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 322.915309 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 54902 37.17% 37.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 40417 27.37% 64.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13633 9.23% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7488 5.07% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 5349 3.62% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3749 2.54% 85.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3045 2.06% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2781 1.88% 88.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16322 11.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 147686 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 17443 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 22.159892 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 209.587687 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 17430 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 147768 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 294.634833 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.118109 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.876505 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 54825 37.10% 37.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 40414 27.35% 64.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13687 9.26% 73.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7337 4.97% 78.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 5611 3.80% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4054 2.74% 85.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2966 2.01% 87.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2800 1.89% 89.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16074 10.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 147768 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 17438 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 22.156612 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 209.316874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 17424 99.92% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 9 0.05% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 17443 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 17443 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.855415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.780849 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 2.647023 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 17241 98.84% 98.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 150 0.86% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.14% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 7 0.04% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 4 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 2 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 2 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 1 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 17438 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 17438 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.855144 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.781564 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.520616 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 17233 98.82% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 149 0.85% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 26 0.15% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 10 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 2 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 2 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 1 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 3 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 1 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.99% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 17443 # Writes before turning the bus around for reads -system.physmem.totQLat 4244351250 # Total ticks spent queuing -system.physmem.totMemAccLat 11491957500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1932695000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10980.40 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 17438 # Writes before turning the bus around for reads +system.physmem.totQLat 4282128000 # Total ticks spent queuing +system.physmem.totMemAccLat 11526678000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1931880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11082.80 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29730.40 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 54.79 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 41.67 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 54.84 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 41.68 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 29832.80 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 54.31 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 41.31 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 54.36 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 41.32 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.75 # Data bus utilization in percentage -system.physmem.busUtilRead 0.43 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.33 # Data bus utilization in percentage for writes +system.physmem.busUtilRead 0.42 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.32 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.42 # Average write queue length when enqueuing -system.physmem.readRowHits 317756 # Number of row buffer hits during reads -system.physmem.writeRowHits 215101 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.21 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes -system.physmem.avgGap 663124.75 # Average gap between requests -system.physmem.pageHitRate 78.30 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 569336040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 310649625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1526881200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 976788720 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64757369970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 214110228000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 311742647955 # Total energy per rank (pJ) -system.physmem_0.averagePower 690.421834 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 355630472000 # Time in different power states -system.physmem_0.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem.avgWrQLen 21.49 # Average write queue length when enqueuing +system.physmem.readRowHits 317407 # Number of row buffer hits during reads +system.physmem.writeRowHits 215108 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.15 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 73.18 # Row buffer hit rate for writes +system.physmem.avgGap 668911.55 # Average gap between requests +system.physmem.pageHitRate 78.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 571588920 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 311878875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1527575400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 977734800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 29738046000 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 65814252570 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 215448936750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 314390013315 # Total energy per rank (pJ) +system.physmem_0.averagePower 690.509916 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 357849000500 # Time in different power states +system.physmem_0.memoryStateTime::REF 15203500000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 80817135000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 82248835500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 547049160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 298489125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1487951400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 928182240 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 29491394400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 62071035210 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216466682250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 311290783785 # Total energy per rank (pJ) -system.physmem_1.averagePower 689.421031 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 359566067000 # Time in different power states -system.physmem_1.memoryStateTime::REF 15077400000 # Time in different power states +system.physmem_1.actEnergy 545280120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 297523875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1485736200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 926555760 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 29738046000 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 63167759955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 217770421500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 313931323410 # Total energy per rank (pJ) +system.physmem_1.averagePower 689.502473 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 361727973250 # Time in different power states +system.physmem_1.memoryStateTime::REF 15203500000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 76881477500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 78369769250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 231910847 # Number of BP lookups -system.cpu.branchPred.condPredicted 231910847 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 9746486 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 132027793 # Number of BTB lookups -system.cpu.branchPred.BTBHits 129309443 # Number of BTB hits +system.cpu.branchPred.lookups 231646337 # Number of BP lookups +system.cpu.branchPred.condPredicted 231646337 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 9741961 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132013407 # Number of BTB lookups +system.cpu.branchPred.BTBHits 129322217 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.941077 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28045741 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1465755 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.961427 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 28025090 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1471468 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 903052797 # number of cpu cycles simulated +system.cpu.numCycles 910608093 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 186172753 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1278263981 # Number of instructions fetch has processed -system.cpu.fetch.Branches 231910847 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 157355184 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 705668368 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 20227891 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 1132 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 96729 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 811106 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 1664 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 49 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 180547715 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 2736967 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 902865746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.633456 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.342016 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 186242841 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1278548490 # Number of instructions fetch has processed +system.cpu.fetch.Branches 231646337 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 157347307 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 713142960 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 20218451 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 1278 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 97934 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 814720 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 1319 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 68 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 180536939 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 2712428 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 910410345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.611396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.336099 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 492504429 54.55% 54.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 33980590 3.76% 58.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 33251729 3.68% 62.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 33383912 3.70% 65.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 27248388 3.02% 68.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 27817475 3.08% 71.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37350305 4.14% 75.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 33792757 3.74% 79.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 183536161 20.33% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 499900768 54.91% 54.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 34011801 3.74% 58.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 33310917 3.66% 62.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 33621227 3.69% 66.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 27137981 2.98% 68.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 27875262 3.06% 72.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 37328628 4.10% 76.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 33745133 3.71% 79.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 183478628 20.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 902865746 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.256808 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.415492 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 127621918 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 442269855 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 240334233 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 82525795 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 10113945 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 2233625829 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 10113945 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 159854620 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 227411371 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 31769 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 285878914 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 219575127 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 2183611721 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 177740 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 139597859 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 24038652 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 44983183 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2288587317 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5525861457 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 3514141602 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 52752 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 910410345 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.254386 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.404060 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 127581888 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 450063290 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 239948731 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 82707211 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 10109225 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 2232998831 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 10109225 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 159900312 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 230280409 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 34090 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 285603646 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 224482663 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 2183077018 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 183617 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 140318739 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 24297006 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 48974479 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2288425781 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5524582783 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 3513207505 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 61088 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 674546463 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2421 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2405 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 426714045 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 530721549 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 210389629 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 240824950 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 72195473 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2112352245 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 24995 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1828962616 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 418654 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 578669571 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1006826210 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 24443 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 902865746 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.025730 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.070839 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 674384927 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2376 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2343 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 427656429 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 530632285 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 210400238 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 240350662 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 72017394 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2112353898 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 24976 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1828941324 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 423887 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 578689030 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1006760945 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24424 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 910410345 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.008920 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.068672 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 318904182 35.32% 35.32% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 130514441 14.46% 49.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 119555800 13.24% 63.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 110903587 12.28% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 91967934 10.19% 85.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 61336498 6.79% 92.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 43115692 4.78% 97.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19163460 2.12% 99.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 7404152 0.82% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 325758066 35.78% 35.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 130835258 14.37% 50.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 120048462 13.19% 63.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 111501441 12.25% 75.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 91294731 10.03% 85.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 61344237 6.74% 92.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 43225981 4.75% 97.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18968528 2.08% 99.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 7433641 0.82% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 902865746 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 910410345 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11303507 42.48% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.48% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 12206863 45.87% 88.35% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3099868 11.65% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11322546 42.44% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 12279843 46.03% 88.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3074079 11.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 2714574 0.15% 0.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1212750239 66.31% 66.46% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 388692 0.02% 66.48% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 3881011 0.21% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 116 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 435509272 23.81% 90.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 173718712 9.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 2717047 0.15% 0.15% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1212867491 66.32% 66.46% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 388152 0.02% 66.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 3881000 0.21% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 102 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 435396374 23.81% 90.50% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 173691158 9.50% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1828962616 # Type of FU issued -system.cpu.iq.rate 2.025311 # Inst issue rate -system.cpu.iq.fu_busy_cnt 26610238 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014549 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 4587788532 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2691313007 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1799275575 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 31338 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 67501 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 6790 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1852843768 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 14512 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 185242573 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1828941324 # Type of FU issued +system.cpu.iq.rate 2.008483 # Inst issue rate +system.cpu.iq.fu_busy_cnt 26676468 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014586 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 4595362463 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2691335659 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1799336607 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 30885 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 66324 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 6516 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1852886556 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 14189 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 185525718 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 146624129 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 213999 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 388901 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 61229443 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 146532886 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 211598 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 388823 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 61240052 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 19562 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 956 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 19518 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1112 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 10113945 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 166739883 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10207354 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 2112377240 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 401313 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 530726286 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 210389629 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7530 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 4519493 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3556436 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 388901 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 5749904 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 4643271 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 10393175 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1807883955 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 429428539 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 21078661 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 10109225 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 169308479 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10486289 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 2112378874 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 393422 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 530635043 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 210400238 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 7587 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4508389 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3837371 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 388823 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 5739135 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 4588886 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 10328021 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1807829650 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 429333816 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 21111674 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 599547832 # number of memory reference insts executed -system.cpu.iew.exec_branches 171967250 # Number of branches executed -system.cpu.iew.exec_stores 170119293 # Number of stores executed -system.cpu.iew.exec_rate 2.001969 # Inst execution rate -system.cpu.iew.wb_sent 1804612346 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1799282365 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1369352269 # num instructions producing a value -system.cpu.iew.wb_consumers 2092896532 # num instructions consuming a value +system.cpu.iew.exec_refs 599464610 # number of memory reference insts executed +system.cpu.iew.exec_branches 171918385 # Number of branches executed +system.cpu.iew.exec_stores 170130794 # Number of stores executed +system.cpu.iew.exec_rate 1.985299 # Inst execution rate +system.cpu.iew.wb_sent 1804630771 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1799343123 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1369373146 # num instructions producing a value +system.cpu.iew.wb_consumers 2092710816 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.992444 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.654286 # average fanout of values written-back +system.cpu.iew.wb_rate 1.975980 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.654354 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 583616621 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 583611522 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 9832190 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 823756093 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.856118 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.505218 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 9827684 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 831323520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.839222 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.498579 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 355425849 43.15% 43.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 174994405 21.24% 64.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 57317339 6.96% 71.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 86207861 10.47% 81.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 27016335 3.28% 85.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 27048633 3.28% 88.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 9853927 1.20% 89.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 8829984 1.07% 90.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 77061760 9.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 362694832 43.63% 43.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 175144101 21.07% 64.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 57358727 6.90% 71.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 86263805 10.38% 81.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 27150861 3.27% 85.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 27127713 3.26% 88.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 9862872 1.19% 89.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 8848382 1.06% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 76872227 9.25% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 823756093 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 831323520 # Number of insts commited each cycle system.cpu.commit.committedInsts 826877109 # Number of instructions committed system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -578,338 +578,339 @@ system.cpu.commit.op_class_0::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction -system.cpu.commit.bw_lim_events 77061760 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 76872227 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 2859299655 # The number of ROB reads -system.cpu.rob.rob_writes 4304507020 # The number of ROB writes -system.cpu.timesIdled 2587 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 187051 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 2867051516 # The number of ROB reads +system.cpu.rob.rob_writes 4304473794 # The number of ROB writes +system.cpu.timesIdled 2567 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 197748 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 826877109 # Number of Instructions Simulated system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.092125 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.092125 # CPI: Total CPI of All Threads -system.cpu.ipc 0.915646 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.915646 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2763619398 # number of integer regfile reads -system.cpu.int_regfile_writes 1467382261 # number of integer regfile writes -system.cpu.fp_regfile_reads 6855 # number of floating regfile reads -system.cpu.fp_regfile_writes 205 # number of floating regfile writes -system.cpu.cc_regfile_reads 600921704 # number of cc regfile reads -system.cpu.cc_regfile_writes 409683570 # number of cc regfile writes -system.cpu.misc_regfile_reads 991700936 # number of misc regfile reads +system.cpu.cpi 1.101262 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.101262 # CPI: Total CPI of All Threads +system.cpu.ipc 0.908049 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.908049 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2763330538 # number of integer regfile reads +system.cpu.int_regfile_writes 1467435539 # number of integer regfile writes +system.cpu.fp_regfile_reads 6574 # number of floating regfile reads +system.cpu.fp_regfile_writes 209 # number of floating regfile writes +system.cpu.cc_regfile_reads 600926529 # number of cc regfile reads +system.cpu.cc_regfile_writes 409661898 # number of cc regfile writes +system.cpu.misc_regfile_reads 991625144 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2534340 # number of replacements -system.cpu.dcache.tags.tagsinuse 4088.717392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 388713882 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2538436 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 153.131252 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1658510250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4088.717392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998222 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998222 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2532368 # number of replacements +system.cpu.dcache.tags.tagsinuse 4088.654602 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 388337333 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2536464 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 153.101851 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4088.654602 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998207 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998207 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 872 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 3178 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 854 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3198 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 786546356 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 786546356 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 240120715 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 240120715 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148188548 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148188548 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 388309263 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 388309263 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 388309263 # number of overall hits -system.cpu.dcache.overall_hits::total 388309263 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2723043 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2723043 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 971654 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 971654 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3694697 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3694697 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3694697 # number of overall misses -system.cpu.dcache.overall_misses::total 3694697 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 55426039088 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 55426039088 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 27751124058 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 27751124058 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 83177163146 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 83177163146 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 83177163146 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 83177163146 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 242843758 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 242843758 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 785792022 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 785792022 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 239684650 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 239684650 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148177346 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148177346 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 387861996 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 387861996 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 387861996 # number of overall hits +system.cpu.dcache.overall_hits::total 387861996 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2782927 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2782927 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 982856 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 982856 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 3765783 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3765783 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3765783 # number of overall misses +system.cpu.dcache.overall_misses::total 3765783 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 59969889588 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 59969889588 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 31202214310 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 31202214310 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 91172103898 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 91172103898 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 91172103898 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 91172103898 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 242467577 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 242467577 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 392003960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 392003960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 392003960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 392003960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011213 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.011213 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006514 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.006514 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009425 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009425 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009425 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009425 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20354.448713 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 20354.448713 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28560.705825 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28560.705825 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22512.580367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22512.580367 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22512.580367 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9748 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 16 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1054 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 391627779 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 391627779 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 391627779 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 391627779 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.011478 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.011478 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.006589 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.006589 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.009616 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009616 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009616 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009616 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21549.214043 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 21549.214043 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31746.475893 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31746.475893 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24210.663200 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24210.663200 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24210.663200 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24210.663200 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 10538 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 7 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1092 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.248577 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 5.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.650183 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 2.333333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2333101 # number of writebacks -system.cpu.dcache.writebacks::total 2333101 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 955922 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 955922 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18334 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 18334 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 974256 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 974256 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 974256 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 974256 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1767121 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1767121 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 953320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 953320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2720441 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2720441 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2720441 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2720441 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 30613583252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 30613583252 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 25522867191 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 25522867191 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 56136450443 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 56136450443 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 56136450443 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 56136450443 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007277 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.006940 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006940 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006940 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17323.988143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17323.988143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26772.612754 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26772.612754 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20635.055288 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20635.055288 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 2331685 # number of writebacks +system.cpu.dcache.writebacks::total 2331685 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1017273 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1017273 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 18365 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 18365 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1035638 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1035638 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1035638 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1035638 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1765654 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1765654 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 964491 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 964491 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2730145 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2730145 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2730145 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2730145 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32740632750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 32740632750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 29421021688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 29421021688 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 62161654438 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 62161654438 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 62161654438 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 62161654438 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007282 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.006466 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006971 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.006971 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006971 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006971 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18543.062656 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18543.062656 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30504.195154 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 30504.195154 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22768.627468 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 22768.627468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22768.627468 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 22768.627468 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 6998 # number of replacements -system.cpu.icache.tags.tagsinuse 1079.308636 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 180351835 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 6982 # number of replacements +system.cpu.icache.tags.tagsinuse 1087.309225 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 180328938 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8606 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 20956.522775 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 20953.862189 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1079.308636 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.527006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.527006 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1608 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 308 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1173 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 361286153 # Number of tag accesses -system.cpu.icache.tags.data_accesses 361286153 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 180354535 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 180354535 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 180354535 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 180354535 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 180354535 # number of overall hits -system.cpu.icache.overall_hits::total 180354535 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 193180 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 193180 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 193180 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 193180 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 193180 # number of overall misses -system.cpu.icache.overall_misses::total 193180 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1193812485 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1193812485 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1193812485 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1193812485 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1193812485 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1193812485 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 180547715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 180547715 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 180547715 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 180547715 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 180547715 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 180547715 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001070 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001070 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001070 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001070 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001070 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001070 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6179.793379 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 6179.793379 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 6179.793379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 6179.793379 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 6179.793379 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1413 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1087.309225 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.530913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.530913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1624 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 309 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1182 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 361276321 # Number of tag accesses +system.cpu.icache.tags.data_accesses 361276321 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 180331996 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 180331996 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 180331996 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 180331996 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 180331996 # number of overall hits +system.cpu.icache.overall_hits::total 180331996 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 204942 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 204942 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 204942 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 204942 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 204942 # number of overall misses +system.cpu.icache.overall_misses::total 204942 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1305386490 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1305386490 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1305386490 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1305386490 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1305386490 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1305386490 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 180536938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 180536938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 180536938 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 180536938 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 180536938 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 180536938 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001135 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001135 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001135 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001135 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001135 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001135 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 6369.541090 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 6369.541090 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 6369.541090 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 6369.541090 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 6369.541090 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 6369.541090 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1486 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 20 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 88.312500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 74.300000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2457 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2457 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2457 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2457 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2457 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2457 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 190723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 190723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 190723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 190723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 190723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 190723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 707574010 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 707574010 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 707574010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 707574010 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 707574010 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 707574010 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001056 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001056 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001056 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001056 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 3709.956377 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 3709.956377 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 3709.956377 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 3709.956377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 3709.956377 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 3709.956377 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2496 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2496 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2496 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2496 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2496 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2496 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 202446 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 202446 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 202446 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 202446 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 202446 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 202446 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 886113510 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 886113510 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 886113510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 886113510 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 886113510 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 886113510 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001121 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001121 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001121 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001121 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001121 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001121 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 4377.036395 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 4377.036395 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 4377.036395 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 4377.036395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 4377.036395 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 4377.036395 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 354199 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29685.281639 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3704222 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 386558 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 9.582578 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 196871476000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21114.810056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.480656 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8318.990927 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.644373 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007675 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.253875 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.905923 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11759 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20270 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987518 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 41657511 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 41657511 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5087 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1590570 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1595657 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 2333101 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 2333101 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 1869 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 1869 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 564466 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 564466 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5087 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2155036 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2160123 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5087 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2155036 # number of overall hits -system.cpu.l2cache.overall_hits::total 2160123 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3515 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 176333 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 179848 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 180136 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 180136 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 207067 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 207067 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3515 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 383400 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 386915 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3515 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 383400 # number of overall misses -system.cpu.l2cache.overall_misses::total 386915 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 262991000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 12902864208 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13165855208 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 9285601 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 9285601 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 14879233462 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 14879233462 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 262991000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 27782097670 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28045088670 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 262991000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 27782097670 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28045088670 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 8602 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1766903 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1775505 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 2333101 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 2333101 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 182005 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 182005 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 771533 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 771533 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 8602 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2538436 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2547038 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 8602 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2538436 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2547038 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.408626 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099798 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.101294 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989731 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989731 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268384 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.268384 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.408626 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.151038 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.151908 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.408626 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.151038 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.151908 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74819.630156 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73173.281280 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73205.457987 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 51.547725 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 51.547725 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71857.096795 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71857.096795 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74819.630156 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72462.435237 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72483.849605 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74819.630156 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72462.435237 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72483.849605 # average overall miss latency +system.cpu.l2cache.tags.replacements 354037 # number of replacements +system.cpu.l2cache.tags.tagsinuse 29694.655553 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3700890 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 386375 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 9.578492 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 197848612000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21120.417264 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 251.711772 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8322.526517 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.644544 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007682 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.253983 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.906209 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32338 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 224 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 11738 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 20294 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.986877 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 41723459 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 41723459 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 5123 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1589228 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1594351 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 2331685 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 2331685 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1852 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1852 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 564007 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 564007 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5123 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2153235 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2158358 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5123 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2153235 # number of overall hits +system.cpu.l2cache.overall_hits::total 2158358 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3523 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 176215 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 179738 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 191829 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 191829 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 207014 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 207014 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3523 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 383229 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 386752 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3523 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 383229 # number of overall misses +system.cpu.l2cache.overall_misses::total 386752 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 289388750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14251176250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14540565000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 12592097 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 12592097 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 16445422468 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 16445422468 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 289388750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 30696598718 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 30985987468 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 289388750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 30696598718 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 30985987468 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 8646 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1765443 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1774089 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 2331685 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 2331685 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 193681 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 193681 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 771021 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 771021 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 8646 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2536464 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2545110 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 8646 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2536464 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2545110 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.407472 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.099813 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.101313 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990438 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990438 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.268493 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.268493 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.407472 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.151088 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.151959 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.407472 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.151088 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.151959 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82142.705081 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80873.797634 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80898.669174 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 65.642301 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 65.642301 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79441.112524 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79441.112524 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82142.705081 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80099.884711 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80118.493164 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82142.705081 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80099.884711 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80118.493164 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -918,121 +919,127 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 294030 # number of writebacks -system.cpu.l2cache.writebacks::total 294030 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3515 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176333 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 179848 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 180136 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 180136 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207067 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 207067 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3515 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 383400 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 386915 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3515 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 383400 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 386915 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 219087000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10656308208 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10875395208 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1818206868 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1818206868 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12245228538 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12245228538 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 219087000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 22901536746 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23120623746 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 219087000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 22901536746 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23120623746 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099798 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101294 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.989731 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.989731 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268384 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268384 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151038 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.151908 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.408626 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151038 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.151908 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.160740 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60432.864002 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60469.925760 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10093.523049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10093.523049 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59136.552604 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59136.552604 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.160740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59732.751033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59756.338591 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.160740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59732.751033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59756.338591 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 293946 # number of writebacks +system.cpu.l2cache.writebacks::total 293946 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 1 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 176215 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 179737 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 191829 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 191829 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 207014 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 207014 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 383229 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 386751 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 383229 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 386751 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 245309750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12046131750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12291441500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3462043228 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3462043228 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13856748032 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13856748032 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 245309750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25902879782 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26148189532 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 245309750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25902879782 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26148189532 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099813 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.101312 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990438 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990438 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.268493 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.268493 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.151088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.151958 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.407356 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.151088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.151958 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69650.695627 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68360.421928 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68385.705225 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18047.548744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18047.548744 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66936.284657 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66936.284657 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69650.695627 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67591.126407 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.882152 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69650.695627 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67591.126407 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.882152 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 1957626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 1957626 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 2333101 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 182005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 182005 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 771533 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 771533 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 199325 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7773983 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7973308 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 550528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311778368 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 312328896 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 182121 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 5244265 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 1967889 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 1967888 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 2331685 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 193681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 193681 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 771021 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 771021 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 211091 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7791975 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8003066 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553280 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311561536 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 312114816 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 193800 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5264276 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 5244265 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 5264276 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 5244265 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 4971600701 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5264276 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 4991831371 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 286576989 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 304197990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3981486557 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3984504311 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 179848 # Transaction distribution -system.membus.trans_dist::ReadResp 179848 # Transaction distribution -system.membus.trans_dist::Writeback 294030 # Transaction distribution -system.membus.trans_dist::UpgradeReq 180174 # Transaction distribution -system.membus.trans_dist::UpgradeResp 180174 # Transaction distribution -system.membus.trans_dist::ReadExReq 207029 # Transaction distribution -system.membus.trans_dist::ReadExResp 207029 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1428132 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43578048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43578048 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43578048 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 179736 # Transaction distribution +system.membus.trans_dist::ReadResp 179736 # Transaction distribution +system.membus.trans_dist::Writeback 293946 # Transaction distribution +system.membus.trans_dist::UpgradeReq 191861 # Transaction distribution +system.membus.trans_dist::UpgradeResp 191861 # Transaction distribution +system.membus.trans_dist::ReadExReq 206982 # Transaction distribution +system.membus.trans_dist::ReadExResp 206982 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1451104 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43562496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43562496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43562496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 861081 # Request fanout histogram +system.membus.snoop_fanout::samples 872525 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 861081 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 872525 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 861081 # Request fanout histogram -system.membus.reqLayer0.occupancy 3467092000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3996161130 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.snoop_fanout::total 872525 # Request fanout histogram +system.membus.reqLayer0.occupancy 2241314053 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 2430435187 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt index 81d0742cf..43971ad10 100644 --- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.647873 # Number of seconds simulated -sim_ticks 1647872849000 # Number of ticks simulated -final_tick 1647872849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1647872738500 # Number of ticks simulated +final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 845545 # Simulator instruction rate (inst/s) -host_op_rate 1563508 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1685075999 # Simulator tick rate (ticks/s) -host_mem_usage 318276 # Number of bytes of host memory used -host_seconds 977.92 # Real time elapsed on the host +host_inst_rate 730118 # Simulator instruction rate (inst/s) +host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1455043701 # Simulator tick rate (ticks/s) +host_mem_usage 323120 # Number of bytes of host memory used +host_seconds 1132.52 # Real time elapsed on the host sim_insts 826877110 # Number of instructions simulated sim_ops 1528988702 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,46 +26,20 @@ system.physmem.num_reads::total 381143 # Nu system.physmem.num_writes::writebacks 292286 # Number of write requests responded to by this memory system.physmem.num_writes::total 292286 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 73248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 14729564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14802812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 14729565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14802813 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 73248 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 73248 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 11351788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 11351788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 11351788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 11351789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 11351789 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 11351789 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 73248 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 14729564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 26154600 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 174452 # Transaction distribution -system.membus.trans_dist::ReadResp 174452 # Transaction distribution -system.membus.trans_dist::Writeback 292286 # Transaction distribution -system.membus.trans_dist::ReadExReq 206691 # Transaction distribution -system.membus.trans_dist::ReadExResp 206691 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 673429 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 673429 # Request fanout histogram -system.membus.reqLayer0.occupancy 3011737000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 3430300500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.physmem.bw_total::cpu.data 14729565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 26154602 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 551 # Number of system calls -system.cpu.numCycles 3295745698 # number of cpu cycles simulated +system.cpu.numCycles 3295745477 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 826877110 # Number of instructions committed @@ -86,7 +60,7 @@ system.cpu.num_mem_refs 533262343 # nu system.cpu.num_load_insts 384102157 # Number of load instructions system.cpu.num_store_insts 149160186 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 3295745697.998000 # Number of busy cycles +system.cpu.num_busy_cycles 3295745476.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 149758583 # Number of branches fetched @@ -125,13 +99,122 @@ system.cpu.op_class::MemWrite 149160186 9.76% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1528988702 # Class of executed instruction +system.cpu.dcache.tags.replacements 2514362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4086.415780 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 8211725000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415780 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits +system.cpu.dcache.overall_hits::total 530743930 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses +system.cpu.dcache.overall_misses::total 2518458 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704183000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 29704183000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964598500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 18964598500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 48668781500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 48668781500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 48668781500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 48668781500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.752147 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.752147 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.138607 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.138607 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.833489 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 19324.833489 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks +system.cpu.dcache.writebacks::total 2323523 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 27113062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 27113062000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17778032500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 17778032500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 44891094500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 44891094500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 44891094500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15695.752147 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15695.752147 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 22474.138607 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 22474.138607 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17824.833489 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17824.833489 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1253 # number of replacements -system.cpu.icache.tags.tagsinuse 881.356491 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 881.356484 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1068344251 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 2814 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 379653.251955 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 881.356491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 881.356484 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.430350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.430350 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1561 # Occupied blocks per task id @@ -155,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 2814 # n system.cpu.icache.demand_misses::total 2814 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 2814 # number of overall misses system.cpu.icache.overall_misses::total 2814 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 115806000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 115806000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 115806000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 115806000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 115806000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 115806000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 115798500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 115798500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 115798500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 115798500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 115798500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 115798500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1068347065 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1068347065 # number of demand (read+write) accesses @@ -173,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000003 system.cpu.icache.demand_miss_rate::total 0.000003 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000003 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000003 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41153.518124 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 41153.518124 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 41153.518124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 41153.518124 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 41153.518124 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41150.852878 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 41150.852878 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 41150.852878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 41150.852878 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 41150.852878 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -193,34 +276,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 2814 system.cpu.icache.demand_mshr_misses::total 2814 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 2814 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 2814 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 110178000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 110178000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 110178000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 110178000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 110178000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 110178000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 111577500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 111577500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 111577500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 111577500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 111577500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 111577500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39153.518124 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39153.518124 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39153.518124 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 39153.518124 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39650.852878 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39650.852878 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39650.852878 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39650.852878 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 348459 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29286.402664 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 29286.402293 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3655011 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380814 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 9.597890 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 755936431000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 21041.299337 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758519 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344807 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 755936423000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 21041.298927 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 139.758524 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8105.344842 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.642129 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004265 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.247355 # Average percentage of cache occupancy @@ -257,17 +340,17 @@ system.cpu.l2cache.demand_misses::total 381143 # nu system.cpu.l2cache.overall_misses::cpu.inst 1886 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 379257 # number of overall misses system.cpu.l2cache.overall_misses::total 381143 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8973561000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 9071645000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10747939500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 10747939500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 98084000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 19721500500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 19819584500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 98084000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 19721500500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 19819584500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99019500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 9059744000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 9158763500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10851282000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10851282000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 99019500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 19911026000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20010045500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 99019500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 19911026000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20010045500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses) @@ -292,17 +375,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.151171 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.670220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.150591 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.151171 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52006.362672 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.747540 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.808245 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.036286 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.036286 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.389618 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52006.362672 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.359914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.389618 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.386002 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.168052 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.192030 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.021772 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.021772 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.099700 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.386002 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.088331 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.099700 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -324,17 +407,17 @@ system.cpu.l2cache.demand_mshr_misses::total 381143 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1886 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 379257 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 381143 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 75452000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6902758000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6978210000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8267645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8267645000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 75452000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15170403000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15245855000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 75452000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15170403000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15245855000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 76387000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6988941000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7065328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8370987500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8370987500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 76387000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 15359928500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15436315500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 76387000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 15359928500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15436315500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.099898 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.100826 # mshr miss rate for ReadReq accesses @@ -346,127 +429,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.151171 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.670220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.150591 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.151171 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.362672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.683796 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.745191 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.024191 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.024191 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.362672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.324318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.354198 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.120891 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.104308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.126109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.009676 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.009676 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.120891 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.052735 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.062968 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2514362 # number of replacements -system.cpu.dcache.tags.tagsinuse 4086.415783 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 530743930 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2518458 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 210.741624 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 8211724000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4086.415783 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997660 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 4038 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1069043234 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1069043234 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 382374772 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 382374772 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 148369158 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 148369158 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 530743930 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 530743930 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 530743930 # number of overall hits -system.cpu.dcache.overall_hits::total 530743930 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1727414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1727414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 791044 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 791044 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2518458 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2518458 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2518458 # number of overall misses -system.cpu.dcache.overall_misses::total 2518458 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29704283000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29704283000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 18964601500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 18964601500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 48668884500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 48668884500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 48668884500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 48668884500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 384102186 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 149160202 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 533262388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 533262388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 533262388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 533262388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.004497 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005303 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.004723 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.004723 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.004723 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.004723 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17195.810037 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17195.810037 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23974.142399 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 23974.142399 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19324.874387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 19324.874387 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 19324.874387 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2323523 # number of writebacks -system.cpu.dcache.writebacks::total 2323523 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1727414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 791044 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 791044 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2518458 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2518458 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2518458 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26249455000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26249455000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 17382513500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 17382513500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 43631968500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 43631968500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 43631968500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 43631968500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.004497 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005303 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.004723 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.004723 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15195.810037 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15195.810037 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21974.142399 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 21974.142399 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17324.874387 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17324.874387 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 1730228 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2323523 # Transaction distribution @@ -498,5 +472,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 4221000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3777687000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 174452 # Transaction distribution +system.membus.trans_dist::ReadResp 174452 # Transaction distribution +system.membus.trans_dist::Writeback 292286 # Transaction distribution +system.membus.trans_dist::ReadExReq 206691 # Transaction distribution +system.membus.trans_dist::ReadExResp 206691 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1054572 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 43099456 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 673429 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 673429 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 673429 # Request fanout histogram +system.membus.reqLayer0.occupancy 1860874000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1905729000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt index 688c5f811..bccf5186d 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.226819 # Number of seconds simulated -sim_ticks 226818771000 # Number of ticks simulated -final_tick 226818771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.226866 # Number of seconds simulated +sim_ticks 226865901500 # Number of ticks simulated +final_tick 226865901500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 207340 # Simulator instruction rate (inst/s) -host_op_rate 207340 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 117965343 # Simulator tick rate (ticks/s) -host_mem_usage 287544 # Number of bytes of host memory used -host_seconds 1922.76 # Real time elapsed on the host +host_inst_rate 324605 # Simulator instruction rate (inst/s) +host_op_rate 324605 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 184721178 # Simulator tick rate (ticks/s) +host_mem_usage 301676 # Number of bytes of host memory used +host_seconds 1228.15 # Real time elapsed on the host sim_insts 398664665 # Number of instructions simulated sim_ops 398664665 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 249280 # Nu system.physmem.num_reads::cpu.inst 3895 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 3978 # Number of read requests responded to by this memory system.physmem.num_reads::total 7873 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1099027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1122447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2221474 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1099027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1099027 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1099027 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1122447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2221474 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1098799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1122214 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2221012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1098799 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1098799 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1098799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1122214 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2221012 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 7873 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 7873 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 226818689500 # Total gap between requests +system.physmem.totGap 226865813000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6808 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 85 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6816 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 974 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.076822 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.330219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.077184 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 516 33.88% 33.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 348 22.85% 56.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 193 12.67% 69.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 104 6.83% 76.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 58 3.81% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 41 2.69% 82.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 32 2.10% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 40 2.63% 87.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 191 12.54% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation -system.physmem.totQLat 50610250 # Total ticks spent queuing -system.physmem.totMemAccLat 198229000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 1561 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 321.065983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 192.383190 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 328.308816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 550 35.23% 35.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 344 22.04% 57.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 200 12.81% 70.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 103 6.60% 76.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 61 3.91% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 52 3.33% 83.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 34 2.18% 86.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 30 1.92% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 187 11.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1561 # Bytes accessed per row activation +system.physmem.totQLat 54380250 # Total ticks spent queuing +system.physmem.totMemAccLat 201999000 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 39365000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6428.33 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6907.18 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25178.33 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25657.18 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.22 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.22 # Average system read bandwidth in MiByte/s @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6341 # Number of row buffer hits during reads +system.physmem.readRowHits 6303 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28809690.02 # Average gap between requests -system.physmem.pageHitRate 80.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6698160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3654750 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 28815675.47 # Average gap between requests +system.physmem.pageHitRate 80.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6902280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3766125 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 34164000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5823127980 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 130980226500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 151662224190 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.664235 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 217898379000 # Time in different power states -system.physmem_0.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_0.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5855918085 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 130979493750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 151697648400 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.682686 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 217896983750 # Time in different power states +system.physmem_0.memoryStateTime::REF 7575360000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1344256000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1391017250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4808160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2623500 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 4891320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2668875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 26910000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14814352800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5572496700 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 131200078500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 151621269660 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.483670 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 218263346500 # Time in different power states -system.physmem_1.memoryStateTime::REF 7573800000 # Time in different power states +system.physmem_1.refreshEnergy 14817404160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5585732100 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 131216499000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 151654105455 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.490749 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 218290626750 # Time in different power states +system.physmem_1.memoryStateTime::REF 7575360000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 976701000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 994701750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 46273761 # Number of BP lookups +system.cpu.branchPred.lookups 46273750 # Number of BP lookups system.cpu.branchPred.condPredicted 26730646 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 1017469 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25595416 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21359944 # Number of BTB hits +system.cpu.branchPred.BTBLookups 25595406 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21359943 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.452224 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 8341649 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 83.452253 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 8341648 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 323 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 95585470 # DTB read hits +system.cpu.dtb.read_hits 95585469 # DTB read hits system.cpu.dtb.read_misses 115 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 95585585 # DTB read accesses -system.cpu.dtb.write_hits 73606436 # DTB write hits +system.cpu.dtb.read_accesses 95585584 # DTB read accesses +system.cpu.dtb.write_hits 73606437 # DTB write hits system.cpu.dtb.write_misses 857 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 73607293 # DTB write accesses +system.cpu.dtb.write_accesses 73607294 # DTB write accesses system.cpu.dtb.data_hits 169191906 # DTB hits system.cpu.dtb.data_misses 972 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 169192878 # DTB accesses -system.cpu.itb.fetch_hits 98781228 # ITB hits -system.cpu.itb.fetch_misses 1237 # ITB misses +system.cpu.itb.fetch_hits 98781212 # ITB hits +system.cpu.itb.fetch_misses 1236 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 98782465 # ITB accesses +system.cpu.itb.fetch_accesses 98782448 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,59 +293,59 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 453637542 # number of cpu cycles simulated +system.cpu.numCycles 453731803 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664665 # Number of instructions committed system.cpu.committedOps 398664665 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4467797 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4467789 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.137893 # CPI: cycles per instruction -system.cpu.ipc 0.878818 # IPC: instructions per cycle -system.cpu.tickCycles 450174327 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3463215 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.138129 # CPI: cycles per instruction +system.cpu.ipc 0.878635 # IPC: instructions per cycle +system.cpu.tickCycles 450174138 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3557665 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 771 # number of replacements -system.cpu.dcache.tags.tagsinuse 3291.955330 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168028615 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3291.677539 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168028622 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4165 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40343.004802 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40343.006483 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3291.955330 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.803700 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.803700 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3291.677539 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.803632 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.803632 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3394 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 216 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 3114 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.828613 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 336075633 # Number of tag accesses system.cpu.dcache.tags.data_accesses 336075633 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94513823 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94513823 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73514792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73514792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168028615 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168028615 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168028615 # number of overall hits -system.cpu.dcache.overall_hits::total 168028615 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1181 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1181 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5938 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5938 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7119 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7119 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7119 # number of overall misses -system.cpu.dcache.overall_misses::total 7119 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 81009750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 81009750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 391587500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 391587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 472597250 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 472597250 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 472597250 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 472597250 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 94513824 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94513824 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73514798 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73514798 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168028622 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168028622 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168028622 # number of overall hits +system.cpu.dcache.overall_hits::total 168028622 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1180 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1180 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5932 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5932 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7112 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7112 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7112 # number of overall misses +system.cpu.dcache.overall_misses::total 7112 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 88706750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 88706750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 435640500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 435640500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 524347250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 524347250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 524347250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 524347250 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 94515004 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000042 system.cpu.dcache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000042 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68594.199831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68594.199831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65946.025598 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65946.025598 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66385.342042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66385.342042 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66385.342042 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75175.211864 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 75175.211864 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73439.059339 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73439.059339 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73727.116142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73727.116142 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73727.116142 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,28 +382,28 @@ system.cpu.dcache.writebacks::writebacks 654 # nu system.cpu.dcache.writebacks::total 654 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 211 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2743 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2743 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2954 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2954 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2954 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2954 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 970 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 970 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3195 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3195 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2736 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2736 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2947 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2947 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2947 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2947 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 969 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 969 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3196 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3196 # number of WriteReq MSHR misses system.cpu.dcache.demand_mshr_misses::cpu.data 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 4165 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4165 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4165 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 64296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 64296000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 214342750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 214342750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 278638750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 278638750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 278638750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 278638750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 70790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 70790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 240139250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 240139250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 310930000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 310930000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 310930000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 310930000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000043 # mshr miss rate for WriteReq accesses @@ -412,68 +412,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66284.536082 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66284.536082 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67086.932707 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67086.932707 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66900.060024 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66900.060024 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73055.469556 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73055.469556 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75137.437422 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75137.437422 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74653.061224 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 74653.061224 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3196 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.781818 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 98776054 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1918.668562 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 98776038 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 5174 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 19090.849246 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 19090.846154 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.781818 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936905 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936905 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1918.668562 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.936850 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.936850 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1978 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 101 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1281 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.965820 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 197567630 # Number of tag accesses -system.cpu.icache.tags.data_accesses 197567630 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 98776054 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 98776054 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 98776054 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 98776054 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 98776054 # number of overall hits -system.cpu.icache.overall_hits::total 98776054 # number of overall hits +system.cpu.icache.tags.tag_accesses 197567598 # Number of tag accesses +system.cpu.icache.tags.data_accesses 197567598 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 98776038 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 98776038 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 98776038 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 98776038 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 98776038 # number of overall hits +system.cpu.icache.overall_hits::total 98776038 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 5174 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 5174 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 5174 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 5174 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 5174 # number of overall misses system.cpu.icache.overall_misses::total 5174 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 293011250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 293011250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 293011250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 293011250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 293011250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 293011250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 98781228 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 98781228 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 98781228 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 98781228 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 98781228 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 98781228 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 320697250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 320697250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 320697250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 320697250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 320697250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 320697250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 98781212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 98781212 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 98781212 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 98781212 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 98781212 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 98781212 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000052 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000052 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000052 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000052 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000052 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000052 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56631.474681 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 56631.474681 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 56631.474681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 56631.474681 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 56631.474681 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61982.460379 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61982.460379 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61982.460379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61982.460379 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61982.460379 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -488,41 +488,41 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 5174 system.cpu.icache.demand_mshr_misses::total 5174 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 5174 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 5174 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281053750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281053750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281053750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281053750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281053750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281053750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 311289750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 311289750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 311289750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 311289750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 311289750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 311289750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000052 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000052 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000052 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000052 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54320.400077 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54320.400077 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54320.400077 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 54320.400077 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60164.234635 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60164.234635 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60164.234635 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60164.234635 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4426.924727 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 4426.526265 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1494 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 5273 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.283330 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 373.138335 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.752394 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 642.033998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011387 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.019593 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.135099 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 373.084024 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3411.466195 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 641.976046 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011386 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.104110 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.019592 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.135087 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 94 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4443 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.160919 # Percentage of cache occupancy per task id @@ -552,17 +552,17 @@ system.cpu.l2cache.demand_misses::total 7873 # nu system.cpu.l2cache.overall_misses::cpu.inst 3895 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3978 # number of overall misses system.cpu.l2cache.overall_misses::total 7873 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263088750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61866750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 324955500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 210698500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 210698500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 263088750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 272565250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 535654000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 263088750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 272565250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 535654000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 292685750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 68346250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 361032000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 236421750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 236421750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 292685750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 304768000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 597453750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 292685750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 304768000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 597453750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 5174 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 967 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 6141 # number of ReadReq accesses(hits+misses) @@ -587,17 +587,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.843024 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.752802 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955102 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.843024 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67545.250321 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73563.317479 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68613.914696 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67165.604080 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67165.604080 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68036.834752 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67545.250321 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68518.162393 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68036.834752 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75143.966624 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81267.835910 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76231.418919 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75365.556264 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75365.556264 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75886.415598 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75143.966624 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76613.373555 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75886.415598 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -617,17 +617,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7873 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3978 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 214177750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 51424250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 265602000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 171025500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 171025500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 214177750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 222449750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 436627500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 214177750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 222449750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 436627500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 243926750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 57790750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 301717500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 197209250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 197209250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 243926750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 255000000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 498926750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 243926750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 255000000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 498926750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869700 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.771210 # mshr miss rate for ReadReq accesses @@ -639,17 +639,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.843024 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.752802 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955102 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.843024 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54987.869063 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61146.551724 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56081.503378 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54518.807778 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54518.807778 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54987.869063 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55919.997486 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55458.846691 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62625.609756 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68716.706302 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63707.242399 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62865.556264 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62865.556264 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62625.609756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64102.564103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63371.872222 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 6141 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 6141 # Transaction distribution @@ -676,9 +676,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 9993 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 5650500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 8565750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 8584250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6972750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7034000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 4736 # Transaction distribution system.membus.trans_dist::ReadResp 4736 # Transaction distribution @@ -699,9 +699,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 7873 # Request fanout histogram -system.membus.reqLayer0.occupancy 9387500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 9289000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 73877500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 41806250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt index 90aeffe97..7866e7931 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.069652 # Number of seconds simulated -sim_ticks 69651704000 # Number of ticks simulated -final_tick 69651704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.069793 # Number of seconds simulated +sim_ticks 69793219500 # Number of ticks simulated +final_tick 69793219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253977 # Simulator instruction rate (inst/s) -host_op_rate 253977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47101012 # Simulator tick rate (ticks/s) -host_mem_usage 302288 # Number of bytes of host memory used -host_seconds 1478.77 # Real time elapsed on the host +host_inst_rate 248568 # Simulator instruction rate (inst/s) +host_op_rate 248568 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 46191499 # Simulator tick rate (ticks/s) +host_mem_usage 302704 # Number of bytes of host memory used +host_seconds 1510.95 # Real time elapsed on the host sim_insts 375574808 # Number of instructions simulated sim_ops 375574808 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 221568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 255744 # Number of bytes read from this memory -system.physmem.bytes_read::total 477312 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 221568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 221568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3462 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3996 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7458 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3181085 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3671755 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6852840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3181085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3181085 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3181085 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3671755 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6852840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7458 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 221440 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 255808 # Number of bytes read from this memory +system.physmem.bytes_read::total 477248 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 221440 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 221440 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3460 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3997 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7457 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 3172801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3665227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6838028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3172801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3172801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3172801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3665227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6838028 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7457 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7458 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7457 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 477312 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 477248 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 477312 # Total read bytes from the system interface side +system.physmem.bytesReadSys 477248 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 528 # Per bank write bursts -system.physmem.perBankRdBursts::1 655 # Per bank write bursts +system.physmem.perBankRdBursts::0 527 # Per bank write bursts +system.physmem.perBankRdBursts::1 657 # Per bank write bursts system.physmem.perBankRdBursts::2 455 # Per bank write bursts system.physmem.perBankRdBursts::3 602 # Per bank write bursts system.physmem.perBankRdBursts::4 446 # Per bank write bursts system.physmem.perBankRdBursts::5 454 # Per bank write bursts system.physmem.perBankRdBursts::6 515 # Per bank write bursts -system.physmem.perBankRdBursts::7 524 # Per bank write bursts -system.physmem.perBankRdBursts::8 439 # Per bank write bursts -system.physmem.perBankRdBursts::9 406 # Per bank write bursts -system.physmem.perBankRdBursts::10 340 # Per bank write bursts +system.physmem.perBankRdBursts::7 522 # Per bank write bursts +system.physmem.perBankRdBursts::8 438 # Per bank write bursts +system.physmem.perBankRdBursts::9 407 # Per bank write bursts +system.physmem.perBankRdBursts::10 339 # Per bank write bursts system.physmem.perBankRdBursts::11 305 # Per bank write bursts system.physmem.perBankRdBursts::12 414 # Per bank write bursts system.physmem.perBankRdBursts::13 542 # Per bank write bursts -system.physmem.perBankRdBursts::14 454 # Per bank write bursts +system.physmem.perBankRdBursts::14 455 # Per bank write bursts system.physmem.perBankRdBursts::15 379 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 69651614500 # Total gap between requests +system.physmem.totGap 69793123000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7458 # Read request sizes (log2) +system.physmem.readPktSize::6 7457 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4228 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 915 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 293 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1915 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1353 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 350.509978 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 208.904608 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.764111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 423 31.26% 31.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 330 24.39% 55.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 152 11.23% 66.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 83 6.13% 73.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 55 4.07% 77.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 43 3.18% 80.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 38 2.81% 83.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 25 1.85% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 204 15.08% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1353 # Bytes accessed per row activation -system.physmem.totQLat 67034750 # Total ticks spent queuing -system.physmem.totMemAccLat 206872250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37290000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8988.30 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1360 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 348.047059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 208.039838 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.646558 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 428 31.47% 31.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 327 24.04% 55.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 157 11.54% 67.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 92 6.76% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 56 4.12% 77.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 39 2.87% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 33 2.43% 83.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 25 1.84% 85.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 203 14.93% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1360 # Bytes accessed per row activation +system.physmem.totQLat 67335750 # Total ticks spent queuing +system.physmem.totMemAccLat 207154500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37285000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9029.87 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27738.30 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 6.85 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27779.87 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 6.84 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 6.85 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 6.84 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.05 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6096 # Number of row buffer hits during reads +system.physmem.readRowHits 6086 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.74 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9339181.35 # Average gap between requests -system.physmem.pageHitRate 81.74 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5843880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3188625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 32385600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9359410.35 # Average gap between requests +system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5828760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3180375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 32377800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2090226195 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 39955428000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 46636141500 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.595153 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 66468117000 # Time in different power states -system.physmem_0.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_0.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2111779035 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 40020613500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 46732002750 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.624038 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 66577889000 # Time in different power states +system.physmem_0.memoryStateTime::REF 2330380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 855864000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 882777000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 4362120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2380125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 25373400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 4430160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2417250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 25272000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 4549069200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1978191270 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 40053704250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 46613080365 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.264045 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 66630949750 # Time in different power states -system.physmem_1.memoryStateTime::REF 2325700000 # Time in different power states +system.physmem_1.refreshEnergy 4558223280 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2013356565 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 40106949000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 46710648255 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.318049 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 66719394750 # Time in different power states +system.physmem_1.memoryStateTime::REF 2330380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 691630250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 738657750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 51167471 # Number of BP lookups -system.cpu.branchPred.condPredicted 29641015 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1213095 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 25804996 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23600999 # Number of BTB hits +system.cpu.branchPred.lookups 51259743 # Number of BP lookups +system.cpu.branchPred.condPredicted 29683169 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233682 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 26552604 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23664767 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.459030 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 9351091 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 307 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.124091 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 9366329 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 317 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 103696202 # DTB read hits -system.cpu.dtb.read_misses 91462 # DTB read misses -system.cpu.dtb.read_acv 49407 # DTB read access violations -system.cpu.dtb.read_accesses 103787664 # DTB read accesses -system.cpu.dtb.write_hits 79414480 # DTB write hits -system.cpu.dtb.write_misses 1579 # DTB write misses +system.cpu.dtb.read_hits 103795078 # DTB read hits +system.cpu.dtb.read_misses 91880 # DTB read misses +system.cpu.dtb.read_acv 49322 # DTB read access violations +system.cpu.dtb.read_accesses 103886958 # DTB read accesses +system.cpu.dtb.write_hits 79431295 # DTB write hits +system.cpu.dtb.write_misses 1540 # DTB write misses system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_accesses 79416059 # DTB write accesses -system.cpu.dtb.data_hits 183110682 # DTB hits -system.cpu.dtb.data_misses 93041 # DTB misses -system.cpu.dtb.data_acv 49409 # DTB access violations -system.cpu.dtb.data_accesses 183203723 # DTB accesses -system.cpu.itb.fetch_hits 51277820 # ITB hits -system.cpu.itb.fetch_misses 422 # ITB misses +system.cpu.dtb.write_accesses 79432835 # DTB write accesses +system.cpu.dtb.data_hits 183226373 # DTB hits +system.cpu.dtb.data_misses 93420 # DTB misses +system.cpu.dtb.data_acv 49324 # DTB access violations +system.cpu.dtb.data_accesses 183319793 # DTB accesses +system.cpu.itb.fetch_hits 51424924 # ITB hits +system.cpu.itb.fetch_misses 367 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 51278242 # ITB accesses +system.cpu.itb.fetch_accesses 51425291 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,239 +293,239 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 139303411 # number of cpu cycles simulated +system.cpu.numCycles 139586442 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 52063926 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 457094521 # Number of instructions fetch has processed -system.cpu.fetch.Branches 51167471 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 32952090 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 85692281 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2532764 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 52218190 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 457878359 # Number of instructions fetch has processed +system.cpu.fetch.Branches 51259743 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33031096 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 85762697 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2573496 # Number of cycles fetch has spent squashing system.cpu.fetch.TlbCycles 4 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 174 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 13783 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 51277820 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 545278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 139036576 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.287585 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.344928 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 172 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 13442 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 10 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 51424924 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 558112 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 139281263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.287437 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.344389 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 58307337 41.94% 41.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4519216 3.25% 45.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 7280822 5.24% 50.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 5545601 3.99% 54.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 11970286 8.61% 63.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 8019991 5.77% 68.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5933032 4.27% 73.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1884761 1.36% 74.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 35575530 25.59% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 58400466 41.93% 41.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4519538 3.24% 45.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 7300185 5.24% 50.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 5568881 4.00% 54.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 11993718 8.61% 63.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 8035210 5.77% 68.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5954127 4.27% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1896980 1.36% 74.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 35612158 25.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 139036576 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367310 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.281287 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 45112383 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 16348146 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 71787003 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 4526860 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1262184 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 9563244 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 4245 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 451283163 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 14196 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1262184 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 47011024 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5663526 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 519113 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 74309218 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 10271511 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 447721649 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 439815 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2540100 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2926498 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 3600527 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 292278306 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 589607782 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 419965282 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 169642499 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 139281263 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367226 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.280250 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 45296559 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 16238717 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 71951122 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 4512320 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1282545 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 9579038 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 4257 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 452073358 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 14179 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1282545 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 47196926 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5664651 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 519192 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 74460720 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 10157229 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 448418638 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 439172 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2532304 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2861217 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3565763 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 292805975 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 590541853 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 420605547 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169936305 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259532329 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 32745977 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 37893 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 316 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 16173797 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 106306370 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 81667386 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 12470725 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 9729569 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 414594685 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 306 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 406915918 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 484036 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 38878487 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 18208107 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 91 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 139036576 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.926683 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.221929 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 33273646 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 37923 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 320 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 15988914 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 106425467 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 81691000 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 12462225 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 9670397 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 415046688 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 308 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 407272286 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 487219 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 39326693 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 18379010 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 93 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 139281263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.924100 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.223091 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23891494 17.18% 17.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 19616678 14.11% 31.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 22677483 16.31% 47.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 18900240 13.59% 61.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 19609416 14.10% 75.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 14153871 10.18% 85.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 9626410 6.92% 92.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 6209797 4.47% 96.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 4351187 3.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24058662 17.27% 17.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 19633951 14.10% 31.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 22674806 16.28% 47.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 18925755 13.59% 61.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 19544360 14.03% 75.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 14234748 10.22% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 9653364 6.93% 92.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 6204842 4.45% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4350775 3.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 139036576 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 139281263 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 258477 1.29% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 145250 0.73% 2.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 90218 0.45% 2.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 2947 0.01% 2.49% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 3497968 17.50% 19.99% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1676632 8.39% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.38% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 9338598 46.73% 75.10% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4976149 24.90% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 264805 1.33% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 148480 0.74% 2.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 91560 0.46% 2.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 2226 0.01% 2.54% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 3500111 17.53% 20.07% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1672568 8.38% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.44% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 9323721 46.69% 75.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4965817 24.87% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 153207490 37.65% 37.66% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2128182 0.52% 38.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 37392506 9.19% 47.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 7524499 1.85% 49.22% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2804822 0.69% 49.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 16757586 4.12% 54.03% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 1601657 0.39% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 105367868 25.89% 80.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 80097727 19.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 153389569 37.66% 37.67% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2128191 0.52% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 38.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 37431648 9.19% 47.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 7537641 1.85% 49.24% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2804878 0.69% 49.92% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 16758896 4.11% 54.04% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 1606846 0.39% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 54.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 105464958 25.90% 80.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 80116078 19.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 406915918 # Type of FU issued -system.cpu.iq.rate 2.921076 # Inst issue rate -system.cpu.iq.fu_busy_cnt 19986240 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.049116 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 625897049 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 265989715 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 237228631 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 347441639 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 187559752 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 163339265 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 246150914 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 180717663 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 19936358 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 407272286 # Type of FU issued +system.cpu.iq.rate 2.917707 # Inst issue rate +system.cpu.iq.fu_busy_cnt 19969288 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.049032 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 626696170 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 266696972 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 237458259 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 347586172 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 187752417 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 163387975 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 246426590 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 180781403 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 19964423 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 11551883 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 163597 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 76334 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 8146657 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 11670980 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 165408 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 76048 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 8170271 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 381699 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4488 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 382447 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 3767 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1262184 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 4471526 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 139208 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 439574480 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 145285 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 106306370 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 81667386 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 306 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 6690 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 131691 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 76334 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 976027 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 412585 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1388612 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 403157736 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 103837102 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3758182 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1282545 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 4525606 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 90420 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 440059104 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 152527 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 106425467 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 81691000 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 308 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 7009 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 82356 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 76048 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1000879 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 421168 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1422047 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 403473304 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 103936308 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3798982 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 24979489 # number of nop insts executed -system.cpu.iew.exec_refs 183253198 # number of memory reference insts executed -system.cpu.iew.exec_branches 46959989 # Number of branches executed -system.cpu.iew.exec_stores 79416096 # Number of stores executed -system.cpu.iew.exec_rate 2.894098 # Inst execution rate -system.cpu.iew.wb_sent 401401507 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 400567896 # cumulative count of insts written-back -system.cpu.iew.wb_producers 198000452 # num instructions producing a value -system.cpu.iew.wb_consumers 283955606 # num instructions consuming a value +system.cpu.iew.exec_nop 25012108 # number of nop insts executed +system.cpu.iew.exec_refs 183369178 # number of memory reference insts executed +system.cpu.iew.exec_branches 46997600 # Number of branches executed +system.cpu.iew.exec_stores 79432870 # Number of stores executed +system.cpu.iew.exec_rate 2.890491 # Inst execution rate +system.cpu.iew.wb_sent 401684713 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 400846234 # cumulative count of insts written-back +system.cpu.iew.wb_producers 198095133 # num instructions producing a value +system.cpu.iew.wb_consumers 284050882 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.875507 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.697294 # average fanout of values written-back +system.cpu.iew.wb_rate 2.871670 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.697393 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 40912072 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 41395670 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1208897 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 133310723 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.990491 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 3.213946 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1229479 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 133482933 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.986633 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 3.212859 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 48555712 36.42% 36.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 18055923 13.54% 49.97% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 9630862 7.22% 57.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 8737322 6.55% 63.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6426217 4.82% 68.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4404759 3.30% 71.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 4988493 3.74% 75.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2616131 1.96% 77.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 29895304 22.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 48683097 36.47% 36.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 18109981 13.57% 50.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 9618460 7.21% 57.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 8715508 6.53% 63.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6449297 4.83% 68.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4412968 3.31% 71.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 5003390 3.75% 75.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2633066 1.97% 77.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 29857166 22.37% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 133310723 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 133482933 # Number of insts commited each cycle system.cpu.commit.committedInsts 398664583 # Number of instructions committed system.cpu.commit.committedOps 398664583 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -571,128 +571,128 @@ system.cpu.commit.op_class_0::MemWrite 73520729 18.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 398664583 # Class of committed instruction -system.cpu.commit.bw_lim_events 29895304 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 29857166 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 542989097 # The number of ROB reads -system.cpu.rob.rob_writes 884890973 # The number of ROB writes -system.cpu.timesIdled 3476 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 266835 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 543683043 # The number of ROB reads +system.cpu.rob.rob_writes 885930772 # The number of ROB writes +system.cpu.timesIdled 3165 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 305179 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 375574808 # Number of Instructions Simulated system.cpu.committedOps 375574808 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.370907 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.370907 # CPI: Total CPI of All Threads -system.cpu.ipc 2.696092 # IPC: Instructions Per Cycle -system.cpu.ipc_total 2.696092 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 403240146 # number of integer regfile reads -system.cpu.int_regfile_writes 171897288 # number of integer regfile writes -system.cpu.fp_regfile_reads 157938395 # number of floating regfile reads -system.cpu.fp_regfile_writes 105579710 # number of floating regfile writes +system.cpu.cpi 0.371661 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.371661 # CPI: Total CPI of All Threads +system.cpu.ipc 2.690625 # IPC: Instructions Per Cycle +system.cpu.ipc_total 2.690625 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 403591803 # number of integer regfile reads +system.cpu.int_regfile_writes 172078772 # number of integer regfile writes +system.cpu.fp_regfile_reads 157997982 # number of floating regfile reads +system.cpu.fp_regfile_writes 105636085 # number of floating regfile writes system.cpu.misc_regfile_reads 350572 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 798 # number of replacements -system.cpu.dcache.tags.tagsinuse 3297.113166 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 156873476 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4201 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37341.936682 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 806 # number of replacements +system.cpu.dcache.tags.tagsinuse 3297.136243 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 156944357 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4209 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37287.801616 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3297.113166 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.804959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.804959 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3297.136243 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.804965 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.804965 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3403 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3116 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3119 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.830811 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 313794583 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 313794583 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 83372633 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 83372633 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73500836 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73500836 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 7 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 7 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 156873469 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 156873469 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 156873469 # number of overall hits -system.cpu.dcache.overall_hits::total 156873469 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1822 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1822 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 19893 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 19893 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 21715 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21715 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21715 # number of overall misses -system.cpu.dcache.overall_misses::total 21715 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 114608500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 114608500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1125293584 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1125293584 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1239902084 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1239902084 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1239902084 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1239902084 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 83374455 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 83374455 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 313935887 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 313935887 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 83443297 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 83443297 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73501051 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73501051 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 156944348 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 156944348 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 156944348 # number of overall hits +system.cpu.dcache.overall_hits::total 156944348 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1804 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1804 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 19678 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 19678 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 21482 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21482 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21482 # number of overall misses +system.cpu.dcache.overall_misses::total 21482 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 122640500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 122640500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1228413709 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1228413709 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1351054209 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1351054209 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1351054209 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1351054209 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 83445101 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 83445101 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 73520729 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 7 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 156895184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 156895184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 156895184 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 156895184 # number of overall (read+write) accesses +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 9 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 9 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 156965830 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 156965830 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 156965830 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 156965830 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000022 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000022 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000271 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000138 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000138 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000138 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000138 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62902.579583 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62902.579583 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56567.314332 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 56567.314332 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 57098.875616 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 57098.875616 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 57098.875616 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 46396 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 61 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 946 # number of cycles access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000268 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000137 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000137 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000137 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000137 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 67982.538803 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 67982.538803 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62425.739862 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62425.739862 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62892.384741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62892.384741 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62892.384741 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 51314 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 108 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 737 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.044397 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 61 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 69.625509 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 108 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 674 # number of writebacks -system.cpu.dcache.writebacks::total 674 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 824 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 824 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16690 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 16690 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 17514 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 17514 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 17514 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 998 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 998 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3203 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3203 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4201 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4201 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4201 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 67693000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 67693000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235962750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 235962750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 303655750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 303655750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 303655750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 303655750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 682 # number of writebacks +system.cpu.dcache.writebacks::total 682 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 803 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 803 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 16470 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 16470 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 17273 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 17273 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 17273 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 17273 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1001 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1001 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3208 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3208 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4209 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4209 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4209 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4209 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72824500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 72824500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 253362750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 253362750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 326187250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 326187250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 326187250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 326187250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000012 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses @@ -701,198 +701,198 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67828.657315 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67828.657315 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73669.294411 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73669.294411 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72281.778148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72281.778148 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72751.748252 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72751.748252 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78978.413342 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78978.413342 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77497.564742 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77497.564742 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2164 # number of replacements -system.cpu.icache.tags.tagsinuse 1832.364532 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 51272141 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4091 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 12532.911513 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2160 # number of replacements +system.cpu.icache.tags.tagsinuse 1831.206745 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 51419247 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4087 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 12581.171275 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1832.364532 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.894709 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.894709 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1831.206745 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.894144 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.894144 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1927 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 294 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1343 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 289 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1348 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.940918 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 102559731 # Number of tag accesses -system.cpu.icache.tags.data_accesses 102559731 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 51272141 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 51272141 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 51272141 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 51272141 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 51272141 # number of overall hits -system.cpu.icache.overall_hits::total 51272141 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5679 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5679 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5679 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5679 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5679 # number of overall misses -system.cpu.icache.overall_misses::total 5679 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 341090499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 341090499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 341090499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 341090499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 341090499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 341090499 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 51277820 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 51277820 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 51277820 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 51277820 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 51277820 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 51277820 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000111 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000111 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000111 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000111 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000111 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000111 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60061.718436 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 60061.718436 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 60061.718436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 60061.718436 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 60061.718436 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 528 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 102853935 # Number of tag accesses +system.cpu.icache.tags.data_accesses 102853935 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 51419247 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 51419247 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 51419247 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 51419247 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 51419247 # number of overall hits +system.cpu.icache.overall_hits::total 51419247 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5677 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5677 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5677 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5677 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5677 # number of overall misses +system.cpu.icache.overall_misses::total 5677 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 373029250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 373029250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 373029250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 373029250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 373029250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 373029250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 51424924 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 51424924 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 51424924 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 51424924 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 51424924 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 51424924 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000110 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000110 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000110 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000110 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000110 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000110 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 65708.869121 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 65708.869121 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 65708.869121 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 65708.869121 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 65708.869121 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 65708.869121 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 290 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 58.666667 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 58 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1588 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1588 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1588 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1588 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1588 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1588 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4091 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4091 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4091 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4091 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4091 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 250258250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 250258250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 250258250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 250258250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 250258250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 250258250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61172.879492 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61172.879492 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61172.879492 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 61172.879492 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1590 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1590 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1590 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1590 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1590 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1590 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4087 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4087 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4087 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4087 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4087 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4087 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 274156250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 274156250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 274156250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 274156250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 274156250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 274156250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000079 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000079 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000079 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67080.070957 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67080.070957 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67080.070957 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 67080.070957 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67080.070957 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 67080.070957 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4021.632512 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 866 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4864 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.178043 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4023.366871 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 875 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4863 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.179930 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.133834 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2983.663344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 666.835334 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.011326 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091054 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020350 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.122730 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4864 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 535 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4046 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148438 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 79795 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 79795 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 629 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 132 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 372.059378 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2982.142231 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 669.165262 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.011354 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.091008 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020421 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.122783 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 4863 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 529 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4051 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.148407 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 79895 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 79895 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 627 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 134 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 761 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 674 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 674 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 73 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 73 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 629 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 205 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 834 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 629 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 205 # number of overall hits -system.cpu.l2cache.overall_hits::total 834 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3462 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 866 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4328 # number of ReadReq misses +system.cpu.l2cache.Writeback_hits::writebacks 682 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 78 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 78 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 627 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 212 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 839 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 627 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 212 # number of overall hits +system.cpu.l2cache.overall_hits::total 839 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3460 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 867 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4327 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 3130 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 3130 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3462 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3996 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7458 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3462 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3996 # number of overall misses -system.cpu.l2cache.overall_misses::total 7458 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 239866750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 65282000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 305148750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 231929750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 231929750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 239866750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 297211750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 537078500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 239866750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 297211750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 537078500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5089 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 674 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 674 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 3203 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 3203 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 4201 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 8292 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 4201 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 8292 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.846248 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.867735 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.850462 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.977209 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.977209 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.846248 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.951202 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.899421 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846248 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.951202 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.899421 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69285.600809 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75383.371824 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70505.718577 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74098.961661 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74098.961661 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72013.743631 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69285.600809 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74377.314815 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72013.743631 # average overall miss latency +system.cpu.l2cache.demand_misses::cpu.inst 3460 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3997 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 7457 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3460 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3997 # number of overall misses +system.cpu.l2cache.overall_misses::total 7457 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 263476500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70328000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 333804500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 249238250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 249238250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 263476500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 319566250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 583042750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 263476500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 319566250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 583042750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4087 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1001 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5088 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 3208 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 3208 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 4087 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 4209 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 8296 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4087 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 4209 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 8296 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.846587 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.866134 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.850432 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.975686 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.975686 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.846587 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.949632 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.898867 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.846587 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.949632 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.898867 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76149.277457 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 81116.493656 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77144.557430 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79628.833866 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79628.833866 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76149.277457 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79951.526145 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78187.307228 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76149.277457 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79951.526145 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78187.307228 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -901,102 +901,102 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3462 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 866 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4328 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3460 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 867 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4327 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3462 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3996 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7458 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3462 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3996 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7458 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 195982250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54610500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 250592750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 193350250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 193350250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 195982250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 247960750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 443943000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 195982250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 247960750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 443943000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867735 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850462 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.977209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.977209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.899421 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846248 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.951202 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.899421 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56609.546505 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63060.623557 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57900.358133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61773.242812 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61773.242812 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56609.546505 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62052.239740 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59525.744167 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3460 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3997 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7457 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3460 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3997 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 7457 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 220205500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59518000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 279723500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 210540750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 210540750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 220205500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 270058750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 490264250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 220205500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 270058750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 490264250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.866134 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.850432 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.975686 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.975686 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.898867 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.846587 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.949632 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.898867 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63643.208092 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68648.212226 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64646.059626 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67265.415335 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67265.415335 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63643.208092 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67565.361521 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65745.507577 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5089 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 674 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 3203 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 3203 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8182 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9076 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 17258 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 312000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 573824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 5088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5088 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 3208 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 3208 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8174 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9100 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 17274 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 261568 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 313024 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 574592 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8966 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 8978 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 8966 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 8978 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8966 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5157000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 8978 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5171000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 6787250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 6830250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 6700250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 6882750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4328 # Transaction distribution -system.membus.trans_dist::ReadResp 4328 # Transaction distribution +system.membus.trans_dist::ReadReq 4327 # Transaction distribution +system.membus.trans_dist::ReadResp 4327 # Transaction distribution system.membus.trans_dist::ReadExReq 3130 # Transaction distribution system.membus.trans_dist::ReadExResp 3130 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14916 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477312 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 477312 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14914 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14914 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 477248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 477248 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7458 # Request fanout histogram +system.membus.snoop_fanout::samples 7457 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7458 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7457 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7458 # Request fanout histogram -system.membus.reqLayer0.occupancy 9422500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7457 # Request fanout histogram +system.membus.reqLayer0.occupancy 9341500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 69712000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 39310250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt index 01baacd99..97440304f 100644 --- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.567335 # Number of seconds simulated -sim_ticks 567335093000 # Number of ticks simulated -final_tick 567335093000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 567335093500 # Number of ticks simulated +final_tick 567335093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1606485 # Simulator instruction rate (inst/s) -host_op_rate 1606484 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2286169690 # Simulator tick rate (ticks/s) -host_mem_usage 295576 # Number of bytes of host memory used -host_seconds 248.16 # Real time elapsed on the host +host_inst_rate 1360508 # Simulator instruction rate (inst/s) +host_op_rate 1360508 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1936123010 # Simulator tick rate (ticks/s) +host_mem_usage 299124 # Number of bytes of host memory used +host_seconds 293.03 # Real time elapsed on the host sim_insts 398664609 # Number of instructions simulated sim_ops 398664609 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 361550 # In system.physmem.bw_total::cpu.inst 361550 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 447735 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 809285 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 4032 # Transaction distribution -system.membus.trans_dist::ReadResp 4032 # Transaction distribution -system.membus.trans_dist::ReadExReq 3142 # Transaction distribution -system.membus.trans_dist::ReadExResp 3142 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7174 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7174 # Request fanout histogram -system.membus.reqLayer0.occupancy 7174000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 64566000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 215 # Number of system calls -system.cpu.numCycles 1134670186 # number of cpu cycles simulated +system.cpu.numCycles 1134670187 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 398664609 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 168275276 # nu system.cpu.num_load_insts 94754511 # Number of load instructions system.cpu.num_store_insts 73520765 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 1134670186 # Number of busy cycles +system.cpu.num_busy_cycles 1134670187 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 44587535 # Number of branches fetched @@ -144,13 +121,122 @@ system.cpu.op_class::MemWrite 73520765 18.44% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 398664665 # Class of executed instruction +system.cpu.dcache.tags.replacements 764 # number of replacements +system.cpu.dcache.tags.tagsinuse 3288.930570 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930570 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits +system.cpu.dcache.overall_hits::total 168271068 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses +system.cpu.dcache.overall_misses::total 4152 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 649 # number of writebacks +system.cpu.dcache.writebacks::total 649 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45659000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 45659000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 168787000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 168787000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214446000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 214446000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214446000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 214446000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48062.105263 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48062.105263 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52712.991880 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52712.991880 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51648.843931 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51648.843931 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1769 # number of replacements -system.cpu.icache.tags.tagsinuse 1795.138964 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1795.138960 # Cycle average of tags in use system.cpu.icache.tags.total_refs 398660993 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3673 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 108538.250204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1795.138960 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.876533 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1904 # Occupied blocks per task id @@ -174,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 3673 # n system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses system.cpu.icache.overall_misses::total 3673 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 182359000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 182359000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 182359000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 182359000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 182359000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 182359500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 182359500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 182359500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 182359500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 182359500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 182359500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 398664666 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 398664666 # number of demand (read+write) accesses @@ -192,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000009 system.cpu.icache.demand_miss_rate::total 0.000009 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000009 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.516199 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49648.516199 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.516199 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49648.516199 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49648.652328 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49648.652328 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49648.652328 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49648.652328 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49648.652328 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3673 system.cpu.icache.demand_mshr_misses::total 3673 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3673 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3673 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 175013000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 175013000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 175013000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 175013000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176850000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 176850000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176850000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 176850000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176850000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 176850000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000009 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000009 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000009 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47648.516199 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47648.516199 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48148.652328 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48148.652328 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48148.652328 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48148.652328 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3772.485305 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3772.485298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 677 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4566 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.148270 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 371.540221 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475161 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 371.540220 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2770.469918 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 630.475159 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.011339 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084548 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.019241 # Average percentage of cache occupancy @@ -277,17 +363,17 @@ system.cpu.l2cache.demand_misses::total 7174 # nu system.cpu.l2cache.overall_misses::cpu.inst 3205 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 3969 # number of overall misses system.cpu.l2cache.overall_misses::total 7174 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 166660000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43004000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 209664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 163384000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 163384000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 166660000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 206388000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 373048000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 166660000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 206388000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 373048000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 168263000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43417500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 211680500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164955000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 164955000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 168263000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 208372500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 376635500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 168263000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 208372500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 376635500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3673 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 950 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 4623 # number of ReadReq accesses(hits+misses) @@ -312,17 +398,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916805 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.955925 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916805 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.156006 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.124008 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.069696 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.156006 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.069696 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,17 +428,17 @@ system.cpu.l2cache.demand_mshr_misses::total 7174 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 3969 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 7174 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 286960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 286960000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 129802500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33493500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163296000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 127251000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 127251000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 129802500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160744500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 290547000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 129802500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160744500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 290547000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870526 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.872161 # mshr miss rate for ReadReq accesses @@ -364,127 +450,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916805 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.955925 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916805 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 764 # number of replacements -system.cpu.dcache.tags.tagsinuse 3288.930576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168271068 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 4152 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40527.713873 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3288.930576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.802962 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 3388 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 210 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 3112 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.827148 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336554592 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336554592 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 94753540 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 94753540 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 73517528 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 73517528 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 168271068 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168271068 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168271068 # number of overall hits -system.cpu.dcache.overall_hits::total 168271068 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 950 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 950 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3202 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3202 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 4152 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4152 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4152 # number of overall misses -system.cpu.dcache.overall_misses::total 4152 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 47084000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 47084000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 173590000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 173590000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 220674000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 220674000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 220674000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 94754490 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 73520730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168275220 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168275220 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168275220 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168275220 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000010 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000044 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49562.105263 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49562.105263 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54212.991880 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54212.991880 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53148.843931 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53148.843931 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 649 # number of writebacks -system.cpu.dcache.writebacks::total 649 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 950 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 950 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 3202 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 3202 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 4152 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 4152 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 4152 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 45184000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 45184000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 167186000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 212370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 212370000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 212370000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 212370000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47562.105263 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52212.991880 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51148.843931 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51148.843931 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 4623 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution @@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 5509500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 6228000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4032 # Transaction distribution +system.membus.trans_dist::ReadResp 4032 # Transaction distribution +system.membus.trans_dist::ReadExReq 3142 # Transaction distribution +system.membus.trans_dist::ReadExResp 3142 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14348 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 459136 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7174 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 7174 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 7174 # Request fanout histogram +system.membus.reqLayer0.occupancy 7174500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 35870500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt index dd174365b..32197bf04 100644 --- a/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.216828 # Number of seconds simulated -sim_ticks 216828260500 # Number of ticks simulated -final_tick 216828260500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.216865 # Number of seconds simulated +sim_ticks 216864820000 # Number of ticks simulated +final_tick 216864820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 113548 # Simulator instruction rate (inst/s) -host_op_rate 136327 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 90171945 # Simulator tick rate (ticks/s) -host_mem_usage 309844 # Number of bytes of host memory used -host_seconds 2404.61 # Real time elapsed on the host +host_inst_rate 175540 # Simulator instruction rate (inst/s) +host_op_rate 210755 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 139425507 # Simulator tick rate (ticks/s) +host_mem_usage 321524 # Number of bytes of host memory used +host_seconds 1555.42 # Real time elapsed on the host sim_insts 273037856 # Number of instructions simulated sim_ops 327812213 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 219072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 219008 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 266368 # Number of bytes read from this memory -system.physmem.bytes_read::total 485440 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 219072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 219072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3423 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 485376 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 219008 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 219008 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3422 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 4162 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7585 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1010348 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1228475 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2238823 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1010348 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1010348 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1228475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2238823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7585 # Number of read requests accepted +system.physmem.num_reads::total 7584 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1009883 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1228267 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2238150 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1009883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1009883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1009883 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1228267 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2238150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7584 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7585 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7584 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 485440 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 485376 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 485440 # Total read bytes from the system interface side +system.physmem.bytesReadSys 485376 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -53,7 +53,7 @@ system.physmem.perBankRdBursts::8 209 # Pe system.physmem.perBankRdBursts::9 311 # Per bank write bursts system.physmem.perBankRdBursts::10 342 # Per bank write bursts system.physmem.perBankRdBursts::11 428 # Per bank write bursts -system.physmem.perBankRdBursts::12 554 # Per bank write bursts +system.physmem.perBankRdBursts::12 553 # Per bank write bursts system.physmem.perBankRdBursts::13 706 # Per bank write bursts system.physmem.perBankRdBursts::14 637 # Per bank write bursts system.physmem.perBankRdBursts::15 541 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 216828031000 # Total gap between requests +system.physmem.totGap 216864583500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7585 # Read request sizes (log2) +system.physmem.readPktSize::6 7584 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 6628 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 896 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 6626 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 898 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1505 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.360797 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 189.304771 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.736324 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 549 36.48% 36.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 346 22.99% 59.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 165 10.96% 70.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 68 4.52% 74.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 70 4.65% 79.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 58 3.85% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 34 2.26% 85.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 33 2.19% 87.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 182 12.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1505 # Bytes accessed per row activation -system.physmem.totQLat 50845500 # Total ticks spent queuing -system.physmem.totMemAccLat 193064250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 37925000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6703.43 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 317.772817 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.476979 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.358112 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 549 36.05% 36.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 352 23.11% 59.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 179 11.75% 70.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 73 4.79% 75.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 70 4.60% 80.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 53 3.48% 83.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 37 2.43% 86.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 29 1.90% 88.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 181 11.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1523 # Bytes accessed per row activation +system.physmem.totQLat 53728750 # Total ticks spent queuing +system.physmem.totMemAccLat 195928750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 37920000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7084.49 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25453.43 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25834.49 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.24 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.02 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 6073 # Number of row buffer hits during reads +system.physmem.readRowHits 6056 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.07 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 28586424.65 # Average gap between requests -system.physmem.pageHitRate 80.07 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5012280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2734875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 29905200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 28595013.65 # Average gap between requests +system.physmem.pageHitRate 79.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 29952000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5652564030 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 125135988750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 144988075455 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.690273 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 208174326250 # Time in different power states -system.physmem_0.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_0.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5668320825 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 125145525750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 145015982220 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.698913 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 208188918000 # Time in different power states +system.physmem_0.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1410814750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1432738500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6342840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3460875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 29000400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 6486480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3539250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 29031600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 14161870320 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5745534165 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 125054436000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 145000644600 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.748242 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 208036674250 # Time in different power states -system.physmem_1.memoryStateTime::REF 7240220000 # Time in different power states +system.physmem_1.refreshEnergy 14164413120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5831746380 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 125002170000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 145037386830 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.797614 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 207947266000 # Time in different power states +system.physmem_1.memoryStateTime::REF 7241520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1549163250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1674122750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 33221230 # Number of BP lookups -system.cpu.branchPred.condPredicted 17174007 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1583983 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 17995686 # Number of BTB lookups -system.cpu.branchPred.BTBHits 15666979 # Number of BTB hits +system.cpu.branchPred.lookups 33219592 # Number of BP lookups +system.cpu.branchPred.condPredicted 17177082 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1581285 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 17974979 # Number of BTB lookups +system.cpu.branchPred.BTBHits 15661112 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 87.059638 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 6611215 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 87.127290 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 6612085 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 433656521 # number of cpu cycles simulated +system.cpu.numCycles 433729640 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 273037856 # Number of instructions committed system.cpu.committedOps 327812213 # Number of ops (including micro ops) committed -system.cpu.discardedOps 4064410 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 4054235 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.588265 # CPI: cycles per instruction -system.cpu.ipc 0.629618 # IPC: instructions per cycle -system.cpu.tickCycles 430211127 # Number of cycles that the object actually ticked -system.cpu.idleCycles 3445394 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.588533 # CPI: cycles per instruction +system.cpu.ipc 0.629512 # IPC: instructions per cycle +system.cpu.tickCycles 430193160 # Number of cycles that the object actually ticked +system.cpu.idleCycles 3536480 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 1354 # number of replacements -system.cpu.dcache.tags.tagsinuse 3086.009488 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 168783807 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 3085.768991 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 168782225 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4511 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37416.051208 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37415.700510 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3086.009488 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.753420 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.753420 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 3085.768991 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.753362 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.753362 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3157 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 672 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 2432 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.770752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 337586705 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 337586705 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 86714567 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 86714567 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 82047450 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 82047450 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 337583521 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 337583521 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 86712977 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 86712977 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 82047458 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 82047458 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 10895 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10895 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 168762017 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 168762017 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 168762017 # number of overall hits -system.cpu.dcache.overall_hits::total 168762017 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2063 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2063 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5227 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5227 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 7290 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7290 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 7290 # number of overall misses -system.cpu.dcache.overall_misses::total 7290 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 126489706 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 126489706 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 360451750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 360451750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 486941456 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 486941456 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 486941456 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 86716630 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 86716630 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 168760435 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 168760435 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 168760435 # number of overall hits +system.cpu.dcache.overall_hits::total 168760435 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2061 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2061 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5219 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5219 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 7280 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7280 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 7280 # number of overall misses +system.cpu.dcache.overall_misses::total 7280 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 137684956 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 137684956 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 400150250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 400150250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 537835206 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 537835206 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 537835206 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 537835206 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 86715038 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 86715038 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052677 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 10895 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 168769307 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 168769307 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 168769307 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 168769307 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 168767715 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 168767715 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 168767715 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 168767715 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000064 # miss rate for WriteReq accesses @@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000043 system.cpu.dcache.demand_miss_rate::total 0.000043 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000043 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000043 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61313.478429 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 61313.478429 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68959.584848 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68959.584848 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66795.810151 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66795.810151 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66804.927705 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66804.927705 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76671.824104 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76671.824104 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 73878.462363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 73878.462363 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 73878.462363 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,14 +472,14 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 1010 # number of writebacks system.cpu.dcache.writebacks::total 1010 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 422 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 422 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2357 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2357 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2779 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2779 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2779 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 420 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 420 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2349 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2349 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 2769 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2769 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2769 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2769 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1641 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 1641 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2870 # number of WriteReq MSHR misses @@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4511 system.cpu.dcache.demand_mshr_misses::total 4511 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4511 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4511 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 100259792 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 197855250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 298115042 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298115042 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 298115042 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 109745542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 109745542 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 219964750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 219964750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 329710292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 329710292 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 329710292 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 329710292 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61096.765387 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 68939.111498 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66086.242962 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66086.242962 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66877.234613 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66877.234613 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76642.770035 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76642.770035 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73090.288628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 73090.288628 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 36927 # number of replacements -system.cpu.icache.tags.tagsinuse 1924.993634 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 73270394 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 38864 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1885.302439 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 36897 # number of replacements +system.cpu.icache.tags.tagsinuse 1924.852609 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 73252005 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 38834 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1886.285343 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1924.993634 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.939938 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.939938 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1924.852609 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.939869 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.939869 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1937 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 275 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1487 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.945801 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146657382 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146657382 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 73270394 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 73270394 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 73270394 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 73270394 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 73270394 # number of overall hits -system.cpu.icache.overall_hits::total 73270394 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 38865 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 38865 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 38865 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 38865 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 38865 # number of overall misses -system.cpu.icache.overall_misses::total 38865 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 703218247 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 703218247 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 703218247 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 703218247 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 703218247 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 703218247 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 73309259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 73309259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 73309259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 73309259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 73309259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 73309259 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 146620514 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146620514 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 73252005 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 73252005 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 73252005 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 73252005 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 73252005 # number of overall hits +system.cpu.icache.overall_hits::total 73252005 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 38835 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 38835 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 38835 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 38835 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 38835 # number of overall misses +system.cpu.icache.overall_misses::total 38835 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 728456748 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 728456748 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 728456748 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 728456748 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 728456748 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 728456748 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 73290840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 73290840 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 73290840 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 73290840 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 73290840 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 73290840 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000530 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000530 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000530 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000530 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000530 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000530 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18093.869729 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18093.869729 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18093.869729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18093.869729 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18093.869729 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18757.737814 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 18757.737814 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 18757.737814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 18757.737814 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 18757.737814 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,123 +575,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38865 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 38865 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 38865 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 38865 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 38865 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 38865 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 624088753 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 624088753 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 624088753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 624088753 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 624088753 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 624088753 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 38835 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 38835 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 38835 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 38835 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 38835 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 38835 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 668757252 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 668757252 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 668757252 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 668757252 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 668757252 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 668757252 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000530 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000530 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000530 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000530 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16057.860620 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16057.860620 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16057.860620 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16057.860620 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17220.477713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17220.477713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17220.477713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17220.477713 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 4198.559801 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 35809 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 5647 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.341243 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 4197.194159 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 35781 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 5646 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.337407 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 353.760842 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3166.451697 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 678.347263 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.010796 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096632 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.020702 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.128130 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 5647 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 353.722028 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3165.177467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 678.294664 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.010795 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.096594 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.020700 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.128088 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 5646 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1252 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4260 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172333 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 363605 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 363605 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 35439 # number of ReadReq hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 4259 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.172302 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 363364 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 363364 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 35411 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 291 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 35730 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 35702 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 1010 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 1010 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 35439 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 35411 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 307 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 35746 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 35439 # number of overall hits +system.cpu.l2cache.demand_hits::total 35718 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 35411 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 307 # number of overall hits -system.cpu.l2cache.overall_hits::total 35746 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3426 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 35718 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3424 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 1350 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 4776 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 4774 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 2854 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 2854 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3426 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 3424 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 4204 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 7630 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3426 # number of overall misses +system.cpu.l2cache.demand_misses::total 7628 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3424 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4204 # number of overall misses -system.cpu.l2cache.overall_misses::total 7630 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 230834250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 95696250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 326530500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 194789750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 194789750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 230834250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 290486000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 521320250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 230834250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 290486000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 521320250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 38865 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 7628 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 258115750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 105039500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 363155250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 216891750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 216891750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 258115750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 321931250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 580047000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 258115750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 321931250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 580047000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 38835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1641 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 40506 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 40476 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 1010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 2870 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 2870 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 38865 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 38835 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 4511 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 43376 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 38865 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 43346 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 38835 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 4511 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 43376 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088151 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 43346 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.088168 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.822669 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.117908 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.117946 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994425 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.994425 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088151 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088168 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.931944 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.175904 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088151 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.175979 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088168 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.931944 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.175904 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67377.189142 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70886.111111 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68369.032663 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68251.489138 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68251.489138 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68325.065531 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67377.189142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69097.526166 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68325.065531 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.175979 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 75384.272780 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77807.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76069.386259 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75995.707779 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75995.707779 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76041.819612 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75384.272780 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.366794 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76041.819612 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,115 +700,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 42 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 45 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 44 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 42 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 45 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3423 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 44 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3422 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1308 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 4731 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 4730 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2854 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 2854 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3423 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3422 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 4162 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 7585 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3423 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 7584 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3422 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4162 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 7585 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187452250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 77027000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 264479250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 158825750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 158825750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187452250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 235852750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 423305000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187452250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 235852750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 423305000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 7584 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 215130250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 85732250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 300862500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 181193250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 181193250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 215130250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 266925500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 482055750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 215130250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 266925500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 482055750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.797075 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116798 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.116859 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994425 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.994425 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.174866 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088074 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.174964 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088116 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.922634 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.174866 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54762.562080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58889.143731 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55903.455929 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55650.227751 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54762.562080 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56668.128304 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55808.174028 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.174964 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62866.817650 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65544.533639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63607.293869 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63487.473721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63487.473721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62866.817650 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64133.950024 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63562.203323 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 40506 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 40505 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 40476 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 40475 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 1010 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 2870 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 2870 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77729 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 77669 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10032 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 87761 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2487296 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 87701 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2485376 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 353344 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2840640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2838720 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 44386 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 44356 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 44386 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 44356 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 44386 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 23203000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 44356 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 23188000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 58996747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 58975248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 7500458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 7577708 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 4731 # Transaction distribution -system.membus.trans_dist::ReadResp 4731 # Transaction distribution +system.membus.trans_dist::ReadReq 4730 # Transaction distribution +system.membus.trans_dist::ReadResp 4730 # Transaction distribution system.membus.trans_dist::ReadExReq 2854 # Transaction distribution system.membus.trans_dist::ReadExResp 2854 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 15170 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 485440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 15168 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15168 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 485376 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 485376 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7585 # Request fanout histogram +system.membus.snoop_fanout::samples 7584 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7585 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7584 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7585 # Request fanout histogram -system.membus.reqLayer0.occupancy 8964000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7584 # Request fanout histogram +system.membus.reqLayer0.occupancy 8969500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 71030500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 40264250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt index 2e0077bb1..869d3326a 100644 --- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.112624 # Number of seconds simulated -sim_ticks 112623767500 # Number of ticks simulated -final_tick 112623767500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.112554 # Number of seconds simulated +sim_ticks 112553814500 # Number of ticks simulated +final_tick 112553814500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123996 # Simulator instruction rate (inst/s) -host_op_rate 148871 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 51146556 # Simulator tick rate (ticks/s) -host_mem_usage 325020 # Number of bytes of host memory used -host_seconds 2201.98 # Real time elapsed on the host +host_inst_rate 125235 # Simulator instruction rate (inst/s) +host_op_rate 150358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51625290 # Simulator tick rate (ticks/s) +host_mem_usage 326264 # Number of bytes of host memory used +host_seconds 2180.21 # Real time elapsed on the host sim_insts 273037219 # Number of instructions simulated sim_ops 327811601 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 187072 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 169856 # Number of bytes read from this memory -system.physmem.bytes_read::total 469120 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 187072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 187072 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2923 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 2654 # Number of read requests responded to by this memory -system.physmem.num_reads::total 7330 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1661035 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 996166 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 1508172 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4165373 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1661035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1661035 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1661035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 996166 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 1508172 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4165373 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 7330 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 187136 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 114176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 167616 # Number of bytes read from this memory +system.physmem.bytes_read::total 468928 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 187136 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 187136 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2924 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1784 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 2619 # Number of read requests responded to by this memory +system.physmem.num_reads::total 7327 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1662636 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1014413 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 1489208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4166256 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1662636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1662636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1662636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1014413 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 1489208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4166256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 7327 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 7330 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 7327 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 469120 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 468928 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 469120 # Total read bytes from the system interface side +system.physmem.bytesReadSys 468928 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,14 +48,14 @@ system.physmem.neitherReadNorWriteReqs 1 # Nu system.physmem.perBankRdBursts::0 589 # Per bank write bursts system.physmem.perBankRdBursts::1 789 # Per bank write bursts system.physmem.perBankRdBursts::2 601 # Per bank write bursts -system.physmem.perBankRdBursts::3 519 # Per bank write bursts +system.physmem.perBankRdBursts::3 520 # Per bank write bursts system.physmem.perBankRdBursts::4 444 # Per bank write bursts system.physmem.perBankRdBursts::5 346 # Per bank write bursts system.physmem.perBankRdBursts::6 153 # Per bank write bursts -system.physmem.perBankRdBursts::7 257 # Per bank write bursts +system.physmem.perBankRdBursts::7 255 # Per bank write bursts system.physmem.perBankRdBursts::8 219 # Per bank write bursts -system.physmem.perBankRdBursts::9 291 # Per bank write bursts -system.physmem.perBankRdBursts::10 316 # Per bank write bursts +system.physmem.perBankRdBursts::9 290 # Per bank write bursts +system.physmem.perBankRdBursts::10 315 # Per bank write bursts system.physmem.perBankRdBursts::11 411 # Per bank write bursts system.physmem.perBankRdBursts::12 547 # Per bank write bursts system.physmem.perBankRdBursts::13 678 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 112623613500 # Total gap between requests +system.physmem.totGap 112553656000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 7330 # Read request sizes (log2) +system.physmem.readPktSize::6 7327 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,19 +94,19 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3927 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1454 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 496 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 298 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 242 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 139 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 41 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3994 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1457 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 301 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 246 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 150 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 184 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see @@ -190,26 +190,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 340.446389 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 197.878789 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.729899 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 488 35.59% 35.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 298 21.74% 57.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 137 9.99% 67.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 90 6.56% 73.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 49 3.57% 77.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 55 4.01% 81.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 23 1.68% 83.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 1.90% 85.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 205 14.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1371 # Bytes accessed per row activation -system.physmem.totQLat 100359280 # Total ticks spent queuing -system.physmem.totMemAccLat 237796780 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 36650000 # Total ticks spent in databus transfers -system.physmem.avgQLat 13691.58 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1397 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.064424 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.482672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.087808 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 504 36.08% 36.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 315 22.55% 58.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 145 10.38% 69.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 78 5.58% 74.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 51 3.65% 78.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 45 3.22% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.00% 83.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 21 1.50% 84.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 210 15.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1397 # Bytes accessed per row activation +system.physmem.totQLat 96387273 # Total ticks spent queuing +system.physmem.totMemAccLat 233768523 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 36635000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13155.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 32441.58 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 31905.08 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.17 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.17 # Average system read bandwidth in MiByte/s @@ -218,51 +218,51 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.38 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 5950 # Number of row buffer hits during reads +system.physmem.readRowHits 5921 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.17 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.81 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 15364749.45 # Average gap between requests -system.physmem.pageHitRate 81.17 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 4906440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2677125 # Energy for precharge commands per rank (pJ) +system.physmem.avgGap 15361492.56 # Average gap between requests +system.physmem.pageHitRate 80.81 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 4883760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2664750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 28688400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3232257390 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 64737034500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 75361375695 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.161673 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 107692958200 # Time in different power states -system.physmem_0.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_0.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3253381020 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 64676459250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 75317311980 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.186805 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 107592163396 # Time in different power states +system.physmem_0.memoryStateTime::REF 3758300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1167342300 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1200480604 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 5435640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2965875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 28165800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 5654880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3085500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 28158000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 7355811840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3291484950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 64685080500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 75368944605 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.228880 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 107605030400 # Time in different power states -system.physmem_1.memoryStateTime::REF 3760640000 # Time in different power states +system.physmem_1.refreshEnergy 7351234800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3298234320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 64637123250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 75323490750 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.241613 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 107525247142 # Time in different power states +system.physmem_1.memoryStateTime::REF 3758300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1254923350 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1266984612 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 37762202 # Number of BP lookups -system.cpu.branchPred.condPredicted 20178978 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1746186 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18669843 # Number of BTB lookups -system.cpu.branchPred.BTBHits 17301885 # Number of BTB hits +system.cpu.branchPred.lookups 37745757 # Number of BP lookups +system.cpu.branchPred.condPredicted 20165080 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1746215 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18666199 # Number of BTB lookups +system.cpu.branchPred.BTBHits 17299874 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 92.672900 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7228775 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 3814 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 92.680218 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7225607 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3815 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,234 +381,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 225247536 # number of cpu cycles simulated +system.cpu.numCycles 225107630 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12260997 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 334142837 # Number of instructions fetch has processed -system.cpu.fetch.Branches 37762202 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 24530660 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 210950106 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3511423 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1112 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 2317 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 89109626 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 21670 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 224970243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.801560 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.228501 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 12251626 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 334050460 # Number of instructions fetch has processed +system.cpu.fetch.Branches 37745757 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 24525481 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 210773788 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3510701 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1259 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 2425 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 89095014 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 21830 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 224784448 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.802641 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.228554 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 51235855 22.77% 22.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 42807602 19.03% 41.80% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30290628 13.46% 55.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 100636158 44.73% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 51100209 22.73% 22.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 42897495 19.08% 41.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 30052167 13.37% 55.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 100734577 44.81% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 224970243 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.167648 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.483447 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 27756041 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 64007493 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 108311444 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 23274289 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1620976 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 6880269 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 135184 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 363488172 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 6272061 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1620976 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 45214868 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 13194135 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 339970 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 113472539 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 51127755 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 355731319 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 2913591 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 6682784 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 150888 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7653578 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 21157029 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 7934488 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 403383639 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 2533813915 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 350195205 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 194873173 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 224784448 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.167679 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.483959 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 27670459 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 63847459 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 108576617 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 23069322 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1620591 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 6880031 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 135198 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 363530052 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 6167703 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1620591 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 44985233 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 17899875 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 341878 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 113387886 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 46548985 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 355747640 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 2899285 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 6598470 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 195112 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7751940 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 21223571 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 2892429 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 403401871 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 2533892950 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 350207607 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 194891234 # Number of floating rename lookups system.cpu.rename.CommittedMaps 372230051 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 31153588 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17016 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 17052 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 55396743 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 92428788 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 88464605 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1673696 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1845347 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 353205084 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 28025 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 346266425 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 2344670 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 24805703 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 73566871 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 5905 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 224970243 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.539165 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.101848 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 31171820 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17015 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 17024 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 55320329 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 92416671 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 88482299 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1659115 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1844729 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 353235129 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 28024 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 346404668 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 2300304 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 24831082 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 73599170 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 5904 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 224784448 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.541053 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.099675 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 40745402 18.11% 18.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 78348887 34.83% 52.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 60751762 27.00% 79.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 34737500 15.44% 95.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 9740629 4.33% 99.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 637380 0.28% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 8683 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 40431348 17.99% 17.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 78272117 34.82% 52.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 61035980 27.15% 79.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 34788778 15.48% 95.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 9595638 4.27% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 651817 0.29% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 8770 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 224970243 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 224784448 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9315798 7.51% 7.51% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7337 0.01% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.52% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 233455 0.19% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 152510 0.12% 7.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 103371 0.08% 7.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 37180 0.03% 7.94% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 820015 0.66% 8.60% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 318375 0.26% 8.86% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 687813 0.55% 9.41% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 53407928 43.05% 52.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58972553 47.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9471276 7.62% 7.62% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 7330 0.01% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.63% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 257049 0.21% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.83% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 126990 0.10% 7.94% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 92940 0.07% 8.01% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 68000 0.05% 8.06% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 719474 0.58% 8.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 316340 0.25% 8.90% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 682824 0.55% 9.45% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.45% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 53604156 43.13% 52.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58946138 47.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 110648263 31.95% 31.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 2148166 0.62% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 6796965 1.96% 34.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 8667386 2.50% 37.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 3331882 0.96% 38.00% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 1592439 0.46% 38.46% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 20937021 6.05% 44.51% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 7180792 2.07% 46.58% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 7147105 2.06% 48.65% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.70% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 91783076 26.51% 75.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 85858044 24.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 110656025 31.94% 31.94% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 2148357 0.62% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 32.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 6798490 1.96% 34.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 34.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 8668315 2.50% 37.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 3332477 0.96% 37.99% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 1592461 0.46% 38.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 20930112 6.04% 44.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 7182294 2.07% 46.57% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 7148952 2.06% 48.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 175286 0.05% 48.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 91886799 26.53% 75.21% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 85885100 24.79% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 346266425 # Type of FU issued -system.cpu.iq.rate 1.537271 # Inst issue rate -system.cpu.iq.fu_busy_cnt 124056335 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.358268 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 756639732 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 251256110 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 223226406 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 287264366 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 126793395 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 117417412 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 302952760 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 167370000 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 5033832 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 346404668 # Type of FU issued +system.cpu.iq.rate 1.538840 # Inst issue rate +system.cpu.iq.fu_busy_cnt 124292517 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.358807 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 756686876 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 251306416 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 223263085 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 287499729 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 126798006 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 117424806 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 303164482 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 167532703 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 5066223 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6696513 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 13646 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 10697 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 6088988 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6684396 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 13685 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10191 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 6106682 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 151171 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 488903 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 154303 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 567640 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1620976 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2121777 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 321028 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 353233977 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 1620591 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2121620 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 330440 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 353264020 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 92428788 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 88464605 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 16992 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 8078 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 328775 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 10697 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 1220281 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 438299 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1658580 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 342303629 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 90585110 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 3962796 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 92416671 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 88482299 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 16991 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 8046 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 336925 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10191 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 1220622 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 439103 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1659725 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 342414286 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 90666955 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 3990382 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 868 # number of nop insts executed -system.cpu.iew.exec_refs 175167602 # number of memory reference insts executed -system.cpu.iew.exec_branches 31752029 # Number of branches executed -system.cpu.iew.exec_stores 84582492 # Number of stores executed -system.cpu.iew.exec_rate 1.519678 # Inst execution rate -system.cpu.iew.wb_sent 340903564 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 340643818 # cumulative count of insts written-back -system.cpu.iew.wb_producers 153542130 # num instructions producing a value -system.cpu.iew.wb_consumers 265815285 # num instructions consuming a value +system.cpu.iew.exec_nop 867 # number of nop insts executed +system.cpu.iew.exec_refs 175255989 # number of memory reference insts executed +system.cpu.iew.exec_branches 31752931 # Number of branches executed +system.cpu.iew.exec_stores 84589034 # Number of stores executed +system.cpu.iew.exec_rate 1.521114 # Inst execution rate +system.cpu.iew.wb_sent 340946352 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 340687891 # cumulative count of insts written-back +system.cpu.iew.wb_producers 153731206 # num instructions producing a value +system.cpu.iew.wb_consumers 266896125 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.512309 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.577627 # average fanout of values written-back +system.cpu.iew.wb_rate 1.513444 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.575996 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 22999072 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 23077118 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 22120 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1611451 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 221242338 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.481688 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.053337 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1611456 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 221059297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.482915 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.052167 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 87860442 39.71% 39.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 69868164 31.58% 71.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 20927833 9.46% 80.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 13474111 6.09% 86.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 8800250 3.98% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 4584845 2.07% 92.89% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 2913190 1.32% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 2446339 1.11% 95.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 10367164 4.69% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 87356112 39.52% 39.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 70369552 31.83% 71.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 20804455 9.41% 80.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 13442204 6.08% 86.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8808979 3.98% 90.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 4514912 2.04% 92.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 2991653 1.35% 94.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 2424695 1.10% 95.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 10346735 4.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 221242338 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 221059297 # Number of insts commited each cycle system.cpu.commit.committedInsts 273037831 # Number of instructions committed system.cpu.commit.committedOps 327812213 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,387 +654,387 @@ system.cpu.commit.op_class_0::MemWrite 82375617 25.13% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 327812213 # Class of committed instruction -system.cpu.commit.bw_lim_events 10367164 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 10346735 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 561683936 # The number of ROB reads -system.cpu.rob.rob_writes 705354391 # The number of ROB writes -system.cpu.timesIdled 50923 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 277293 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 561599370 # The number of ROB reads +system.cpu.rob.rob_writes 705507733 # The number of ROB writes +system.cpu.timesIdled 50679 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 323182 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 273037219 # Number of Instructions Simulated system.cpu.committedOps 327811601 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.824970 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.824970 # CPI: Total CPI of All Threads -system.cpu.ipc 1.212165 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.212165 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 331186150 # number of integer regfile reads -system.cpu.int_regfile_writes 136908474 # number of integer regfile writes -system.cpu.fp_regfile_reads 187099872 # number of floating regfile reads -system.cpu.fp_regfile_writes 132166295 # number of floating regfile writes -system.cpu.cc_regfile_reads 1296656595 # number of cc regfile reads -system.cpu.cc_regfile_writes 80246016 # number of cc regfile writes -system.cpu.misc_regfile_reads 1182266137 # number of misc regfile reads +system.cpu.cpi 0.824458 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.824458 # CPI: Total CPI of All Threads +system.cpu.ipc 1.212919 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.212919 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 331300708 # number of integer regfile reads +system.cpu.int_regfile_writes 136940215 # number of integer regfile writes +system.cpu.fp_regfile_reads 187107289 # number of floating regfile reads +system.cpu.fp_regfile_writes 132177847 # number of floating regfile writes +system.cpu.cc_regfile_reads 1297030245 # number of cc regfile reads +system.cpu.cc_regfile_writes 80242169 # number of cc regfile writes +system.cpu.misc_regfile_reads 1182847920 # number of misc regfile reads system.cpu.misc_regfile_writes 34421755 # number of misc regfile writes -system.cpu.dcache.tags.replacements 1533739 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.852624 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 163803903 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1534251 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 106.764736 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 77087500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.852624 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999712 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999712 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 1533856 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.843197 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 163689216 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1534368 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 106.681849 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 83394000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.843197 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999694 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999694 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 336684823 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 336684823 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 82726313 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 82726313 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 80985354 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 80985354 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 70429 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 70429 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 10910 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 10910 # number of LoadLockedReq hits +system.cpu.dcache.tags.tag_accesses 336633502 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 336633502 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 82631348 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 82631348 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 80965582 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 80965582 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 70480 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 70480 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 10909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 10909 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 10895 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 10895 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 163711667 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 163711667 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 163782096 # number of overall hits -system.cpu.dcache.overall_hits::total 163782096 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 2704016 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 2704016 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1067345 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1067345 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 19 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 19 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 163596930 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 163596930 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 163667410 # number of overall hits +system.cpu.dcache.overall_hits::total 163667410 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 2773213 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 2773213 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1087117 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1087117 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 18 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 18 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 5 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 5 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 3771361 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3771361 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3771380 # number of overall misses -system.cpu.dcache.overall_misses::total 3771380 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21429430210 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21429430210 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8382362067 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8382362067 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 174750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 174750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 29811792277 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 29811792277 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 29811792277 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 29811792277 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 85430329 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 85430329 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 3860330 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3860330 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3860348 # number of overall misses +system.cpu.dcache.overall_misses::total 3860348 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 22349106216 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 22349106216 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8902471046 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8902471046 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 189750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 189750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 31251577262 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 31251577262 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 31251577262 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 31251577262 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 85404561 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 85404561 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052699 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 82052699 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 70448 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 70448 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10915 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 10915 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 70498 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 70498 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 10914 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 10914 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 10895 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 10895 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 167483028 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 167483028 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 167553476 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 167553476 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.031652 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.031652 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013008 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013008 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000270 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.000270 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 167457260 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 167457260 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 167527758 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 167527758 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032471 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032471 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013249 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013249 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.000255 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.000255 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000458 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000458 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.022518 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.022518 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.022509 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.022509 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 7925.038243 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 7925.038243 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 7853.470122 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 7853.470122 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 34950 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 34950 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 7904.783519 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 7904.783519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 7904.743695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 7904.743695 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.023053 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.023053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.023043 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.023043 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 8058.921625 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 8058.921625 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 8189.064329 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 8189.064329 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37950 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37950 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 8095.571431 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 8095.571431 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 8095.533683 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 8095.533683 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 768686 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 918314 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 111802 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 117385 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 6.875423 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 7.823095 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 966281 # number of writebacks -system.cpu.dcache.writebacks::total 966281 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1390263 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1390263 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 846856 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 846856 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 966341 # number of writebacks +system.cpu.dcache.writebacks::total 966341 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1459499 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1459499 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866472 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 866472 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 5 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 2237119 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 2237119 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 2237119 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 2237119 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313753 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1313753 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220489 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 220489 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 2325971 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 2325971 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 2325971 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 2325971 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1313714 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1313714 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 220645 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 220645 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 11 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 11 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1534242 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1534242 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1534253 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1534253 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9313835285 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 9313835285 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1599508327 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1599508327 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 613250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 613250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10913343612 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10913343612 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10913956862 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10913956862 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015378 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015378 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002687 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002687 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 1534359 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1534359 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1534370 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1534370 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9969290033 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9969290033 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1717345064 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1717345064 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1161750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1161750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11686635097 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11686635097 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11687796847 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11687796847 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015382 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015382 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.002689 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.002689 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.000156 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.000156 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009161 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.009161 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009157 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.009157 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7089.487358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7089.487358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7254.367914 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7254.367914 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 55750 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 55750 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7113.182674 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7113.182674 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7113.531381 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7113.531381 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.009163 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.009163 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.009159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.009159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7588.630427 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7588.630427 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7783.294722 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7783.294722 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 105613.636364 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 105613.636364 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7616.623683 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 7616.623683 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7617.326230 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 7617.326230 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 715275 # number of replacements -system.cpu.icache.tags.tagsinuse 511.840362 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 88389408 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 715787 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 123.485629 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 315060000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.840362 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999688 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999688 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 715719 # number of replacements +system.cpu.icache.tags.tagsinuse 511.828705 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 88373879 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 716231 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 123.387397 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 326261250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.828705 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999665 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999665 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 68 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 244 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 69 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 178935006 # Number of tag accesses -system.cpu.icache.tags.data_accesses 178935006 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 88389408 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 88389408 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 88389408 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 88389408 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 88389408 # number of overall hits -system.cpu.icache.overall_hits::total 88389408 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 720201 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 720201 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 720201 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 720201 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 720201 # number of overall misses -system.cpu.icache.overall_misses::total 720201 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 5943843584 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 5943843584 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 5943843584 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 5943843584 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 5943843584 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 5943843584 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 89109609 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 89109609 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 89109609 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 89109609 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 89109609 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 89109609 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008082 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.008082 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.008082 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.008082 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.008082 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.008082 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8253.034339 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8253.034339 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8253.034339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8253.034339 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8253.034339 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 51882 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 52 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 1935 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 178906226 # Number of tag accesses +system.cpu.icache.tags.data_accesses 178906226 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 88373879 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 88373879 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 88373879 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 88373879 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 88373879 # number of overall hits +system.cpu.icache.overall_hits::total 88373879 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 721118 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 721118 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 721118 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 721118 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 721118 # number of overall misses +system.cpu.icache.overall_misses::total 721118 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 5972962690 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 5972962690 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 5972962690 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 5972962690 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 5972962690 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 5972962690 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 89094997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 89094997 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 89094997 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 89094997 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 89094997 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 89094997 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.008094 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.008094 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.008094 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.008094 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.008094 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.008094 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8282.919980 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8282.919980 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8282.919980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8282.919980 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8282.919980 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 60262 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 95 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2026 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 26.812403 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 29.744324 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 31.666667 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4413 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 4413 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 4413 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 4413 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 4413 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 4413 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 715788 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 715788 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 715788 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 715788 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 715788 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 715788 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 4812391061 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 4812391061 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 4812391061 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 4812391061 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 4812391061 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 4812391061 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008033 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.008033 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008033 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.008033 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6723.207236 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6723.207236 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6723.207236 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6723.207236 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 4886 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 4886 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 4886 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 4886 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 4886 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 4886 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 716232 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 716232 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 716232 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 716232 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 716232 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 716232 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5192936459 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 5192936459 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5192936459 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 5192936459 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5192936459 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 5192936459 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.008039 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.008039 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.008039 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.008039 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7250.355275 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7250.355275 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7250.355275 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7250.355275 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 406270 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 406521 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 191 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 404550 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 404804 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 188 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 28111 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 28140 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 5993.755359 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2805980 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 7304 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 384.170318 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 5993.813794 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2806615 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 7301 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 384.415149 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2575.357550 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2680.182450 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 614.569855 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 123.645504 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.157187 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163585 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037510 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007547 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.365830 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 515 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 6789 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 2575.149913 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2681.614006 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 610.589138 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 126.460737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.157175 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.163673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.037267 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.007719 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.365833 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 517 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 6784 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 16 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::2 344 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 133 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 135 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 775 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5746 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031433 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414368 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 51674481 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 51674481 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 711950 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1312705 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2024655 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 966281 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 966281 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 126 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 5743 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.031555 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.414062 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 51684538 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 51684538 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 712391 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1312672 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2025063 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 966341 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 966341 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 219662 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 219662 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 711950 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1532367 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2244317 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 711950 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1532367 # number of overall hits -system.cpu.l2cache.overall_hits::total 2244317 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2934 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1059 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3993 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 219831 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 219831 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 712391 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1532503 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2244894 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 712391 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1532503 # number of overall hits +system.cpu.l2cache.overall_hits::total 2244894 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2935 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1053 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3988 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 825 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 825 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2934 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1884 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 4818 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2934 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1884 # number of overall misses -system.cpu.l2cache.overall_misses::total 4818 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 179619250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70145000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 249764250 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 15499 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 50824468 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 50824468 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 179619250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 120969468 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 300588718 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 179619250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 120969468 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 300588718 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 714884 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1313764 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2028648 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 966281 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 966281 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 812 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 812 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2935 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1865 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 4800 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2935 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1865 # number of overall misses +system.cpu.l2cache.overall_misses::total 4800 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200800474 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 76846248 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 277646722 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 23499 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57691250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 57691250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 200800474 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 134537498 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 335337972 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 200800474 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 134537498 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 335337972 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 715326 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1313725 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2029051 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 966341 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 966341 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 220487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 220487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 714884 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1534251 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2249135 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 714884 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1534251 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2249135 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004104 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000806 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.001968 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 220643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 220643 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 715326 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1534368 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2249694 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 715326 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1534368 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2249694 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.004103 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000802 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.001965 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003742 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003742 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004104 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.001228 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.002142 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004104 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.001228 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.002142 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61219.921609 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66237.016053 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62550.525920 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15499 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15499 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61605.415758 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61605.415758 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 62388.691988 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61219.921609 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64208.847134 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 62388.691988 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003680 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003680 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.004103 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.001215 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.002134 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.004103 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.001215 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.002134 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68415.834412 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72978.393162 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69620.542126 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 23499 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 23499 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71048.337438 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71048.337438 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 69862.077500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68415.834412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72138.068633 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 69862.077500 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1044,141 +1044,139 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 44 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 98 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 98 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 34 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 47 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 47 # number of ReadExReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 131 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 81 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 131 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 142 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2923 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1026 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3949 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30530 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 30530 # number of HardPFReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::cpu.data 81 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 92 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2924 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1019 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3943 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 30395 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 30395 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 727 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 727 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2923 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 4676 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2923 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30530 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 35206 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 153898250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 59960500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 213858750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 204942291 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6001 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 41351500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 41351500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 153898250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 101312000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 255210250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 153898250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 101312000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 204942291 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 460152541 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000781 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001947 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 765 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 765 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2924 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1784 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 4708 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2924 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1784 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 30395 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 35103 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 175338026 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 66096002 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 241434028 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 176500042 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14001 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 49863251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 49863251 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 175338026 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 115959253 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 291297279 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 175338026 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 115959253 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 176500042 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 467797321 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000776 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001943 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003297 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003297 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.002079 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004089 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001143 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.003467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.003467 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.002093 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.004088 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.001163 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.015653 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52650.786863 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58441.033138 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54155.165865 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 6712.816607 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56879.642366 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56879.642366 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54578.753208 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52650.786863 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57793.496863 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 6712.816607 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13070.287479 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.015603 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59965.125171 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64863.593719 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61231.049455 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 5806.877513 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14001 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65180.720261 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65180.720261 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61872.829014 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59965.125171 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64999.581278 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 5806.877513 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 13326.419993 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2029552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2029552 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 966281 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 32098 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2029957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2029957 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 966341 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 31800 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 220487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 220487 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1430672 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4034787 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5465459 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45752576 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160034048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205786624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 33002 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3248420 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.009881 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.098911 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 220643 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 220643 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1431558 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4035081 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5466639 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 45780864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 160045376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205826240 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 32706 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3248743 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.009788 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.098451 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3216322 99.01% 99.01% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 32098 0.99% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3216943 99.02% 99.02% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 31800 0.98% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3248420 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2574443497 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3248743 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2574812500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1074521893 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1075185997 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2301598998 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2301792968 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 6603 # Transaction distribution -system.membus.trans_dist::ReadResp 6603 # Transaction distribution +system.membus.trans_dist::ReadReq 6562 # Transaction distribution +system.membus.trans_dist::ReadResp 6562 # Transaction distribution system.membus.trans_dist::UpgradeReq 1 # Transaction distribution system.membus.trans_dist::UpgradeResp 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 727 # Transaction distribution -system.membus.trans_dist::ReadExResp 727 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14662 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 14662 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 469120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 469120 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 765 # Transaction distribution +system.membus.trans_dist::ReadExResp 765 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 468928 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 7331 # Request fanout histogram +system.membus.snoop_fanout::samples 7328 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 7331 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 7328 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 7331 # Request fanout histogram -system.membus.reqLayer0.occupancy 9338317 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 7328 # Request fanout histogram +system.membus.reqLayer0.occupancy 9247379 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 68128868 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 38369962 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt index 8e74d72ee..833e406c9 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.201717 # Nu sim_ticks 201717313500 # Number of ticks simulated final_tick 201717313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1117455 # Simulator instruction rate (inst/s) -host_op_rate 1341629 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 825564009 # Simulator tick rate (ticks/s) -host_mem_usage 308812 # Number of bytes of host memory used -host_seconds 244.34 # Real time elapsed on the host +host_inst_rate 1235958 # Simulator instruction rate (inst/s) +host_op_rate 1483905 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 913112758 # Simulator tick rate (ticks/s) +host_mem_usage 308700 # Number of bytes of host memory used +host_seconds 220.91 # Real time elapsed on the host sim_insts 273037594 # Number of instructions simulated sim_ops 327811949 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 880756979 system.membus.pkt_size::total 2275398071 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 517024351 # Request fanout histogram -system.membus.snoop_fanout::mean 4.674359 # Request fanout histogram +system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 168364078 32.56% 32.56% # Request fanout histogram -system.membus.snoop_fanout::5 348660273 67.44% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram +system.membus.snoop_fanout::3 348660273 67.44% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 517024351 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt index c39fe9424..426aa68c6 100644 --- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.517235 # Number of seconds simulated -sim_ticks 517235411000 # Number of ticks simulated -final_tick 517235411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 517235404500 # Number of ticks simulated +final_tick 517235404500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 761441 # Simulator instruction rate (inst/s) -host_op_rate 914138 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1444030997 # Simulator tick rate (ticks/s) -host_mem_usage 318052 # Number of bytes of host memory used -host_seconds 358.19 # Real time elapsed on the host +host_inst_rate 693666 # Simulator instruction rate (inst/s) +host_op_rate 832772 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1315500911 # Simulator tick rate (ticks/s) +host_mem_usage 318184 # Number of bytes of host memory used +host_seconds 393.19 # Real time elapsed on the host sim_insts 272739285 # Number of instructions simulated sim_ops 327433743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 191 # Number of system calls -system.cpu.numCycles 1034470822 # number of cpu cycles simulated +system.cpu.numCycles 1034470809 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 272739285 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 168107847 # nu system.cpu.num_load_insts 85732248 # Number of load instructions system.cpu.num_store_insts 82375599 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 1034470821.998000 # Number of busy cycles +system.cpu.num_busy_cycles 1034470808.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 30563502 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 327812213 # Class of executed instruction system.cpu.dcache.tags.replacements 1332 # number of replacements -system.cpu.dcache.tags.tagsinuse 3078.445016 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3078.445039 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 168359617 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 4478 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 37597.056052 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445016 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 3078.445039 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.751573 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 3146 # Occupied blocks per task id @@ -251,12 +251,12 @@ system.cpu.dcache.overall_misses::cpu.data 4479 # system.cpu.dcache.overall_misses::total 4479 # number of overall misses system.cpu.dcache.ReadReq_miss_latency::cpu.data 78354000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 78354000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 157425500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 157425500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 235779500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 235779500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 235779500 # number of overall miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 157422500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 157422500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 235776500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 235776500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 235776500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 235776500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 86235567 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 82052677 # number of WriteReq accesses(hits+misses) @@ -283,12 +283,12 @@ system.cpu.dcache.overall_miss_rate::cpu.data 0.000027 system.cpu.dcache.overall_miss_rate::total 0.000027 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48849.127182 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 48849.127182 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54813.892758 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54813.892758 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52676.385165 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52676.385165 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52641.102925 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52641.102925 # average overall miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54812.848189 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54812.848189 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52675.714924 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52675.714924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52640.433132 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52640.433132 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,16 +315,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 4475 system.cpu.dcache.demand_mshr_misses::total 4475 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 4478 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 4478 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 75108000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 151681500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 159000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 226789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 226948500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 226948500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75909500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 153114500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 153114500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 160500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 160500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 229024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 229024000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 229184500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 229184500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000019 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for WriteReq accesses @@ -335,24 +335,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000027 system.cpu.dcache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000027 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46854.647536 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52813.892758 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50679.217877 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50679.217877 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50680.772666 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50680.772666 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47354.647536 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47354.647536 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53312.848189 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53312.848189 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51178.547486 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 51178.547486 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51180.102724 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 51180.102724 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13796 # number of replacements -system.cpu.icache.tags.tagsinuse 1766.007645 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1766.007658 # Cycle average of tags in use system.cpu.icache.tags.total_refs 348644749 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15603 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 22344.725309 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007645 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1766.007658 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.862308 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1807 # Occupied blocks per task id @@ -376,12 +376,12 @@ system.cpu.icache.demand_misses::cpu.inst 15603 # n system.cpu.icache.demand_misses::total 15603 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15603 # number of overall misses system.cpu.icache.overall_misses::total 15603 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 312527500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 312527500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 312527500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 312527500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 312527500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 312527500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 312524000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 312524000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 312524000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 312524000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 312524000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 312524000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 348660352 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 348660352 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 348660352 # number of demand (read+write) accesses @@ -394,12 +394,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000045 system.cpu.icache.demand_miss_rate::total 0.000045 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000045 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.962187 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20029.962187 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20029.962187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.962187 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20029.962187 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20029.737871 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20029.737871 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20029.737871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20029.737871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20029.737871 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -414,34 +414,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15603 system.cpu.icache.demand_mshr_misses::total 15603 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15603 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15603 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 281321500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 281321500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 281321500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 281321500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 281321500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 281321500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 289119500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 289119500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 289119500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 289119500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 289119500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 289119500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000045 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000045 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18029.962187 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18029.962187 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18029.962187 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18029.962187 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18529.737871 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18529.737871 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18529.737871 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18529.737871 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 3487.764987 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 3487.765017 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 13310 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4882 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.726342 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 341.623056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427143 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714788 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 341.623060 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2408.427163 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 737.714793 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.010426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073499 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.022513 # Average percentage of cache occupancy @@ -479,17 +479,17 @@ system.cpu.l2cache.demand_misses::total 6832 # nu system.cpu.l2cache.overall_misses::cpu.inst 2609 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses system.cpu.l2cache.overall_misses::total 6832 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135778500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71271000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 207049500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148649500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 148649500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 135778500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 219920500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 355699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 135778500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 219920500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 355699000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137079500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71954500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 209034000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 150074500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 150074500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137079500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 222029000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 359108500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137079500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 222029000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 359108500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses) @@ -514,17 +514,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.340222 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167211 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.340222 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52042.353392 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52136.795903 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52074.823944 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52048.144258 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52048.144258 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52063.670960 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52042.353392 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52076.841108 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52063.670960 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52541.011882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52636.795903 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52573.943662 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52547.093838 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52547.093838 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52562.719555 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52541.011882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52576.130713 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52562.719555 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,17 +544,17 @@ system.cpu.l2cache.demand_mshr_misses::total 6832 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2609 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 6832 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104365000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159045000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114243000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114243000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104365000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168923000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 273288000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104365000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168923000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 273288000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 105665500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 55363500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161029000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 115668000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 115668000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 105665500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 171031500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 276697000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 105665500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 171031500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 276697000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.231042 # mshr miss rate for ReadReq accesses @@ -566,17 +566,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.340222 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167211 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.340222 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40001.916443 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40001.257545 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.050420 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.050420 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40001.916443 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.710395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40001.170960 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500.383289 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.251509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500.383289 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.146370 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 17209 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 17209 # Transaction distribution @@ -591,19 +591,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 21079 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -630,9 +628,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 6833 # Request fanout histogram -system.membus.reqLayer0.occupancy 7260000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 7260500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 61915000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 34587500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt index 7bcf4595f..f83552a37 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.559962 # Number of seconds simulated -sim_ticks 559961514500 # Number of ticks simulated -final_tick 559961514500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.561963 # Number of seconds simulated +sim_ticks 561962991000 # Number of ticks simulated +final_tick 561962991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216839 # Simulator instruction rate (inst/s) -host_op_rate 216839 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 130731039 # Simulator tick rate (ticks/s) -host_mem_usage 291560 # Number of bytes of host memory used -host_seconds 4283.31 # Real time elapsed on the host +host_inst_rate 333136 # Simulator instruction rate (inst/s) +host_op_rate 333136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 201563357 # Simulator tick rate (ticks/s) +host_mem_usage 305440 # Number of bytes of host memory used +host_seconds 2788.02 # Real time elapsed on the host sim_insts 928789150 # Number of instructions simulated sim_ops 928789150 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,45 +25,45 @@ system.physmem.num_reads::cpu.data 288600 # Nu system.physmem.num_reads::total 291519 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 333623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 32985124 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 33318747 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 333623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 333623 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7621438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7621438 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7621438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 333623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 32985124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 40940185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 332435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 32867645 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 33200080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 332435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 332435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7594294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7594294 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7594294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 332435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 32867645 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 40794373 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 291519 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted system.physmem.readBursts 291519 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18640064 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 17152 # Total number of bytes read from write queue +system.physmem.bytesReadDRAM 18640576 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 16640 # Total number of bytes read from write queue system.physmem.bytesWritten 4266560 # Total number of bytes written to DRAM system.physmem.bytesReadSys 18657216 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 268 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 260 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17935 # Per bank write bursts -system.physmem.perBankRdBursts::1 18289 # Per bank write bursts -system.physmem.perBankRdBursts::2 18306 # Per bank write bursts +system.physmem.perBankRdBursts::0 17933 # Per bank write bursts +system.physmem.perBankRdBursts::1 18288 # Per bank write bursts +system.physmem.perBankRdBursts::2 18309 # Per bank write bursts system.physmem.perBankRdBursts::3 18250 # Per bank write bursts -system.physmem.perBankRdBursts::4 18167 # Per bank write bursts -system.physmem.perBankRdBursts::5 18240 # Per bank write bursts -system.physmem.perBankRdBursts::6 18320 # Per bank write bursts -system.physmem.perBankRdBursts::7 18299 # Per bank write bursts -system.physmem.perBankRdBursts::8 18230 # Per bank write bursts -system.physmem.perBankRdBursts::9 18226 # Per bank write bursts -system.physmem.perBankRdBursts::10 18219 # Per bank write bursts -system.physmem.perBankRdBursts::11 18391 # Per bank write bursts -system.physmem.perBankRdBursts::12 18259 # Per bank write bursts -system.physmem.perBankRdBursts::13 18042 # Per bank write bursts -system.physmem.perBankRdBursts::14 17977 # Per bank write bursts -system.physmem.perBankRdBursts::15 18101 # Per bank write bursts +system.physmem.perBankRdBursts::4 18165 # Per bank write bursts +system.physmem.perBankRdBursts::5 18241 # Per bank write bursts +system.physmem.perBankRdBursts::6 18322 # Per bank write bursts +system.physmem.perBankRdBursts::7 18300 # Per bank write bursts +system.physmem.perBankRdBursts::8 18229 # Per bank write bursts +system.physmem.perBankRdBursts::9 18227 # Per bank write bursts +system.physmem.perBankRdBursts::10 18214 # Per bank write bursts +system.physmem.perBankRdBursts::11 18389 # Per bank write bursts +system.physmem.perBankRdBursts::12 18260 # Per bank write bursts +system.physmem.perBankRdBursts::13 18047 # Per bank write bursts +system.physmem.perBankRdBursts::14 17980 # Per bank write bursts +system.physmem.perBankRdBursts::15 18105 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -82,7 +82,7 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 559961438500 # Total gap between requests +system.physmem.totGap 561962908000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -97,9 +97,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 290737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 290755 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 475 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 29 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,20 +144,20 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 997 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see system.physmem.wrQLenPdf::17 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4043 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 4043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 4042 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 4042 # What write queue length does an incoming req see @@ -193,24 +193,24 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 104680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 218.802598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.854989 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 269.267896 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 39513 37.75% 37.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43924 41.96% 79.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8711 8.32% 88.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 724 0.69% 88.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 705 0.67% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 815 0.78% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1323 1.26% 91.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 784 0.75% 92.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8181 7.82% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 104680 # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 106018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 216.046030 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 139.156746 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 265.673827 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41726 39.36% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42732 40.31% 79.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8674 8.18% 87.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 811 0.76% 88.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1515 1.43% 90.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1173 1.11% 91.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 577 0.54% 91.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 518 0.49% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8292 7.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 106018 # Bytes accessed per row activation system.physmem.rdPerTurnAround::samples 4042 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 71.196932 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.193109 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 784.958037 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 71.199159 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.197763 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 784.963064 # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::0-2047 4035 99.83% 99.83% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-14335 1 0.02% 99.85% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.95% # Reads before turning the bus around for writes @@ -219,92 +219,92 @@ system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # system.physmem.rdPerTurnAround::total 4042 # Reads before turning the bus around for writes system.physmem.wrPerTurnAround::samples 4042 # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::mean 16.493073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.471357 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.863386 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3047 75.38% 75.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 992 24.54% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3 0.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.471396 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.862526 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3046 75.36% 75.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 995 24.62% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::total 4042 # Writes before turning the bus around for reads -system.physmem.totQLat 2985206750 # Total ticks spent queuing -system.physmem.totMemAccLat 8446163000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1456255000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10249.60 # Average queueing delay per DRAM burst +system.physmem.totQLat 2975536250 # Total ticks spent queuing +system.physmem.totMemAccLat 8436642500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1456295000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10216.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28999.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 33.29 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.62 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 33.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.62 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28966.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 33.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.59 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 33.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.59 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.32 # Data bus utilization in percentage system.physmem.busUtilRead 0.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 202789 # Number of row buffer hits during reads -system.physmem.writeRowHits 50437 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.64 # Row buffer hit rate for writes -system.physmem.avgGap 1563256.04 # Average gap between requests -system.physmem.pageHitRate 70.75 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 394057440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 215011500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136889000 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.49 # Average write queue length when enqueuing +system.physmem.readRowHits 201381 # Number of row buffer hits during reads +system.physmem.writeRowHits 50515 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.14 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.75 # Row buffer hit rate for writes +system.physmem.avgGap 1568843.58 # Average gap between requests +system.physmem.pageHitRate 70.37 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 399311640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 217878375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136904600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 108420572385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 240867963750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 387824533515 # Total energy per rank (pJ) -system.physmem_0.averagePower 692.597962 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 400029552000 # Time in different power states -system.physmem_0.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_0.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 110801606310 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 239979977250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 389456417535 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.035628 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 398531952000 # Time in different power states +system.physmem_0.memoryStateTime::REF 18764980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 141228516750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 144660363000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 397232640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 216744000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1134299400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 402093720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 219396375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1134346200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 215550720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 36573600960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 108773347950 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 240558511500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 387869287170 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.677886 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 399509975000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18698160000 # Time in different power states +system.physmem_1.refreshEnergy 36704300880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 111289898520 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 239551650750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 389517237165 # Total energy per rank (pJ) +system.physmem_1.averagePower 693.143857 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 397813996000 # Time in different power states +system.physmem_1.memoryStateTime::REF 18764980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 141748516500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 145378777500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 125749069 # Number of BP lookups -system.cpu.branchPred.condPredicted 81144276 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12157130 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 103970439 # Number of BTB lookups -system.cpu.branchPred.BTBHits 83513487 # Number of BTB hits +system.cpu.branchPred.lookups 125749002 # Number of BP lookups +system.cpu.branchPred.condPredicted 81144241 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12157248 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 103981751 # Number of BTB lookups +system.cpu.branchPred.BTBHits 83513628 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.324261 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18691097 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 9450 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.315658 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18691101 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 9451 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 237537681 # DTB read hits -system.cpu.dtb.read_misses 198468 # DTB read misses +system.cpu.dtb.read_hits 237537715 # DTB read hits +system.cpu.dtb.read_misses 198475 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 237736149 # DTB read accesses -system.cpu.dtb.write_hits 98305023 # DTB write hits -system.cpu.dtb.write_misses 7212 # DTB write misses +system.cpu.dtb.read_accesses 237736190 # DTB read accesses +system.cpu.dtb.write_hits 98305031 # DTB write hits +system.cpu.dtb.write_misses 7188 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 98312235 # DTB write accesses -system.cpu.dtb.data_hits 335842704 # DTB hits -system.cpu.dtb.data_misses 205680 # DTB misses +system.cpu.dtb.write_accesses 98312219 # DTB write accesses +system.cpu.dtb.data_hits 335842746 # DTB hits +system.cpu.dtb.data_misses 205663 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 336048384 # DTB accesses -system.cpu.itb.fetch_hits 317138761 # ITB hits +system.cpu.dtb.data_accesses 336048409 # DTB accesses +system.cpu.itb.fetch_hits 317139351 # ITB hits system.cpu.itb.fetch_misses 120 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 317138881 # ITB accesses +system.cpu.itb.fetch_accesses 317139471 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,67 +318,67 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 1119923029 # number of cpu cycles simulated +system.cpu.numCycles 1123925982 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928789150 # Number of instructions committed system.cpu.committedOps 928789150 # Number of ops (including micro ops) committed -system.cpu.discardedOps 27043480 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 27043469 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.205788 # CPI: cycles per instruction -system.cpu.ipc 0.829333 # IPC: instructions per cycle -system.cpu.tickCycles 1060170406 # Number of cycles that the object actually ticked -system.cpu.idleCycles 59752623 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.210098 # CPI: cycles per instruction +system.cpu.ipc 0.826379 # IPC: instructions per cycle +system.cpu.tickCycles 1060172068 # Number of cycles that the object actually ticked +system.cpu.idleCycles 63753914 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 776532 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.890165 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 323503178 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4092.699416 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 323503203 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 780628 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 414.414008 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 845912250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.890165 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999241 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999241 # Average percentage of cache occupancy +system.cpu.dcache.tags.avg_refs 414.414040 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 905250250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.699416 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999194 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999194 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 202 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 949 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1244 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1640 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 952 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1647 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 649485148 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 649485148 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 225339131 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 225339131 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98164047 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98164047 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 323503178 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 323503178 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 323503178 # number of overall hits -system.cpu.dcache.overall_hits::total 323503178 # number of overall hits +system.cpu.dcache.tags.tag_accesses 649485188 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 649485188 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 225339151 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 225339151 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98164052 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98164052 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 323503203 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 323503203 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 323503203 # number of overall hits +system.cpu.dcache.overall_hits::total 323503203 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 711929 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 711929 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137153 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137153 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 849082 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 849082 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 849082 # number of overall misses -system.cpu.dcache.overall_misses::total 849082 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23417135750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23417135750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9028767000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9028767000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32445902750 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32445902750 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32445902750 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32445902750 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 226051060 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 226051060 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 137148 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137148 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 849077 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 849077 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 849077 # number of overall misses +system.cpu.dcache.overall_misses::total 849077 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24941013500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24941013500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10047073750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10047073750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34988087250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34988087250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34988087250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34988087250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 226051080 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 226051080 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 324352260 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 324352260 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 324352260 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 324352260 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 324352280 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 324352280 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 324352280 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 324352280 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003149 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.003149 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001395 # miss rate for WriteReq accesses @@ -387,14 +387,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002618 system.cpu.dcache.demand_miss_rate::total 0.002618 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002618 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32892.515616 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32892.515616 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65829.890706 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65829.890706 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 38212.920248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 38212.920248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 38212.920248 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35033.006803 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35033.006803 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73257.165617 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73257.165617 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 41207.201761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 41207.201761 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 41207.201761 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -407,12 +407,12 @@ system.cpu.dcache.writebacks::writebacks 91489 # nu system.cpu.dcache.writebacks::total 91489 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 312 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 312 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68142 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68142 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 68454 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 68454 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 68454 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 68454 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68137 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68137 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 68449 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 68449 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 68449 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 68449 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711617 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 711617 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69011 # number of WriteReq MSHR misses @@ -421,14 +421,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 780628 system.cpu.dcache.demand_mshr_misses::total 780628 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 780628 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 780628 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21915650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21915650000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4445743250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4445743250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26361393250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26361393250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26361393250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26361393250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23795842750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23795842750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4974141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4974141500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28769984250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28769984250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28769984250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28769984250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003148 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses @@ -437,69 +437,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002407 system.cpu.dcache.demand_mshr_miss_rate::total 0.002407 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002407 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002407 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30796.973653 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30796.973653 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64420.791613 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64420.791613 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33769.469261 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33769.469261 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33439.115072 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33439.115072 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72077.516628 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72077.516628 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36854.922255 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36854.922255 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 10606 # number of replacements -system.cpu.icache.tags.tagsinuse 1687.447497 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 317126411 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 12349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 25680.331282 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 10603 # number of replacements +system.cpu.icache.tags.tagsinuse 1687.326033 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 317127004 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 12346 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 25686.619472 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1687.447497 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.823949 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.823949 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1687.326033 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.823890 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.823890 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1743 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1574 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1575 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.851074 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 634289871 # Number of tag accesses -system.cpu.icache.tags.data_accesses 634289871 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 317126411 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 317126411 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 317126411 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 317126411 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 317126411 # number of overall hits -system.cpu.icache.overall_hits::total 317126411 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 12350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 12350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 12350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 12350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 12350 # number of overall misses -system.cpu.icache.overall_misses::total 12350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 333924000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 333924000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 333924000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 333924000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 333924000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 333924000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 317138761 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 317138761 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 317138761 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 317138761 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 317138761 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 317138761 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 634291048 # Number of tag accesses +system.cpu.icache.tags.data_accesses 634291048 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 317127004 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 317127004 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 317127004 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 317127004 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 317127004 # number of overall hits +system.cpu.icache.overall_hits::total 317127004 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 12347 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 12347 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 12347 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 12347 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 12347 # number of overall misses +system.cpu.icache.overall_misses::total 12347 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 354892250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 354892250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 354892250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 354892250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 354892250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 354892250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 317139351 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 317139351 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 317139351 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 317139351 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 317139351 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 317139351 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000039 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000039 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000039 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000039 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000039 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000039 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27038.380567 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27038.380567 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27038.380567 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27038.380567 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27038.380567 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28743.196728 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 28743.196728 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 28743.196728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 28743.196728 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 28743.196728 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -508,66 +508,66 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12350 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 12350 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 12350 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 12350 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 12350 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 12350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 307968000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 307968000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 307968000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 307968000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 307968000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 307968000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12347 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 12347 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 12347 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 12347 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 12347 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 12347 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 335095750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 335095750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 335095750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 335095750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 335095750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 335095750 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000039 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000039 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24936.680162 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24936.680162 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24936.680162 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 24936.680162 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 27139.851786 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 27139.851786 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27139.851786 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 27139.851786 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27139.851786 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 27139.851786 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 258740 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32601.451844 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 523849 # Total number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 32592.816287 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 523846 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 291476 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.797229 # Average number of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.797218 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2865.934205 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 83.731537 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29651.786103 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087461 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002555 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.904901 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994917 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2877.420242 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 84.474359 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29630.921686 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087812 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002578 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.904264 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994654 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32736 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 275 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2657 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29474 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 272 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2647 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29487 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7436223 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7436223 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 9430 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 7436199 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7436199 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 9427 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 489662 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 499092 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 499089 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91489 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91489 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 2366 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 2366 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 9430 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 9427 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 492028 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 501458 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 9430 # number of overall hits +system.cpu.l2cache.demand_hits::total 501455 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 9427 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 492028 # number of overall hits -system.cpu.l2cache.overall_hits::total 501458 # number of overall hits +system.cpu.l2cache.overall_hits::total 501455 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 2920 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 221955 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 224875 # number of ReadReq misses @@ -579,52 +579,52 @@ system.cpu.l2cache.demand_misses::total 291520 # nu system.cpu.l2cache.overall_misses::cpu.inst 2920 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288600 # number of overall misses system.cpu.l2cache.overall_misses::total 291520 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 201319000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16307399500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16508718500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4353044250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4353044250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 201319000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20660443750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20861762750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 201319000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20660443750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20861762750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 12350 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 223766250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17942761250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18166527500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4880260500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4880260500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 223766250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22823021750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23046788000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 223766250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22823021750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23046788000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 12347 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 711617 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 723967 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 723964 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91489 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91489 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69011 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69011 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 12350 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 12347 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 780628 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 792978 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 12350 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 792975 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 12347 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 780628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 792978 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236437 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 792975 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.236495 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311902 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.310615 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.310616 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.965716 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.965716 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236437 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.236495 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.369702 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.367627 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236437 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.367628 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.236495 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369702 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.367627 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68944.863014 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73471.647406 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73412.867148 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65316.891740 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65316.891740 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71562.029192 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68944.863014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71588.509182 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71562.029192 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.367628 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76632.277397 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80839.635286 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80785.002779 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73227.706505 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73227.706505 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79057.313392 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76632.277397 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79081.849446 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79057.313392 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,68 +646,68 @@ system.cpu.l2cache.demand_mshr_misses::total 291520 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2920 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288600 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 291520 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 164600500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13505684500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13670285000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3519774750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3519774750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 164600500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17025459250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17190059750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 164600500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17025459250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17190059750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 187160250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15168425250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15355585500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4046889000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4046889000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 187160250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19215314250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19402474500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 187160250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19215314250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19402474500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311902 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310615 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.310616 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.965716 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.965716 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.367627 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236437 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.367628 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.236495 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369702 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.367627 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56370.034247 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60848.750873 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60790.594775 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52813.785730 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52813.785730 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56370.034247 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58993.275295 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58966.999691 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.367628 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64095.976027 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68340.092586 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68284.982768 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60723.069998 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60723.069998 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64095.976027 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66581.130457 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66556.237994 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 723967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 723966 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 723964 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 723963 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91489 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69011 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69011 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 24693 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1652745 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1677444 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1677438 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 790144 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55815488 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56605824 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56605632 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 884467 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 884464 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 884467 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 884464 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 884467 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 533722500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 884464 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 533721000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 19152500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 19157750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1222191750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1221759250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) system.membus.trans_dist::ReadReq 224874 # Transaction distribution system.membus.trans_dist::ReadResp 224874 # Transaction distribution @@ -729,9 +729,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 358202 # Request fanout histogram -system.membus.reqLayer0.occupancy 975503000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2745267250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.reqLayer0.occupancy 667013500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1552224500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt index 8cb1b2d37..492f134ce 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt @@ -1,69 +1,69 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.278180 # Number of seconds simulated -sim_ticks 278180234500 # Number of ticks simulated -final_tick 278180234500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.279669 # Number of seconds simulated +sim_ticks 279668927000 # Number of ticks simulated +final_tick 279668927000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 185742 # Simulator instruction rate (inst/s) -host_op_rate 185742 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 61337566 # Simulator tick rate (ticks/s) -host_mem_usage 305284 # Number of bytes of host memory used -host_seconds 4535.23 # Real time elapsed on the host +host_inst_rate 180963 # Simulator instruction rate (inst/s) +host_op_rate 180963 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60079385 # Simulator tick rate (ticks/s) +host_mem_usage 306712 # Number of bytes of host memory used +host_seconds 4654.99 # Real time elapsed on the host sim_insts 842382029 # Number of instructions simulated sim_ops 842382029 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 175680 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18477184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18652864 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 175680 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 175680 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 176256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18476288 # Number of bytes read from this memory +system.physmem.bytes_read::total 18652544 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 176256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 176256 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4267712 # Number of bytes written to this memory system.physmem.bytes_written::total 4267712 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 288706 # Number of read requests responded to by this memory -system.physmem.num_reads::total 291451 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 288692 # Number of read requests responded to by this memory +system.physmem.num_reads::total 291446 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66683 # Number of write requests responded to by this memory system.physmem.num_writes::total 66683 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 631533 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 66421628 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 67053161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 631533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 631533 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 15341536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 15341536 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 15341536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 631533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 66421628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 82394697 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 291451 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 630231 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 66064858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 66695089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 630231 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 630231 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 15259872 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 15259872 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 15259872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 630231 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 66064858 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 81954961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 291446 # Number of read requests accepted system.physmem.writeReqs 66683 # Number of write requests accepted -system.physmem.readBursts 291451 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 291446 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66683 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18633536 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue -system.physmem.bytesWritten 4266432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18652864 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18633664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18880 # Total number of bytes read from write queue +system.physmem.bytesWritten 4265984 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18652544 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4267712 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 295 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 17916 # Per bank write bursts -system.physmem.perBankRdBursts::1 18271 # Per bank write bursts +system.physmem.perBankRdBursts::0 17911 # Per bank write bursts +system.physmem.perBankRdBursts::1 18258 # Per bank write bursts system.physmem.perBankRdBursts::2 18306 # Per bank write bursts -system.physmem.perBankRdBursts::3 18248 # Per bank write bursts -system.physmem.perBankRdBursts::4 18157 # Per bank write bursts -system.physmem.perBankRdBursts::5 18220 # Per bank write bursts -system.physmem.perBankRdBursts::6 18319 # Per bank write bursts -system.physmem.perBankRdBursts::7 18312 # Per bank write bursts -system.physmem.perBankRdBursts::8 18226 # Per bank write bursts -system.physmem.perBankRdBursts::9 18223 # Per bank write bursts -system.physmem.perBankRdBursts::10 18210 # Per bank write bursts -system.physmem.perBankRdBursts::11 18385 # Per bank write bursts -system.physmem.perBankRdBursts::12 18240 # Per bank write bursts -system.physmem.perBankRdBursts::13 18040 # Per bank write bursts -system.physmem.perBankRdBursts::14 17965 # Per bank write bursts -system.physmem.perBankRdBursts::15 18111 # Per bank write bursts +system.physmem.perBankRdBursts::3 18250 # Per bank write bursts +system.physmem.perBankRdBursts::4 18158 # Per bank write bursts +system.physmem.perBankRdBursts::5 18224 # Per bank write bursts +system.physmem.perBankRdBursts::6 18321 # Per bank write bursts +system.physmem.perBankRdBursts::7 18307 # Per bank write bursts +system.physmem.perBankRdBursts::8 18228 # Per bank write bursts +system.physmem.perBankRdBursts::9 18222 # Per bank write bursts +system.physmem.perBankRdBursts::10 18213 # Per bank write bursts +system.physmem.perBankRdBursts::11 18393 # Per bank write bursts +system.physmem.perBankRdBursts::12 18247 # Per bank write bursts +system.physmem.perBankRdBursts::13 18043 # Per bank write bursts +system.physmem.perBankRdBursts::14 17966 # Per bank write bursts +system.physmem.perBankRdBursts::15 18104 # Per bank write bursts system.physmem.perBankWrBursts::0 4125 # Per bank write bursts system.physmem.perBankWrBursts::1 4164 # Per bank write bursts system.physmem.perBankWrBursts::2 4223 # Per bank write bursts @@ -73,7 +73,7 @@ system.physmem.perBankWrBursts::5 4099 # Pe system.physmem.perBankWrBursts::6 4262 # Per bank write bursts system.physmem.perBankWrBursts::7 4226 # Per bank write bursts system.physmem.perBankWrBursts::8 4233 # Per bank write bursts -system.physmem.perBankWrBursts::9 4187 # Per bank write bursts +system.physmem.perBankWrBursts::9 4180 # Per bank write bursts system.physmem.perBankWrBursts::10 4150 # Per bank write bursts system.physmem.perBankWrBursts::11 4241 # Per bank write bursts system.physmem.perBankWrBursts::12 4098 # Per bank write bursts @@ -82,14 +82,14 @@ system.physmem.perBankWrBursts::14 4096 # Pe system.physmem.perBankWrBursts::15 4157 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 278180151500 # Total gap between requests +system.physmem.totGap 279668837500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 291451 # Read request sizes (log2) +system.physmem.readPktSize::6 291446 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,13 +97,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66683 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 211637 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46647 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 32683 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 154 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 215531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 47086 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 28307 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 198 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,25 +144,25 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4089 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4097 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4725 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4058 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 11 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see @@ -193,118 +193,117 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 100542 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 227.760100 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 146.180809 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 278.034024 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36066 35.87% 35.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 42234 42.01% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10234 10.18% 88.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 483 0.48% 88.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 471 0.47% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 384 0.38% 89.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 767 0.76% 90.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1163 1.16% 91.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8740 8.69% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 100542 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4045 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 70.840049 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.159268 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 778.757650 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 4038 99.83% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-14335 2 0.05% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-16383 4 0.10% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 100388 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 228.091007 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.320458 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 278.791024 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35777 35.64% 35.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 42525 42.36% 78.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10061 10.02% 88.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 470 0.47% 88.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 508 0.51% 89.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 391 0.39% 89.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 492 0.49% 89.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1510 1.50% 91.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8654 8.62% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100388 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4044 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 69.235658 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.129419 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 756.508896 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 4037 99.83% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::6144-8191 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-16383 5 0.12% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::32768-34815 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4045 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4045 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.480346 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.459004 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.856073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3075 76.02% 76.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1 0.02% 76.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 965 23.86% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4 0.10% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4045 # Writes before turning the bus around for reads -system.physmem.totQLat 3369536750 # Total ticks spent queuing -system.physmem.totMemAccLat 8828580500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1455745000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11573.24 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4044 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4044 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.482690 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.461191 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.859365 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3072 75.96% 75.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 964 23.84% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 8 0.20% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4044 # Writes before turning the bus around for reads +system.physmem.totQLat 3601508250 # Total ticks spent queuing +system.physmem.totMemAccLat 9060589500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1455755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12369.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30323.24 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 66.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 15.34 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 67.05 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 15.34 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31119.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 66.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 15.25 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 66.70 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 15.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.64 # Data bus utilization in percentage system.physmem.busUtilRead 0.52 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.12 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.40 # Average write queue length when enqueuing -system.physmem.readRowHits 206912 # Number of row buffer hits during reads -system.physmem.writeRowHits 50353 # Number of row buffer hits during writes -system.physmem.readRowHitRate 71.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.51 # Row buffer hit rate for writes -system.physmem.avgGap 776748.79 # Average gap between requests -system.physmem.pageHitRate 71.90 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 378604800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 206580000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1136756400 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 206952 # Number of row buffer hits during reads +system.physmem.writeRowHits 50458 # Number of row buffer hits during writes +system.physmem.readRowHitRate 71.08 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.67 # Row buffer hit rate for writes +system.physmem.avgGap 780916.48 # Average gap between requests +system.physmem.pageHitRate 71.94 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 378650160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 206604750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1136467800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 216438480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79832621385 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96879153000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 196819477185 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.526603 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 160651755000 # Time in different power states -system.physmem_0.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_0.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79892908290 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 97718574000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 197816101560 # Total energy per rank (pJ) +system.physmem_0.averagePower 707.327829 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 162042939000 # Time in different power states +system.physmem_0.memoryStateTime::REF 9338680000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 108238852500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 108285182250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 381470040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 208143375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 380207520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 207454500 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1134088800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 215537760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 18169323120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79968075615 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 96760333500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 196836972210 # Total energy per rank (pJ) -system.physmem_1.averagePower 707.589494 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 160452636750 # Time in different power states -system.physmem_1.memoryStateTime::REF 9289020000 # Time in different power states +system.physmem_1.writeEnergy 215492400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 18266458080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80233432560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 97419868500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 197857002360 # Total energy per rank (pJ) +system.physmem_1.averagePower 707.474077 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 161543146250 # Time in different power states +system.physmem_1.memoryStateTime::REF 9338680000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 108437970750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 108784975000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 192516083 # Number of BP lookups -system.cpu.branchPred.condPredicted 125602202 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 11889251 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 155393318 # Number of BTB lookups -system.cpu.branchPred.BTBHits 126938973 # Number of BTB hits +system.cpu.branchPred.lookups 192995150 # Number of BP lookups +system.cpu.branchPred.condPredicted 125739221 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 11883936 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 145375032 # Number of BTB lookups +system.cpu.branchPred.BTBHits 127081867 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 81.688823 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 28938957 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 146 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 87.416570 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 29018342 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 151 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 244535558 # DTB read hits -system.cpu.dtb.read_misses 309848 # DTB read misses +system.cpu.dtb.read_hits 244533779 # DTB read hits +system.cpu.dtb.read_misses 309591 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 244845406 # DTB read accesses -system.cpu.dtb.write_hits 135688740 # DTB write hits -system.cpu.dtb.write_misses 31438 # DTB write misses +system.cpu.dtb.read_accesses 244843370 # DTB read accesses +system.cpu.dtb.write_hits 135671849 # DTB write hits +system.cpu.dtb.write_misses 31346 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 135720178 # DTB write accesses -system.cpu.dtb.data_hits 380224298 # DTB hits -system.cpu.dtb.data_misses 341286 # DTB misses +system.cpu.dtb.write_accesses 135703195 # DTB write accesses +system.cpu.dtb.data_hits 380205628 # DTB hits +system.cpu.dtb.data_misses 340937 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 380565584 # DTB accesses -system.cpu.itb.fetch_hits 196974389 # ITB hits -system.cpu.itb.fetch_misses 282 # ITB misses +system.cpu.dtb.data_accesses 380546565 # DTB accesses +system.cpu.itb.fetch_hits 197011138 # ITB hits +system.cpu.itb.fetch_misses 297 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 196974671 # ITB accesses +system.cpu.itb.fetch_accesses 197011435 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -318,138 +317,137 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 556360470 # number of cpu cycles simulated +system.cpu.numCycles 559337855 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 202471372 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1648161036 # Number of instructions fetch has processed -system.cpu.fetch.Branches 192516083 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 155877930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 341537101 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 24247434 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 71 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 163 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 6713 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 24 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 196974389 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 6735628 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 556139161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.963577 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.176192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 202154435 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1649182914 # Number of instructions fetch has processed +system.cpu.fetch.Branches 192995150 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 156100209 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 344813807 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 24235896 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 140 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 6519 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 26 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 197011138 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 7083229 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 559092875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.949748 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.175515 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 236974879 42.61% 42.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30241040 5.44% 48.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 22122460 3.98% 52.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 36446378 6.55% 58.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 67887841 12.21% 70.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 21615986 3.89% 74.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 19300231 3.47% 78.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3499506 0.63% 78.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 118050840 21.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 239653225 42.86% 42.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30449692 5.45% 48.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 22058642 3.95% 52.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 36467190 6.52% 58.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 68017058 12.17% 70.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 21431579 3.83% 74.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 19299153 3.45% 78.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3537365 0.63% 78.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 118178971 21.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 556139161 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.346028 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.962398 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 168673381 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 88906441 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 273702922 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 12739464 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 12116953 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 15366288 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 7026 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1584564231 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 25244 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 12116953 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176662049 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 61884123 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 13864 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 278433046 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 27029126 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1538057639 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 6904 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2373775 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17934465 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 6832008 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1026949046 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1768413823 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1728631636 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 39782186 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 559092875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.345042 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.948456 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 168803167 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 91739479 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 273671215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 12767829 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 12111185 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 15522167 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 6976 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1584668893 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 25197 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 12111185 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176688622 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 61751221 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14050 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 278532777 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 29995020 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1538585292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 9438 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2658750 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 20386888 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 7267964 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1027382191 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1769248125 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1729530138 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 39717986 # Number of floating rename lookups system.cpu.rename.CommittedMaps 638967158 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 387981888 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 388415033 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 1375 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 99 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 9559876 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 372392006 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 175420299 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 40717360 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11158065 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1304772774 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 81 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1015651643 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 8789932 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 462366805 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 427709940 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 556139161 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.826254 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.901646 # Number of insts issued each cycle +system.cpu.rename.tempSerializingInsts 100 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 9495582 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 372551032 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 175434243 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40723012 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11258595 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1304972518 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 89 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1016009395 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 8790765 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 462565445 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 427723515 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 52 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 559092875 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.817246 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.904787 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 196811929 35.39% 35.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 93156725 16.75% 52.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 91633615 16.48% 68.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 59891442 10.77% 79.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 56837976 10.22% 89.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 29662833 5.33% 94.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 17038989 3.06% 98.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 7191857 1.29% 99.30% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 3913795 0.70% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 200119998 35.79% 35.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 93029621 16.64% 52.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 91384631 16.35% 68.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 59843024 10.70% 79.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 56522593 10.11% 89.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 29852885 5.34% 94.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 17077557 3.05% 97.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 7239227 1.29% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 4023339 0.72% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 556139161 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 559092875 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2464081 10.47% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15568992 66.16% 76.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 5500305 23.37% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 2463450 10.43% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 10.43% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 15566876 65.90% 76.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 5592414 23.67% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 1276 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 579437623 57.05% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7930 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 13181925 1.30% 58.35% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 3826542 0.38% 58.73% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 3339802 0.33% 59.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 579702610 57.06% 57.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7931 0.00% 57.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 13180646 1.30% 58.36% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 3826544 0.38% 58.73% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 3339801 0.33% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 4 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.06% # Type of FU issued @@ -473,84 +471,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.06% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 276912765 27.26% 86.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 138943776 13.68% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 277022873 27.27% 86.33% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 138927710 13.67% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1015651643 # Type of FU issued -system.cpu.iq.rate 1.825528 # Inst issue rate -system.cpu.iq.fu_busy_cnt 23533378 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023171 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 2548957351 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1725871307 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 940019268 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 70808406 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 41313833 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 34425264 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1002821720 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 36362025 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 50456367 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1016009395 # Type of FU issued +system.cpu.iq.rate 1.816450 # Inst issue rate +system.cpu.iq.fu_busy_cnt 23622740 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023251 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 2552720615 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1726495098 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 940123896 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 70804555 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 41088088 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 34423394 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1003270759 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 36360100 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 50476055 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 134881409 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1145791 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 45978 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 77119099 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 135040435 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1174528 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 45615 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 77133043 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2647 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4470 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2509 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4123 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 12116953 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 60932529 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 189663 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1479247252 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 16168 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 372392006 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 175420299 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 79 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 26629 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 174749 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 45978 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 11882583 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 16645 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 11899228 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 976172370 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 244845576 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 39479273 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 12111185 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 60760024 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 216464 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1479434002 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 17901 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 372551032 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 175434243 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 87 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21559 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 205996 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 45615 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 11877701 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 16644 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 11894345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 976302878 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 244843546 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 39706517 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 174474397 # number of nop insts executed -system.cpu.iew.exec_refs 380566182 # number of memory reference insts executed -system.cpu.iew.exec_branches 129102826 # Number of branches executed -system.cpu.iew.exec_stores 135720606 # Number of stores executed -system.cpu.iew.exec_rate 1.754568 # Inst execution rate -system.cpu.iew.wb_sent 974964146 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 974444532 # cumulative count of insts written-back -system.cpu.iew.wb_producers 556292557 # num instructions producing a value -system.cpu.iew.wb_consumers 832443785 # num instructions consuming a value +system.cpu.iew.exec_nop 174461395 # number of nop insts executed +system.cpu.iew.exec_refs 380547191 # number of memory reference insts executed +system.cpu.iew.exec_branches 129259483 # Number of branches executed +system.cpu.iew.exec_stores 135703645 # Number of stores executed +system.cpu.iew.exec_rate 1.745462 # Inst execution rate +system.cpu.iew.wb_sent 975066188 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 974547290 # cumulative count of insts written-back +system.cpu.iew.wb_producers 556173359 # num instructions producing a value +system.cpu.iew.wb_consumers 831980820 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.751463 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.668264 # average fanout of values written-back +system.cpu.iew.wb_rate 1.742323 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.668493 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 543416365 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 543601549 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 11882488 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 483294798 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.921369 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.600805 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 11877174 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 486379014 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.909185 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.596644 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 205311965 42.48% 42.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 102147195 21.14% 63.62% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 51748026 10.71% 74.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 25735966 5.33% 79.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 21537447 4.46% 84.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 9139527 1.89% 86.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 10425967 2.16% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6656382 1.38% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 50592323 10.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 208258289 42.82% 42.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 102386957 21.05% 63.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 51676822 10.62% 74.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 25636051 5.27% 79.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 21554637 4.43% 84.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 9250657 1.90% 86.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 10396507 2.14% 88.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6664753 1.37% 89.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 50554341 10.39% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 483294798 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 486379014 # Number of insts commited each cycle system.cpu.commit.committedInsts 928587628 # Number of instructions committed system.cpu.commit.committedOps 928587628 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -596,330 +594,346 @@ system.cpu.commit.op_class_0::MemWrite 98301200 10.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 928587628 # Class of committed instruction -system.cpu.commit.bw_lim_events 50592323 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 50554341 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1902085330 # The number of ROB reads -system.cpu.rob.rob_writes 3016853590 # The number of ROB writes -system.cpu.timesIdled 3284 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 221309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1905392712 # The number of ROB reads +system.cpu.rob.rob_writes 3017093514 # The number of ROB writes +system.cpu.timesIdled 3164 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 244980 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 842382029 # Number of Instructions Simulated system.cpu.committedOps 842382029 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.660461 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.660461 # CPI: Total CPI of All Threads -system.cpu.ipc 1.514094 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.514094 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 1237238749 # number of integer regfile reads -system.cpu.int_regfile_writes 705818584 # number of integer regfile writes -system.cpu.fp_regfile_reads 36691517 # number of floating regfile reads -system.cpu.fp_regfile_writes 24411333 # number of floating regfile writes +system.cpu.cpi 0.663995 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.663995 # CPI: Total CPI of All Threads +system.cpu.ipc 1.506034 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.506034 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 1237178642 # number of integer regfile reads +system.cpu.int_regfile_writes 705781417 # number of integer regfile writes +system.cpu.fp_regfile_reads 36689419 # number of floating regfile reads +system.cpu.fp_regfile_writes 24410667 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 777239 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.040110 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 289873961 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 781335 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 370.998305 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 354310000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.040110 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999277 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999277 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 777209 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.895157 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 289903947 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 781305 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 371.050930 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 374093250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.895157 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999242 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999242 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 964 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2501 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 244 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 86 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 295 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 967 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 2495 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 253 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 585528663 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 585528663 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 192492893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 192492893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 97381046 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 97381046 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 289873939 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 289873939 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 289873939 # number of overall hits -system.cpu.dcache.overall_hits::total 289873939 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1579549 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1579549 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 920154 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 920154 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2499703 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2499703 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2499703 # number of overall misses -system.cpu.dcache.overall_misses::total 2499703 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 79817656500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 79817656500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57409075211 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57409075211 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 137226731711 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 137226731711 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 137226731711 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 137226731711 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 194072442 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 194072442 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 585486411 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 585486411 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 192496951 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 192496951 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 97406971 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 97406971 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 25 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 25 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 289903922 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 289903922 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 289903922 # number of overall hits +system.cpu.dcache.overall_hits::total 289903922 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1554376 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1554376 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 894229 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 894229 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 2448605 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2448605 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2448605 # number of overall misses +system.cpu.dcache.overall_misses::total 2448605 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84529453750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84529453750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 62304618080 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 62304618080 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 100250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 100250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 146834071830 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 146834071830 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 146834071830 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 146834071830 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 194051327 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 194051327 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 22 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 292373642 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 292373642 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 292373642 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 292373642 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008139 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.008139 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009361 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009361 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.008550 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.008550 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.008550 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.008550 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50531.928101 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50531.928101 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62390.725043 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62390.725043 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54897.214473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54897.214473 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54897.214473 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 21908 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 55699 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 467 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 516 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.912206 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 107.943798 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 26 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 26 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 292352527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 292352527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 292352527 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 292352527 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.008010 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.008010 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009097 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009097 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.038462 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.038462 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.008376 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.008376 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.008376 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.008376 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54381.599915 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54381.599915 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69674.119359 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69674.119359 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 100250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 100250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 59966.418361 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 59966.418361 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 59966.418361 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 21964 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 69527 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 343 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 515 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 64.034985 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 135.003883 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91488 # number of writebacks -system.cpu.dcache.writebacks::total 91488 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 867045 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 867045 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 851323 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 851323 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1718368 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1718368 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1718368 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1718368 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712504 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712504 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68831 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 68831 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 781335 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 781335 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 781335 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 781335 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21874292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21874292000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5221022246 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5221022246 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27095314246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 27095314246 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27095314246 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 27095314246 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003671 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003671 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 91524 # number of writebacks +system.cpu.dcache.writebacks::total 91524 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 841911 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 841911 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 825390 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 825390 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1667301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1667301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1667301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1667301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712465 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712465 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 68839 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 68839 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 781304 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 781304 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 781304 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 781304 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23794966500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23794966500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5675142998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5675142998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 98250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 98250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 29470109498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 29470109498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 29470109498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 29470109498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003672 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003672 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000700 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000700 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038462 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.038462 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.002672 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002672 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30700.588348 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30700.588348 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75852.773402 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75852.773402 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34678.229244 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 34678.229244 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33398.084818 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33398.084818 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82440.811139 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82440.811139 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 98250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 98250 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37719.133011 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 37719.133011 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 4662 # number of replacements -system.cpu.icache.tags.tagsinuse 1655.102487 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 196966072 # Total number of references to valid blocks. +system.cpu.icache.tags.replacements 4665 # number of replacements +system.cpu.icache.tags.tagsinuse 1651.262169 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 197002801 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6374 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 30901.486037 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 30907.248353 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1655.102487 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.808156 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.808156 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1712 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 70 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1651.262169 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.806280 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.806280 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1709 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1560 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.835938 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 393955150 # Number of tag accesses -system.cpu.icache.tags.data_accesses 393955150 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 196966072 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 196966072 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 196966072 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 196966072 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 196966072 # number of overall hits -system.cpu.icache.overall_hits::total 196966072 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 8316 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 8316 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 8316 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 8316 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 8316 # number of overall misses -system.cpu.icache.overall_misses::total 8316 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 334444749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 334444749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 334444749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 334444749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 334444749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 334444749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 196974388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 196974388 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 196974388 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 196974388 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 196974388 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 196974388 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 1547 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.834473 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 394028650 # Number of tag accesses +system.cpu.icache.tags.data_accesses 394028650 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 197002801 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 197002801 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 197002801 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 197002801 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 197002801 # number of overall hits +system.cpu.icache.overall_hits::total 197002801 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 8337 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 8337 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 8337 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 8337 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 8337 # number of overall misses +system.cpu.icache.overall_misses::total 8337 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 359956749 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 359956749 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 359956749 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 359956749 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 359956749 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 359956749 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 197011138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 197011138 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 197011138 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 197011138 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 197011138 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 197011138 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000042 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000042 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000042 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000042 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000042 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000042 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40217.021284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 40217.021284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 40217.021284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 40217.021284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 40217.021284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 710 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43175.812522 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 43175.812522 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 43175.812522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 43175.812522 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 43175.812522 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 938 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 64.545455 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.533333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1941 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 1941 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 1941 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 1941 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 1941 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 1941 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1962 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 1962 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 1962 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 1962 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 1962 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 1962 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6375 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 6375 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 6375 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 6375 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6375 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6375 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 242697999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 242697999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 242697999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 242697999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 242697999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 242697999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 264410499 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 264410499 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 264410499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 264410499 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 264410499 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 264410499 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 38070.274353 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 38070.274353 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 38070.274353 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 38070.274353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 38070.274353 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 38070.274353 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41476.156706 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41476.156706 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41476.156706 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41476.156706 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41476.156706 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41476.156706 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 258673 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32635.253710 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 518833 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 291412 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.780411 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 258668 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32630.441536 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 518837 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 291405 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.780467 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2796.039745 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.590417 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29770.623548 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.085328 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002093 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.908527 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995949 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32739 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 534 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5316 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26528 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999115 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7393827 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7393827 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 3629 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 490422 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 494051 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 91488 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 91488 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 2207 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 2207 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3629 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 492629 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 496258 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3629 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 492629 # number of overall hits -system.cpu.l2cache.overall_hits::total 496258 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2746 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 222082 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224828 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 66624 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 66624 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2746 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 288706 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 291452 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2746 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 288706 # number of overall misses -system.cpu.l2cache.overall_misses::total 291452 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 200009500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16257189500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16457199000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5129902750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5129902750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 200009500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 21387092250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21587101750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 200009500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 21387092250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21587101750 # number of overall miss cycles +system.cpu.l2cache.tags.occ_blocks::writebacks 2805.006533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 68.921998 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29756.513005 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.085602 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002103 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.908097 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.995802 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32737 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 531 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5300 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26536 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999054 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7393876 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7393876 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 3620 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 490402 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 494022 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 91524 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 91524 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 2211 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 2211 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 3620 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 492613 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 496233 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 3620 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 492613 # number of overall hits +system.cpu.l2cache.overall_hits::total 496233 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2755 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 222064 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224819 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 66628 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 66628 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 2755 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 288692 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 291447 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2755 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 288692 # number of overall misses +system.cpu.l2cache.overall_misses::total 291447 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 220003750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17932762250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18152766000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5574569250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5574569250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 220003750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 23507331500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23727335250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 220003750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 23507331500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23727335250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6375 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 712504 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 718879 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 91488 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 91488 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 68831 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 68831 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712466 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 718841 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 91524 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 91524 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 68839 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 68839 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 6375 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 781335 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 787710 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 781305 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 787680 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 6375 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 781335 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 787710 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.430745 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311692 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.312748 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.967936 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.967936 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.430745 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.369503 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.369999 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.430745 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.369503 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.369999 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72836.671522 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73203.544186 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73199.063284 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76997.819855 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76997.819855 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72836.671522 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74079.140198 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74067.433917 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72836.671522 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74079.140198 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74067.433917 # average overall miss latency +system.cpu.l2cache.overall_accesses::cpu.data 781305 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 787680 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.432157 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311684 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.312752 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.967882 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.967882 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.432157 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.369500 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.370007 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.432157 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.369500 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.370007 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79856.170599 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80754.927633 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80743.913993 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83667.065648 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83667.065648 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79856.170599 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81427.027767 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81412.178715 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79856.170599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81427.027767 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81412.178715 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -930,103 +944,103 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66683 # number of writebacks system.cpu.l2cache.writebacks::total 66683 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2746 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224828 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66624 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 66624 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2746 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 288706 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 291452 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2746 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 288706 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 291452 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 165368000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13488499500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13653867500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4314074750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4314074750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 165368000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 17802574250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17967942250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 165368000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 17802574250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17967942250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311692 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312748 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967936 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.369999 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.430745 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369503 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.369999 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60221.412964 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60736.572527 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60730.280481 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64752.562890 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64752.562890 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60221.412964 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61663.333114 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61649.747643 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2755 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 222064 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224819 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66628 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 66628 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2755 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 288692 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 291447 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2755 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 288692 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 291447 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 185539750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15158114250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15343654000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4753161750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4753161750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 185539750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19911276000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20096815750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 185539750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19911276000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20096815750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311684 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312752 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.967882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.967882 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.370007 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.432157 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.370007 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67346.551724 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68260.115327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68248.920243 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71338.802756 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71338.802756 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67346.551724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68970.653846 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68955.301478 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 718879 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 718878 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 91488 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 68831 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 68831 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 718841 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 718840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 91524 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 68839 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 68839 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12749 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1666907 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1654134 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1666883 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 407936 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55860672 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 56268608 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55861056 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 56268992 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 879198 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 879204 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 879198 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 879204 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 879198 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 531087000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 879204 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 531126000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 10054750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 10103500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1207495250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1213595000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224827 # Transaction distribution -system.membus.trans_dist::ReadResp 224827 # Transaction distribution +system.membus.trans_dist::ReadReq 224818 # Transaction distribution +system.membus.trans_dist::ReadResp 224818 # Transaction distribution system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66624 # Transaction distribution -system.membus.trans_dist::ReadExResp 66624 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649585 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 649585 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22920576 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 66628 # Transaction distribution +system.membus.trans_dist::ReadExResp 66628 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 649575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 649575 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22920256 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22920256 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 358134 # Request fanout histogram +system.membus.snoop_fanout::samples 358129 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 358134 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 358129 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 358134 # Request fanout histogram -system.membus.reqLayer0.occupancy 959207000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2708819750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.0 # Layer utilization (%) +system.membus.snoop_fanout::total 358129 # Request fanout histogram +system.membus.reqLayer0.occupancy 682357500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1548216750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt index 8acd26381..eff48cf7e 100644 --- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.286250 # Number of seconds simulated -sim_ticks 1286249820000 # Number of ticks simulated -final_tick 1286249820000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1286249817500 # Number of ticks simulated +final_tick 1286249817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1681245 # Simulator instruction rate (inst/s) -host_op_rate 1681245 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2328806930 # Simulator tick rate (ticks/s) -host_mem_usage 298588 # Number of bytes of host memory used -host_seconds 552.32 # Real time elapsed on the host +host_inst_rate 1412500 # Simulator instruction rate (inst/s) +host_op_rate 1412500 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1956550284 # Simulator tick rate (ticks/s) +host_mem_usage 303116 # Number of bytes of host memory used +host_seconds 657.41 # Real time elapsed on the host sim_insts 928587629 # Number of instructions simulated sim_ops 928587629 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -36,30 +36,6 @@ system.physmem.bw_total::writebacks 3317950 # To system.physmem.bw_total::cpu.inst 107127 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 14356203 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 17781280 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 224031 # Transaction distribution -system.membus.trans_dist::ReadResp 224031 # Transaction distribution -system.membus.trans_dist::Writeback 66683 # Transaction distribution -system.membus.trans_dist::ReadExReq 66648 # Transaction distribution -system.membus.trans_dist::ReadExResp 66648 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 357362 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 357362 # Request fanout histogram -system.membus.reqLayer0.occupancy 890826000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2616111000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 37 # Number of system calls -system.cpu.numCycles 2572499640 # number of cpu cycles simulated +system.cpu.numCycles 2572499635 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 928587629 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 336013318 # nu system.cpu.num_load_insts 237705247 # Number of load instructions system.cpu.num_store_insts 98308071 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 2572499640 # Number of busy cycles +system.cpu.num_busy_cycles 2572499635 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 123111018 # Number of branches fetched @@ -152,13 +128,122 @@ system.cpu.op_class::MemWrite 98308071 10.58% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 928789150 # Class of executed instruction +system.cpu.dcache.tags.replacements 776432 # number of replacements +system.cpu.dcache.tags.tagsinuse 4094.261321 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1046537000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261321 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits +system.cpu.dcache.overall_hits::total 335031269 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses +system.cpu.dcache.overall_misses::total 780528 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568558000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 18568558000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22264956000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22264956000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22264956000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22264956000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.248965 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.248965 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.505811 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28525.505811 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks +system.cpu.dcache.writebacks::total 91660 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17501287000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17501287000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3592877000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3592877000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21094164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21094164000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21094164000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24597.248965 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24597.248965 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52060.118237 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52060.118237 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27025.505811 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 27025.505811 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 4618 # number of replacements -system.cpu.icache.tags.tagsinuse 1474.486239 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1474.486238 # Cycle average of tags in use system.cpu.icache.tags.total_refs 928782983 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 6168 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 150580.898671 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486239 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1474.486238 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.719964 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1550 # Occupied blocks per task id @@ -181,12 +266,12 @@ system.cpu.icache.demand_misses::cpu.inst 6168 # n system.cpu.icache.demand_misses::total 6168 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 6168 # number of overall misses system.cpu.icache.overall_misses::total 6168 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 170610000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 170610000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 170610000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 170610000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 170610000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 170610500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 170610500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 170610500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 170610500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 170610500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 170610500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 928789151 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 928789151 # number of demand (read+write) accesses @@ -199,12 +284,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000007 system.cpu.icache.demand_miss_rate::total 0.000007 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000007 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000007 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.505837 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 27660.505837 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 27660.505837 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.505837 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 27660.505837 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 27660.586900 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 27660.586900 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 27660.586900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 27660.586900 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 27660.586900 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -219,34 +304,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 6168 system.cpu.icache.demand_mshr_misses::total 6168 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 6168 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 6168 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 158274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 158274000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 158274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 158274000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 158274000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 158274000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 161358500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 161358500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 161358500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 161358500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 161358500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 161358500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000007 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000007 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 25660.505837 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 25660.505837 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 25660.505837 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 25660.505837 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26160.586900 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26160.586900 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26160.586900 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 26160.586900 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 257900 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32657.894031 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32657.894008 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 518578 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 290634 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.784299 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249737 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2768.249705 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 50.156527 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29839.487776 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.084480 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001531 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.910629 # Average percentage of cache occupancy @@ -284,17 +369,17 @@ system.cpu.l2cache.demand_misses::total 290679 # nu system.cpu.l2cache.overall_misses::cpu.inst 2153 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 288526 # number of overall misses system.cpu.l2cache.overall_misses::total 290679 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 111956000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11537659000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11649615000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3465696000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3465696000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 111956000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15003355000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15115311000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 111956000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15003355000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15115311000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 113033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11648595000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11761628000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3499020000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3499020000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 113033000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15147615000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15260648000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 113033000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15147615000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15260648000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 6168 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 711514 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 717682 # number of ReadReq accesses(hits+misses) @@ -319,17 +404,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.369493 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.349060 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.369655 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.369493 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.013521 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.013391 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.010321 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010398 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.010321 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.232234 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.002232 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.001720 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.232234 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.001720 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,17 +436,17 @@ system.cpu.l2cache.demand_mshr_misses::total 290679 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2153 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 288526 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 290679 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 86120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8875123000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8961243000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2665920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2665920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 86120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11541043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11627163000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 86120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11541043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11627163000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 87196500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8986059000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9073255500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2699244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2699244000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87196500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11685303000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11772499500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87196500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11685303000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11772499500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311839 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.312159 # mshr miss rate for ReadReq accesses @@ -373,127 +458,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.369493 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.349060 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369655 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.369493 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.013521 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.013391 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.010398 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.010321 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 776432 # number of replacements -system.cpu.dcache.tags.tagsinuse 4094.261324 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 335031269 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 780528 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 429.236708 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1046536000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4094.261324 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999576 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 468 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 993 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2427 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 672404122 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 672404122 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 236799083 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 236799083 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 98232186 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 98232186 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 335031269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 335031269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 335031269 # number of overall hits -system.cpu.dcache.overall_hits::total 335031269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 711514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 711514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 69014 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 69014 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 780528 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 780528 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 780528 # number of overall misses -system.cpu.dcache.overall_misses::total 780528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 18568561000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 18568561000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3696398000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 22264959000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 22264959000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 22264959000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 22264959000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 237510597 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 98301200 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 335811797 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 335811797 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 335811797 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 335811797 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002996 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000702 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002324 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002324 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002324 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002324 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26097.253181 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 26097.253181 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53560.118237 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53560.118237 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 28525.509655 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 28525.509655 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 28525.509655 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 91660 # number of writebacks -system.cpu.dcache.writebacks::total 91660 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 711514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 711514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69014 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 69014 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 780528 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 780528 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 780528 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17145533000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17145533000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3558370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3558370000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20703903000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20703903000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20703903000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20703903000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002996 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000702 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002324 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002324 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24097.253181 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24097.253181 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51560.118237 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51560.118237 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26525.509655 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26525.509655 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 717682 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91660 # Transaction distribution @@ -523,5 +499,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 9252000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 1170792000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 224031 # Transaction distribution +system.membus.trans_dist::ReadResp 224031 # Transaction distribution +system.membus.trans_dist::Writeback 66683 # Transaction distribution +system.membus.trans_dist::ReadExReq 66648 # Transaction distribution +system.membus.trans_dist::ReadExResp 66648 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 648041 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22871168 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 357362 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 357362 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 357362 # Request fanout histogram +system.membus.reqLayer0.occupancy 636219000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 1453395500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt index 7a6d5db32..3406c4e55 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.541786 # Number of seconds simulated -sim_ticks 541786101000 # Number of ticks simulated -final_tick 541786101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.545057 # Number of seconds simulated +sim_ticks 545056655500 # Number of ticks simulated +final_tick 545056655500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 115987 # Simulator instruction rate (inst/s) -host_op_rate 142796 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98087491 # Simulator tick rate (ticks/s) -host_mem_usage 309428 # Number of bytes of host memory used -host_seconds 5523.50 # Real time elapsed on the host +host_inst_rate 182072 # Simulator instruction rate (inst/s) +host_op_rate 224154 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 154902851 # Simulator tick rate (ticks/s) +host_mem_usage 321108 # Number of bytes of host memory used +host_seconds 3518.70 # Real time elapsed on the host sim_insts 640655084 # Number of instructions simulated sim_ops 788730743 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 164672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 18429184 # Number of bytes read from this memory -system.physmem.bytes_read::total 18593856 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 164672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 164672 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 164864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 18429248 # Number of bytes read from this memory +system.physmem.bytes_read::total 18594112 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 164864 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 164864 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 2573 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 287956 # Number of read requests responded to by this memory -system.physmem.num_reads::total 290529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 2576 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 287957 # Number of read requests responded to by this memory +system.physmem.num_reads::total 290533 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 303943 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 34015609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 34319552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 303943 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 303943 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 7808011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 7808011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 7808011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 303943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 34015609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 42127563 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 290529 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 302471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 33811619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 34114090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302471 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 7761160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7761160 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 7761160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302471 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 33811619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 41875251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 290533 # Number of read requests accepted system.physmem.writeReqs 66098 # Number of write requests accepted -system.physmem.readBursts 290529 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 290533 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 18572736 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 21120 # Total number of bytes read from write queue -system.physmem.bytesWritten 4228480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 18593856 # Total read bytes from the system interface side +system.physmem.bytesReadDRAM 18574784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 19328 # Total number of bytes read from write queue +system.physmem.bytesWritten 4228736 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 18594112 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 330 # Number of DRAM read bursts serviced by the write queue +system.physmem.servicedByWrQ 302 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 18289 # Per bank write bursts -system.physmem.perBankRdBursts::1 18137 # Per bank write bursts -system.physmem.perBankRdBursts::2 18222 # Per bank write bursts +system.physmem.perBankRdBursts::0 18287 # Per bank write bursts +system.physmem.perBankRdBursts::1 18141 # Per bank write bursts +system.physmem.perBankRdBursts::2 18224 # Per bank write bursts system.physmem.perBankRdBursts::3 18184 # Per bank write bursts -system.physmem.perBankRdBursts::4 18266 # Per bank write bursts -system.physmem.perBankRdBursts::5 18308 # Per bank write bursts -system.physmem.perBankRdBursts::6 18094 # Per bank write bursts -system.physmem.perBankRdBursts::7 17914 # Per bank write bursts -system.physmem.perBankRdBursts::8 17939 # Per bank write bursts -system.physmem.perBankRdBursts::9 17962 # Per bank write bursts -system.physmem.perBankRdBursts::10 18018 # Per bank write bursts -system.physmem.perBankRdBursts::11 18110 # Per bank write bursts +system.physmem.perBankRdBursts::4 18267 # Per bank write bursts +system.physmem.perBankRdBursts::5 18318 # Per bank write bursts +system.physmem.perBankRdBursts::6 18100 # Per bank write bursts +system.physmem.perBankRdBursts::7 17916 # Per bank write bursts +system.physmem.perBankRdBursts::8 17940 # Per bank write bursts +system.physmem.perBankRdBursts::9 17966 # Per bank write bursts +system.physmem.perBankRdBursts::10 18025 # Per bank write bursts +system.physmem.perBankRdBursts::11 18111 # Per bank write bursts system.physmem.perBankRdBursts::12 18143 # Per bank write bursts -system.physmem.perBankRdBursts::13 18270 # Per bank write bursts -system.physmem.perBankRdBursts::14 18077 # Per bank write bursts -system.physmem.perBankRdBursts::15 18266 # Per bank write bursts -system.physmem.perBankWrBursts::0 4174 # Per bank write bursts -system.physmem.perBankWrBursts::1 4101 # Per bank write bursts -system.physmem.perBankWrBursts::2 4137 # Per bank write bursts -system.physmem.perBankWrBursts::3 4147 # Per bank write bursts +system.physmem.perBankRdBursts::13 18269 # Per bank write bursts +system.physmem.perBankRdBursts::14 18078 # Per bank write bursts +system.physmem.perBankRdBursts::15 18262 # Per bank write bursts +system.physmem.perBankWrBursts::0 4173 # Per bank write bursts +system.physmem.perBankWrBursts::1 4099 # Per bank write bursts +system.physmem.perBankWrBursts::2 4136 # Per bank write bursts +system.physmem.perBankWrBursts::3 4146 # Per bank write bursts system.physmem.perBankWrBursts::4 4225 # Per bank write bursts -system.physmem.perBankWrBursts::5 4225 # Per bank write bursts +system.physmem.perBankWrBursts::5 4223 # Per bank write bursts system.physmem.perBankWrBursts::6 4171 # Per bank write bursts -system.physmem.perBankWrBursts::7 4096 # Per bank write bursts -system.physmem.perBankWrBursts::8 4093 # Per bank write bursts +system.physmem.perBankWrBursts::7 4094 # Per bank write bursts +system.physmem.perBankWrBursts::8 4094 # Per bank write bursts system.physmem.perBankWrBursts::9 4093 # Per bank write bursts -system.physmem.perBankWrBursts::10 4090 # Per bank write bursts -system.physmem.perBankWrBursts::11 4094 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts -system.physmem.perBankWrBursts::13 4094 # Per bank write bursts +system.physmem.perBankWrBursts::10 4093 # Per bank write bursts +system.physmem.perBankWrBursts::11 4097 # Per bank write bursts +system.physmem.perBankWrBursts::12 4098 # Per bank write bursts +system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4138 # Per bank write bursts +system.physmem.perBankWrBursts::15 4140 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 541786012500 # Total gap between requests +system.physmem.totGap 545056561000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 290529 # Read request sizes (log2) +system.physmem.readPktSize::6 290533 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -97,8 +97,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 66098 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 289803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 289840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 375 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4011 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4009 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,97 +193,95 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 111554 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 204.382452 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.554579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 255.928936 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 47007 42.14% 42.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 43571 39.06% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8721 7.82% 89.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 769 0.69% 89.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1361 1.22% 90.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1221 1.09% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 537 0.48% 92.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 497 0.45% 92.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7870 7.05% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 111554 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4006 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 48.553919 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 36.073633 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 507.732262 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4003 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 112305 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 203.035662 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.214062 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 254.437736 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47268 42.09% 42.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 43750 38.96% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8988 8.00% 89.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1909 1.70% 90.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 489 0.44% 91.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 737 0.66% 91.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 726 0.65% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 505 0.45% 92.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7933 7.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 112305 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4009 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 48.526066 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 36.050433 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 507.549530 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4006 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.95% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4006 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4006 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.492761 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.471115 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.861913 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3018 75.34% 75.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 3 0.07% 75.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 984 24.56% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4006 # Writes before turning the bus around for reads -system.physmem.totQLat 2707676000 # Total ticks spent queuing -system.physmem.totMemAccLat 8148907250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1450995000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9330.41 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4009 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4009 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.481417 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.460113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.855134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3044 75.93% 75.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 965 24.07% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4009 # Writes before turning the bus around for reads +system.physmem.totQLat 2737356250 # Total ticks spent queuing +system.physmem.totMemAccLat 8179187500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1451155000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9431.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28080.41 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 34.28 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 7.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 34.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 7.81 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 28181.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 34.08 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 7.76 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 34.11 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 7.76 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.33 # Data bus utilization in percentage system.physmem.busUtilRead 0.27 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.42 # Average write queue length when enqueuing -system.physmem.readRowHits 194608 # Number of row buffer hits during reads -system.physmem.writeRowHits 50098 # Number of row buffer hits during writes -system.physmem.readRowHitRate 67.06 # Row buffer hit rate for reads +system.physmem.avgWrQLen 23.96 # Average write queue length when enqueuing +system.physmem.readRowHits 193898 # Number of row buffer hits during reads +system.physmem.writeRowHits 50093 # Number of row buffer hits during writes +system.physmem.readRowHitRate 66.81 # Row buffer hit rate for reads system.physmem.writeRowHitRate 75.79 # Row buffer hit rate for writes -system.physmem.avgGap 1519195.16 # Average gap between requests -system.physmem.pageHitRate 68.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 421810200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 230154375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1134190200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 215628480 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 106352983170 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 231777774000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 375519162345 # Total energy per rank (pJ) -system.physmem_0.averagePower 693.117148 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 384873582500 # Time in different power states -system.physmem_0.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem.avgGap 1528348.80 # Average gap between requests +system.physmem.pageHitRate 68.47 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 424002600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 231350625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1134369600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 215570160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 106884947925 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 233273273250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 377763731280 # Total energy per rank (pJ) +system.physmem_0.averagePower 693.076638 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 387358600750 # Time in different power states +system.physmem_0.memoryStateTime::REF 18200520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 138818819500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 139494961250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 421477560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 229972875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1129034400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212505120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 35386621920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 105425199585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 232591619250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 375396430710 # Total energy per rank (pJ) -system.physmem_1.averagePower 692.890615 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 386233048000 # Time in different power states -system.physmem_1.memoryStateTime::REF 18091320000 # Time in different power states +system.physmem_1.actEnergy 424962720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 231874500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1129096800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212589360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 35600217120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 105917359815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 234122034750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 377638135065 # Total energy per rank (pJ) +system.physmem_1.averagePower 692.846209 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 388771820250 # Time in different power states +system.physmem_1.memoryStateTime::REF 18200520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 137458753250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 138081006000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 156937341 # Number of BP lookups -system.cpu.branchPred.condPredicted 106680042 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 12891228 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 97536058 # Number of BTB lookups -system.cpu.branchPred.BTBHits 81874318 # Number of BTB hits +system.cpu.branchPred.lookups 155213668 # Number of BP lookups +system.cpu.branchPred.condPredicted 105449696 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 12879317 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 90304208 # Number of BTB lookups +system.cpu.branchPred.BTBHits 82854286 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 83.942615 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 19487919 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1320 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 91.750194 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 19341274 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1316 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -402,75 +400,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 1083572202 # number of cpu cycles simulated +system.cpu.numCycles 1090113311 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 640655084 # Number of instructions committed system.cpu.committedOps 788730743 # Number of ops (including micro ops) committed -system.cpu.discardedOps 22655429 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 22623250 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.691350 # CPI: cycles per instruction -system.cpu.ipc 0.591244 # IPC: instructions per cycle -system.cpu.tickCycles 1029141566 # Number of cycles that the object actually ticked -system.cpu.idleCycles 54430636 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 778221 # number of replacements -system.cpu.dcache.tags.tagsinuse 4092.645412 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 378457747 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 782317 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 483.765209 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 751751250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4092.645412 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999181 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999181 # Average percentage of cache occupancy +system.cpu.cpi 1.701560 # CPI: cycles per instruction +system.cpu.ipc 0.587696 # IPC: instructions per cycle +system.cpu.tickCycles 1030411592 # Number of cycles that the object actually ticked +system.cpu.idleCycles 59701719 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 778141 # number of replacements +system.cpu.dcache.tags.tagsinuse 4092.460106 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 378456482 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 782237 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 483.813067 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 802330000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4092.460106 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999136 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999136 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 962 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1341 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1589 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 963 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1339 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1594 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 759400731 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 759400731 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 249632505 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 249632505 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 128813764 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 128813764 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 759397955 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 759397955 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 249631239 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 249631239 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 378446269 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 378446269 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 378446269 # number of overall hits -system.cpu.dcache.overall_hits::total 378446269 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 713747 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 713747 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 137713 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 137713 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 851460 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 851460 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 851460 # number of overall misses -system.cpu.dcache.overall_misses::total 851460 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23055853217 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23055853217 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9199211000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9199211000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32255064217 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32255064217 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32255064217 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32255064217 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 250346252 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 250346252 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 378445004 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 378445004 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 378445004 # number of overall hits +system.cpu.dcache.overall_hits::total 378445004 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 713665 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 713665 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 851377 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 851377 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 851377 # number of overall misses +system.cpu.dcache.overall_misses::total 851377 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 24698082718 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 24698082718 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10190251750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10190251750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 34888334468 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 34888334468 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 34888334468 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 34888334468 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 250344904 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 250344904 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 379297729 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 379297729 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 379297729 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 379297729 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 379296381 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 379296381 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 379296381 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 379296381 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002851 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses @@ -479,14 +477,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002245 system.cpu.dcache.demand_miss_rate::total 0.002245 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002245 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002245 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32302.557092 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32302.557092 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 66799.873650 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 66799.873650 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37882.066353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37882.066353 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37882.066353 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34607.389627 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34607.389627 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73996.832157 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 73996.832157 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40978.713858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40978.713858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40978.713858 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,99 +495,99 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 91420 # number of writebacks system.cpu.dcache.writebacks::total 91420 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 752 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 752 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68391 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 68391 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 69143 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 69143 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 69143 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 69143 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712995 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 712995 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 750 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 750 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 69140 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 69140 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 69140 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 69140 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712915 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 712915 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 782317 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 782317 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 782317 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 782317 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21545578028 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21545578028 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4531082000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4531082000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26076660028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26076660028 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26076660028 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26076660028 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 782237 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 782237 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 782237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 782237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23543649027 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23543649027 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5045531250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5045531250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28589180277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28589180277 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28589180277 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28589180277 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002848 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002063 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002063 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30218.413913 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30218.413913 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65362.828539 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65362.828539 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33332.600503 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 33332.600503 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33024.482620 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33024.482620 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72783.982718 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72783.982718 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36547.977502 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36547.977502 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 23590 # number of replacements -system.cpu.icache.tags.tagsinuse 1712.180561 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 289921723 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 25341 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11440.816187 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 23596 # number of replacements +system.cpu.icache.tags.tagsinuse 1712.064969 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 291953853 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 25347 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11518.280388 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1712.180561 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.836026 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.836026 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1712.064969 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.835969 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.835969 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1602 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1600 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 579919471 # Number of tag accesses -system.cpu.icache.tags.data_accesses 579919471 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 289921723 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 289921723 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 289921723 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 289921723 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 289921723 # number of overall hits -system.cpu.icache.overall_hits::total 289921723 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 25342 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 25342 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 25342 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 25342 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 25342 # number of overall misses -system.cpu.icache.overall_misses::total 25342 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 480693746 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 480693746 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 480693746 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 480693746 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 480693746 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 480693746 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 289947065 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 289947065 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 289947065 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 289947065 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 289947065 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 289947065 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 583983749 # Number of tag accesses +system.cpu.icache.tags.data_accesses 583983749 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 291953853 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 291953853 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 291953853 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 291953853 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 291953853 # number of overall hits +system.cpu.icache.overall_hits::total 291953853 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 25348 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 25348 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 25348 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 25348 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 25348 # number of overall misses +system.cpu.icache.overall_misses::total 25348 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 499968245 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 499968245 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 499968245 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 499968245 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 499968245 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 499968245 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 291979201 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 291979201 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 291979201 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 291979201 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 291979201 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 291979201 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000087 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000087 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000087 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000087 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000087 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000087 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18968.263989 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18968.263989 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18968.263989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18968.263989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18968.263989 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19724.169362 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19724.169362 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19724.169362 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19724.169362 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19724.169362 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -598,123 +596,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25342 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 25342 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 25342 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 25342 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 25342 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 25342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 428909254 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 428909254 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 428909254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 428909254 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 428909254 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 428909254 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 25348 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 25348 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 25348 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 25348 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 25348 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 460840255 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 460840255 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 460840255 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 460840255 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 460840255 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 460840255 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000087 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000087 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000087 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000087 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16924.838371 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16924.838371 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16924.838371 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16924.838371 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18180.537123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18180.537123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18180.537123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18180.537123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 257749 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32583.111771 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 539070 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 290493 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.855707 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 257753 # number of replacements +system.cpu.l2cache.tags.tagsinuse 32573.758002 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 538992 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 290497 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.855413 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2860.665235 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.519731 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29632.926805 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.087301 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002732 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.904325 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.994358 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 2882.231587 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.601373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29601.925042 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.087959 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002734 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.903379 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.994072 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32744 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2800 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29426 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 287 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2793 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29433 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999268 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7552447 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7552447 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 22764 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 491102 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 513866 # number of ReadReq hits +system.cpu.l2cache.tags.tag_accesses 7551859 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7551859 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 22766 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 491022 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 513788 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 91420 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 91420 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 22764 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 494333 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 517097 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 22764 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 494333 # number of overall hits -system.cpu.l2cache.overall_hits::total 517097 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2578 # number of ReadReq misses +system.cpu.l2cache.demand_hits::cpu.inst 22766 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 494253 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 517019 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 22766 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 494253 # number of overall hits +system.cpu.l2cache.overall_hits::total 517019 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2582 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 221893 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 224471 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 224475 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2578 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2582 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 287984 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 290562 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2578 # number of overall misses +system.cpu.l2cache.demand_misses::total 290566 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2582 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 287984 # number of overall misses -system.cpu.l2cache.overall_misses::total 290562 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175909750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 15921496500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16097406250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4429448000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4429448000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 175909750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20350944500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20526854250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 175909750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20350944500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20526854250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 25342 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 712995 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 738337 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 290566 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 196449750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17674937000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17871386750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4942281750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4942281750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 196449750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22617218750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22813668500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 196449750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22617218750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22813668500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 25348 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 712915 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 738263 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 91420 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 25342 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 782317 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 807659 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 25342 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 782317 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 807659 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101728 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311213 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.304022 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 25348 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 782237 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 807585 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 25348 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 782237 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 807585 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.101862 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.311247 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.304058 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101728 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.368117 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.359758 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101728 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.368117 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.359758 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68234.968968 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71753.036373 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71712.632144 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67020.441512 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67020.441512 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70645.350218 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68234.968968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70666.927677 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70645.350218 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.101862 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.368154 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.359796 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.101862 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.368154 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.359796 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76084.333850 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79655.225717 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79614.151910 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74779.951128 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74779.951128 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78514.583606 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76084.333850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78536.372680 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78514.583606 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -725,116 +723,114 @@ system.cpu.l2cache.fast_writes 0 # nu system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks system.cpu.l2cache.writebacks::total 66098 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 28 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 27 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 28 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 27 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 28 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 27 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 32 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2574 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221865 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 224439 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2577 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 221866 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 224443 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2574 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 287956 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 290530 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2574 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 287956 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 290530 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143321250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13141995500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13285316750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3577310000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3577310000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143321250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 16719305500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16862626750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143321250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 16719305500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16862626750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311173 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.303979 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2577 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 287957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 290534 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2577 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 287957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 290534 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 163845000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14897681250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15061526250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4113937750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4113937750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 163845000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19011619000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19175464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 163845000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19011619000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19175464000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311210 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.304015 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.359719 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368081 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.359719 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55680.361305 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59234.198724 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59193.441202 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54127.036964 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54127.036964 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55680.361305 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 58062.014683 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58040.914019 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.359757 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.101665 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368120 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.359757 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63579.743888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67147.202591 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67106.241897 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62246.565342 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62246.565342 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63579.743888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66022.423487 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66000.757226 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 738337 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 738336 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 738263 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 738262 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 91420 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50683 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1656054 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1706737 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1621824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55919168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 57540992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50695 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1655894 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1706589 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1622208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55914048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 57536256 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 899079 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 899005 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 899079 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 899005 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 899079 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 540959500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 899005 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 540922500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 38562746 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 38574245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1224351972 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1224003723 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 224438 # Transaction distribution -system.membus.trans_dist::ReadResp 224438 # Transaction distribution +system.membus.trans_dist::ReadReq 224442 # Transaction distribution +system.membus.trans_dist::ReadResp 224442 # Transaction distribution system.membus.trans_dist::Writeback 66098 # Transaction distribution system.membus.trans_dist::ReadExReq 66091 # Transaction distribution system.membus.trans_dist::ReadExResp 66091 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647156 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 647156 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824128 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22824128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 647164 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 647164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22824384 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22824384 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 356627 # Request fanout histogram +system.membus.snoop_fanout::samples 356631 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 356627 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 356631 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 356627 # Request fanout histogram -system.membus.reqLayer0.occupancy 983550500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2739032750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.snoop_fanout::total 356631 # Request fanout histogram +system.membus.reqLayer0.occupancy 731515500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 1551221000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt index 5cb40d175..c41e8c5e9 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.408037 # Number of seconds simulated -sim_ticks 408037199500 # Number of ticks simulated -final_tick 408037199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.409399 # Number of seconds simulated +sim_ticks 409399480000 # Number of ticks simulated +final_tick 409399480000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90640 # Simulator instruction rate (inst/s) -host_op_rate 111590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57729920 # Simulator tick rate (ticks/s) -host_mem_usage 318440 # Number of bytes of host memory used -host_seconds 7068.04 # Real time elapsed on the host +host_inst_rate 93383 # Simulator instruction rate (inst/s) +host_op_rate 114967 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59675446 # Simulator tick rate (ticks/s) +host_mem_usage 317532 # Number of bytes of host memory used +host_seconds 6860.43 # Real time elapsed on the host sim_insts 640649298 # Number of instructions simulated sim_ops 788724957 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7008448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 12940608 # Number of bytes read from this memory -system.physmem.bytes_read::total 20176256 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4244736 # Number of bytes written to this memory -system.physmem.bytes_written::total 4244736 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 109507 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 202197 # Number of read requests responded to by this memory -system.physmem.num_reads::total 315254 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66324 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66324 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 556812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 17176003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 31714285 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 49447099 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 556812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 556812 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 10402816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10402816 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 10402816 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 556812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 17176003 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 31714285 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59849916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 315254 # Number of read requests accepted -system.physmem.writeReqs 66324 # Number of write requests accepted -system.physmem.readBursts 315254 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 66324 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 20157248 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 19008 # Total number of bytes read from write queue -system.physmem.bytesWritten 4240064 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 20176256 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4244736 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 297 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 51 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 19893 # Per bank write bursts -system.physmem.perBankRdBursts::1 19507 # Per bank write bursts -system.physmem.perBankRdBursts::2 19696 # Per bank write bursts -system.physmem.perBankRdBursts::3 19811 # Per bank write bursts -system.physmem.perBankRdBursts::4 19755 # Per bank write bursts -system.physmem.perBankRdBursts::5 20266 # Per bank write bursts -system.physmem.perBankRdBursts::6 19606 # Per bank write bursts -system.physmem.perBankRdBursts::7 19431 # Per bank write bursts -system.physmem.perBankRdBursts::8 19468 # Per bank write bursts -system.physmem.perBankRdBursts::9 19384 # Per bank write bursts -system.physmem.perBankRdBursts::10 19414 # Per bank write bursts -system.physmem.perBankRdBursts::11 19672 # Per bank write bursts -system.physmem.perBankRdBursts::12 19624 # Per bank write bursts -system.physmem.perBankRdBursts::13 19992 # Per bank write bursts -system.physmem.perBankRdBursts::14 19481 # Per bank write bursts -system.physmem.perBankRdBursts::15 19957 # Per bank write bursts -system.physmem.perBankWrBursts::0 4278 # Per bank write bursts -system.physmem.perBankWrBursts::1 4105 # Per bank write bursts +system.physmem.bytes_read::cpu.inst 232192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7025088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 12938560 # Number of bytes read from this memory +system.physmem.bytes_read::total 20195840 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 232192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 232192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4244864 # Number of bytes written to this memory +system.physmem.bytes_written::total 4244864 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3628 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 109767 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 202165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 315560 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66326 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66326 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 567153 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 17159494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 31603753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 49330400 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 567153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 567153 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 10368513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10368513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 10368513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 567153 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 17159494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 31603753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 59698913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 315560 # Number of read requests accepted +system.physmem.writeReqs 66326 # Number of write requests accepted +system.physmem.readBursts 315560 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 66326 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 20177344 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 18496 # Total number of bytes read from write queue +system.physmem.bytesWritten 4238912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 20195840 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4244864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 289 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 63 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 16 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 19910 # Per bank write bursts +system.physmem.perBankRdBursts::1 19474 # Per bank write bursts +system.physmem.perBankRdBursts::2 19822 # Per bank write bursts +system.physmem.perBankRdBursts::3 19845 # Per bank write bursts +system.physmem.perBankRdBursts::4 19720 # Per bank write bursts +system.physmem.perBankRdBursts::5 20103 # Per bank write bursts +system.physmem.perBankRdBursts::6 19622 # Per bank write bursts +system.physmem.perBankRdBursts::7 19424 # Per bank write bursts +system.physmem.perBankRdBursts::8 19577 # Per bank write bursts +system.physmem.perBankRdBursts::9 19501 # Per bank write bursts +system.physmem.perBankRdBursts::10 19475 # Per bank write bursts +system.physmem.perBankRdBursts::11 19731 # Per bank write bursts +system.physmem.perBankRdBursts::12 19558 # Per bank write bursts +system.physmem.perBankRdBursts::13 20043 # Per bank write bursts +system.physmem.perBankRdBursts::14 19546 # Per bank write bursts +system.physmem.perBankRdBursts::15 19920 # Per bank write bursts +system.physmem.perBankWrBursts::0 4269 # Per bank write bursts +system.physmem.perBankWrBursts::1 4104 # Per bank write bursts system.physmem.perBankWrBursts::2 4141 # Per bank write bursts -system.physmem.perBankWrBursts::3 4152 # Per bank write bursts -system.physmem.perBankWrBursts::4 4250 # Per bank write bursts -system.physmem.perBankWrBursts::5 4232 # Per bank write bursts +system.physmem.perBankWrBursts::3 4150 # Per bank write bursts +system.physmem.perBankWrBursts::4 4244 # Per bank write bursts +system.physmem.perBankWrBursts::5 4227 # Per bank write bursts system.physmem.perBankWrBursts::6 4174 # Per bank write bursts system.physmem.perBankWrBursts::7 4096 # Per bank write bursts system.physmem.perBankWrBursts::8 4096 # Per bank write bursts system.physmem.perBankWrBursts::9 4096 # Per bank write bursts -system.physmem.perBankWrBursts::10 4095 # Per bank write bursts +system.physmem.perBankWrBursts::10 4096 # Per bank write bursts system.physmem.perBankWrBursts::11 4097 # Per bank write bursts -system.physmem.perBankWrBursts::12 4096 # Per bank write bursts +system.physmem.perBankWrBursts::12 4097 # Per bank write bursts system.physmem.perBankWrBursts::13 4096 # Per bank write bursts system.physmem.perBankWrBursts::14 4096 # Per bank write bursts -system.physmem.perBankWrBursts::15 4151 # Per bank write bursts +system.physmem.perBankWrBursts::15 4154 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 408037145000 # Total gap between requests +system.physmem.totGap 409399425500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 315254 # Read request sizes (log2) +system.physmem.readPktSize::6 315560 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66324 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 128804 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 111420 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 14471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6711 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6396 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7547 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8690 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 7182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 6341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 3273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 2426 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 1825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 1270 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66326 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 122658 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 117599 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 14107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 6797 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8395 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 8262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 10480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 3294 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 2442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1850 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1337 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see @@ -148,48 +148,48 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 590 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1667 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 3865 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4750 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5565 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 4251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 4042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 589 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 613 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2652 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4387 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4886 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4821 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 4400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 4184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 4072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 53 # What write queue length does an incoming req see system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 4 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see @@ -197,113 +197,109 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 136345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 178.922586 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 128.860330 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 198.953379 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 53850 39.50% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 57322 42.04% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14832 10.88% 92.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1348 0.99% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1343 0.99% 94.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1322 0.97% 95.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1347 0.99% 96.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1288 0.94% 97.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3693 2.71% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 136345 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 4024 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 74.490060 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 34.867874 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 683.746449 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 4004 99.50% 99.50% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 7 0.17% 99.68% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 3 0.07% 99.75% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 2 0.05% 99.80% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 1 0.02% 99.83% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7168-8191 2 0.05% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::8192-9215 2 0.05% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::16384-17407 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 4024 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 4024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.463966 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.422591 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.272940 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 3359 83.47% 83.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 14 0.35% 83.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 449 11.16% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 91 2.26% 97.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 36 0.89% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 19 0.47% 98.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 14 0.35% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 17 0.42% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.20% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 6 0.15% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 4 0.10% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.12% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 4024 # Writes before turning the bus around for reads -system.physmem.totQLat 9384520258 # Total ticks spent queuing -system.physmem.totMemAccLat 15289964008 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1574785000 # Total ticks spent in databus transfers -system.physmem.avgQLat 29796.20 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 136638 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 178.677557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 128.806703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 198.419690 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 53973 39.50% 39.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 57563 42.13% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14775 10.81% 92.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1288 0.94% 93.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1420 1.04% 94.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1465 1.07% 95.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1207 0.88% 96.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1190 0.87% 97.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3757 2.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 136638 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4034 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 68.784581 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 34.732770 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 517.054396 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 4014 99.50% 99.50% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 8 0.20% 99.70% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 5 0.12% 99.83% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.02% 99.85% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::7168-8191 3 0.07% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::13312-14335 1 0.02% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::14336-15359 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::19456-20479 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4034 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4034 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.418691 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.384198 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.147646 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 3405 84.41% 84.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.17% 84.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 450 11.16% 95.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 75 1.86% 97.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 34 0.84% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 21 0.52% 98.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 13 0.32% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 12 0.30% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 6 0.15% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.15% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 3 0.07% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.05% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4034 # Writes before turning the bus around for reads +system.physmem.totQLat 9487812639 # Total ticks spent queuing +system.physmem.totMemAccLat 15399143889 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1576355000 # Total ticks spent in databus transfers +system.physmem.avgQLat 30094.15 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 48546.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 49.40 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 10.39 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 49.45 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 10.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48844.15 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 49.29 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 49.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 10.37 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.47 # Data bus utilization in percentage system.physmem.busUtilRead 0.39 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.48 # Average write queue length when enqueuing -system.physmem.readRowHits 218395 # Number of row buffer hits during reads -system.physmem.writeRowHits 26455 # Number of row buffer hits during writes -system.physmem.readRowHitRate 69.34 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing +system.physmem.readRowHits 218399 # Number of row buffer hits during reads +system.physmem.writeRowHits 26454 # Number of row buffer hits during writes +system.physmem.readRowHitRate 69.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate 39.92 # Row buffer hit rate for writes -system.physmem.avgGap 1069341.38 # Average gap between requests -system.physmem.pageHitRate 64.23 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 517708800 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 282480000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1231869600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 216613440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 96151044510 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 160475521500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 285525816090 # Total energy per rank (pJ) -system.physmem_0.averagePower 699.765171 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 266332221673 # Time in different power states -system.physmem_0.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem.avgGap 1072046.17 # Average gap between requests +system.physmem.pageHitRate 64.18 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 517640760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 282442875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1231518600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 216464400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 96784987680 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 160736987250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 286509617805 # Total energy per rank (pJ) +system.physmem_0.averagePower 699.839198 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 266762765318 # Time in different power states +system.physmem_0.memoryStateTime::REF 13670540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 128074629327 # Time in different power states +system.physmem_0.memoryStateTime::ACT 128960598682 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 512870400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 279840000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1224147600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 212693040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 26650578240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 96078218175 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 160539404250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 285497751705 # Total energy per rank (pJ) -system.physmem_1.averagePower 699.696391 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 266439995679 # Time in different power states -system.physmem_1.memoryStateTime::REF 13625040000 # Time in different power states +system.physmem_1.actEnergy 515168640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 281094000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1226955600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 212725440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 26739576240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 96280028955 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 161179933500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 286435482375 # Total energy per rank (pJ) +system.physmem_1.averagePower 699.658112 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 267502793659 # Time in different power states +system.physmem_1.memoryStateTime::REF 13670540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 127966985321 # Time in different power states +system.physmem_1.memoryStateTime::ACT 128220707341 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 233958621 # Number of BP lookups -system.cpu.branchPred.condPredicted 161821709 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15514987 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 121572023 # Number of BTB lookups -system.cpu.branchPred.BTBHits 108258061 # Number of BTB hits +system.cpu.branchPred.lookups 234006176 # Number of BP lookups +system.cpu.branchPred.condPredicted 161868409 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15514584 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 121529948 # Number of BTB lookups +system.cpu.branchPred.BTBHits 108213709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 89.048498 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 25035636 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1300514 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 89.042833 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 25036783 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1300149 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -422,84 +418,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 816074400 # number of cpu cycles simulated +system.cpu.numCycles 818798961 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 84077011 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 1200073954 # Number of instructions fetch has processed -system.cpu.fetch.Branches 233958621 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 133293697 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 716167787 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 31064641 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 2347 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 84078294 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 1200783068 # Number of instructions fetch has processed +system.cpu.fetch.Branches 234006176 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 133250492 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 718844861 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 31063585 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2466 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 2996 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 370071850 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 652472 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 815782492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.838759 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.161594 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 3349 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 370656305 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 652882 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 818460793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.833394 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.163540 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 134746116 16.52% 16.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 222503118 27.27% 43.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 98075778 12.02% 55.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 360457480 44.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 136795118 16.71% 16.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 223180654 27.27% 43.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 98074923 11.98% 55.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 360410098 44.04% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 815782492 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.286688 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.470545 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 119982553 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 156985722 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 484662665 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 38632910 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 15518642 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 25180928 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 13826 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 1248143840 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 39966741 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 15518642 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 176992343 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 77462427 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 207446 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 464957580 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 80644054 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1190653894 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 25546220 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 24993767 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2267123 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 40253162 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1738390 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1225396904 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 5812470532 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 1358186197 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 40876541 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 818460793 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.285792 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.466518 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 119991092 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 159658898 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 484662986 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 38629701 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 15518116 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 25135087 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 13824 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 1248129900 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 39966537 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 15518116 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 176998470 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 78894904 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 210510 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 464956548 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 81882245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1190637892 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 25457774 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 24955109 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2267146 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 41533192 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1699566 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1225425199 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 5812490436 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 1358169789 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 40876588 # Number of floating rename lookups system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 350618674 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 350646969 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 7267 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 108147318 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 366118935 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 236099157 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1781337 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5349105 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1168566408 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 108140115 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 366205100 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 236096667 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1646330 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5328678 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1168639452 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 12360 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1017104063 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 18374377 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 379747029 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1032159170 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 1017122920 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 18523621 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 379819992 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1032577011 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 206 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 815782492 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.246783 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 818460793 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.242727 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.084979 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 258071655 31.63% 31.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 228431382 28.00% 59.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 215339964 26.40% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 97765220 11.98% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 16174262 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 260810349 31.87% 31.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 227739162 27.83% 59.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 216495712 26.45% 86.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 97269955 11.88% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 16145606 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -507,44 +503,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 815782492 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 818460793 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 64513595 19.12% 19.12% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 18145 0.01% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.13% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 155496772 46.10% 65.41% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 116668709 34.59% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 64512117 19.12% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 18144 0.01% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.12% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 636889 0.19% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.31% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 155573719 46.11% 65.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 116674794 34.58% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 456384260 44.87% 44.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5195827 0.51% 45.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 456371749 44.87% 44.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 45.38% # Type of FU issued @@ -568,88 +564,88 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 45.44% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 3187675 0.31% 45.76% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 2550147 0.25% 46.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.01% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 11478996 1.13% 47.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 11478997 1.13% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.14% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 322085949 31.67% 78.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 215583681 21.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 322115143 31.67% 78.80% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 215585851 21.20% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1017104063 # Type of FU issued -system.cpu.iq.rate 1.246337 # Inst issue rate -system.cpu.iq.fu_busy_cnt 337334110 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.331661 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 3143822052 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 1504778489 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 934283929 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 61877053 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 43565817 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 26152444 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 1320627818 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 33810355 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9960647 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1017122920 # Type of FU issued +system.cpu.iq.rate 1.242213 # Inst issue rate +system.cpu.iq.fu_busy_cnt 337415663 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.331735 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 3146768879 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 1504924384 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 934270592 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 61877038 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 43565805 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 1320728240 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 33810343 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 9960122 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 113877997 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1254 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18512 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 107118661 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 113964162 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1106 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18388 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 107116171 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 2065827 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 22129 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 2065787 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 22375 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 15518642 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 35326933 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 672265 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1168584324 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 15518116 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 35326355 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41902 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1168657365 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 366118935 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 236099157 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 366205100 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 236096667 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6620 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 110 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 675878 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18512 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 15437821 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3784778 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19222599 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 974764839 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 303299768 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 42339224 # Number of squashed instructions skipped in execute +system.cpu.iew.iewIQFullEvents 109 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 45517 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18388 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 15437362 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3784555 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19221917 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 974750423 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 303297711 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 42372497 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 5556 # number of nop insts executed -system.cpu.iew.exec_refs 497763810 # number of memory reference insts executed -system.cpu.iew.exec_branches 150614661 # Number of branches executed -system.cpu.iew.exec_stores 194464042 # Number of stores executed -system.cpu.iew.exec_rate 1.194456 # Inst execution rate -system.cpu.iew.wb_sent 963735760 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 960436373 # cumulative count of insts written-back -system.cpu.iew.wb_producers 536684839 # num instructions producing a value -system.cpu.iew.wb_consumers 893296754 # num instructions consuming a value +system.cpu.iew.exec_nop 5553 # number of nop insts executed +system.cpu.iew.exec_refs 497763737 # number of memory reference insts executed +system.cpu.iew.exec_branches 150613650 # Number of branches executed +system.cpu.iew.exec_stores 194466026 # Number of stores executed +system.cpu.iew.exec_rate 1.190464 # Inst execution rate +system.cpu.iew.wb_sent 963723367 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 960423035 # cumulative count of insts written-back +system.cpu.iew.wb_producers 536681402 # num instructions producing a value +system.cpu.iew.wb_consumers 893284482 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.176898 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.600791 # average fanout of values written-back +system.cpu.iew.wb_rate 1.172966 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 357425480 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 357409752 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 15501309 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 764959828 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.031074 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.790810 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 15500908 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 767640271 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.027474 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.786859 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 428887379 56.07% 56.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 171843268 22.46% 78.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 73566556 9.62% 88.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 31622898 4.13% 92.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 7902308 1.03% 93.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 14889162 1.95% 95.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 7268582 0.95% 96.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 6618939 0.87% 97.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 22360736 2.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 430932808 56.14% 56.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 172476946 22.47% 78.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 73566678 9.58% 88.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 31624021 4.12% 92.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 8540196 1.11% 93.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 14250754 1.86% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 7269409 0.95% 96.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 6618976 0.86% 97.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 22360483 2.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 764959828 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 767640271 # Number of insts commited each cycle system.cpu.commit.committedInsts 640654410 # Number of instructions committed system.cpu.commit.committedOps 788730069 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -695,382 +691,382 @@ system.cpu.commit.op_class_0::MemWrite 128980496 16.35% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 788730069 # Class of committed instruction -system.cpu.commit.bw_lim_events 22360736 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 22360483 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 1888745890 # The number of ROB reads -system.cpu.rob.rob_writes 2343137518 # The number of ROB writes -system.cpu.timesIdled 647360 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 291908 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 1891410858 # The number of ROB reads +system.cpu.rob.rob_writes 2343104087 # The number of ROB writes +system.cpu.timesIdled 647398 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 338168 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 640649298 # Number of Instructions Simulated system.cpu.committedOps 788724957 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 1.273824 # CPI: Cycles Per Instruction -system.cpu.cpi_total 1.273824 # CPI: Total CPI of All Threads -system.cpu.ipc 0.785038 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.785038 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 995816176 # number of integer regfile reads -system.cpu.int_regfile_writes 567918829 # number of integer regfile writes -system.cpu.fp_regfile_reads 31889844 # number of floating regfile reads +system.cpu.cpi 1.278077 # CPI: Cycles Per Instruction +system.cpu.cpi_total 1.278077 # CPI: Total CPI of All Threads +system.cpu.ipc 0.782426 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.782426 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 995803851 # number of integer regfile reads +system.cpu.int_regfile_writes 567906934 # number of integer regfile writes +system.cpu.fp_regfile_reads 31889841 # number of floating regfile reads system.cpu.fp_regfile_writes 22959492 # number of floating regfile writes -system.cpu.cc_regfile_reads 3794477294 # number of cc regfile reads -system.cpu.cc_regfile_writes 384905750 # number of cc regfile writes -system.cpu.misc_regfile_reads 715814324 # number of misc regfile reads +system.cpu.cc_regfile_reads 3794434058 # number of cc regfile reads +system.cpu.cc_regfile_writes 384899317 # number of cc regfile writes +system.cpu.misc_regfile_reads 715816288 # number of misc regfile reads system.cpu.misc_regfile_writes 6386808 # number of misc regfile writes -system.cpu.dcache.tags.replacements 2756166 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.936576 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 414250087 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2756678 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 150.271481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 246939500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.936576 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999876 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999876 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 2756182 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.932940 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 414226912 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2756694 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 150.262202 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 257775000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.932940 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999869 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999869 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 189 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 839347788 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 839347788 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 286297988 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 286297988 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 127937398 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 127937398 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 3156 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 3156 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 839344268 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 839344268 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 286295518 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 286295518 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 127916671 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 127916671 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 3177 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 3177 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 5737 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 5737 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 414235386 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 414235386 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 414238542 # number of overall hits -system.cpu.dcache.overall_hits::total 414238542 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 3030809 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 3030809 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1014079 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1014079 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 646 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 646 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 414212189 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 414212189 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 414215366 # number of overall hits +system.cpu.dcache.overall_hits::total 414215366 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 3031489 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 3031489 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1034806 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1034806 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 647 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 647 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 4044888 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4044888 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4045534 # number of overall misses -system.cpu.dcache.overall_misses::total 4045534 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 33766010929 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 33766010929 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9872401734 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9872401734 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 175500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 175500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 43638412663 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 43638412663 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 43638412663 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 43638412663 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 289328797 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 289328797 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 4066295 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4066295 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4066942 # number of overall misses +system.cpu.dcache.overall_misses::total 4066942 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 35316006617 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 35316006617 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10004118304 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10004118304 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 202750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 202750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 45320124921 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 45320124921 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 45320124921 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 45320124921 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 289327007 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 289327007 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 3802 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 3802 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 3824 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 3824 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5740 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 418280274 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 418280274 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 418284076 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 418284076 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010475 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.010475 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.007864 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.007864 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169911 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.169911 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 418278484 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 418278484 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 418282308 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 418282308 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.010478 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.010478 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.008025 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.008025 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.169195 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.169195 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000523 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000523 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.009670 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.009670 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.009672 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.009672 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11140.923407 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 11140.923407 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9735.337912 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9735.337912 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 58500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 58500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 10788.534235 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 10788.534235 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 10786.811497 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 10786.811497 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.009722 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.009722 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.009723 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.009723 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11649.722832 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 11649.722832 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9667.626883 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 9667.626883 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 67583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 67583.333333 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 11145.311622 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 11145.311622 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 11143.538541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 11143.538541 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 383706 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 349732 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 5260 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5194 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 72.947909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 67.333847 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 735128 # number of writebacks -system.cpu.dcache.writebacks::total 735128 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 995619 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 995619 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 293215 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 293215 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 735277 # number of writebacks +system.cpu.dcache.writebacks::total 735277 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 996280 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 996280 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 313945 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 313945 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1288834 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1288834 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1288834 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1288834 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035190 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 2035190 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720864 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 720864 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 1310225 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1310225 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1310225 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1310225 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 2035209 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 2035209 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 720861 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 720861 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 641 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 641 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2756054 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2756054 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2756695 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2756695 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 21052594116 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 21052594116 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5256752100 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5256752100 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5684476 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5684476 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26309346216 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 26309346216 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26315030692 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26315030692 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2756070 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2756070 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2756711 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2756711 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23121613833 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23121613833 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5599042571 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5599042571 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5366500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5366500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28720656404 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 28720656404 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28726022904 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28726022904 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007034 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005590 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005590 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.168595 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.168595 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.167626 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.167626 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.006589 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.006589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006590 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.006590 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10344.289288 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10344.289288 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7292.293831 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7292.293831 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8868.137285 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8868.137285 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 9546.019859 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 9546.019859 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 9545.862234 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 9545.862234 # average overall mshr miss latency +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.006591 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.006591 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11360.805614 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11360.805614 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 7767.159787 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 7767.159787 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8372.074883 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8372.074883 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10420.873346 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 10420.873346 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10420.396953 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 10420.396953 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5169210 # number of replacements -system.cpu.icache.tags.tagsinuse 510.721915 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 364899992 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 5169720 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 70.584092 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 237857250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.721915 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997504 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997504 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 5169874 # number of replacements +system.cpu.icache.tags.tagsinuse 510.641329 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 365482216 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 5170384 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 70.687635 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 247770250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.641329 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997346 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997346 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 327 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 328 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 745313375 # Number of tag accesses -system.cpu.icache.tags.data_accesses 745313375 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 364900028 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 364900028 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 364900028 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 364900028 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 364900028 # number of overall hits -system.cpu.icache.overall_hits::total 364900028 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 5171791 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 5171791 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 5171791 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 5171791 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 5171791 # number of overall misses -system.cpu.icache.overall_misses::total 5171791 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 41611685167 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 41611685167 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 41611685167 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 41611685167 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 41611685167 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 41611685167 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 370071819 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 370071819 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 370071819 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 370071819 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 370071819 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 370071819 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013975 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.013975 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.013975 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.013975 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.013975 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.013975 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8045.894578 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 8045.894578 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 8045.894578 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 8045.894578 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 8045.894578 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 67339 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 39 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2239 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 30.075480 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 9.750000 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 746482947 # Number of tag accesses +system.cpu.icache.tags.data_accesses 746482947 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 365482251 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 365482251 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 365482251 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 365482251 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 365482251 # number of overall hits +system.cpu.icache.overall_hits::total 365482251 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 5174022 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 5174022 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 5174022 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 5174022 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 5174022 # number of overall misses +system.cpu.icache.overall_misses::total 5174022 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 41654200685 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 41654200685 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 41654200685 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 41654200685 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 41654200685 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 41654200685 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 370656273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 370656273 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 370656273 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 370656273 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 370656273 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 370656273 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013959 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013959 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013959 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013959 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013959 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013959 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 8050.642360 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 8050.642360 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 8050.642360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 8050.642360 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 8050.642360 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 76485 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 100 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3140 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 24.358280 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 20 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2054 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2054 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2054 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2054 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2054 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5169737 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 5169737 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 5169737 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 5169737 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 5169737 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 5169737 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33819004202 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 33819004202 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33819004202 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 33819004202 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33819004202 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 33819004202 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013970 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.013970 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.013970 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 6541.726243 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 6541.726243 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 6541.726243 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 6541.726243 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3620 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3620 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3620 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3620 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3620 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3620 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 5170402 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 5170402 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 5170402 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 5170402 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 5170402 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 5170402 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36439121179 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36439121179 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36439121179 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36439121179 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36439121179 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36439121179 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013949 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013949 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013949 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013949 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 7047.637917 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 7047.637917 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 7047.637917 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 7047.637917 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 1345350 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 1355301 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 8714 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 1347058 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 1355234 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 7153 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4790331 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 298968 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16361.863198 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 7823723 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 315332 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.811066 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 13372026000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 741.351492 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.669964 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 8767.936523 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6722.905220 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.045249 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007914 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.535152 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.410334 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.998649 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 6534 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 9830 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1473 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4885 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 223 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2092 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7253 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.398804 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.599976 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 139620886 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 139620886 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 5166160 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1926359 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 7092519 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 735128 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 735128 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 717996 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 717996 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 5166160 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 2644355 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7810515 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 5166160 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 2644355 # number of overall hits -system.cpu.l2cache.overall_hits::total 7810515 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3561 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 109472 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 113033 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 14 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 2851 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 2851 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3561 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 112323 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 115884 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3561 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 112323 # number of overall misses -system.cpu.l2cache.overall_misses::total 115884 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 237049229 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7458222067 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 7695271296 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 224011514 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 224011514 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 237049229 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7682233581 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7919282810 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 237049229 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7682233581 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7919282810 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 5169721 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 2035831 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7205552 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 735128 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 735128 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.prefetcher.pfSpanPage 4790478 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 299258 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16361.552831 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 7824313 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 315622 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 24.790138 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 13409363000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 738.976811 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 129.067019 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 8785.583028 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 6707.925973 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.045104 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.007878 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.536229 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.409419 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.998630 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 6482 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 9882 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 17 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 155 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 1470 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4840 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2079 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 7315 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.395630 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.603149 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 139634451 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 139634451 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 5166743 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1926167 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 7092910 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 735277 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 735277 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 718012 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 718012 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 5166743 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 2644179 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7810922 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 5166743 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 2644179 # number of overall hits +system.cpu.l2cache.overall_hits::total 7810922 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3643 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 109683 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 113326 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 16 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 16 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 2832 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 2832 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3643 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 112515 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 116158 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3643 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 112515 # number of overall misses +system.cpu.l2cache.overall_misses::total 116158 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 270029959 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8565404562 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8835434521 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 207607487 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 207607487 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 270029959 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8773012049 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9043042008 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 270029959 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8773012049 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9043042008 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 5170386 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 2035850 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7206236 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 735277 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 735277 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 720847 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 5169721 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2756678 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 7926399 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 5169721 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2756678 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 7926399 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000689 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053773 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015687 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.823529 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.823529 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003955 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.003955 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000689 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.040746 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.014620 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000689 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.040746 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.014620 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66568.163156 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68129.038174 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68079.864252 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78572.961768 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78572.961768 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68338.017414 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66568.163156 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68394.127481 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68338.017414 # average overall miss latency +system.cpu.l2cache.ReadExReq_accesses::cpu.data 720844 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 720844 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 5170386 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2756694 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 7927080 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 5170386 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2756694 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 7927080 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.000705 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.053876 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015726 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.941176 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.941176 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.003929 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.003929 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.000705 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.040815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.014653 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.000705 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.040815 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.014653 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74122.964315 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78092.362189 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77964.761140 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73307.728460 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73307.728460 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77851.219959 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74122.964315 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77971.933067 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77851.219959 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1079,145 +1075,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 66324 # number of writebacks -system.cpu.l2cache.writebacks::total 66324 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1342 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 1353 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1474 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 1474 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 2816 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 2827 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 2816 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 2827 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3550 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108130 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 111680 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202272 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 202272 # number of HardPFReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1377 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1377 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3550 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 109507 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 113057 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3550 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 109507 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202272 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 315329 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 205967021 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6469574626 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 6675541647 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 18462254833 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 84014 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 84014 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126131000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126131000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 205967021 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6595705626 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6801672647 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 205967021 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6595705626 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 18462254833 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25263927480 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053113 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015499 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 66326 # number of writebacks +system.cpu.l2cache.writebacks::total 66326 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 1303 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 1318 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1445 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 1445 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 2748 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 2763 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 2748 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 2763 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3628 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108380 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 112008 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 202241 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 202241 # number of HardPFReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 16 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1387 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3628 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 109767 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 113395 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3628 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 109767 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 202241 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 315636 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 238098541 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7611970750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7850069291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 17087057356 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 219516 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 219516 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114561754 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114561754 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 238098541 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7726532504 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7964631045 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 238098541 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7726532504 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 17087057356 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25051688401 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053236 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015543 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.823529 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.823529 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001910 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000687 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039724 # mshr miss rate for overall accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.941176 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001924 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.014305 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.000702 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039818 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.039782 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58018.879155 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59831.449422 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59773.832799 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 91274.397015 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6001 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 91598.402324 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 91598.402324 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60161.446412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58018.879155 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60230.904198 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 91274.397015 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80119.264261 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.039817 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65628.043275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70234.090699 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70084.898320 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84488.592105 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13719.750000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13719.750000 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 82596.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 82596.794521 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70237.938578 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65628.043275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70390.304044 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84488.592105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79368.919898 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7205568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7205568 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 735128 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 316987 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 7206252 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7206251 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 735277 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 248818 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 720847 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 720847 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10339458 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248518 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 16587976 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330862144 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223475584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 554337728 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 317003 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 8978547 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.035305 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.184549 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 720844 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 720844 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340787 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6248699 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 16589486 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330904640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223486144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 554390784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 248834 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 8911208 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.027922 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.164749 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 8661560 96.47% 96.47% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 316987 3.53% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 8662390 97.21% 97.21% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 248818 2.79% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 8978547 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5065908000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 8911208 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5066472000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7755114990 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7756152507 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 4143326908 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 4138701196 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 313877 # Transaction distribution -system.membus.trans_dist::ReadResp 313877 # Transaction distribution -system.membus.trans_dist::Writeback 66324 # Transaction distribution -system.membus.trans_dist::UpgradeReq 14 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14 # Transaction distribution -system.membus.trans_dist::ReadExReq 1377 # Transaction distribution -system.membus.trans_dist::ReadExResp 1377 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 696860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 696860 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24420992 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24420992 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 314173 # Transaction distribution +system.membus.trans_dist::ReadResp 314173 # Transaction distribution +system.membus.trans_dist::Writeback 66326 # Transaction distribution +system.membus.trans_dist::UpgradeReq 16 # Transaction distribution +system.membus.trans_dist::UpgradeResp 16 # Transaction distribution +system.membus.trans_dist::ReadExReq 1387 # Transaction distribution +system.membus.trans_dist::ReadExResp 1387 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697478 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697478 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24440704 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24440704 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 381592 # Request fanout histogram +system.membus.snoop_fanout::samples 381902 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 381592 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 381902 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 381592 # Request fanout histogram -system.membus.reqLayer0.occupancy 993954700 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 381902 # Request fanout histogram +system.membus.reqLayer0.occupancy 746879857 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 2896150900 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1648874306 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt index 4817ec8a9..ba52b772d 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.395727 # Nu sim_ticks 395726778000 # Number of ticks simulated final_tick 395726778000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1395078 # Simulator instruction rate (inst/s) -host_op_rate 1717525 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 861727739 # Simulator tick rate (ticks/s) -host_mem_usage 309420 # Number of bytes of host memory used -host_seconds 459.22 # Real time elapsed on the host +host_inst_rate 1601804 # Simulator instruction rate (inst/s) +host_op_rate 1972032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 989420456 # Simulator tick rate (ticks/s) +host_mem_usage 309588 # Number of bytes of host memory used +host_seconds 399.96 # Real time elapsed on the host sim_insts 640654410 # Number of instructions simulated sim_ops 788730069 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 1668035929 system.membus.pkt_size::total 4241547521 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 1022670352 # Request fanout histogram -system.membus.snoop_fanout::mean 4.629116 # Request fanout histogram +system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 379292454 37.09% 37.09% # Request fanout histogram -system.membus.snoop_fanout::5 643377898 62.91% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram +system.membus.snoop_fanout::3 643377898 62.91% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 1022670352 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt index c5e3a18fc..e078716d2 100644 --- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.043695 # Number of seconds simulated -sim_ticks 1043695084000 # Number of ticks simulated -final_tick 1043695084000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1043695077500 # Number of ticks simulated +final_tick 1043695077500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 894518 # Simulator instruction rate (inst/s) -host_op_rate 1098969 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1460200235 # Simulator tick rate (ticks/s) -host_mem_usage 317628 # Number of bytes of host memory used -host_seconds 714.76 # Real time elapsed on the host +host_inst_rate 877071 # Simulator instruction rate (inst/s) +host_op_rate 1077535 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1431720298 # Simulator tick rate (ticks/s) +host_mem_usage 317788 # Number of bytes of host memory used +host_seconds 728.98 # Real time elapsed on the host sim_insts 639366786 # Number of instructions simulated sim_ops 785501034 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 673 # Number of system calls -system.cpu.numCycles 2087390168 # number of cpu cycles simulated +system.cpu.numCycles 2087390155 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 639366786 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 381221435 # nu system.cpu.num_load_insts 252240938 # Number of load instructions system.cpu.num_store_insts 128980497 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 2087390167.998000 # Number of busy cycles +system.cpu.num_busy_cycles 2087390154.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 137364859 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 788730743 # Class of executed instruction system.cpu.dcache.tags.replacements 778046 # number of replacements -system.cpu.dcache.tags.tagsinuse 4093.640576 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4093.640588 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 378510311 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 782142 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 483.940654 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 996417000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640576 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 996414000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4093.640588 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999424 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -322,16 +322,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 782003 system.cpu.dcache.demand_mshr_misses::total 782003 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 782142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 782142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17157298000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3538506000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1613000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20695804000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20697417000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20697417000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17513638000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17513638000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3573167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3573167500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1682500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21086805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 21086805500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 21088488000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 21088488000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses @@ -342,24 +342,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24074.336308 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51043.751713 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 11604.316547 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26465.120978 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26465.120978 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26462.479959 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26462.479959 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24574.336308 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24574.336308 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51543.751713 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51543.751713 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12104.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12104.316547 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26965.120978 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26965.120978 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26962.479959 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26962.479959 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 8769 # number of replacements -system.cpu.icache.tags.tagsinuse 1391.464499 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1391.464503 # Cycle average of tags in use system.cpu.icache.tags.total_refs 643367691 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 10208 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 63025.831799 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464499 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1391.464503 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.679426 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1439 # Occupied blocks per task id @@ -381,12 +381,12 @@ system.cpu.icache.demand_misses::cpu.inst 10208 # n system.cpu.icache.demand_misses::total 10208 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 10208 # number of overall misses system.cpu.icache.overall_misses::total 10208 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 207122500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 207122500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 207122500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 207122500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 207122500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 207122500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 207116000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 207116000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 207116000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 207116000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 207116000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 207116000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 643377899 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 643377899 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 643377899 # number of demand (read+write) accesses @@ -399,12 +399,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20290.213558 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20290.213558 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20290.213558 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20290.213558 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20290.213558 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20289.576803 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20289.576803 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20289.576803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20289.576803 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20289.576803 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -419,34 +419,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 10208 system.cpu.icache.demand_mshr_misses::total 10208 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 10208 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 10208 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 186706500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 186706500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 186706500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 186706500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 186706500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 186706500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 191804000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 191804000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 191804000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 191804000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 191804000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 191804000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18290.213558 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18290.213558 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18290.213558 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 18290.213558 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18789.576803 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18789.576803 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18789.576803 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 18789.576803 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 256932 # number of replacements -system.cpu.l2cache.tags.tagsinuse 32626.698092 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 32626.698188 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 524746 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 289675 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.811499 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505475 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 2792.505447 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 49.080663 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.111953 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29785.112078 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.085221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001498 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.908969 # Average percentage of cache occupancy @@ -484,17 +484,17 @@ system.cpu.l2cache.demand_misses::total 289712 # nu system.cpu.l2cache.overall_misses::cpu.inst 1770 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 287942 # number of overall misses system.cpu.l2cache.overall_misses::total 289712 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92118500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11536392000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11628510500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3436883000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3436883000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 92118500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 14973275000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15065393500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 92118500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 14973275000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15065393500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 92997000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11647316500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11740313500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3469929500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3469929500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 92997000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 15117246000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15210243000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 92997000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 15117246000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15210243000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 10208 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712819 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 723027 # number of ReadReq accesses(hits+misses) @@ -519,17 +519,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.365636 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.173393 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.368145 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.365636 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52044.350282 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52001.099847 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52001.442185 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.711119 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.711119 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52001.275405 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52044.350282 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.010620 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52001.275405 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52540.677966 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52501.099847 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.413118 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.711119 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.711119 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.252968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52540.677966 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52501.010620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.252968 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,17 +551,17 @@ system.cpu.l2cache.demand_mshr_misses::total 289712 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1770 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 287942 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 289712 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70811000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8873960000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8944771000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2643720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70811000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11517680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11588491000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70811000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11517680000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11588491000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 71689000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8984884500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9056573500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2676766500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2676766500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 71689000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11661651000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11733340000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 71689000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11661651000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11733340000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.311228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309282 # mshr miss rate for ReadReq accesses @@ -573,17 +573,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.365636 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.173393 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.368145 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.365636 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.214689 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.049191 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40006.214689 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.037969 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40502.259887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.017888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40502.259887 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.013807 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 723027 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 723027 # Transaction distribution @@ -598,19 +598,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 883911 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) @@ -638,9 +636,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 355811 # Request fanout histogram -system.membus.reqLayer0.occupancy 884977500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 632634000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 2607766500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1448919000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt index 47efecce5..acacb719c 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.058585 # Number of seconds simulated -sim_ticks 58584661500 # Number of ticks simulated -final_tick 58584661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.059745 # Number of seconds simulated +sim_ticks 59744560000 # Number of ticks simulated +final_tick 59744560000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 201524 # Simulator instruction rate (inst/s) -host_op_rate 201524 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 133496887 # Simulator tick rate (ticks/s) -host_mem_usage 290684 # Number of bytes of host memory used -host_seconds 438.85 # Real time elapsed on the host +host_inst_rate 336953 # Simulator instruction rate (inst/s) +host_op_rate 336953 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 227629544 # Simulator tick rate (ticks/s) +host_mem_usage 304552 # Number of bytes of host memory used +host_seconds 262.46 # Real time elapsed on the host sim_insts 88438073 # Number of instructions simulated sim_ops 88438073 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 516608 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 517248 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10147776 # Number of bytes read from this memory -system.physmem.bytes_read::total 10664384 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 516608 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 516608 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7299072 # Number of bytes written to this memory -system.physmem.bytes_written::total 7299072 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 8072 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 10665024 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 517248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 517248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7299008 # Number of bytes written to this memory +system.physmem.bytes_written::total 7299008 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8082 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 158559 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166631 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114048 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114048 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 8818144 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 173215578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 182033722 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8818144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8818144 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 124590154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 124590154 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 124590154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8818144 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 173215578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 306623876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166631 # Number of read requests accepted -system.physmem.writeReqs 114048 # Number of write requests accepted -system.physmem.readBursts 166631 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114048 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10663872 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7297088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10664384 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7299072 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_reads::total 166641 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114047 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114047 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 8657659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 169852720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 178510378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8657659 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8657659 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 122170253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 122170253 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 122170253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8657659 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 169852720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 300680631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166641 # Number of read requests accepted +system.physmem.writeReqs 114047 # Number of write requests accepted +system.physmem.readBursts 166641 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114047 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10664448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7297216 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10665024 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7299008 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10466 # Per bank write bursts -system.physmem.perBankRdBursts::1 10512 # Per bank write bursts +system.physmem.perBankRdBursts::0 10464 # Per bank write bursts +system.physmem.perBankRdBursts::1 10514 # Per bank write bursts system.physmem.perBankRdBursts::2 10315 # Per bank write bursts -system.physmem.perBankRdBursts::3 10093 # Per bank write bursts -system.physmem.perBankRdBursts::4 10429 # Per bank write bursts +system.physmem.perBankRdBursts::3 10095 # Per bank write bursts +system.physmem.perBankRdBursts::4 10432 # Per bank write bursts system.physmem.perBankRdBursts::5 10431 # Per bank write bursts -system.physmem.perBankRdBursts::6 9849 # Per bank write bursts -system.physmem.perBankRdBursts::7 10302 # Per bank write bursts -system.physmem.perBankRdBursts::8 10595 # Per bank write bursts +system.physmem.perBankRdBursts::6 9850 # Per bank write bursts +system.physmem.perBankRdBursts::7 10303 # Per bank write bursts +system.physmem.perBankRdBursts::8 10594 # Per bank write bursts system.physmem.perBankRdBursts::9 10644 # Per bank write bursts -system.physmem.perBankRdBursts::10 10598 # Per bank write bursts -system.physmem.perBankRdBursts::11 10258 # Per bank write bursts -system.physmem.perBankRdBursts::12 10302 # Per bank write bursts -system.physmem.perBankRdBursts::13 10653 # Per bank write bursts +system.physmem.perBankRdBursts::10 10596 # Per bank write bursts +system.physmem.perBankRdBursts::11 10260 # Per bank write bursts +system.physmem.perBankRdBursts::12 10303 # Per bank write bursts +system.physmem.perBankRdBursts::13 10654 # Per bank write bursts system.physmem.perBankRdBursts::14 10528 # Per bank write bursts -system.physmem.perBankRdBursts::15 10648 # Per bank write bursts +system.physmem.perBankRdBursts::15 10649 # Per bank write bursts system.physmem.perBankWrBursts::0 7087 # Per bank write bursts system.physmem.perBankWrBursts::1 7261 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6998 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7176 # Per bank write bursts +system.physmem.perBankWrBursts::5 7178 # Per bank write bursts system.physmem.perBankWrBursts::6 6771 # Per bank write bursts -system.physmem.perBankWrBursts::7 7084 # Per bank write bursts -system.physmem.perBankWrBursts::8 7223 # Per bank write bursts -system.physmem.perBankWrBursts::9 6938 # Per bank write bursts -system.physmem.perBankWrBursts::10 7096 # Per bank write bursts -system.physmem.perBankWrBursts::11 6991 # Per bank write bursts -system.physmem.perBankWrBursts::12 6966 # Per bank write bursts +system.physmem.perBankWrBursts::7 7080 # Per bank write bursts +system.physmem.perBankWrBursts::8 7224 # Per bank write bursts +system.physmem.perBankWrBursts::9 6940 # Per bank write bursts +system.physmem.perBankWrBursts::10 7097 # Per bank write bursts +system.physmem.perBankWrBursts::11 6990 # Per bank write bursts +system.physmem.perBankWrBursts::12 6967 # Per bank write bursts system.physmem.perBankWrBursts::13 7289 # Per bank write bursts system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 58584634500 # Total gap between requests +system.physmem.totGap 59744533000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166631 # Read request sizes (log2) +system.physmem.readPktSize::6 166641 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114048 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 165000 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1595 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 28 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114047 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 165067 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1538 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 751 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 770 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7034 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7065 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7138 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 7045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7086 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7071 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7023 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,122 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 54549 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 329.259345 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.795576 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.998077 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19535 35.81% 35.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11763 21.56% 57.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5616 10.30% 67.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3566 6.54% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2684 4.92% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2055 3.77% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1672 3.07% 85.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1540 2.82% 88.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6118 11.22% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 54549 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7016 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.746152 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 348.264922 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 7014 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 54673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 328.521940 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 195.158907 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.861003 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19447 35.57% 35.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11824 21.63% 57.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5661 10.35% 67.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3636 6.65% 74.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2772 5.07% 79.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2160 3.95% 83.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1686 3.08% 86.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1520 2.78% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5967 10.91% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 54673 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7019 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.740134 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 348.174119 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 7017 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7016 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7016 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.250998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.234711 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.764594 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6252 89.11% 89.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 8 0.11% 89.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 591 8.42% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 125 1.78% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 23 0.33% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 8 0.11% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 5 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7016 # Writes before turning the bus around for reads -system.physmem.totQLat 1948128750 # Total ticks spent queuing -system.physmem.totMemAccLat 5072310000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 833115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11691.84 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7019 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7018 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.245939 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.230597 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.737975 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6255 89.13% 89.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 17 0.24% 89.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 574 8.18% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 144 2.05% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 20 0.28% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 4 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7018 # Writes before turning the bus around for reads +system.physmem.totQLat 1983100250 # Total ticks spent queuing +system.physmem.totMemAccLat 5107450250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 833160000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11901.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30441.84 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 182.02 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 124.56 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 182.03 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 124.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30651.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 178.50 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 122.14 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 178.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 122.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.40 # Data bus utilization in percentage -system.physmem.busUtilRead 1.42 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.97 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.35 # Data bus utilization in percentage +system.physmem.busUtilRead 1.39 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.95 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.07 # Average write queue length when enqueuing -system.physmem.readRowHits 144841 # Number of row buffer hits during reads -system.physmem.writeRowHits 81248 # Number of row buffer hits during writes -system.physmem.readRowHitRate 86.93 # Row buffer hit rate for reads +system.physmem.avgWrQLen 24.05 # Average write queue length when enqueuing +system.physmem.readRowHits 144723 # Number of row buffer hits during reads +system.physmem.writeRowHits 81251 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.85 # Row buffer hit rate for reads system.physmem.writeRowHitRate 71.24 # Row buffer hit rate for writes -system.physmem.avgGap 208724.68 # Average gap between requests -system.physmem.pageHitRate 80.55 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 199077480 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 108623625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 642681000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367791840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 12184332255 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24462392250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 41791303890 # Total energy per rank (pJ) -system.physmem_0.averagePower 713.356895 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40549753500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem.avgGap 212850.33 # Average gap between requests +system.physmem.pageHitRate 80.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 199115280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 108644250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 642735600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367778880 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12699594585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24706498500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 42626547975 # Total energy per rank (pJ) +system.physmem_0.averagePower 713.484810 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40950314500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1994980000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16078529000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16799112000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 213282720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 116374500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 656908200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 371038320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3826405440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 12703202685 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24007242750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 41894454615 # Total energy per rank (pJ) -system.physmem_1.averagePower 715.117627 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 39789307500 # Time in different power states -system.physmem_1.memoryStateTime::REF 1956240000 # Time in different power states +system.physmem_1.actEnergy 214197480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 116873625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 656962800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 371031840 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3902180880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 13192492680 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 24274131750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 42727871055 # Total energy per rank (pJ) +system.physmem_1.averagePower 715.180760 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 40226086750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1994980000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 16838471250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17523103250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14678313 # Number of BP lookups -system.cpu.branchPred.condPredicted 9498021 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 389703 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9975544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6390264 # Number of BTB hits +system.cpu.branchPred.lookups 14679718 # Number of BP lookups +system.cpu.branchPred.condPredicted 9498983 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 392764 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10434122 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6393495 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 64.059303 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1709596 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 85905 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 61.274873 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1709689 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 85822 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 20567455 # DTB read hits -system.cpu.dtb.read_misses 96888 # DTB read misses +system.cpu.dtb.read_hits 20566953 # DTB read hits +system.cpu.dtb.read_misses 96874 # DTB read misses system.cpu.dtb.read_acv 11 # DTB read access violations -system.cpu.dtb.read_accesses 20664343 # DTB read accesses -system.cpu.dtb.write_hits 14665775 # DTB write hits -system.cpu.dtb.write_misses 9411 # DTB write misses +system.cpu.dtb.read_accesses 20663827 # DTB read accesses +system.cpu.dtb.write_hits 14666692 # DTB write hits +system.cpu.dtb.write_misses 9419 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 14675186 # DTB write accesses -system.cpu.dtb.data_hits 35233230 # DTB hits -system.cpu.dtb.data_misses 106299 # DTB misses +system.cpu.dtb.write_accesses 14676111 # DTB write accesses +system.cpu.dtb.data_hits 35233645 # DTB hits +system.cpu.dtb.data_misses 106293 # DTB misses system.cpu.dtb.data_acv 11 # DTB access violations -system.cpu.dtb.data_accesses 35339529 # DTB accesses -system.cpu.itb.fetch_hits 25627333 # ITB hits -system.cpu.itb.fetch_misses 5261 # ITB misses +system.cpu.dtb.data_accesses 35339938 # DTB accesses +system.cpu.itb.fetch_hits 25640132 # ITB hits +system.cpu.itb.fetch_misses 5244 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 25632594 # ITB accesses +system.cpu.itb.fetch_accesses 25645376 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -322,81 +321,81 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 117169323 # number of cpu cycles simulated +system.cpu.numCycles 119489120 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88438073 # Number of instructions committed system.cpu.committedOps 88438073 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1098705 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1100288 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.324874 # CPI: cycles per instruction -system.cpu.ipc 0.754789 # IPC: instructions per cycle -system.cpu.tickCycles 91571156 # Number of cycles that the object actually ticked -system.cpu.idleCycles 25598167 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 200776 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.523211 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34616515 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204872 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 168.966550 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 644809250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.523211 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994024 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994024 # Average percentage of cache occupancy +system.cpu.cpi 1.351105 # CPI: cycles per instruction +system.cpu.ipc 0.740135 # IPC: instructions per cycle +system.cpu.tickCycles 91601603 # Number of cycles that the object actually ticked +system.cpu.idleCycles 27887517 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 200784 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.582702 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34615842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204880 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 168.956667 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 693853250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.582702 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993795 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993795 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 745 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3298 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 678 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3372 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 70176892 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 70176892 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20283193 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20283193 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14333322 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14333322 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34616515 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34616515 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34616515 # number of overall hits -system.cpu.dcache.overall_hits::total 34616515 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89440 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89440 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 280055 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 280055 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 369495 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369495 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369495 # number of overall misses -system.cpu.dcache.overall_misses::total 369495 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4407640500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4407640500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19996177500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19996177500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24403818000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24403818000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24403818000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24403818000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20372633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20372633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 70175650 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 70175650 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20282569 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20282569 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14333273 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14333273 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34615842 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34615842 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34615842 # number of overall hits +system.cpu.dcache.overall_hits::total 34615842 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89439 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89439 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 280104 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 280104 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 369543 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 369543 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 369543 # number of overall misses +system.cpu.dcache.overall_misses::total 369543 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4793461000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4793461000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 21859170750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21859170750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26652631750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26652631750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26652631750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26652631750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20372008 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20372008 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34986010 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34986010 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34986010 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34986010 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 34985385 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34985385 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34985385 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34985385 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004390 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.004390 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019164 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.019164 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.010561 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.010561 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.010561 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.010561 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49280.417039 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 49280.417039 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71400.894467 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 71400.894467 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66046.409288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66046.409288 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66046.409288 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.019168 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.010563 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.010563 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.010563 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.010563 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53594.751730 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 53594.751730 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 78039.480871 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 78039.480871 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72123.221790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72123.221790 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72123.221790 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -405,32 +404,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168546 # number of writebacks -system.cpu.dcache.writebacks::total 168546 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28125 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 28125 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136498 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 136498 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 164623 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 164623 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 164623 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 164623 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61315 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 61315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143557 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143557 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204872 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204872 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204872 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204872 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2422248250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2422248250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9931035500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 9931035500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12353283750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12353283750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12353283750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12353283750 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 168547 # number of writebacks +system.cpu.dcache.writebacks::total 168547 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 28118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 28118 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 136545 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 136545 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 164663 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 164663 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 164663 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 164663 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61321 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61321 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143559 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143559 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204880 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204880 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204880 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204880 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2650982250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2650982250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10919810750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 10919810750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13570793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13570793000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13570793000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13570793000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.003010 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009824 # mshr miss rate for WriteReq accesses @@ -439,68 +438,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005856 system.cpu.dcache.demand_mshr_miss_rate::total 0.005856 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005856 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005856 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39504.986545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39504.986545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69178.343794 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69178.343794 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60297.569946 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60297.569946 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60297.569946 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60297.569946 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 43231.229921 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 43231.229921 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76064.968062 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76064.968062 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66237.763569 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66237.763569 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66237.763569 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66237.763569 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 153786 # number of replacements -system.cpu.icache.tags.tagsinuse 1934.126530 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25471498 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 155834 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 163.452764 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 41649701250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1934.126530 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.944398 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.944398 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 153858 # number of replacements +system.cpu.icache.tags.tagsinuse 1932.426254 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25484225 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 155906 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 163.458911 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42458251250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1932.426254 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.943568 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.943568 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1053 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 788 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 163 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1044 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 797 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 51410500 # Number of tag accesses -system.cpu.icache.tags.data_accesses 51410500 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25471498 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25471498 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25471498 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25471498 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25471498 # number of overall hits -system.cpu.icache.overall_hits::total 25471498 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 155835 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 155835 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 155835 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 155835 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 155835 # number of overall misses -system.cpu.icache.overall_misses::total 155835 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2527958991 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2527958991 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2527958991 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2527958991 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2527958991 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2527958991 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25627333 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25627333 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25627333 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25627333 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25627333 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25627333 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 51436170 # Number of tag accesses +system.cpu.icache.tags.data_accesses 51436170 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25484225 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25484225 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25484225 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25484225 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25484225 # number of overall hits +system.cpu.icache.overall_hits::total 25484225 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 155907 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 155907 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 155907 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 155907 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 155907 # number of overall misses +system.cpu.icache.overall_misses::total 155907 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2585038742 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2585038742 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2585038742 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2585038742 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2585038742 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2585038742 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25640132 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25640132 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25640132 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25640132 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25640132 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25640132 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.006081 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.006081 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.006081 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.006081 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.006081 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.006081 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16222.023236 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16222.023236 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16222.023236 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16222.023236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16222.023236 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16222.023236 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16580.645782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16580.645782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16580.645782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16580.645782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16580.645782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16580.645782 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -509,123 +508,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155835 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 155835 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 155835 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 155835 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 155835 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 155835 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2213169009 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2213169009 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2213169009 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2213169009 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2213169009 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2213169009 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 155907 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 155907 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 155907 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 155907 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 155907 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 155907 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2348059258 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2348059258 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2348059258 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2348059258 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2348059258 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2348059258 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006081 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.006081 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006081 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.006081 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14202.002175 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14202.002175 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14202.002175 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14202.002175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14202.002175 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14202.002175 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15060.640369 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15060.640369 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15060.640369 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15060.640369 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15060.640369 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15060.640369 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 132704 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30477.430936 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 220653 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164780 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.339076 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 132715 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30422.088467 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 220721 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164791 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.339400 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26240.320965 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2376.783596 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1860.326375 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.800791 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072534 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.056773 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.930097 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 26158.947481 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2368.396244 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1894.744742 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.798308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072278 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.057823 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.928408 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32076 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1021 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11978 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 18839 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 935 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11645 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19273 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 113 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978882 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4542362 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4542362 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 147762 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 33637 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 181399 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168546 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168546 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12676 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12676 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 147762 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46313 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 194075 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 147762 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46313 # number of overall hits -system.cpu.l2cache.overall_hits::total 194075 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 8073 # number of ReadReq misses +system.cpu.l2cache.tags.tag_accesses 4543023 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4543023 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 147824 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 33643 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 181467 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168547 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168547 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12678 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12678 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 147824 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46321 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 194145 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 147824 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46321 # number of overall hits +system.cpu.l2cache.overall_hits::total 194145 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 8083 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 27677 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35750 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 35760 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 130882 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 130882 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 8073 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 8083 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 158559 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166632 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 8073 # number of overall misses +system.cpu.l2cache.demand_misses::total 166642 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 8083 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158559 # number of overall misses -system.cpu.l2cache.overall_misses::total 166632 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 579593000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2024136750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2603729750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9660681500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 9660681500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 579593000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11684818250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12264411250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 579593000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11684818250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12264411250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 155835 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 61314 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 217149 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168546 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168546 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143558 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143558 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 155835 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 204872 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 360707 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 155835 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 204872 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 360707 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.051805 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.451398 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.164634 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911701 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911701 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.051805 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.773942 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.461959 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.051805 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.773942 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.461959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71794.004707 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73134.254074 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72831.601399 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73812.147583 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73812.147583 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71794.004707 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73693.819020 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73601.776670 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71794.004707 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73693.819020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73601.776670 # average overall miss latency +system.cpu.l2cache.overall_misses::total 166642 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 639821250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2235970750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2875792000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10643101750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10643101750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 639821250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12879072500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13518893750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 639821250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12879072500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13518893750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 155907 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 61320 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 217227 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168547 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168547 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143560 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143560 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 155907 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 204880 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 360787 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 155907 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 204880 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 360787 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.051845 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.451354 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.164620 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911688 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.911688 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.051845 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.773912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.461885 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.051845 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.773912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.461885 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79156.408512 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80788.046031 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80419.239374 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81318.300072 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81318.300072 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79156.408512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81225.742468 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81125.369055 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79156.408512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81225.742468 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81125.369055 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -634,105 +633,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114048 # number of writebacks -system.cpu.l2cache.writebacks::total 114048 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8073 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 114047 # number of writebacks +system.cpu.l2cache.writebacks::total 114047 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8083 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27677 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35750 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 35760 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130882 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 130882 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 8073 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 8083 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 158559 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166632 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 8073 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166642 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 8083 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158559 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166632 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 478164000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1670924750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2149088750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7975554000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7975554000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 478164000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9646478750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 10124642750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 478164000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9646478750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 10124642750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.051805 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.451398 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.164634 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911701 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.051805 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773942 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.461959 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.051805 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773942 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.461959 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59230.026013 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60372.321783 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60114.370629 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60936.981403 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60936.981403 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59230.026013 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60838.418191 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59230.026013 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60838.418191 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60760.494683 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::total 166642 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 538585250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1889755250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2428340500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9006674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9006674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 538585250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10896429500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11435014750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 538585250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10896429500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11435014750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.051845 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.451354 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.164620 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911688 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911688 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.051845 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.461885 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.051845 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.461885 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66631.850798 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68278.904867 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67906.613535 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68815.224783 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68815.224783 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66631.850798 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68721.608360 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68620.244296 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66631.850798 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68721.608360 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68620.244296 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 217149 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 217148 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168546 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143558 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143558 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311669 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578290 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 889959 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9973376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23898752 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 33872128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 217227 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 217226 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168547 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143560 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143560 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 311813 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 578307 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 890120 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9977984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23899328 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 33877312 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 529253 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 529334 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 529253 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 529334 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 529253 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 433172500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 529334 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 433214000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 235311991 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 235419242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 343212750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 343262500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35749 # Transaction distribution -system.membus.trans_dist::ReadResp 35749 # Transaction distribution -system.membus.trans_dist::Writeback 114048 # Transaction distribution +system.membus.trans_dist::ReadReq 35759 # Transaction distribution +system.membus.trans_dist::ReadResp 35759 # Transaction distribution +system.membus.trans_dist::Writeback 114047 # Transaction distribution system.membus.trans_dist::ReadExReq 130882 # Transaction distribution system.membus.trans_dist::ReadExResp 130882 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447310 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 447310 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17963456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17963456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447329 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 447329 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17964032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17964032 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280679 # Request fanout histogram +system.membus.snoop_fanout::samples 280688 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280679 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280688 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280679 # Request fanout histogram -system.membus.reqLayer0.occupancy 1304618000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 1602414250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.7 # Layer utilization (%) +system.membus.snoop_fanout::total 280688 # Request fanout histogram +system.membus.reqLayer0.occupancy 817068000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 879892750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt index 6d3efb0ae..c7130e3ac 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022282 # Number of seconds simulated -sim_ticks 22281815500 # Number of ticks simulated -final_tick 22281815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022578 # Number of seconds simulated +sim_ticks 22578120000 # Number of ticks simulated +final_tick 22578120000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 227860 # Simulator instruction rate (inst/s) -host_op_rate 227860 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 63789654 # Simulator tick rate (ticks/s) -host_mem_usage 305428 # Number of bytes of host memory used -host_seconds 349.30 # Real time elapsed on the host +host_inst_rate 224564 # Simulator instruction rate (inst/s) +host_op_rate 224564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63702871 # Simulator tick rate (ticks/s) +host_mem_usage 305848 # Number of bytes of host memory used +host_seconds 354.43 # Real time elapsed on the host sim_insts 79591756 # Number of instructions simulated sim_ops 79591756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 487168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10151488 # Number of bytes read from this memory -system.physmem.bytes_read::total 10638656 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 487168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 487168 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7296384 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296384 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 7612 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158617 # Number of read requests responded to by this memory -system.physmem.num_reads::total 166229 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 114006 # Number of write requests responded to by this memory -system.physmem.num_writes::total 114006 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 21863928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455595192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 477459119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 21863928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 21863928 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 327459134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 327459134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 327459134 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 21863928 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455595192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 804918253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 166229 # Number of read requests accepted -system.physmem.writeReqs 114006 # Number of write requests accepted -system.physmem.readBursts 166229 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 114006 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytes_read::cpu.inst 487616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10151104 # Number of bytes read from this memory +system.physmem.bytes_read::total 10638720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 487616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 487616 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7296832 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296832 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 7619 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158611 # Number of read requests responded to by this memory +system.physmem.num_reads::total 166230 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114013 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114013 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 21596838 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 449599169 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 471196007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 21596838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 21596838 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 323181558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 323181558 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 323181558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 21596838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 449599169 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 794377566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 166230 # Number of read requests accepted +system.physmem.writeReqs 114013 # Number of write requests accepted +system.physmem.readBursts 166230 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 114013 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 10638144 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 512 # Total number of bytes read from write queue -system.physmem.bytesWritten 7294656 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10638656 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7296384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 8 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytesReadWrQ 576 # Total number of bytes read from write queue +system.physmem.bytesWritten 7294912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10638720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7296832 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 9 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10438 # Per bank write bursts -system.physmem.perBankRdBursts::1 10454 # Per bank write bursts -system.physmem.perBankRdBursts::2 10317 # Per bank write bursts -system.physmem.perBankRdBursts::3 10059 # Per bank write bursts -system.physmem.perBankRdBursts::4 10417 # Per bank write bursts -system.physmem.perBankRdBursts::5 10393 # Per bank write bursts +system.physmem.perBankRdBursts::0 10435 # Per bank write bursts +system.physmem.perBankRdBursts::1 10460 # Per bank write bursts +system.physmem.perBankRdBursts::2 10318 # Per bank write bursts +system.physmem.perBankRdBursts::3 10058 # Per bank write bursts +system.physmem.perBankRdBursts::4 10413 # Per bank write bursts +system.physmem.perBankRdBursts::5 10396 # Per bank write bursts system.physmem.perBankRdBursts::6 9837 # Per bank write bursts -system.physmem.perBankRdBursts::7 10310 # Per bank write bursts -system.physmem.perBankRdBursts::8 10606 # Per bank write bursts -system.physmem.perBankRdBursts::9 10643 # Per bank write bursts -system.physmem.perBankRdBursts::10 10543 # Per bank write bursts -system.physmem.perBankRdBursts::11 10224 # Per bank write bursts -system.physmem.perBankRdBursts::12 10268 # Per bank write bursts -system.physmem.perBankRdBursts::13 10616 # Per bank write bursts -system.physmem.perBankRdBursts::14 10478 # Per bank write bursts -system.physmem.perBankRdBursts::15 10618 # Per bank write bursts +system.physmem.perBankRdBursts::7 10308 # Per bank write bursts +system.physmem.perBankRdBursts::8 10587 # Per bank write bursts +system.physmem.perBankRdBursts::9 10644 # Per bank write bursts +system.physmem.perBankRdBursts::10 10547 # Per bank write bursts +system.physmem.perBankRdBursts::11 10228 # Per bank write bursts +system.physmem.perBankRdBursts::12 10270 # Per bank write bursts +system.physmem.perBankRdBursts::13 10618 # Per bank write bursts +system.physmem.perBankRdBursts::14 10481 # Per bank write bursts +system.physmem.perBankRdBursts::15 10621 # Per bank write bursts system.physmem.perBankWrBursts::0 7083 # Per bank write bursts -system.physmem.perBankWrBursts::1 7253 # Per bank write bursts +system.physmem.perBankWrBursts::1 7259 # Per bank write bursts system.physmem.perBankWrBursts::2 7255 # Per bank write bursts system.physmem.perBankWrBursts::3 6997 # Per bank write bursts system.physmem.perBankWrBursts::4 7126 # Per bank write bursts -system.physmem.perBankWrBursts::5 7169 # Per bank write bursts -system.physmem.perBankWrBursts::6 6770 # Per bank write bursts -system.physmem.perBankWrBursts::7 7085 # Per bank write bursts -system.physmem.perBankWrBursts::8 7220 # Per bank write bursts -system.physmem.perBankWrBursts::9 6943 # Per bank write bursts -system.physmem.perBankWrBursts::10 7084 # Per bank write bursts +system.physmem.perBankWrBursts::5 7171 # Per bank write bursts +system.physmem.perBankWrBursts::6 6772 # Per bank write bursts +system.physmem.perBankWrBursts::7 7083 # Per bank write bursts +system.physmem.perBankWrBursts::8 7219 # Per bank write bursts +system.physmem.perBankWrBursts::9 6939 # Per bank write bursts +system.physmem.perBankWrBursts::10 7083 # Per bank write bursts system.physmem.perBankWrBursts::11 6988 # Per bank write bursts system.physmem.perBankWrBursts::12 6964 # Per bank write bursts -system.physmem.perBankWrBursts::13 7287 # Per bank write bursts -system.physmem.perBankWrBursts::14 7283 # Per bank write bursts +system.physmem.perBankWrBursts::13 7288 # Per bank write bursts +system.physmem.perBankWrBursts::14 7284 # Per bank write bursts system.physmem.perBankWrBursts::15 7472 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22281781500 # Total gap between requests +system.physmem.totGap 22578086500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 166229 # Read request sizes (log2) +system.physmem.readPktSize::6 166230 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 114006 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 51659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 54099 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 45462 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14988 # What read queue length does an incoming req see +system.physmem.writePktSize::6 114013 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 52462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 43160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 32153 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,33 +144,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2462 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4500 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5890 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6743 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7087 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7911 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8638 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8038 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 257 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 784 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4829 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6617 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 7222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7835 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8007 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8246 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 9963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -193,124 +193,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 52189 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 343.580755 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 201.430431 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 344.457165 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 18353 35.17% 35.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 10742 20.58% 55.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5641 10.81% 66.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3092 5.92% 72.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2629 5.04% 77.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1694 3.25% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1790 3.43% 84.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1288 2.47% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6960 13.34% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 52189 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6966 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 23.861757 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 342.246517 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 6964 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 52260 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 343.127440 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 201.641716 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 343.309325 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 18423 35.25% 35.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 10477 20.05% 55.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5934 11.35% 66.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2978 5.70% 72.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2855 5.46% 77.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1509 2.89% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2072 3.96% 84.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 924 1.77% 86.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7088 13.56% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 52260 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6982 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 23.804927 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 342.249057 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 6981 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::27648-28671 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6966 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6965 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.363676 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.332802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.079402 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 6068 87.12% 87.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 30 0.43% 87.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 495 7.11% 94.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 185 2.66% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 91 1.31% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 46 0.66% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 21 0.30% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 10 0.14% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 10 0.14% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.07% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6965 # Writes before turning the bus around for reads -system.physmem.totQLat 5436579750 # Total ticks spent queuing -system.physmem.totMemAccLat 8553223500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.rdPerTurnAround::total 6982 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6982 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.325265 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.299310 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.979398 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 6150 88.08% 88.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 25 0.36% 88.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 468 6.70% 95.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 181 2.59% 97.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 78 1.12% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 46 0.66% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 19 0.27% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 10 0.14% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 4 0.06% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6982 # Writes before turning the bus around for reads +system.physmem.totQLat 5742111500 # Total ticks spent queuing +system.physmem.totMemAccLat 8858755250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 831105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32706.94 # Average queueing delay per DRAM burst +system.physmem.avgQLat 34545.04 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51456.94 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 477.44 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 327.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 477.46 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 327.46 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53295.04 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 471.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 323.10 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 471.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 323.18 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.29 # Data bus utilization in percentage -system.physmem.busUtilRead 3.73 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 2.56 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing -system.physmem.readRowHits 146012 # Number of row buffer hits during reads -system.physmem.writeRowHits 81986 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.84 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.91 # Row buffer hit rate for writes -system.physmem.avgGap 79511.06 # Average gap between requests -system.physmem.pageHitRate 81.36 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 190496880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 103941750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 641043000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 367539120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 6553751985 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 7617131250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 16928894145 # Total energy per rank (pJ) -system.physmem_0.averagePower 759.936312 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12590169250 # Time in different power states -system.physmem_0.memoryStateTime::REF 743860000 # Time in different power states +system.physmem.busUtil 6.21 # Data bus utilization in percentage +system.physmem.busUtilRead 3.68 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 2.52 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.91 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.41 # Average write queue length when enqueuing +system.physmem.readRowHits 146222 # Number of row buffer hits during reads +system.physmem.writeRowHits 81709 # Number of row buffer hits during writes +system.physmem.readRowHitRate 87.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.67 # Row buffer hit rate for writes +system.physmem.avgGap 80566.10 # Average gap between requests +system.physmem.pageHitRate 81.34 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 190685880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 104044875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 641035200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 367584480 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 6555814245 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 7792863750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 17126343870 # Total energy per rank (pJ) +system.physmem_0.averagePower 758.721685 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12883309000 # Time in different power states +system.physmem_0.memoryStateTime::REF 753740000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 8942711000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 8935594000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 203779800 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111189375 # Energy for precharge commands per rank (pJ) +system.physmem_1.actEnergy 204104880 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 111366750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 654919200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 370694880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1454990160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 6762785805 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 7433764500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 16992123720 # Total energy per rank (pJ) -system.physmem_1.averagePower 762.774895 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 12284853000 # Time in different power states -system.physmem_1.memoryStateTime::REF 743860000 # Time in different power states +system.physmem_1.writeEnergy 370701360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 1474315440 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 6889050495 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 7500532500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 17204990625 # Total energy per rank (pJ) +system.physmem_1.averagePower 762.206905 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 12395641000 # Time in different power states +system.physmem_1.memoryStateTime::REF 753740000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9248437000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9423231500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16624924 # Number of BP lookups -system.cpu.branchPred.condPredicted 10755300 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 362268 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 10924107 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7374828 # Number of BTB hits +system.cpu.branchPred.lookups 16619938 # Number of BP lookups +system.cpu.branchPred.condPredicted 10751763 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 361573 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 10694449 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7373128 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 67.509665 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1991560 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 2903 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 68.943505 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1990233 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 3119 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 22639897 # DTB read hits -system.cpu.dtb.read_misses 226363 # DTB read misses -system.cpu.dtb.read_acv 23 # DTB read access violations -system.cpu.dtb.read_accesses 22866260 # DTB read accesses -system.cpu.dtb.write_hits 15870343 # DTB write hits -system.cpu.dtb.write_misses 44837 # DTB write misses +system.cpu.dtb.read_hits 22587975 # DTB read hits +system.cpu.dtb.read_misses 226213 # DTB read misses +system.cpu.dtb.read_acv 17 # DTB read access violations +system.cpu.dtb.read_accesses 22814188 # DTB read accesses +system.cpu.dtb.write_hits 15866557 # DTB write hits +system.cpu.dtb.write_misses 44947 # DTB write misses system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 15915180 # DTB write accesses -system.cpu.dtb.data_hits 38510240 # DTB hits -system.cpu.dtb.data_misses 271200 # DTB misses -system.cpu.dtb.data_acv 24 # DTB access violations -system.cpu.dtb.data_accesses 38781440 # DTB accesses -system.cpu.itb.fetch_hits 13919462 # ITB hits -system.cpu.itb.fetch_misses 31654 # ITB misses +system.cpu.dtb.write_accesses 15911504 # DTB write accesses +system.cpu.dtb.data_hits 38454532 # DTB hits +system.cpu.dtb.data_misses 271160 # DTB misses +system.cpu.dtb.data_acv 18 # DTB access violations +system.cpu.dtb.data_accesses 38725692 # DTB accesses +system.cpu.itb.fetch_hits 13913083 # ITB hits +system.cpu.itb.fetch_misses 32600 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 13951116 # ITB accesses +system.cpu.itb.fetch_accesses 13945683 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -324,240 +321,240 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 44563634 # number of cpu cycles simulated +system.cpu.numCycles 45156244 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 15791560 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 106158478 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16624924 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9366388 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 27217966 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 963396 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 137 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4946 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337279 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 13919462 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 206375 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 43833697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.421846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.133787 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 15767330 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 106100961 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16619938 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9363361 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 27775290 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 962592 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 208 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5030 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 339291 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 71 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 13913083 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 207051 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 44368516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.391357 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.125574 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 24095007 54.97% 54.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1538131 3.51% 58.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1406372 3.21% 61.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1524721 3.48% 65.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4235690 9.66% 74.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1846144 4.21% 79.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 685371 1.56% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1070354 2.44% 83.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 7431907 16.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 24640012 55.53% 55.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1537852 3.47% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1401576 3.16% 62.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1522530 3.43% 65.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4244947 9.57% 75.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1845094 4.16% 79.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 677475 1.53% 80.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1069981 2.41% 83.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 7429049 16.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 43833697 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.373060 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.382177 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 15105656 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9282610 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18470395 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 592044 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 382992 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3741910 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 100605 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 104048931 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 315835 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 382992 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 15490766 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6387964 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 95966 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 18655378 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2820631 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102900646 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4493 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 152365 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 320462 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 2296242 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 61929819 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 124171537 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 123841536 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 330000 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44368516 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.368054 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.349641 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 15099347 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9823247 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18465046 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 597969 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 382907 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3741515 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 100209 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 104016227 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 314595 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 382907 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 15487504 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6707215 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 96849 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 18654699 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3039342 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102867556 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 4643 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 101006 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 348263 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 2491758 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 61906530 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 124122948 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 123794647 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 328300 # Number of floating rename lookups system.cpu.rename.CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 9382938 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 5791 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 5849 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2464589 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 23265416 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16459353 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1262626 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 544604 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 91320451 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5681 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 89124415 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 80151 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11242959 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4725710 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1098 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 43833697 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.033240 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.247678 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 9359649 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 5745 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 5793 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2522683 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 23265731 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16453437 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1244012 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 539260 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 91299347 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 5639 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 89055311 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 77552 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11218941 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4714239 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1056 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44368516 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.007174 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.246117 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17209661 39.26% 39.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 5800175 13.23% 52.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 5098270 11.63% 64.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 4410681 10.06% 74.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4347575 9.92% 84.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2649961 6.05% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1950790 4.45% 94.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1381860 3.15% 97.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 984724 2.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17795444 40.11% 40.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 5774110 13.01% 53.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 5077311 11.44% 64.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 4396727 9.91% 74.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4357066 9.82% 84.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2650893 5.97% 90.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1948119 4.39% 94.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1385813 3.12% 97.78% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 983033 2.22% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 43833697 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44368516 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 244354 9.65% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.65% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 1175209 46.41% 56.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 1112799 43.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 243204 9.64% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.64% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 1172094 46.45% 56.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 1108166 43.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49663354 55.72% 55.72% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 44187 0.05% 55.77% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.77% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 122171 0.14% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 88 0.00% 55.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 121874 0.14% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 57 0.00% 56.05% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 39065 0.04% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.09% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 23057459 25.87% 81.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 16076160 18.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49651741 55.75% 55.75% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 44157 0.05% 55.80% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 55.80% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 121956 0.14% 55.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 89 0.00% 55.94% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 121436 0.14% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 54 0.00% 56.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 39055 0.04% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.12% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 23004684 25.83% 81.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 16072139 18.05% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 89124415 # Type of FU issued -system.cpu.iq.rate 1.999936 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2532362 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.028414 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 224079080 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 102152200 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 87178162 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 615960 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 437940 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 301333 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 91348643 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 308134 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1658507 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 89055311 # Type of FU issued +system.cpu.iq.rate 1.972159 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2523465 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.028336 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 224465346 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 102111433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 87163804 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 614809 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 433572 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 300747 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 91271228 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 307548 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1661543 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 2988778 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6943 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 21591 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1845976 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 2989093 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6317 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 21548 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1840060 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 3051 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 325532 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 3023 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 186080 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 382992 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1216204 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4841557 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 100851766 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 147146 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 23265416 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 16459353 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 5598 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3356 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 4819285 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 21591 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 151679 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 156559 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 308238 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 88344034 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 22866899 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 780381 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 382907 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1413856 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 4974138 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 100829471 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 151929 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 23265731 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 16453437 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 5565 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 4999 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4957861 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 21548 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 151078 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 158072 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 309150 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 88275465 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 22814985 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 779846 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9525634 # number of nop insts executed -system.cpu.iew.exec_refs 38782381 # number of memory reference insts executed -system.cpu.iew.exec_branches 15172546 # Number of branches executed -system.cpu.iew.exec_stores 15915482 # Number of stores executed -system.cpu.iew.exec_rate 1.982424 # Inst execution rate -system.cpu.iew.wb_sent 87895909 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 87479495 # cumulative count of insts written-back -system.cpu.iew.wb_producers 33899568 # num instructions producing a value -system.cpu.iew.wb_consumers 44349597 # num instructions consuming a value +system.cpu.iew.exec_nop 9524485 # number of nop insts executed +system.cpu.iew.exec_refs 38726852 # number of memory reference insts executed +system.cpu.iew.exec_branches 15171568 # Number of branches executed +system.cpu.iew.exec_stores 15911867 # Number of stores executed +system.cpu.iew.exec_rate 1.954889 # Inst execution rate +system.cpu.iew.wb_sent 87882002 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 87464551 # cumulative count of insts written-back +system.cpu.iew.wb_producers 33900833 # num instructions producing a value +system.cpu.iew.wb_consumers 44342613 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.963024 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.764372 # average fanout of values written-back +system.cpu.iew.wb_rate 1.936931 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.764520 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9308985 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9282281 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 263562 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 42463328 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.080399 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.884681 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 263184 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 43000551 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.054408 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.876009 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 20917493 49.26% 49.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 6333939 14.92% 64.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 2944595 6.93% 71.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1757333 4.14% 75.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1653620 3.89% 79.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1138333 2.68% 81.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1205391 2.84% 84.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 793939 1.87% 86.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 5718685 13.47% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21467431 49.92% 49.92% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 6329802 14.72% 64.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 2918642 6.79% 71.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1760390 4.09% 75.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1670777 3.89% 79.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1138707 2.65% 82.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1203989 2.80% 84.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 794665 1.85% 86.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 5716148 13.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 42463328 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 43000551 # Number of insts commited each cycle system.cpu.commit.committedInsts 88340672 # Number of instructions committed system.cpu.commit.committedOps 88340672 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -603,344 +600,344 @@ system.cpu.commit.op_class_0::MemWrite 14613377 16.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 88340672 # Class of committed instruction -system.cpu.commit.bw_lim_events 5718685 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 5716148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133076958 # The number of ROB reads -system.cpu.rob.rob_writes 196673244 # The number of ROB writes -system.cpu.timesIdled 48172 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 729937 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 133590014 # The number of ROB reads +system.cpu.rob.rob_writes 196617452 # The number of ROB writes +system.cpu.timesIdled 47547 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 787728 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedOps 79591756 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.559903 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.559903 # CPI: Total CPI of All Threads -system.cpu.ipc 1.786025 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.786025 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 116925772 # number of integer regfile reads -system.cpu.int_regfile_writes 57936362 # number of integer regfile writes -system.cpu.fp_regfile_reads 255891 # number of floating regfile reads -system.cpu.fp_regfile_writes 241873 # number of floating regfile writes -system.cpu.misc_regfile_reads 38152 # number of misc regfile reads +system.cpu.cpi 0.567348 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.567348 # CPI: Total CPI of All Threads +system.cpu.ipc 1.762586 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.762586 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 116851082 # number of integer regfile reads +system.cpu.int_regfile_writes 57926468 # number of integer regfile writes +system.cpu.fp_regfile_reads 255690 # number of floating regfile reads +system.cpu.fp_regfile_writes 241313 # number of floating regfile writes +system.cpu.misc_regfile_reads 38160 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 201381 # number of replacements -system.cpu.dcache.tags.tagsinuse 4071.852002 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34090259 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 205477 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 165.907907 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 215961000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4071.852002 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.994104 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.994104 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 201362 # number of replacements +system.cpu.dcache.tags.tagsinuse 4070.706489 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34086491 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 205458 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 165.904910 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 231989000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4070.706489 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993825 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993825 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2773 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2590 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 71020605 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 71020605 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20525911 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20525911 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 13564288 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 13564288 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 34090199 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34090199 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34090199 # number of overall hits -system.cpu.dcache.overall_hits::total 34090199 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 268215 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 268215 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1049089 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1049089 # number of WriteReq misses +system.cpu.dcache.tags.tag_accesses 71020044 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 71020044 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20525035 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20525035 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 13561393 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 13561393 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 34086428 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34086428 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34086428 # number of overall hits +system.cpu.dcache.overall_hits::total 34086428 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 268817 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 268817 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1051984 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1051984 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1317304 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1317304 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1317304 # number of overall misses -system.cpu.dcache.overall_misses::total 1317304 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 16911598996 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 16911598996 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 85714857886 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 85714857886 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 102626456882 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 102626456882 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 102626456882 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 102626456882 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20794126 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20794126 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1320801 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1320801 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1320801 # number of overall misses +system.cpu.dcache.overall_misses::total 1320801 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17503667749 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17503667749 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 89467046923 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 89467046923 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 99750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 99750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 106970714672 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 106970714672 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 106970714672 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 106970714672 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20793852 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20793852 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 35407503 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 35407503 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 35407503 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 35407503 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012899 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.012899 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071790 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.071790 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.016393 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.016393 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037204 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037204 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037204 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037204 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63052.398248 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63052.398248 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81704.086008 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81704.086008 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77906.433809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77906.433809 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77906.433809 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 6293239 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 254 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146230 # number of cycles access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 64 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 64 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 35407229 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 35407229 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 35407229 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 35407229 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012928 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.012928 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071988 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.071988 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.015625 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.015625 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037303 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037303 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037303 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037303 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65113.693513 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 65113.693513 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 85046.014885 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 85046.014885 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 99750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 99750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 80989.274442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 80989.274442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 80989.274442 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 6831456 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 275 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 88055 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.036579 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 127 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 77.581693 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 137.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168920 # number of writebacks -system.cpu.dcache.writebacks::total 168920 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206147 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 206147 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 905681 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 905681 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1111828 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1111828 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1111828 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1111828 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62068 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62068 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143408 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143408 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 168921 # number of writebacks +system.cpu.dcache.writebacks::total 168921 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 206754 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 206754 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 908590 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 908590 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1115344 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1115344 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1115344 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1115344 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62063 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 62063 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143394 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143394 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 205476 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 205476 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 205476 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 205476 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3016288253 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3016288253 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13368781676 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13368781676 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16385069929 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16385069929 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16385069929 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 16385069929 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 205457 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 205457 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 205457 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 205457 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3191920501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3191920501 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 14187677704 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 14187677704 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 97750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 97750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17379598205 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17379598205 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17379598205 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 17379598205 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002985 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002985 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009813 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.016393 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.016393 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.015625 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.015625 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.005803 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005803 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005803 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48596.511133 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48596.511133 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93222.007670 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93222.007670 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 79742.013320 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 79742.013320 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51430.328875 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51430.328875 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98941.920192 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98941.920192 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 97750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 97750 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84589.954127 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84589.954127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84589.954127 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84589.954127 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 93674 # number of replacements -system.cpu.icache.tags.tagsinuse 1918.313943 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 13810732 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 95722 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 144.279601 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18796346250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1918.313943 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.936677 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.936677 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 92948 # number of replacements +system.cpu.icache.tags.tagsinuse 1916.254210 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 13805160 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 94996 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 145.323593 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 19026930250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 1916.254210 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.935671 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.935671 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 1489 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 370 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1478 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 379 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 27934642 # Number of tag accesses -system.cpu.icache.tags.data_accesses 27934642 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 13810732 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 13810732 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 13810732 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 13810732 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 13810732 # number of overall hits -system.cpu.icache.overall_hits::total 13810732 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 108728 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 108728 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 108728 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 108728 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 108728 # number of overall misses -system.cpu.icache.overall_misses::total 108728 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2006428959 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2006428959 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2006428959 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2006428959 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2006428959 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2006428959 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 13919460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 13919460 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 13919460 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 13919460 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 13919460 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 13919460 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007811 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.007811 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.007811 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.007811 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.007811 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.007811 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18453.654615 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 18453.654615 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 18453.654615 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 18453.654615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 18453.654615 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 18453.654615 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1061 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 27921160 # Number of tag accesses +system.cpu.icache.tags.data_accesses 27921160 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 13805160 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 13805160 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 13805160 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 13805160 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 13805160 # number of overall hits +system.cpu.icache.overall_hits::total 13805160 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 107922 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 107922 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 107922 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 107922 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 107922 # number of overall misses +system.cpu.icache.overall_misses::total 107922 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2071977734 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2071977734 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2071977734 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2071977734 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2071977734 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2071977734 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 13913082 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 13913082 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 13913082 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 13913082 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 13913082 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 13913082 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.007757 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.007757 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.007757 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.007757 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.007757 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.007757 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19198.844851 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 19198.844851 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 19198.844851 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 19198.844851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 19198.844851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 19198.844851 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 448 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 16 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 66.312500 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 44.800000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 13005 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 13005 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 13005 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 13005 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 13005 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 13005 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 95723 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 95723 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 95723 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 95723 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 95723 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 95723 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1546277535 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1546277535 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1546277535 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1546277535 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1546277535 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1546277535 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006877 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.006877 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006877 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.006877 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16153.667718 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16153.667718 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16153.667718 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 16153.667718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16153.667718 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 16153.667718 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 12925 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 12925 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 12925 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 12925 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 12925 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 12925 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 94997 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 94997 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 94997 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 94997 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 94997 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 94997 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1636224764 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1636224764 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1636224764 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1636224764 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1636224764 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1636224764 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006828 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006828 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006828 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.006828 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006828 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.006828 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17223.962483 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17223.962483 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17223.962483 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 17223.962483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17223.962483 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 17223.962483 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 132323 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30650.354019 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 162059 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 164389 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.985826 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 30601.222528 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 161333 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 164386 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.981428 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26718.517593 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2110.418463 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1821.417963 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.815384 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064405 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.055585 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.935375 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 32066 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3005 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28611 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 209 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 58 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978577 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4068759 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4068759 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 88110 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 34237 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 122347 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 168920 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 168920 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 12623 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 12623 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 88110 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 46860 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 134970 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 88110 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 46860 # number of overall hits -system.cpu.l2cache.overall_hits::total 134970 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 7613 # number of ReadReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 26658.229296 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2102.973655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1840.019577 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.813545 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064178 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.056153 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.933875 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 32063 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2820 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 28790 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 228 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 57 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978485 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4062789 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4062789 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 87377 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34233 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 121610 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 168921 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 168921 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 12614 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 12614 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 87377 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 46847 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 134224 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 87377 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 46847 # number of overall hits +system.cpu.l2cache.overall_hits::total 134224 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 7620 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 27830 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 35443 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130787 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130787 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 7613 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 158617 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 166230 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 7613 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 158617 # number of overall misses -system.cpu.l2cache.overall_misses::total 166230 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 568819250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2608707000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3177526250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13094816500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 13094816500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 568819250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 15703523500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16272342750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 568819250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 15703523500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16272342750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 95723 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62067 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 157790 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 168920 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 168920 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 143410 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 143410 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 95723 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 205477 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 301200 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 95723 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 205477 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 301200 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.079532 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448386 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.224621 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911980 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911980 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.079532 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771945 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.551892 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.079532 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771945 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.551892 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74716.833049 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 93737.226015 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 89651.729538 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 100123.227079 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 100123.227079 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74716.833049 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 99002.777130 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 97890.529688 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74716.833049 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 99002.777130 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 97890.529688 # average overall miss latency +system.cpu.l2cache.ReadReq_misses::total 35450 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 130781 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 130781 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 7620 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 158611 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 166231 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 7620 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 158611 # number of overall misses +system.cpu.l2cache.overall_misses::total 166231 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 623216750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2766024500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3389241250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13898935250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 13898935250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 623216750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 16664959750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 17288176500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 623216750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 16664959750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 17288176500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 94997 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 62063 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 157060 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 168921 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 168921 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 143395 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 143395 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 94997 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 205458 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 300455 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 94997 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 205458 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 300455 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.080213 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.448415 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.225710 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.912033 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.912033 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.080213 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771987 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.553264 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.080213 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771987 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.553264 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81786.975066 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 99390.028746 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 95606.241185 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106276.410564 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106276.410564 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81786.975066 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 105068.121063 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 104000.917398 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81786.975066 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 105068.121063 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 104000.917398 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -949,105 +946,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 114006 # number of writebacks -system.cpu.l2cache.writebacks::total 114006 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7613 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 114013 # number of writebacks +system.cpu.l2cache.writebacks::total 114013 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7620 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 35443 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130787 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130787 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 7613 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158617 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 166230 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 7613 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158617 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 166230 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 472609250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2266008500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2738617750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11494650500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11494650500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 472609250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 13760659000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14233268250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 472609250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 13760659000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14233268250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448386 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.224621 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911980 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.551892 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.079532 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771945 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.551892 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62079.239459 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 81423.230327 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77268.226448 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 87888.326057 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 87888.326057 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62079.239459 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 86753.998626 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85623.944234 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::total 35450 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130781 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130781 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 7620 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158611 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 166231 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 7620 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158611 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 166231 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 527900750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2422370000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2950270750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 12290499750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 12290499750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 527900750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14712869750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15240770500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 527900750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14712869750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15240770500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.448415 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.225710 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.912033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.912033 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.553264 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.080213 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771987 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.553264 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69278.313648 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 87041.681639 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 83223.434415 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93977.716564 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93977.716564 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69278.313648 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 92760.714894 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91684.285723 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 157790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 157789 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168920 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 143410 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 143410 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 191445 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579874 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 771319 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6126208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23961408 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 30087616 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 157060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 157059 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 168921 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 143395 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 143395 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 189993 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 579837 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 769830 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 6079744 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23960256 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 30040000 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 470120 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 469376 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 470120 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 469376 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 470120 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 403980000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 469376 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 403609000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 144944965 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 0.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 321950247 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 143899236 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.6 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 325469999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 35442 # Transaction distribution -system.membus.trans_dist::ReadResp 35442 # Transaction distribution -system.membus.trans_dist::Writeback 114006 # Transaction distribution -system.membus.trans_dist::ReadExReq 130787 # Transaction distribution -system.membus.trans_dist::ReadExResp 130787 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 446464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17935040 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 35449 # Transaction distribution +system.membus.trans_dist::ReadResp 35449 # Transaction distribution +system.membus.trans_dist::Writeback 114013 # Transaction distribution +system.membus.trans_dist::ReadExReq 130781 # Transaction distribution +system.membus.trans_dist::ReadExResp 130781 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446473 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 446473 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17935552 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17935552 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 280235 # Request fanout histogram +system.membus.snoop_fanout::samples 280243 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 280235 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 280243 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 280235 # Request fanout histogram -system.membus.reqLayer0.occupancy 1235714000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 1525262750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.8 # Layer utilization (%) +system.membus.snoop_fanout::total 280243 # Request fanout histogram +system.membus.reqLayer0.occupancy 786749500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 865056500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 06edb9753..987ba828d 100644 --- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133635 # Number of seconds simulated -sim_ticks 133634727000 # Number of ticks simulated -final_tick 133634727000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133634 # Number of seconds simulated +sim_ticks 133634149500 # Number of ticks simulated +final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1471745 # Simulator instruction rate (inst/s) -host_op_rate 1471745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2226337698 # Simulator tick rate (ticks/s) -host_mem_usage 297712 # Number of bytes of host memory used -host_seconds 60.02 # Real time elapsed on the host +host_inst_rate 1329181 # Simulator instruction rate (inst/s) +host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2010669405 # Simulator tick rate (ticks/s) +host_mem_usage 301232 # Number of bytes of host memory used +host_seconds 66.46 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,41 +25,17 @@ system.physmem.num_reads::cpu.data 158389 # Nu system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3239397 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75855253 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 79094650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3239397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3239397 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54587966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54587966 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54587966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3239397 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75855253 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 133682617 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 34272 # Transaction distribution -system.membus.trans_dist::ReadResp 34272 # Transaction distribution -system.membus.trans_dist::Writeback 113982 # Transaction distribution -system.membus.trans_dist::ReadExReq 130881 # Transaction distribution -system.membus.trans_dist::ReadExResp 130881 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 279135 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 279135 # Request fanout histogram -system.membus.reqLayer0.occupancy 1190991000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 1486377000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 267269454 # number of cpu cycles simulated +system.cpu.numCycles 267268299 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267269454 # Number of busy cycles +system.cpu.num_busy_cycles 267268299 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched @@ -152,13 +128,120 @@ system.cpu.op_class::MemWrite 14620629 16.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction +system.cpu.dcache.tags.replacements 200248 # number of replacements +system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits +system.cpu.dcache.overall_hits::total 34685671 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses +system.cpu.dcache.overall_misses::total 204344 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945427000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1945427000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363527000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7363527000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9308954000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9308954000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9308954000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9308954000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks +system.cpu.dcache.writebacks::total 168375 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1854278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1854278000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7148160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7148160000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9002438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9002438000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1871.686406 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1871.686268 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686406 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686268 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id @@ -181,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1278112000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1278112000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1278112000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1278112000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1278112000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1278112000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1277887500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1277887500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1277887500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1277887500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1277887500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1277887500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -199,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16721.335496 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16721.335496 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16721.335496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16721.335496 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16721.335496 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16718.398399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16718.398399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -219,43 +302,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1125240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1125240000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1125240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1125240000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1125240000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 1125240000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1163233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 1163233500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1163233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 1163233500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1163233500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 1163233500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000864 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000864 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000864 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000864 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14721.335496 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14721.335496 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14721.335496 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 14721.335496 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15218.398399 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 15218.398399 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15218.398399 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 15218.398399 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 131235 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30728.810101 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30728.805700 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 142024 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 163291 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.869760 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27298.448351 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.507766 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853984 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.833083 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27298.442194 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1874.509533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1555.853974 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.833082 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.057205 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.047481 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.937769 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 32056 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9976 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 654 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21193 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses @@ -284,17 +367,17 @@ system.cpu.l2cache.demand_misses::total 165153 # nu system.cpu.l2cache.overall_misses::cpu.inst 6764 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 158389 # number of overall misses system.cpu.l2cache.overall_misses::total 165153 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 352084000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1430874000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1782958000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6805851000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6805851000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 352084000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8236725000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 8588809000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 352084000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8236725000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 8588809000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 355241500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1444303000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1799544500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6871263500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6871263500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 355241500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8315566500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 8670808000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 355241500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8315566500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 8670808000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses) @@ -319,17 +402,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.588194 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088492 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.775110 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.588194 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52052.631579 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52016.649702 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52023.751167 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.297981 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.297981 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52005.164908 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52052.631579 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52003.137844 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52005.164908 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.084046 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.084046 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.668150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.441159 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.909154 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.668150 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -351,17 +434,17 @@ system.cpu.l2cache.demand_mshr_misses::total 165153 system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 270916000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1100778000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1371694000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5235279000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5235279000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 270916000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6336057000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6606973000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 270916000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6336057000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6606973000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses @@ -373,125 +456,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40052.631579 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40016.649702 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40023.751167 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.297981 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.297981 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40052.631579 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40003.137844 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.164908 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.863631 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 936463000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863631 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 482 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3562 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 69984374 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 69984374 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20215872 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 14469799 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 34685671 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 34685671 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 34685671 # number of overall hits -system.cpu.dcache.overall_hits::total 34685671 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 60766 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 143578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 204344 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses -system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945752000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1945752000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363555000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7363555000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9309307000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9309307000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9309307000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9309307000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32020.406148 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32020.406148 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51286.095363 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51286.095363 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45557.036174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45557.036174 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45557.036174 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks -system.cpu.dcache.writebacks::total 168375 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 143578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1824220000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1824220000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7076399000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7076399000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8900619000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8900619000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8900619000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8900619000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30020.406148 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30020.406148 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49286.095363 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49286.095363 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43557.036174 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43557.036174 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution @@ -521,5 +497,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 114654000 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 34272 # Transaction distribution +system.membus.trans_dist::ReadResp 34272 # Transaction distribution +system.membus.trans_dist::Writeback 113982 # Transaction distribution +system.membus.trans_dist::ReadExReq 130881 # Transaction distribution +system.membus.trans_dist::ReadExResp 130881 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 279135 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 279135 # Request fanout histogram +system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt index b9814d1e2..20f3ef2c3 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt @@ -1,95 +1,95 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.057816 # Number of seconds simulated -sim_ticks 57815555000 # Number of ticks simulated -final_tick 57815555000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.058730 # Number of seconds simulated +sim_ticks 58730125500 # Number of ticks simulated +final_tick 58730125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 131971 # Simulator instruction rate (inst/s) -host_op_rate 168772 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107593052 # Simulator tick rate (ticks/s) -host_mem_usage 309228 # Number of bytes of host memory used -host_seconds 537.35 # Real time elapsed on the host +host_inst_rate 197162 # Simulator instruction rate (inst/s) +host_op_rate 252141 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 163284235 # Simulator tick rate (ticks/s) +host_mem_usage 321164 # Number of bytes of host memory used +host_seconds 359.68 # Real time elapsed on the host sim_insts 70915127 # Number of instructions simulated sim_ops 90690083 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 324480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7923328 # Number of bytes read from this memory -system.physmem.bytes_read::total 8247808 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 324480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 324480 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7923392 # Number of bytes read from this memory +system.physmem.bytes_read::total 8247744 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 5372864 # Number of bytes written to this memory system.physmem.bytes_written::total 5372864 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 5070 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 123802 # Number of read requests responded to by this memory -system.physmem.num_reads::total 128872 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 123803 # Number of read requests responded to by this memory +system.physmem.num_reads::total 128871 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83951 # Number of write requests responded to by this memory system.physmem.num_writes::total 83951 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 5612330 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 137044918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 142657249 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 5612330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 5612330 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 92931115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 92931115 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 92931115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 5612330 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 137044918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 235588364 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 128872 # Number of read requests accepted +system.physmem.bw_read::cpu.inst 5522753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 134911886 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140434639 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 5522753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 5522753 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 91483952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 91483952 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 91483952 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 5522753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 134911886 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 231918592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 128871 # Number of read requests accepted system.physmem.writeReqs 83951 # Number of write requests accepted -system.physmem.readBursts 128872 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 128871 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 83951 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 8247424 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 8247360 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue -system.physmem.bytesWritten 5370880 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 8247808 # Total read bytes from the system interface side +system.physmem.bytesWritten 5371136 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 8247744 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 5372864 # Total written bytes from the system interface side system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 8159 # Per bank write bursts -system.physmem.perBankRdBursts::1 8375 # Per bank write bursts -system.physmem.perBankRdBursts::2 8229 # Per bank write bursts +system.physmem.perBankRdBursts::1 8376 # Per bank write bursts +system.physmem.perBankRdBursts::2 8228 # Per bank write bursts system.physmem.perBankRdBursts::3 8171 # Per bank write bursts -system.physmem.perBankRdBursts::4 8320 # Per bank write bursts +system.physmem.perBankRdBursts::4 8319 # Per bank write bursts system.physmem.perBankRdBursts::5 8450 # Per bank write bursts system.physmem.perBankRdBursts::6 8088 # Per bank write bursts -system.physmem.perBankRdBursts::7 7970 # Per bank write bursts +system.physmem.perBankRdBursts::7 7969 # Per bank write bursts system.physmem.perBankRdBursts::8 8071 # Per bank write bursts system.physmem.perBankRdBursts::9 7640 # Per bank write bursts -system.physmem.perBankRdBursts::10 7820 # Per bank write bursts -system.physmem.perBankRdBursts::11 7830 # Per bank write bursts +system.physmem.perBankRdBursts::10 7818 # Per bank write bursts +system.physmem.perBankRdBursts::11 7832 # Per bank write bursts system.physmem.perBankRdBursts::12 7881 # Per bank write bursts system.physmem.perBankRdBursts::13 7879 # Per bank write bursts system.physmem.perBankRdBursts::14 7977 # Per bank write bursts -system.physmem.perBankRdBursts::15 8006 # Per bank write bursts -system.physmem.perBankWrBursts::0 5183 # Per bank write bursts +system.physmem.perBankRdBursts::15 8007 # Per bank write bursts +system.physmem.perBankWrBursts::0 5180 # Per bank write bursts system.physmem.perBankWrBursts::1 5376 # Per bank write bursts system.physmem.perBankWrBursts::2 5285 # Per bank write bursts system.physmem.perBankWrBursts::3 5155 # Per bank write bursts system.physmem.perBankWrBursts::4 5266 # Per bank write bursts system.physmem.perBankWrBursts::5 5517 # Per bank write bursts -system.physmem.perBankWrBursts::6 5194 # Per bank write bursts -system.physmem.perBankWrBursts::7 5048 # Per bank write bursts +system.physmem.perBankWrBursts::6 5197 # Per bank write bursts +system.physmem.perBankWrBursts::7 5050 # Per bank write bursts system.physmem.perBankWrBursts::8 5033 # Per bank write bursts -system.physmem.perBankWrBursts::9 5086 # Per bank write bursts -system.physmem.perBankWrBursts::10 5252 # Per bank write bursts +system.physmem.perBankWrBursts::9 5087 # Per bank write bursts +system.physmem.perBankWrBursts::10 5251 # Per bank write bursts system.physmem.perBankWrBursts::11 5143 # Per bank write bursts system.physmem.perBankWrBursts::12 5343 # Per bank write bursts system.physmem.perBankWrBursts::13 5363 # Per bank write bursts system.physmem.perBankWrBursts::14 5451 # Per bank write bursts -system.physmem.perBankWrBursts::15 5225 # Per bank write bursts +system.physmem.perBankWrBursts::15 5227 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 57815523000 # Total gap between requests +system.physmem.totGap 58730091000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 128872 # Read request sizes (log2) +system.physmem.readPktSize::6 128871 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -98,8 +98,8 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 83951 # Write request sizes (log2) system.physmem.rdQLenPdf::0 126560 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,24 +144,24 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 616 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 603 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5167 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 5167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 5178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 5172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 5292 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 5260 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 5248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 5669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5174 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 5189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 5236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 5228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5161 # What write queue length does an incoming req see system.physmem.wrQLenPdf::33 5 # What write queue length does an incoming req see system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see @@ -193,100 +193,98 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 354.194267 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 215.182491 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 335.610229 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12218 31.78% 31.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8019 20.86% 52.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4166 10.84% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2872 7.47% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2487 6.47% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1677 4.36% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1283 3.34% 85.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1207 3.14% 88.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4513 11.74% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38442 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5157 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.976343 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 360.782218 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 5154 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 38559 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 353.122851 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 215.043714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.345734 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12150 31.51% 31.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8188 21.23% 52.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4125 10.70% 63.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2946 7.64% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2498 6.48% 77.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1699 4.41% 81.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1309 3.39% 85.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1159 3.01% 88.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4485 11.63% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 38559 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5160 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.968217 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 360.537784 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 5158 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5157 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5157 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.273027 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.256397 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 0.767804 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4530 87.84% 87.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 6 0.12% 87.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 497 9.64% 97.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 105 2.04% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 11 0.21% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 3 0.06% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 2 0.04% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5157 # Writes before turning the bus around for reads -system.physmem.totQLat 1505377000 # Total ticks spent queuing -system.physmem.totMemAccLat 3921614500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 644330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11681.72 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5160 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.264341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.248462 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 0.748642 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4548 88.14% 88.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 7 0.14% 88.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 485 9.40% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 104 2.02% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 10 0.19% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.06% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5160 # Writes before turning the bus around for reads +system.physmem.totQLat 1533027250 # Total ticks spent queuing +system.physmem.totMemAccLat 3949246000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 644325000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11896.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30431.72 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 142.65 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 92.90 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 142.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 92.93 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30646.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 140.43 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 91.45 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 140.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 91.48 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.84 # Data bus utilization in percentage -system.physmem.busUtilRead 1.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes +system.physmem.busUtil 1.81 # Data bus utilization in percentage +system.physmem.busUtilRead 1.10 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.71 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.46 # Average write queue length when enqueuing -system.physmem.readRowHits 112203 # Number of row buffer hits during reads -system.physmem.writeRowHits 62134 # Number of row buffer hits during writes -system.physmem.readRowHitRate 87.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 74.01 # Row buffer hit rate for writes -system.physmem.avgGap 271660.13 # Average gap between requests -system.physmem.pageHitRate 81.92 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 150995880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 82388625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 512779800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 272315520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11724732990 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 24403046250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 40922317065 # Total energy per rank (pJ) -system.physmem_0.averagePower 707.837327 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 40469303500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem.avgWrQLen 23.44 # Average write queue length when enqueuing +system.physmem.readRowHits 112070 # Number of row buffer hits during reads +system.physmem.writeRowHits 62147 # Number of row buffer hits during writes +system.physmem.readRowHitRate 86.97 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.03 # Row buffer hit rate for writes +system.physmem.avgGap 275958.74 # Average gap between requests +system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 152069400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 82974375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 512499000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 272270160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 12264762105 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 24475931250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 41596065810 # Total energy per rank (pJ) +system.physmem_0.averagePower 708.329716 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 40585694500 # Time in different power states +system.physmem_0.memoryStateTime::REF 1960920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15413376500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16178034500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139625640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 76184625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 492086400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 271486080 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3776058000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11316053250 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 24761537250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 40833031245 # Total energy per rank (pJ) -system.physmem_1.averagePower 706.292941 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 41066657000 # Time in different power states -system.physmem_1.memoryStateTime::REF 1930500000 # Time in different power states +system.physmem_1.actEnergy 139308120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 76011375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 492024000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 271453680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3835559520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11655970470 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 25009959000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 41480286165 # Total energy per rank (pJ) +system.physmem_1.averagePower 706.358131 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 41477231750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1960920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14816189000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15286019500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 14822198 # Number of BP lookups -system.cpu.branchPred.condPredicted 9914609 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 394622 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9489453 # Number of BTB lookups -system.cpu.branchPred.BTBHits 6747157 # Number of BTB hits +system.cpu.branchPred.lookups 14827059 # Number of BP lookups +system.cpu.branchPred.condPredicted 9919255 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 395881 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9555564 # Number of BTB lookups +system.cpu.branchPred.BTBHits 6751205 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.101643 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1719210 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 70.652083 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1718768 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -406,89 +404,89 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 115631110 # number of cpu cycles simulated +system.cpu.numCycles 117460251 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70915127 # Number of instructions committed system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1144126 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1148249 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.630556 # CPI: cycles per instruction -system.cpu.ipc 0.613288 # IPC: instructions per cycle -system.cpu.tickCycles 96933125 # Number of cycles that the object actually ticked -system.cpu.idleCycles 18697985 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 156428 # number of replacements -system.cpu.dcache.tags.tagsinuse 4068.581764 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42664902 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 160524 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 265.785191 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 784159000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4068.581764 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.993306 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.993306 # Average percentage of cache occupancy +system.cpu.cpi 1.656350 # CPI: cycles per instruction +system.cpu.ipc 0.603737 # IPC: instructions per cycle +system.cpu.tickCycles 97003390 # Number of cycles that the object actually ticked +system.cpu.idleCycles 20456861 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 156434 # number of replacements +system.cpu.dcache.tags.tagsinuse 4067.721714 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42666461 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 160530 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 265.784969 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 833735250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4067.721714 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.993096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.993096 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 749 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 710 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3342 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 86014590 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 86014590 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22989229 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22989229 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 19643835 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 19643835 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 86017904 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 86017904 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22990876 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22990876 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 19643747 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 19643747 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42633064 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42633064 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42633064 # number of overall hits -system.cpu.dcache.overall_hits::total 42633064 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 56065 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 56065 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 206066 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 206066 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 262131 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 262131 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 262131 # number of overall misses -system.cpu.dcache.overall_misses::total 262131 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2147242437 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 15196521000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17343763437 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17343763437 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17343763437 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23045294 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23045294 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 42634623 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42634623 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42634623 # number of overall hits +system.cpu.dcache.overall_hits::total 42634623 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 56072 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56072 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 206154 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 206154 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 262226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 262226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 262226 # number of overall misses +system.cpu.dcache.overall_misses::total 262226 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2301185937 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2301185937 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 16676998250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 16676998250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18978184187 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18978184187 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18978184187 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18978184187 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23046948 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23046948 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42895195 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42895195 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42895195 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42895195 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 42896849 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42896849 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42896849 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42896849 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002433 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.002433 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.010381 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.006111 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.006111 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.006111 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.006111 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38299.160564 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38299.160564 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73745.892093 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73745.892093 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 66164.488126 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 66164.488126 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010386 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.010386 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.006113 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.006113 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.006113 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.006113 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 41039.840509 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 41039.840509 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80895.826664 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 80895.826664 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 72373.388554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 72373.388554 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 72373.388554 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -497,32 +495,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128441 # number of writebacks -system.cpu.dcache.writebacks::total 128441 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2577 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2577 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99030 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 99030 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 101607 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 101607 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 101607 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 101607 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53488 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53488 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107036 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 107036 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 160524 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 160524 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 160524 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1987609313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1987609313 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7609976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7609976000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9597585313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9597585313 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9597585313 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9597585313 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 128445 # number of writebacks +system.cpu.dcache.writebacks::total 128445 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2576 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 2576 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 99120 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 99120 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 101696 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 101696 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 101696 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 101696 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53496 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53496 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 160530 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 160530 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 160530 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 160530 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2163468813 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2163468813 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8402400750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8402400750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10565869563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10565869563 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10565869563 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10565869563 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002321 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -531,68 +529,68 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003742 system.cpu.dcache.demand_mshr_miss_rate::total 0.003742 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 37159.910877 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71097.350424 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59789.098907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59789.098907 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40441.693080 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40441.693080 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78502.165200 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78502.165200 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65818.660456 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65818.660456 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 42682 # number of replacements -system.cpu.icache.tags.tagsinuse 1858.929385 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 25083355 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 44724 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 560.847755 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 42774 # number of replacements +system.cpu.icache.tags.tagsinuse 1856.910000 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 25093452 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 44816 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 559.921724 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1858.929385 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.907680 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.907680 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1856.910000 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.906694 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.906694 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 87 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 803 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1117 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 730 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1192 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 50300884 # Number of tag accesses -system.cpu.icache.tags.data_accesses 50300884 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 25083355 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 25083355 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 25083355 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 25083355 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 25083355 # number of overall hits -system.cpu.icache.overall_hits::total 25083355 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 44725 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 44725 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 44725 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 44725 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 44725 # number of overall misses -system.cpu.icache.overall_misses::total 44725 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 895927489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 895927489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 895927489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 895927489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 895927489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 895927489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 25128080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 25128080 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 25128080 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 25128080 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 25128080 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 25128080 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001780 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.001780 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.001780 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.001780 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.001780 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.001780 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20031.917026 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 20031.917026 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 20031.917026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 20031.917026 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 20031.917026 # average overall miss latency +system.cpu.icache.tags.tag_accesses 50321354 # Number of tag accesses +system.cpu.icache.tags.data_accesses 50321354 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 25093452 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 25093452 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 25093452 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 25093452 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 25093452 # number of overall hits +system.cpu.icache.overall_hits::total 25093452 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 44817 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 44817 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 44817 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 44817 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 44817 # number of overall misses +system.cpu.icache.overall_misses::total 44817 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 937886990 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 937886990 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 937886990 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 937886990 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 937886990 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 937886990 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 25138269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 25138269 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 25138269 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 25138269 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 25138269 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 25138269 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001783 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.001783 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.001783 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.001783 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.001783 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.001783 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20927.036392 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 20927.036392 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 20927.036392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 20927.036392 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 20927.036392 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -601,123 +599,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44725 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 44725 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 44725 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 44725 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 44725 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 44725 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 804564511 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 804564511 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 804564511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 804564511 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 804564511 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 804564511 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001780 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.001780 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 17989.145020 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 17989.145020 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 17989.145020 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 17989.145020 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44817 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 44817 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 44817 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 44817 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 44817 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 44817 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 868759010 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 868759010 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 868759010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 868759010 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 868759010 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 868759010 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001783 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.001783 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001783 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.001783 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19384.586429 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19384.586429 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19384.586429 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 19384.586429 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 95733 # number of replacements -system.cpu.l2cache.tags.tagsinuse 29936.958460 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 99697 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 126852 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.785932 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 29885.598621 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 99802 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 126851 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.786766 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26707.516998 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1563.058609 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1666.382853 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.815049 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047701 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.050854 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.913603 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 31119 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1137 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9778 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 19493 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 583 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949677 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2903408 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2903408 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 39644 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31904 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 71548 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128441 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 128441 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 4755 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 4755 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 39644 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 76303 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 39644 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits -system.cpu.l2cache.overall_hits::total 76303 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 5081 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21584 # number of ReadReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 26636.535052 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1559.339588 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1689.723980 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.812883 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047587 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.051566 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.912036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1015 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 20264 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 591 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 2904221 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 2904221 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 39738 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 31910 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 71648 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 128445 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 128445 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 4754 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 4754 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 39738 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 36664 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 76402 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 39738 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 36664 # number of overall hits +system.cpu.l2cache.overall_hits::total 76402 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 5079 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 21586 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 26665 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 102281 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 102281 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 5081 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 123865 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 128946 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 5081 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 123865 # number of overall misses -system.cpu.l2cache.overall_misses::total 128946 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 363309000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1614754750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1978063750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7455355000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7455355000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 363309000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9070109750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9433418750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 363309000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9070109750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9433418750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 44725 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 53488 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 98213 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 128441 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 128441 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 107036 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 107036 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 44725 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 160524 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 205249 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 44725 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 160524 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 205249 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113605 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403530 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.271502 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955576 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.955576 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113605 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.771629 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.628242 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113605 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.771629 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.628242 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71503.444204 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74812.581079 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74182.027002 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72890.908380 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72890.908380 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73157.901370 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71503.444204 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73225.767973 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73157.901370 # average overall miss latency +system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 5079 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 123866 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 128945 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 5079 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 123866 # number of overall misses +system.cpu.l2cache.overall_misses::total 128945 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 406663000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1774587250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2181250250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8245411750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8245411750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 406663000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10019999000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 10426662000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 406663000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10019999000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 10426662000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 44817 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 53496 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 98313 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 128445 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 128445 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 44817 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 160530 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 205347 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 44817 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 160530 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 205347 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113328 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403507 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.271226 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955584 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.955584 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113328 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.771607 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.627937 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113328 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.771607 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.627937 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80067.532979 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82210.101455 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81801.997000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80616.071079 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80616.071079 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80067.532979 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80893.861108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80861.312963 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80067.532979 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80893.861108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80861.312963 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,107 +735,105 @@ system.cpu.l2cache.demand_mshr_hits::total 73 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 63 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5071 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21521 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5069 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21523 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 26592 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 102281 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 5071 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 123802 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 128873 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 5071 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 123802 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 128873 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 298810000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1336295500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1635105500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6164329000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6164329000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 298810000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7500624500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 7799434500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 298810000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7500624500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 7799434500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402352 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270758 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955576 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955576 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.627886 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113382 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771237 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.627886 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58925.261290 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62092.630454 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61488.624398 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60268.564054 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60268.564054 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58925.261290 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60585.648859 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60520.314573 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 5069 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123803 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 128872 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 5069 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123803 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 128872 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 342505250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1501079000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1843584250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6966637250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6966637250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 342505250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8467716250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8810221500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 342505250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8467716250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8810221500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402329 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270483 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955584 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955584 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.627582 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113104 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771214 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.627582 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67568.603275 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69743.019096 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69328.529257 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68113.387270 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68113.387270 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67568.603275 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68396.696768 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68364.124868 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 98213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 98212 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128441 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 107036 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 107036 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89449 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449489 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 538938 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2862336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18493760 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 21356096 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 98313 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 98312 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 128445 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89633 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449505 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 539138 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2868224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18494400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 21362624 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 333690 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 333792 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 333690 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 333792 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 333690 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 295286000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 333792 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 295341000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 68043489 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 68175990 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 268450687 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 268644937 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) system.membus.trans_dist::ReadReq 26591 # Transaction distribution system.membus.trans_dist::ReadResp 26591 # Transaction distribution system.membus.trans_dist::Writeback 83951 # Transaction distribution -system.membus.trans_dist::ReadExReq 102281 # Transaction distribution -system.membus.trans_dist::ReadExResp 102281 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 341695 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620672 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13620672 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 102280 # Transaction distribution +system.membus.trans_dist::ReadExResp 102280 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341693 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 341693 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13620608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 212823 # Request fanout histogram +system.membus.snoop_fanout::samples 212822 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 212823 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 212822 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 212823 # Request fanout histogram -system.membus.reqLayer0.occupancy 929408000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1213401000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.membus.snoop_fanout::total 212822 # Request fanout histogram +system.membus.reqLayer0.occupancy 579596500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 680391500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt index 6394c9beb..c55c80533 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.033020 # Number of seconds simulated -sim_ticks 33019504000 # Number of ticks simulated -final_tick 33019504000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.033359 # Number of seconds simulated +sim_ticks 33359312000 # Number of ticks simulated +final_tick 33359312000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123822 # Simulator instruction rate (inst/s) -host_op_rate 158353 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 57659893 # Simulator tick rate (ticks/s) -host_mem_usage 322352 # Number of bytes of host memory used -host_seconds 572.66 # Real time elapsed on the host +host_inst_rate 125450 # Simulator instruction rate (inst/s) +host_op_rate 160435 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59019201 # Simulator tick rate (ticks/s) +host_mem_usage 322444 # Number of bytes of host memory used +host_seconds 565.23 # Real time elapsed on the host sim_insts 70907629 # Number of instructions simulated sim_ops 90682584 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 588736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 2517376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 6201600 # Number of bytes read from this memory -system.physmem.bytes_read::total 9307712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 588736 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 588736 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 6262016 # Number of bytes written to this memory -system.physmem.bytes_written::total 6262016 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 39334 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 96900 # Number of read requests responded to by this memory -system.physmem.num_reads::total 145433 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 97844 # Number of write requests responded to by this memory -system.physmem.num_writes::total 97844 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 17829947 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 76239062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 187816268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 281885276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 17829947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 17829947 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 189645974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 189645974 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 189645974 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 17829947 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 76239062 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 187816268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 471531250 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 145433 # Number of read requests accepted -system.physmem.writeReqs 97844 # Number of write requests accepted -system.physmem.readBursts 145433 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 97844 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9300480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7232 # Total number of bytes read from write queue -system.physmem.bytesWritten 6260352 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9307712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6262016 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 113 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 593600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 2515776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 6204544 # Number of bytes read from this memory +system.physmem.bytes_read::total 9313920 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 593600 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 593600 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 6264768 # Number of bytes written to this memory +system.physmem.bytes_written::total 6264768 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 9275 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 39309 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 96946 # Number of read requests responded to by this memory +system.physmem.num_reads::total 145530 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 97887 # Number of write requests responded to by this memory +system.physmem.num_writes::total 97887 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 17794132 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75414505 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 185991366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 279200003 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 17794132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 17794132 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 187796679 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 187796679 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 187796679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 17794132 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75414505 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 185991366 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 466996681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 145530 # Number of read requests accepted +system.physmem.writeReqs 97887 # Number of write requests accepted +system.physmem.readBursts 145530 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 97887 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9306560 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7360 # Total number of bytes read from write queue +system.physmem.bytesWritten 6263296 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9313920 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 6264768 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 115 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 6 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9146 # Per bank write bursts -system.physmem.perBankRdBursts::1 9381 # Per bank write bursts -system.physmem.perBankRdBursts::2 9349 # Per bank write bursts -system.physmem.perBankRdBursts::3 9489 # Per bank write bursts -system.physmem.perBankRdBursts::4 9691 # Per bank write bursts -system.physmem.perBankRdBursts::5 9742 # Per bank write bursts -system.physmem.perBankRdBursts::6 9065 # Per bank write bursts -system.physmem.perBankRdBursts::7 9033 # Per bank write bursts -system.physmem.perBankRdBursts::8 9160 # Per bank write bursts -system.physmem.perBankRdBursts::9 8585 # Per bank write bursts -system.physmem.perBankRdBursts::10 8818 # Per bank write bursts -system.physmem.perBankRdBursts::11 8754 # Per bank write bursts -system.physmem.perBankRdBursts::12 8666 # Per bank write bursts -system.physmem.perBankRdBursts::13 8713 # Per bank write bursts -system.physmem.perBankRdBursts::14 8726 # Per bank write bursts -system.physmem.perBankRdBursts::15 9002 # Per bank write bursts -system.physmem.perBankWrBursts::0 5993 # Per bank write bursts -system.physmem.perBankWrBursts::1 6194 # Per bank write bursts -system.physmem.perBankWrBursts::2 6159 # Per bank write bursts -system.physmem.perBankWrBursts::3 6198 # Per bank write bursts -system.physmem.perBankWrBursts::4 6133 # Per bank write bursts -system.physmem.perBankWrBursts::5 6325 # Per bank write bursts -system.physmem.perBankWrBursts::6 6074 # Per bank write bursts -system.physmem.perBankWrBursts::7 6046 # Per bank write bursts -system.physmem.perBankWrBursts::8 6012 # Per bank write bursts -system.physmem.perBankWrBursts::9 6139 # Per bank write bursts -system.physmem.perBankWrBursts::10 6243 # Per bank write bursts -system.physmem.perBankWrBursts::11 5934 # Per bank write bursts -system.physmem.perBankWrBursts::12 6049 # Per bank write bursts -system.physmem.perBankWrBursts::13 6103 # Per bank write bursts -system.physmem.perBankWrBursts::14 6164 # Per bank write bursts -system.physmem.perBankWrBursts::15 6052 # Per bank write bursts +system.physmem.perBankRdBursts::0 9160 # Per bank write bursts +system.physmem.perBankRdBursts::1 9419 # Per bank write bursts +system.physmem.perBankRdBursts::2 9305 # Per bank write bursts +system.physmem.perBankRdBursts::3 9483 # Per bank write bursts +system.physmem.perBankRdBursts::4 9789 # Per bank write bursts +system.physmem.perBankRdBursts::5 9711 # Per bank write bursts +system.physmem.perBankRdBursts::6 9074 # Per bank write bursts +system.physmem.perBankRdBursts::7 9074 # Per bank write bursts +system.physmem.perBankRdBursts::8 9205 # Per bank write bursts +system.physmem.perBankRdBursts::9 8628 # Per bank write bursts +system.physmem.perBankRdBursts::10 8849 # Per bank write bursts +system.physmem.perBankRdBursts::11 8741 # Per bank write bursts +system.physmem.perBankRdBursts::12 8642 # Per bank write bursts +system.physmem.perBankRdBursts::13 8695 # Per bank write bursts +system.physmem.perBankRdBursts::14 8691 # Per bank write bursts +system.physmem.perBankRdBursts::15 8949 # Per bank write bursts +system.physmem.perBankWrBursts::0 5976 # Per bank write bursts +system.physmem.perBankWrBursts::1 6255 # Per bank write bursts +system.physmem.perBankWrBursts::2 6149 # Per bank write bursts +system.physmem.perBankWrBursts::3 6169 # Per bank write bursts +system.physmem.perBankWrBursts::4 6151 # Per bank write bursts +system.physmem.perBankWrBursts::5 6334 # Per bank write bursts +system.physmem.perBankWrBursts::6 6086 # Per bank write bursts +system.physmem.perBankWrBursts::7 6007 # Per bank write bursts +system.physmem.perBankWrBursts::8 5979 # Per bank write bursts +system.physmem.perBankWrBursts::9 6153 # Per bank write bursts +system.physmem.perBankWrBursts::10 6241 # Per bank write bursts +system.physmem.perBankWrBursts::11 5938 # Per bank write bursts +system.physmem.perBankWrBursts::12 6061 # Per bank write bursts +system.physmem.perBankWrBursts::13 6105 # Per bank write bursts +system.physmem.perBankWrBursts::14 6219 # Per bank write bursts +system.physmem.perBankWrBursts::15 6041 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 33019298500 # Total gap between requests +system.physmem.totGap 33359040500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 145433 # Read request sizes (log2) +system.physmem.readPktSize::6 145530 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 97844 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 47136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 46826 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17078 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9801 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6398 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5373 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4750 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4278 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3551 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 94 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 5 # What read queue length does an incoming req see +system.physmem.writePktSize::6 97887 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 42093 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 51689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 18360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5319 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4669 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3562 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see @@ -148,33 +148,33 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1935 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 5608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 5930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 6581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7838 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6437 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1920 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3444 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4432 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5283 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5659 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7427 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6411 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see @@ -197,102 +197,104 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 88783 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.237151 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 110.501041 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 239.251674 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 52191 58.78% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 22671 25.54% 84.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4463 5.03% 89.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 1678 1.89% 91.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 979 1.10% 92.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 876 0.99% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 737 0.83% 94.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 796 0.90% 95.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4392 4.95% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 88783 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5909 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.589101 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 21.077809 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 187.247746 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-511 5908 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 88927 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.072858 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 110.491943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 238.713124 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 52339 58.86% 58.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 22656 25.48% 84.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4441 4.99% 89.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 1741 1.96% 91.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1037 1.17% 92.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 849 0.95% 93.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 689 0.77% 94.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 765 0.86% 95.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4410 4.96% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88927 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5911 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 24.598207 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 21.088924 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 187.219466 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-511 5910 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::14336-14847 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5909 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.554070 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.510446 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.278697 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 4738 80.18% 80.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 25 0.42% 80.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 725 12.27% 92.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 165 2.79% 95.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 107 1.81% 97.48% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 76 1.29% 98.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 36 0.61% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 24 0.41% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 8 0.14% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 4 0.07% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5909 # Writes before turning the bus around for reads -system.physmem.totQLat 7598607995 # Total ticks spent queuing -system.physmem.totMemAccLat 10323357995 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 726600000 # Total ticks spent in databus transfers -system.physmem.avgQLat 52288.80 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5911 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5911 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.556251 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.512708 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.281856 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 4715 79.77% 79.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 33 0.56% 80.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 741 12.54% 92.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 193 3.27% 96.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 104 1.76% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 53 0.90% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 34 0.58% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 17 0.29% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.19% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 4 0.07% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5911 # Writes before turning the bus around for reads +system.physmem.totQLat 7478329771 # Total ticks spent queuing +system.physmem.totMemAccLat 10204861021 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 727075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 51427.50 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 71038.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 281.67 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 189.60 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 281.89 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 189.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 70177.50 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 278.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 187.75 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 279.20 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 187.80 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.68 # Data bus utilization in percentage -system.physmem.busUtilRead 2.20 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.48 # Data bus utilization in percentage for writes +system.physmem.busUtil 3.65 # Data bus utilization in percentage +system.physmem.busUtilRead 2.18 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.61 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.57 # Average write queue length when enqueuing -system.physmem.readRowHits 118226 # Number of row buffer hits during reads -system.physmem.writeRowHits 36119 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.36 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 36.91 # Row buffer hit rate for writes -system.physmem.avgGap 135727.17 # Average gap between requests -system.physmem.pageHitRate 63.47 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 342362160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 186804750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 583720800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 318193920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 11787255720 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 9468687000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 24843318750 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.509165 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15653624306 # Time in different power states -system.physmem_0.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing +system.physmem.readRowHits 118188 # Number of row buffer hits during reads +system.physmem.writeRowHits 36158 # Number of row buffer hits during writes +system.physmem.readRowHitRate 81.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 36.94 # Row buffer hit rate for writes +system.physmem.avgGap 137044.83 # Average gap between requests +system.physmem.pageHitRate 63.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 343556640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 187456500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 584859600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 318226320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 11869125390 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 9602419500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 25084314990 # Total energy per rank (pJ) +system.physmem_0.averagePower 752.005565 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 15876395968 # Time in different power states +system.physmem_0.memoryStateTime::REF 1113840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 16257963444 # Time in different power states +system.physmem_0.memoryStateTime::ACT 16366332782 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328376160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179173500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 549010800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 315414000 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 2156294400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 11313288180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 9884473500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 24726030540 # Total energy per rank (pJ) -system.physmem_1.averagePower 748.955517 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 16351310453 # Time in different power states -system.physmem_1.memoryStateTime::REF 1102400000 # Time in different power states +system.physmem_1.actEnergy 328413960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179194125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 548948400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 315725040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 2178671040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 11416289175 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 9999644250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 24966885990 # Total energy per rank (pJ) +system.physmem_1.averagePower 748.485148 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 16542747198 # Time in different power states +system.physmem_1.memoryStateTime::REF 1113840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15560341797 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15699981552 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 17204705 # Number of BP lookups -system.cpu.branchPred.condPredicted 11516912 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 648025 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9345879 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7673903 # Number of BTB hits +system.cpu.branchPred.lookups 17207670 # Number of BP lookups +system.cpu.branchPred.condPredicted 11518844 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 648137 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9345275 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7675164 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 82.110019 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1872530 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 101564 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 82.128819 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1873048 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 101561 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -411,234 +413,234 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 66039009 # number of cpu cycles simulated +system.cpu.numCycles 66718625 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4981802 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 88178088 # Number of instructions fetch has processed -system.cpu.fetch.Branches 17204705 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9546433 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 59635234 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1322107 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 4931 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 10977 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 22758925 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 68935 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 65294039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.709071 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.292735 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 4981358 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 88194612 # Number of instructions fetch has processed +system.cpu.fetch.Branches 17207670 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9548212 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 60206161 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1322349 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 5969 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 25 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13195 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 22764676 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 68972 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 65867882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.694526 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.296864 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19515211 29.89% 29.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 8274054 12.67% 42.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 9196195 14.08% 56.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 28308579 43.36% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20086614 30.50% 30.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 8263984 12.55% 43.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 9201027 13.97% 57.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 28316257 42.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 65294039 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.260523 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.335242 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8590503 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 19016582 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 31530881 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 5663983 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 492090 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3178633 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 170869 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 101389113 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3042046 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 492090 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13367671 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5222790 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 763292 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 32193949 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 13254247 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 99181436 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 981589 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3720885 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 53337 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 4029509 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 5185175 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 103906436 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 457606733 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 115387380 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 65867882 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.257914 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.321889 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8560400 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 19609685 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 31575881 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 5629864 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 492052 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3179520 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171002 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 101414286 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3048471 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 492052 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13316863 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5341740 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 787564 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 32235527 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 13694136 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 99203918 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 983561 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3871797 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 66642 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 4317748 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 5384160 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 103925780 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 457714134 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 115415425 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 550 # Number of floating rename lookups system.cpu.rename.CommittedMaps 93629226 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10277210 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18665 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 18651 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12765420 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 24319642 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21987038 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1312197 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2209009 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 98145273 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34526 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 94858951 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 691771 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 7393055 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 20168064 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 740 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 65294039 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.452796 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.148580 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 10296554 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18659 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 18650 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12695794 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 24322207 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21994092 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1403605 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2365005 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 98166864 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 34522 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 94891849 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 694587 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 7414208 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 20250811 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 736 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 65867882 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.440639 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.150059 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 17159256 26.28% 26.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 17193875 26.33% 52.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 17194261 26.33% 78.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 11711028 17.94% 96.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 2034625 3.12% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 994 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17597825 26.72% 26.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 17436284 26.47% 53.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 17101122 25.96% 79.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 11678255 17.73% 96.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 2053424 3.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 972 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 65294039 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 65867882 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6670808 22.11% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 41 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.11% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 11293243 37.42% 59.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 12213472 40.47% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6717330 22.42% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 38 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 22.42% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 11201861 37.39% 59.81% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 12041280 40.19% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 49494148 52.18% 52.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 89879 0.09% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24035201 25.34% 77.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21239685 22.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 49497025 52.16% 52.16% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 89873 0.09% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 31 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.26% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24063293 25.36% 77.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21241620 22.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 94858951 # Type of FU issued -system.cpu.iq.rate 1.436408 # Inst issue rate -system.cpu.iq.fu_busy_cnt 30177564 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.318131 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 285881069 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 105584154 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 93463006 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 94891849 # Type of FU issued +system.cpu.iq.rate 1.422269 # Inst issue rate +system.cpu.iq.fu_busy_cnt 29960509 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.315733 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 286306469 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 105626883 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 93465742 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 207 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 248 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 57 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 125036397 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 124852240 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 118 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1353483 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 1363033 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1453380 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2068 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11797 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1431300 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1455945 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2039 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11790 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1438354 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 120407 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 169543 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 142055 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 176720 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 492090 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 617243 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 370435 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 98189662 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 492052 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 623106 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 467581 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 98211247 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 24319642 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21987038 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 18606 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1603 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 365951 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 11797 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 302833 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 221503 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 524336 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 93942350 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 23727911 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 916601 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 24322207 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21994092 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 18602 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 1655 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 463043 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 11790 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 303168 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 221686 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 524854 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 93974313 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 23756309 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 917536 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 9863 # number of nop insts executed -system.cpu.iew.exec_refs 44710370 # number of memory reference insts executed -system.cpu.iew.exec_branches 14251746 # Number of branches executed -system.cpu.iew.exec_stores 20982459 # Number of stores executed -system.cpu.iew.exec_rate 1.422528 # Inst execution rate -system.cpu.iew.wb_sent 93584307 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 93463063 # cumulative count of insts written-back -system.cpu.iew.wb_producers 44927637 # num instructions producing a value -system.cpu.iew.wb_consumers 76497349 # num instructions consuming a value +system.cpu.iew.exec_nop 9861 # number of nop insts executed +system.cpu.iew.exec_refs 44740784 # number of memory reference insts executed +system.cpu.iew.exec_branches 14252664 # Number of branches executed +system.cpu.iew.exec_stores 20984475 # Number of stores executed +system.cpu.iew.exec_rate 1.408517 # Inst execution rate +system.cpu.iew.wb_sent 93587501 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 93465799 # cumulative count of insts written-back +system.cpu.iew.wb_producers 44986533 # num instructions producing a value +system.cpu.iew.wb_consumers 76576760 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.415271 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.587310 # average fanout of values written-back +system.cpu.iew.wb_rate 1.400895 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.587470 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6519180 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6538748 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 479062 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 64238392 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.411744 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.175817 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 479015 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 64808930 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.399315 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.164562 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 30786432 47.93% 47.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 16709618 26.01% 73.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 4274980 6.65% 80.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4124415 6.42% 87.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1949899 3.04% 90.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1296449 2.02% 92.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 706597 1.10% 93.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 586126 0.91% 94.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3803876 5.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 31222194 48.18% 48.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 16795938 25.92% 74.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 4338232 6.69% 80.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4159188 6.42% 87.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1936724 2.99% 90.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1268170 1.96% 92.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 738929 1.14% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 579590 0.89% 94.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3769965 5.82% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 64238392 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 64808930 # Number of insts commited each cycle system.cpu.commit.committedInsts 70913181 # Number of instructions committed system.cpu.commit.committedOps 90688136 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -684,381 +686,381 @@ system.cpu.commit.op_class_0::MemWrite 20555738 22.67% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 90688136 # Class of committed instruction -system.cpu.commit.bw_lim_events 3803876 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3769965 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 157616533 # The number of ROB reads -system.cpu.rob.rob_writes 195472136 # The number of ROB writes -system.cpu.timesIdled 23660 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 744970 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 158240550 # The number of ROB reads +system.cpu.rob.rob_writes 195514428 # The number of ROB writes +system.cpu.timesIdled 23835 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 850743 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 70907629 # Number of Instructions Simulated system.cpu.committedOps 90682584 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.931339 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.931339 # CPI: Total CPI of All Threads -system.cpu.ipc 1.073723 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.073723 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 102238235 # number of integer regfile reads -system.cpu.int_regfile_writes 56792997 # number of integer regfile writes +system.cpu.cpi 0.940923 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.940923 # CPI: Total CPI of All Threads +system.cpu.ipc 1.062786 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.062786 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 102271067 # number of integer regfile reads +system.cpu.int_regfile_writes 56793819 # number of integer regfile writes system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_writes 21 # number of floating regfile writes -system.cpu.cc_regfile_reads 345997909 # number of cc regfile reads -system.cpu.cc_regfile_writes 38804494 # number of cc regfile writes -system.cpu.misc_regfile_reads 44208348 # number of misc regfile reads +system.cpu.cc_regfile_reads 346093039 # number of cc regfile reads +system.cpu.cc_regfile_writes 38805147 # number of cc regfile writes +system.cpu.misc_regfile_reads 44210055 # number of misc regfile reads system.cpu.misc_regfile_writes 31840 # number of misc regfile writes -system.cpu.dcache.tags.replacements 485280 # number of replacements -system.cpu.dcache.tags.tagsinuse 510.769602 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40441610 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 485792 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 83.248818 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 148406000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 510.769602 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997597 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997597 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 485079 # number of replacements +system.cpu.dcache.tags.tagsinuse 510.744077 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40428139 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 485591 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 83.255536 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 152734000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 510.744077 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997547 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997547 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 454 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 84635072 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 84635072 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 21513403 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 21513403 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18834640 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18834640 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 62245 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 62245 # number of SoftPFReq hits +system.cpu.dcache.tags.tag_accesses 84616103 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 84616103 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 21501727 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 21501727 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18833421 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18833421 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 61667 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 61667 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15379 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15379 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40348043 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40348043 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40410288 # number of overall hits -system.cpu.dcache.overall_hits::total 40410288 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 550665 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 550665 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1015261 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1015261 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 66581 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 66581 # number of SoftPFReq misses +system.cpu.dcache.demand_hits::cpu.data 40335148 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40335148 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40396815 # number of overall hits +system.cpu.dcache.overall_hits::total 40396815 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 552941 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 552941 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1016480 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1016480 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 67175 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 67175 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 547 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 547 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1565926 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1565926 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1632507 # number of overall misses -system.cpu.dcache.overall_misses::total 1632507 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8659099753 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8659099753 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14372727937 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14372727937 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4891750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4891750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 23031827690 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 23031827690 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 23031827690 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 23031827690 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22064068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22064068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1569421 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1569421 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1636596 # number of overall misses +system.cpu.dcache.overall_misses::total 1636596 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9116754245 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9116754245 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14723087903 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14723087903 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 5168250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 5168250 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23839842148 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23839842148 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23839842148 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23839842148 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22054668 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22054668 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 128826 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 128826 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 128842 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 128842 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15926 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41913969 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41913969 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 42042795 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42042795 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.024958 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024958 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051147 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.051147 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.516829 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.516829 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_accesses::cpu.data 41904569 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41904569 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 42033411 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 42033411 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.025071 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.025071 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.051208 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.051208 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.521375 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.521375 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.034346 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.034346 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037360 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037360 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.038830 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.038830 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15724.805014 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15724.805014 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14156.682801 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 14156.682801 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8942.870201 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8942.870201 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 14708.120109 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 14708.120109 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14108.256620 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14108.256620 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 24 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2883834 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 127457 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 22.625937 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.037452 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037452 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.038936 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.038936 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16487.752301 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 16487.752301 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 14484.385234 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 14484.385234 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 9448.354662 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 9448.354662 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 15190.214830 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 15190.214830 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 14566.723949 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 14566.723949 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 97 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3023244 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 128456 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8.818182 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 23.535249 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 264417 # number of writebacks -system.cpu.dcache.writebacks::total 264417 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 250985 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 250985 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 866735 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 866735 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 262833 # number of writebacks +system.cpu.dcache.writebacks::total 262833 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 253459 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 253459 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 867955 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 867955 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 547 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 547 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1117720 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1117720 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1117720 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1117720 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299680 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 299680 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148526 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 148526 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 37597 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 448206 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 448206 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 485803 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 485803 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2833367604 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2833367604 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2154211948 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2154211948 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1934780357 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1934780357 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4987579552 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4987579552 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6922359909 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6922359909 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013582 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013582 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_hits::cpu.data 1121414 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1121414 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1121414 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1121414 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 299482 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 299482 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 148525 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 148525 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 37595 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 37595 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 448007 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 448007 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 485602 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 485602 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3044598863 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3044598863 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2289083292 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2289083292 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 2038189218 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 2038189218 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5333682155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5333682155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7371871373 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7371871373 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.013579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.013579 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.007482 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.007482 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291843 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291843 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010693 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.010693 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.011555 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9454.643633 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9454.643633 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14503.938354 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 14503.938354 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 51461.030322 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 51461.030322 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11127.873237 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 11127.873237 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14249.314864 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 14249.314864 # average overall mshr miss latency +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.291791 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.291791 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.010691 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.010691 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.011553 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.011553 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10166.216544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10166.216544 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 15412.107672 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 15412.107672 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54214.369411 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54214.369411 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11905.354503 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 11905.354503 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15180.891703 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 15180.891703 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 322868 # number of replacements -system.cpu.icache.tags.tagsinuse 510.284584 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 22426703 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 323380 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 69.350928 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 1086653000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.284584 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996650 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996650 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 322801 # number of replacements +system.cpu.icache.tags.tagsinuse 510.305225 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 22431720 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 323313 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 69.380817 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 1103729250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.305225 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996690 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996690 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 351 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 58 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 352 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 45841045 # Number of tag accesses -system.cpu.icache.tags.data_accesses 45841045 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 22426703 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 22426703 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 22426703 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 22426703 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 22426703 # number of overall hits -system.cpu.icache.overall_hits::total 22426703 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 332124 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 332124 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 332124 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 332124 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 332124 # number of overall misses -system.cpu.icache.overall_misses::total 332124 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 3299467842 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 3299467842 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 3299467842 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 3299467842 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 3299467842 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 3299467842 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 22758827 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 22758827 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 22758827 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 22758827 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 22758827 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 22758827 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014593 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014593 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014593 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014593 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014593 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014593 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 9934.445695 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 9934.445695 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 9934.445695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 9934.445695 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 9934.445695 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 226617 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 46 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 14091 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 45852448 # Number of tag accesses +system.cpu.icache.tags.data_accesses 45852448 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 22431720 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 22431720 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 22431720 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 22431720 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 22431720 # number of overall hits +system.cpu.icache.overall_hits::total 22431720 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 332842 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 332842 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 332842 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 332842 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 332842 # number of overall misses +system.cpu.icache.overall_misses::total 332842 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 3383637839 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 3383637839 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 3383637839 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 3383637839 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 3383637839 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 3383637839 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 22764562 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 22764562 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 22764562 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 22764562 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 22764562 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 22764562 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014621 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014621 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014621 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014621 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014621 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014621 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10165.898051 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10165.898051 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10165.898051 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10165.898051 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10165.898051 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10165.898051 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 260603 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 49 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 14904 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 16.082393 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 23 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.485440 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 24.500000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 8733 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 8733 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 8733 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 8733 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 8733 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 8733 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323391 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 323391 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 323391 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 323391 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 323391 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 323391 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2699093031 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2699093031 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2699093031 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2699093031 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2699093031 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2699093031 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014209 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014209 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014209 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014209 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8346.221852 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8346.221852 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8346.221852 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8346.221852 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 9518 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 9518 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 9518 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 9518 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 9518 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 9518 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 323324 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 323324 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 323324 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 323324 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 323324 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 323324 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2932923000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2932923000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2932923000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2932923000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2932923000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2932923000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014203 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014203 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014203 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014203 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9071.157724 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9071.157724 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9071.157724 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9071.157724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9071.157724 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9071.157724 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 812320 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 826786 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 12696 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 824674 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 826525 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 1627 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 79190 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 129572 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16081.031642 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 872493 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 145853 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 5.982002 # Average number of references to valid blocks. +system.cpu.l2cache.prefetcher.pfSpanPage 78731 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 129661 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16079.092385 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 870667 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 145945 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 5.965720 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 12593.782282 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.951130 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1938.685438 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 114.612791 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.768663 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087521 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.118328 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006995 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.981508 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 28 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 16253 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 2 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 15 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 4 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2807 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11875 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 526 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 887 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.001709 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.992004 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 17471961 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 17471961 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 314144 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 305991 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 620135 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 264417 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 264417 # number of Writeback hits +system.cpu.l2cache.tags.occ_blocks::writebacks 12574.733150 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1436.327637 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1964.109767 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 103.921830 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.767501 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.087666 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.119880 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.006343 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.981390 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 37 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 16247 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 19 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 6 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2630 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 11951 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 605 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 907 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.002258 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.991638 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 17442481 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 17442481 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 313998 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 305857 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 619855 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 262833 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 262833 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 5 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 5 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 137166 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 137166 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 314144 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 443157 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 757301 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 314144 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 443157 # number of overall hits -system.cpu.l2cache.overall_hits::total 757301 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 9232 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 31234 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 40466 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 137138 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 137138 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 313998 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 442995 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 756993 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 313998 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 442995 # number of overall hits +system.cpu.l2cache.overall_hits::total 756993 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 9315 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 31171 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 40486 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 11401 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 11401 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 9232 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 42635 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 51867 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 9232 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 42635 # number of overall misses -system.cpu.l2cache.overall_misses::total 51867 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 649699988 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2574698315 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3224398303 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1168450243 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1168450243 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 649699988 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3743148558 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 4392848546 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 649699988 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3743148558 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 4392848546 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 323376 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 337225 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 660601 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 264417 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 264417 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 11425 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 11425 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 9315 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 42596 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 51911 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 9315 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 42596 # number of overall misses +system.cpu.l2cache.overall_misses::total 51911 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 727315493 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2737689508 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3465005001 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1245872330 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1245872330 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 727315493 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3983561838 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 4710877331 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 727315493 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3983561838 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 4710877331 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 323313 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 337028 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 660341 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 262833 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 262833 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 11 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 11 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 148567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 148567 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 323376 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 485792 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 809168 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 323376 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 485792 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 809168 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.028549 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.092621 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.061256 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 148563 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 148563 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 323313 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 485591 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 808904 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 323313 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 485591 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 808904 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.028811 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.092488 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.061311 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.545455 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.545455 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076740 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.076740 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.028549 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087764 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.064099 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.028549 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087764 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.064099 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70374.782062 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82432.551546 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79681.666164 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102486.645294 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102486.645294 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70374.782062 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87795.204832 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 84694.479071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70374.782062 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87795.204832 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 84694.479071 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.076903 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.076903 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.028811 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087720 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.064174 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.028811 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087720 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.064174 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78080.031455 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87828.093677 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 85585.264067 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 109047.906346 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 109047.906346 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78080.031455 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93519.622453 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 90749.115428 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78080.031455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93519.622453 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 90749.115428 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1067,145 +1069,143 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 97844 # number of writebacks -system.cpu.l2cache.writebacks::total 97844 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 33 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 152 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 185 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3161 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3161 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 33 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 3313 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 3346 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 33 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 3313 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 3346 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9199 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31082 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 40281 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112599 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 112599 # number of HardPFReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 97887 # number of writebacks +system.cpu.l2cache.writebacks::total 97887 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 40 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 132 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 172 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3155 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3155 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 40 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 3287 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 3327 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 40 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 3287 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 3327 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9275 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31039 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 40314 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 112789 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 112789 # number of HardPFReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8240 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 8240 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 9199 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 39322 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 48521 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 9199 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 39322 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112599 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 161120 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 569300762 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2303617903 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872918665 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 11396158527 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 39006 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 39006 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 539005297 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 539005297 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 569300762 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2842623200 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 3411923962 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 569300762 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2842623200 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 11396158527 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14808082489 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092170 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.060976 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 8270 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 8270 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 9275 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 39309 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 48584 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 9275 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 39309 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 112789 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 161373 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 645635507 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2465712994 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3111348501 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 10913543372 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 10913543372 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 83006 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 83006 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 614828776 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 614828776 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 645635507 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3080541770 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 3726177277 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 645635507 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3080541770 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 10913543372 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14639720649 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.092096 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.061050 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.545455 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.545455 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055463 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.059964 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028447 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080944 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.055667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.055667 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.080951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.060062 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.028687 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.080951 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.199118 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61887.244483 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74114.210894 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71321.930066 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 101210.121999 # average HardPFReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 6501 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 6501 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 65413.264199 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 65413.264199 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70318.500484 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61887.244483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72290.910940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 101210.121999 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 91907.165398 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.199496 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69610.297251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 79439.189214 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77177.866275 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 96760.706913 # average HardPFReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13834.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13834.333333 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74344.471100 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74344.471100 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76695.563910 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69610.297251 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78367.340049 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 96760.706913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 90719.765072 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 660616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 660616 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 264417 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 169278 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 660352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 660352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 262833 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 151427 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 11 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 11 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 148567 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 148567 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646767 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1236023 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1882790 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20696064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 48013376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 68709440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 169293 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 1242889 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.136197 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.342998 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 148563 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 148563 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 646637 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1234037 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1880674 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20692032 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 47899136 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 68591168 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 151438 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 1223186 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.123797 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.329350 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 1073611 86.38% 86.38% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 169278 13.62% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 1071759 87.62% 87.62% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 151427 12.38% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 1242889 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 801222500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 1223186 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 798712500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486660171 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 486658187 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 734282302 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 734620345 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 137181 # Transaction distribution -system.membus.trans_dist::ReadResp 137181 # Transaction distribution -system.membus.trans_dist::Writeback 97844 # Transaction distribution +system.membus.trans_dist::ReadReq 137260 # Transaction distribution +system.membus.trans_dist::ReadResp 137260 # Transaction distribution +system.membus.trans_dist::Writeback 97887 # Transaction distribution system.membus.trans_dist::UpgradeReq 6 # Transaction distribution system.membus.trans_dist::UpgradeResp 6 # Transaction distribution -system.membus.trans_dist::ReadExReq 8252 # Transaction distribution -system.membus.trans_dist::ReadExResp 8252 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 388722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15569728 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15569728 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadExReq 8270 # Transaction distribution +system.membus.trans_dist::ReadExResp 8270 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 388959 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 388959 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15578688 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15578688 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 243283 # Request fanout histogram +system.membus.snoop_fanout::samples 243423 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 243283 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 243423 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 243283 # Request fanout histogram -system.membus.reqLayer0.occupancy 1077095188 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 1335208239 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 4.0 # Layer utilization (%) +system.membus.snoop_fanout::total 243423 # Request fanout histogram +system.membus.reqLayer0.occupancy 692237323 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 758965490 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 2.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 23c0d1c87..93e5e3e06 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu sim_ticks 48960011000 # Number of ticks simulated final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1376675 # Simulator instruction rate (inst/s) -host_op_rate 1760576 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 950486092 # Simulator tick rate (ticks/s) -host_mem_usage 308184 # Number of bytes of host memory used -host_seconds 51.51 # Real time elapsed on the host +host_inst_rate 1566427 # Simulator instruction rate (inst/s) +host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1081494789 # Simulator tick rate (ticks/s) +host_mem_usage 308080 # Number of bytes of host memory used +host_seconds 45.27 # Real time elapsed on the host sim_insts 70913181 # Number of instructions simulated sim_ops 90688136 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 120930618 # Request fanout histogram -system.membus.snoop_fanout::mean 4.646198 # Request fanout histogram +system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::5 78145068 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram +system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 120930618 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 938385651..6d597c67f 100644 --- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.127294 # Number of seconds simulated -sim_ticks 127293983000 # Number of ticks simulated -final_tick 127293983000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.127293 # Number of seconds simulated +sim_ticks 127293405500 # Number of ticks simulated +final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 894668 # Simulator instruction rate (inst/s) -host_op_rate 1142240 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618302823 # Simulator tick rate (ticks/s) -host_mem_usage 317432 # Number of bytes of host memory used -host_seconds 78.66 # Real time elapsed on the host +host_inst_rate 802256 # Simulator instruction rate (inst/s) +host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1451138855 # Simulator tick rate (ticks/s) +host_mem_usage 317568 # Number of bytes of host memory used +host_seconds 87.72 # Real time elapsed on the host sim_insts 70373628 # Number of instructions simulated sim_ops 89847362 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,17 +25,17 @@ system.physmem.num_reads::cpu.data 123820 # Nu system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2007071 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62253375 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64260445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2007071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2007071 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42187194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42187194 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42187194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2007071 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62253375 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106447639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254587966 # number of cpu cycles simulated +system.cpu.numCycles 254586811 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373628 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254587965.998000 # Number of busy cycles +system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741485 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690083 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389354 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608166 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304366 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061073000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389354 # Average occupied blocks per requestor +system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -230,8 +230,8 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749836 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749836 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits @@ -240,28 +240,28 @@ system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492705 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492705 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576328 # number of overall hits -system.cpu.dcache.overall_hits::total 42576328 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30231 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30231 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits +system.cpu.dcache.overall_hits::total 42576331 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137263 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137263 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177384 # number of overall misses -system.cpu.dcache.overall_misses::total 177384 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 516746500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 516746500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689859500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206606000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206606000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206606000 # number of overall miss cycles +system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses +system.cpu.dcache.overall_misses::total 177381 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17093.265191 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17093.265191 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53160.358584 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53160.358584 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45216.890203 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45216.890203 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34989.660849 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34989.660849 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,12 +304,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1123 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1123 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1123 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1123 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1123 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 443576500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5475795500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1053888500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5919372000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6973260500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6973260500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -340,26 +340,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15238.989281 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51160.358584 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44173.379998 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43480.035258 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43480.035258 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 43583.422918 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 43583.422918 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.675052 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.675052 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.846521 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.846521 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id @@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 414091500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 414091500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 414091500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 414091500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 414091500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 414091500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses @@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21900.333192 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21900.333192 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21900.333192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21900.333192 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21900.333192 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,43 +418,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 376275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 376275500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 376275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 376275500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 376275500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 376275500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000242 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19900.333192 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19900.333192 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19900.333192 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 19900.333192 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20392.056272 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 20392.056272 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30351.010864 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30351.006010 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27796.806295 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.765897 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.438673 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.848291 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 27796.868072 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768401 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.042799 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.926239 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15086 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13934 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15103 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13917 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses @@ -483,17 +483,17 @@ system.cpu.l2cache.demand_misses::total 127812 # nu system.cpu.l2cache.overall_misses::cpu.inst 3992 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 123820 # number of overall misses system.cpu.l2cache.overall_misses::total 127812 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 208207500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1130236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1338443500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5321243500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5321243500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 208207500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6451479500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6659687000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 208207500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6451479500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6659687000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210047000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1133331500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1343378500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5371640000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5371640000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 210047000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6504971500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6715018500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 210047000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6504971500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6715018500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 18908 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 52966 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 71874 # number of ReadReq accesses(hits+misses) @@ -518,17 +518,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.714409 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.211128 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.773885 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.714409 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52156.187375 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52471.494893 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52422.195676 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52026.236801 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52026.236801 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52105.334397 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52156.187375 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52103.694880 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52105.334397 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52616.983968 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52615.204271 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52615.482532 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52518.967540 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52518.967540 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52538.247582 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52616.983968 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52535.709094 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52538.247582 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -550,17 +550,17 @@ system.cpu.l2cache.demand_mshr_misses::total 127812 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3992 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 123820 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 127812 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 159943500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 868345500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028289000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4091943000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4091943000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 159943500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4960288500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5120232000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 159943500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4960288500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5120232000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 161778000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 873989500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1035767500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4142346500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4142346500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 161778000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses @@ -572,17 +572,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.007014 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40313.161560 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40274.518252 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40007.264372 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40007.264372 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40066.007014 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40060.478921 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40060.651582 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution @@ -597,19 +597,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 307145 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) @@ -627,19 +625,19 @@ system.membus.pkt_count::total 339533 # Pa system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214631 # Request fanout histogram +system.membus.snoop_fanout::samples 214640 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214631 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214631 # Request fanout histogram -system.membus.reqLayer0.occupancy 895030780 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 1156019000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.9 # Layer utilization (%) +system.membus.snoop_fanout::total 214640 # Request fanout histogram +system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 3c1945f38..718e317fa 100644 --- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.202242 # Number of seconds simulated -sim_ticks 202242260000 # Number of ticks simulated -final_tick 202242260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 202242028500 # Number of ticks simulated +final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1318449 # Simulator instruction rate (inst/s) -host_op_rate 1335520 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1983988186 # Simulator tick rate (ticks/s) -host_mem_usage 297988 # Number of bytes of host memory used -host_seconds 101.94 # Real time elapsed on the host +host_inst_rate 1201078 # Simulator instruction rate (inst/s) +host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1807368744 # Simulator tick rate (ticks/s) +host_mem_usage 300888 # Number of bytes of host memory used +host_seconds 111.90 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -25,44 +25,20 @@ system.physmem.num_reads::cpu.data 122291 # Nu system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2924651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38699251 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41623902 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2924651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2924651 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26223758 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26223758 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26223758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2924651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38699251 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67847660 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 30277 # Transaction distribution -system.membus.trans_dist::ReadResp 30277 # Transaction distribution -system.membus.trans_dist::Writeback 82868 # Transaction distribution -system.membus.trans_dist::ReadExReq 101256 # Transaction distribution -system.membus.trans_dist::ReadExResp 101256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214401 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214401 # Request fanout histogram -system.membus.reqLayer0.occupancy 877345000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 1183797000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.6 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404484520 # number of cpu cycles simulated +system.cpu.numCycles 404484057 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -81,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 404484519.998000 # Number of busy cycles +system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12719095 # Number of branches fetched @@ -120,13 +96,140 @@ system.cpu.op_class::MemWrite 20884381 15.32% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293798 # Class of executed instruction +system.cpu.dcache.tags.replacements 146582 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.648320 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 769041000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648320 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits +system.cpu.dcache.overall_hits::total 57944941 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses +system.cpu.dcache.overall_misses::total 150663 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475000000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475000000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619674000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5619674000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7094674000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7094674000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7094674000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7094674000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32418.294908 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32418.294908 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.240881 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.240881 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47089.690236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47089.690236 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks +system.cpu.dcache.writebacks::total 123970 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1406751500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1406751500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5461928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5461928000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 382500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 382500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6868679500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6868679500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6868679500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6868679500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30918.294908 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30918.294908 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51937.240881 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51937.240881 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.815325 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 2004.815289 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 143972294000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815325 # Average occupied blocks per requestor +system.cpu.icache.tags.warmup_cycle 143972077000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815289 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id @@ -150,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819681000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2819681000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2819681000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2819681000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2819681000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2819681000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819561500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2819561500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2819561500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2819561500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2819561500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2819561500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -168,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15076.573060 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15076.573060 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15076.573060 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15076.573060 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15076.573060 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15075.934105 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15075.934105 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15075.934105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15075.934105 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -188,34 +291,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2445633000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2445633000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2445633000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2445633000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2445633000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2445633000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2539025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2539025500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2539025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2539025500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2539025500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2539025500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13076.573060 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13076.573060 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13076.573060 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13076.573060 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13575.934105 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13575.934105 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 98540 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30850.759699 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30850.758845 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26245.550341 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.944777 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264582 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 26245.549112 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.945467 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264265 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy @@ -253,17 +356,17 @@ system.cpu.l2cache.demand_misses::total 131533 # nu system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses system.cpu.l2cache.overall_misses::total 131533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 480789000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1093974000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1574763000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5265313000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5265313000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 480789000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6359287000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 6840076000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 480789000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6359287000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 6840076000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 485290500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1104380500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1589671000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5315940000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5315940000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 485290500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6420320500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 6905611000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 485290500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6420320500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 6905611000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187024 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 45499 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 232523 # number of ReadReq accesses(hits+misses) @@ -288,17 +391,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.389494 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.049416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.811605 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.389494 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.181346 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52007.321131 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52011.857185 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.009876 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.009876 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52002.736956 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.181346 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52001.267469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52002.736956 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52509.251244 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52502.044212 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52504.244146 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.976941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52509.251244 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.351620 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.976941 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -320,17 +423,17 @@ system.cpu.l2cache.demand_mshr_misses::total 131533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 9242 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122291 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 131533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 369885000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 841554000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1211439000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4050241000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4050241000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 369885000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4891795000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5261680000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 369885000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4891795000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5261680000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 374386000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 851960500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1226346500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4100868000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4100868000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 374386000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4952828500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5327214500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 374386000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4952828500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5327214500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.462318 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.130211 # mshr miss rate for ReadReq accesses @@ -342,145 +445,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.389494 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.049416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811605 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.389494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40022.181346 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40007.321131 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40011.857185 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.009876 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.009876 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40022.181346 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40001.267469 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40002.736956 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40509.197143 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40502.044212 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40504.227632 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40509.197143 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.351620 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.973140 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.648350 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 769040000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648350 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 37185801 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 37185801 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20759140 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20759140 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 15901 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 15901 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 57944941 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 57944941 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 57944941 # number of overall hits -system.cpu.dcache.overall_hits::total 57944941 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 45499 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 45499 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 105164 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 105164 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 15 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 15 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 150663 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses -system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475111000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1475111000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619675000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5619675000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7094786000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7094786000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7094786000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7094786000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20864304 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 15916 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 58095604 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 58095604 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 58095604 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 58095604 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.001222 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.005040 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000942 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32420.734522 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32420.734522 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.250390 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.250390 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47090.433617 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47090.433617 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47090.433617 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks -system.cpu.dcache.writebacks::total 123970 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 105164 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 15 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 15 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1384113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1384113000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5409347000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5409347000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 375000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 375000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6793460000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6793460000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6793460000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6793460000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005040 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000942 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30420.734522 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30420.734522 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51437.250390 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51437.250390 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45090.433617 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45090.433617 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution @@ -510,5 +486,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 280536000 # La system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.trans_dist::ReadReq 30277 # Transaction distribution +system.membus.trans_dist::ReadResp 30277 # Transaction distribution +system.membus.trans_dist::Writeback 82868 # Transaction distribution +system.membus.trans_dist::ReadExReq 101256 # Transaction distribution +system.membus.trans_dist::ReadExResp 101256 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 214401 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 214401 # Request fanout histogram +system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt index 0dacf1436..520a2b090 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.199774 # Number of seconds simulated -sim_ticks 1199774280000 # Number of ticks simulated -final_tick 1199774280000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.211624 # Number of seconds simulated +sim_ticks 1211624479500 # Number of ticks simulated +final_tick 1211624479500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 216625 # Simulator instruction rate (inst/s) -host_op_rate 216625 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 142303871 # Simulator tick rate (ticks/s) -host_mem_usage 282608 # Number of bytes of host memory used -host_seconds 8431.08 # Real time elapsed on the host +host_inst_rate 333436 # Simulator instruction rate (inst/s) +host_op_rate 333436 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 221202175 # Simulator tick rate (ticks/s) +host_mem_usage 295444 # Number of bytes of host memory used +host_seconds 5477.45 # Real time elapsed on the host sim_insts 1826378509 # Number of instructions simulated sim_ops 1826378509 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61376 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125444608 # Number of bytes read from this memory -system.physmem.bytes_read::total 125505984 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65167488 # Number of bytes written to this memory -system.physmem.bytes_written::total 65167488 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 959 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1960072 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1961031 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1018242 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1018242 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 51156 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 104556840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 104607997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 51156 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 51156 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54316457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54316457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54316457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 51156 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 104556840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 158924454 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1961031 # Number of read requests accepted -system.physmem.writeReqs 1018242 # Number of write requests accepted -system.physmem.readBursts 1961031 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1018242 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125423808 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 82176 # Total number of bytes read from write queue -system.physmem.bytesWritten 65166208 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 125505984 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65167488 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1284 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 61248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125444544 # Number of bytes read from this memory +system.physmem.bytes_read::total 125505792 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 61248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65167616 # Number of bytes written to this memory +system.physmem.bytes_written::total 65167616 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 957 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1960071 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1961028 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1018244 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1018244 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 50550 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 103534178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 103584728 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 50550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 50550 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 53785325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 53785325 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 53785325 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 50550 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 103534178 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 157370053 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1961028 # Number of read requests accepted +system.physmem.writeReqs 1018244 # Number of write requests accepted +system.physmem.readBursts 1961028 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1018244 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125424064 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81728 # Total number of bytes read from write queue +system.physmem.bytesWritten 65166336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 125505792 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65167616 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1277 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 118757 # Per bank write bursts -system.physmem.perBankRdBursts::1 114096 # Per bank write bursts -system.physmem.perBankRdBursts::2 116226 # Per bank write bursts -system.physmem.perBankRdBursts::3 117770 # Per bank write bursts -system.physmem.perBankRdBursts::4 117824 # Per bank write bursts -system.physmem.perBankRdBursts::5 117523 # Per bank write bursts -system.physmem.perBankRdBursts::6 119882 # Per bank write bursts -system.physmem.perBankRdBursts::7 124516 # Per bank write bursts -system.physmem.perBankRdBursts::8 126973 # Per bank write bursts -system.physmem.perBankRdBursts::9 130090 # Per bank write bursts -system.physmem.perBankRdBursts::10 128654 # Per bank write bursts -system.physmem.perBankRdBursts::11 130347 # Per bank write bursts -system.physmem.perBankRdBursts::12 126055 # Per bank write bursts -system.physmem.perBankRdBursts::13 125249 # Per bank write bursts -system.physmem.perBankRdBursts::14 122591 # Per bank write bursts -system.physmem.perBankRdBursts::15 123194 # Per bank write bursts -system.physmem.perBankWrBursts::0 61222 # Per bank write bursts -system.physmem.perBankWrBursts::1 61485 # Per bank write bursts -system.physmem.perBankWrBursts::2 60564 # Per bank write bursts +system.physmem.perBankRdBursts::0 118746 # Per bank write bursts +system.physmem.perBankRdBursts::1 114093 # Per bank write bursts +system.physmem.perBankRdBursts::2 116238 # Per bank write bursts +system.physmem.perBankRdBursts::3 117765 # Per bank write bursts +system.physmem.perBankRdBursts::4 117832 # Per bank write bursts +system.physmem.perBankRdBursts::5 117522 # Per bank write bursts +system.physmem.perBankRdBursts::6 119888 # Per bank write bursts +system.physmem.perBankRdBursts::7 124523 # Per bank write bursts +system.physmem.perBankRdBursts::8 126979 # Per bank write bursts +system.physmem.perBankRdBursts::9 130092 # Per bank write bursts +system.physmem.perBankRdBursts::10 128645 # Per bank write bursts +system.physmem.perBankRdBursts::11 130343 # Per bank write bursts +system.physmem.perBankRdBursts::12 126054 # Per bank write bursts +system.physmem.perBankRdBursts::13 125251 # Per bank write bursts +system.physmem.perBankRdBursts::14 122593 # Per bank write bursts +system.physmem.perBankRdBursts::15 123187 # Per bank write bursts +system.physmem.perBankWrBursts::0 61219 # Per bank write bursts +system.physmem.perBankWrBursts::1 61484 # Per bank write bursts +system.physmem.perBankWrBursts::2 60571 # Per bank write bursts system.physmem.perBankWrBursts::3 61239 # Per bank write bursts -system.physmem.perBankWrBursts::4 61658 # Per bank write bursts -system.physmem.perBankWrBursts::5 63101 # Per bank write bursts -system.physmem.perBankWrBursts::6 64148 # Per bank write bursts -system.physmem.perBankWrBursts::7 65617 # Per bank write bursts -system.physmem.perBankWrBursts::8 65332 # Per bank write bursts -system.physmem.perBankWrBursts::9 65778 # Per bank write bursts -system.physmem.perBankWrBursts::10 65295 # Per bank write bursts -system.physmem.perBankWrBursts::11 65646 # Per bank write bursts -system.physmem.perBankWrBursts::12 64171 # Per bank write bursts -system.physmem.perBankWrBursts::13 64211 # Per bank write bursts -system.physmem.perBankWrBursts::14 64568 # Per bank write bursts +system.physmem.perBankWrBursts::4 61659 # Per bank write bursts +system.physmem.perBankWrBursts::5 63100 # Per bank write bursts +system.physmem.perBankWrBursts::6 64152 # Per bank write bursts +system.physmem.perBankWrBursts::7 65616 # Per bank write bursts +system.physmem.perBankWrBursts::8 65335 # Per bank write bursts +system.physmem.perBankWrBursts::9 65774 # Per bank write bursts +system.physmem.perBankWrBursts::10 65298 # Per bank write bursts +system.physmem.perBankWrBursts::11 65641 # Per bank write bursts +system.physmem.perBankWrBursts::12 64170 # Per bank write bursts +system.physmem.perBankWrBursts::13 64210 # Per bank write bursts +system.physmem.perBankWrBursts::14 64569 # Per bank write bursts system.physmem.perBankWrBursts::15 64187 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1199774169500 # Total gap between requests +system.physmem.totGap 1211624362000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1961031 # Read request sizes (log2) +system.physmem.readPktSize::6 1961028 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1018242 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1834284 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125445 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1018244 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1838105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 121629 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,35 +144,35 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 30311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 31746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 55277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 59244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59773 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 59999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 59968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 60029 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 60015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 60058 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 60509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 60796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 60183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 61128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 59690 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 59431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 30236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 31717 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 55111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 59442 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59878 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 59957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 59979 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 59955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 60009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 59970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 60003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 60022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 60856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 60315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 60403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 61125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 59710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 59424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::35 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see @@ -193,129 +193,130 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1838370 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.671596 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.054008 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 129.842659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1459678 79.40% 79.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 262161 14.26% 93.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 49287 2.68% 96.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 20645 1.12% 97.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12893 0.70% 98.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7143 0.39% 98.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5357 0.29% 98.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4451 0.24% 99.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 16755 0.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1838370 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59429 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.975652 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 161.968947 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59388 99.93% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1839318 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.618163 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.033976 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 129.636069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1460921 79.43% 79.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 261839 14.24% 93.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 49211 2.68% 96.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 20654 1.12% 97.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12987 0.71% 98.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7330 0.40% 98.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5324 0.29% 98.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4553 0.25% 99.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 16499 0.90% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1839318 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59419 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.981269 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 162.030420 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59379 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59429 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59429 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.133420 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.097680 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.110939 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27565 46.38% 46.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1269 2.14% 48.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 26249 44.17% 92.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3908 6.58% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 362 0.61% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 56 0.09% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 12 0.02% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 5 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59429 # Writes before turning the bus around for reads -system.physmem.totQLat 36751953000 # Total ticks spent queuing -system.physmem.totMemAccLat 73497209250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9798735000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18753.42 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 59419 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59419 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.136337 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.100269 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.116106 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27590 46.43% 46.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1250 2.10% 48.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 26098 43.92% 92.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3967 6.68% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 431 0.73% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 63 0.11% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 13 0.02% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 4 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59419 # Writes before turning the bus around for reads +system.physmem.totQLat 36831870500 # Total ticks spent queuing +system.physmem.totMemAccLat 73577201750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9798755000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18794.16 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37503.42 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 104.54 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 54.32 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 104.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 54.32 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37544.16 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 103.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 53.78 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 103.58 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 53.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.24 # Data bus utilization in percentage -system.physmem.busUtilRead 0.82 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.23 # Data bus utilization in percentage +system.physmem.busUtilRead 0.81 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.42 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.53 # Average write queue length when enqueuing -system.physmem.readRowHits 726418 # Number of row buffer hits during reads -system.physmem.writeRowHits 413172 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.07 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.58 # Row buffer hit rate for writes -system.physmem.avgGap 402707.03 # Average gap between requests -system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6745500720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3680580750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7383386400 # Energy for read commands per rank (pJ) +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 725319 # Number of row buffer hits during reads +system.physmem.writeRowHits 413326 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.59 # Row buffer hit rate for writes +system.physmem.avgGap 406684.71 # Average gap between requests +system.physmem.pageHitRate 38.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6747405840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3681620250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7383487800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 3233733840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 409753789290 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 360427621500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 869587605780 # Total energy per rank (pJ) -system.physmem_0.averagePower 724.796496 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 596865139750 # Time in different power states -system.physmem_0.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_0.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 416124660195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361949541750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 878257471275 # Total energy per rank (pJ) +system.physmem_0.averagePower 724.862968 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 599359370250 # Time in different power states +system.physmem_0.memoryStateTime::REF 40458600000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 562842538250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 571802499750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7152516000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3902662500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7901961600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3364241040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 78362993280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 422708761260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 349063611000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 872456746680 # Total energy per rank (pJ) -system.physmem_1.averagePower 727.187909 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 577877428500 # Time in different power states -system.physmem_1.memoryStateTime::REF 40062880000 # Time in different power states +system.physmem_1.actEnergy 7157785320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3905537625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7902000600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3364254000 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 79137021600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 427714080030 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 351783384000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 880964063175 # Total energy per rank (pJ) +system.physmem_1.averagePower 727.096833 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 582370760250 # Time in different power states +system.physmem_1.memoryStateTime::REF 40458600000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 581827655250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 588789276000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 246222594 # Number of BP lookups -system.cpu.branchPred.condPredicted 186441188 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 15682162 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 167748253 # Number of BTB lookups -system.cpu.branchPred.BTBHits 165224895 # Number of BTB hits +system.cpu.branchPred.lookups 246245862 # Number of BP lookups +system.cpu.branchPred.condPredicted 186459693 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 15680292 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 167860438 # Number of BTB lookups +system.cpu.branchPred.BTBHits 165233261 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.495747 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 18427327 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 104678 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.434904 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 18428492 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 104737 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 452533853 # DTB read hits -system.cpu.dtb.read_misses 4979561 # DTB read misses +system.cpu.dtb.read_hits 452534136 # DTB read hits +system.cpu.dtb.read_misses 4979812 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 457513414 # DTB read accesses -system.cpu.dtb.write_hits 161377742 # DTB write hits -system.cpu.dtb.write_misses 1710117 # DTB write misses +system.cpu.dtb.read_accesses 457513948 # DTB read accesses +system.cpu.dtb.write_hits 161377662 # DTB write hits +system.cpu.dtb.write_misses 1710258 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 163087859 # DTB write accesses -system.cpu.dtb.data_hits 613911595 # DTB hits -system.cpu.dtb.data_misses 6689678 # DTB misses +system.cpu.dtb.write_accesses 163087920 # DTB write accesses +system.cpu.dtb.data_hits 613911798 # DTB hits +system.cpu.dtb.data_misses 6690070 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 620601273 # DTB accesses -system.cpu.itb.fetch_hits 598493672 # ITB hits +system.cpu.dtb.data_accesses 620601868 # DTB accesses +system.cpu.itb.fetch_hits 598519306 # ITB hits system.cpu.itb.fetch_misses 19 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 598493691 # ITB accesses +system.cpu.itb.fetch_accesses 598519325 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -329,82 +330,82 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 2399548560 # number of cpu cycles simulated +system.cpu.numCycles 2423248959 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1826378509 # Number of instructions committed system.cpu.committedOps 1826378509 # Number of ops (including micro ops) committed -system.cpu.discardedOps 52395177 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 52407440 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.313829 # CPI: cycles per instruction -system.cpu.ipc 0.761134 # IPC: instructions per cycle -system.cpu.tickCycles 2077217503 # Number of cycles that the object actually ticked -system.cpu.idleCycles 322331057 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9121997 # number of replacements -system.cpu.dcache.tags.tagsinuse 4080.675710 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 601828569 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9126093 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.945917 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 16789907000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4080.675710 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.996259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.996259 # Average percentage of cache occupancy +system.cpu.cpi 1.326805 # CPI: cycles per instruction +system.cpu.ipc 0.753690 # IPC: instructions per cycle +system.cpu.tickCycles 2077336659 # Number of cycles that the object actually ticked +system.cpu.idleCycles 345912300 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9122013 # number of replacements +system.cpu.dcache.tags.tagsinuse 4080.749026 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 601822613 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9126109 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.945148 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 16826930000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4080.749026 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.996277 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.996277 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1613 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2310 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1542 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2418 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 71 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1231839903 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1231839903 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 443338834 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 443338834 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158489735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158489735 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 601828569 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 601828569 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 601828569 # number of overall hits -system.cpu.dcache.overall_hits::total 601828569 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7289569 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7289569 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2238767 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238767 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9528336 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9528336 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9528336 # number of overall misses -system.cpu.dcache.overall_misses::total 9528336 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 178039686000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 178039686000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 100958450500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 100958450500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 278998136500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 278998136500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 278998136500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 278998136500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 450628403 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 450628403 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1231838683 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1231838683 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 443338219 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 443338219 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158484394 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158484394 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 601822613 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 601822613 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 601822613 # number of overall hits +system.cpu.dcache.overall_hits::total 601822613 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7289566 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7289566 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2244108 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2244108 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9533674 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9533674 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9533674 # number of overall misses +system.cpu.dcache.overall_misses::total 9533674 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 186798880750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 186798880750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 108940864000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 108940864000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 295739744750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 295739744750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 295739744750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 295739744750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 450627785 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 450627785 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 611356905 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 611356905 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 611356905 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 611356905 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 611356287 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 611356287 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 611356287 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 611356287 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016176 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.016176 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013929 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.013929 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015586 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015586 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015586 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015586 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24423.897490 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24423.897490 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45095.559520 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45095.559520 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29280.887712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29280.887712 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29280.887712 # average overall miss latency +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013962 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013962 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015594 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015594 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015594 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015594 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25625.514708 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 25625.514708 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48545.285699 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48545.285699 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31020.543051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31020.543051 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31020.543051 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -413,32 +414,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3700624 # number of writebacks -system.cpu.dcache.writebacks::total 3700624 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50811 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 50811 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 351432 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 351432 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 402243 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 402243 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 402243 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 402243 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238758 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7238758 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887335 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1887335 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9126093 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9126093 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9126093 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9126093 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162083992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 162083992000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 75948494500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 75948494500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 238032486500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 238032486500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 238032486500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 238032486500 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 3700625 # number of writebacks +system.cpu.dcache.writebacks::total 3700625 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 50791 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 50791 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 356774 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 356774 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 407565 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 407565 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 407565 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 407565 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7238775 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7238775 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1887334 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1887334 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9126109 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9126109 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9126109 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9126109 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 174334776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 174334776000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 82397045250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 82397045250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 256731821250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 256731821250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 256731821250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 256731821250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016064 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011742 # mshr miss rate for WriteReq accesses @@ -447,66 +448,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014928 system.cpu.dcache.demand_mshr_miss_rate::total 0.014928 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014928 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014928 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22391.132844 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22391.132844 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40241.130748 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40241.130748 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26082.627747 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26082.627747 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24083.463846 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24083.463846 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 43657.903291 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 43657.903291 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28131.575160 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28131.575160 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28131.575160 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28131.575160 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 752.081160 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 598492713 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 959 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 624079.992701 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 751.304686 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 598518349 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 957 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 625411.022989 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 752.081160 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.367227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.367227 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 956 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 751.304686 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.366848 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.366848 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 954 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 80 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 876 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.466797 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1196988303 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1196988303 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 598492713 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 598492713 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 598492713 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 598492713 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 598492713 # number of overall hits -system.cpu.icache.overall_hits::total 598492713 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 959 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 959 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 959 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 959 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 959 # number of overall misses -system.cpu.icache.overall_misses::total 959 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 71027250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 71027250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 71027250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 71027250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 71027250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 71027250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 598493672 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 598493672 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 598493672 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 598493672 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 598493672 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 598493672 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::4 874 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.465820 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 1197039569 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1197039569 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 598518349 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 598518349 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 598518349 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 598518349 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 598518349 # number of overall hits +system.cpu.icache.overall_hits::total 598518349 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 957 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 957 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 957 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 957 # number of overall misses +system.cpu.icache.overall_misses::total 957 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 77501250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 77501250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 77501250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 77501250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 77501250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 77501250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 598519306 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 598519306 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 598519306 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 598519306 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 598519306 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 598519306 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74063.868613 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74063.868613 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74063.868613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74063.868613 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74063.868613 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80983.542320 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 80983.542320 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 80983.542320 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 80983.542320 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 80983.542320 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -515,120 +516,120 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 959 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 959 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 959 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 68715750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 68715750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 68715750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 68715750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 68715750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 68715750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 957 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 957 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 957 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75665250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 75665250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75665250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 75665250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75665250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 75665250 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71653.545360 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71653.545360 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71653.545360 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71653.545360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71653.545360 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71653.545360 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79065.047022 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79065.047022 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79065.047022 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79065.047022 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79065.047022 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79065.047022 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1928296 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30756.810610 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8981713 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1958100 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.586953 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 89009074750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14951.890642 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 43.293989 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15761.625979 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.456295 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001321 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.481007 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.938623 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 1928293 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30768.859371 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8981732 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1958097 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.586970 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 89233172750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14926.329939 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 42.856216 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15799.673216 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.455515 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001308 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.482168 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.938991 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29804 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1226 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12860 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15531 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 160 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1214 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12866 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15537 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909546 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 106466843 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 106466843 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6058136 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6058136 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3700624 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3700624 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1107885 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107885 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7166021 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7166021 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7166021 # number of overall hits -system.cpu.l2cache.overall_hits::total 7166021 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 959 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1180622 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1181581 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 779450 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 779450 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 959 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1960072 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1961031 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 959 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1960072 # number of overall misses -system.cpu.l2cache.overall_misses::total 1961031 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 67755750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94247592500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 94315348250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 62933867000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 62933867000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 67755750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 157181459500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 157249215250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 67755750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 157181459500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 157249215250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 959 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7238758 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7239717 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3700624 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3700624 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887335 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1887335 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 959 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9126093 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9127052 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 959 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9126093 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9127052 # number of overall (read+write) accesses +system.cpu.l2cache.tags.tag_accesses 106466959 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 106466959 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.data 6058152 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6058152 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3700625 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3700625 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1107886 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107886 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7166038 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7166038 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7166038 # number of overall hits +system.cpu.l2cache.overall_hits::total 7166038 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 957 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1180623 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1181580 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 779448 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 779448 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 957 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1960071 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1961028 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 957 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1960071 # number of overall misses +system.cpu.l2cache.overall_misses::total 1961028 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 74707750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 103467793000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 103542500750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 68812477000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 68812477000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 74707750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 172280270000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 172354977750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 74707750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 172280270000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 172354977750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 957 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7238775 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7239732 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3700625 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3700625 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1887334 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1887334 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 957 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9126109 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9127066 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 957 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9126109 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9127066 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163097 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.163208 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412990 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.412990 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.412989 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.412989 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.214777 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.214776 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.214859 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.214777 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.214776 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214859 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70652.502607 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79828.761873 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79821.314197 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80741.377895 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80741.377895 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70652.502607 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80191.676377 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80187.011450 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70652.502607 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80191.676377 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80187.011450 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78064.524556 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87638.300287 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 87630.546175 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88283.601985 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88283.601985 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78064.524556 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87894.912990 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87890.115669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78064.524556 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87894.912990 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87890.115669 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -637,105 +638,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1018242 # number of writebacks -system.cpu.l2cache.writebacks::total 1018242 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 959 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1180622 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1181581 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 779450 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 779450 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 959 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1960072 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1961031 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 959 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1960072 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1961031 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 55699750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 79417889000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79473588750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53122771000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53122771000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 55699750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132540660000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 132596359750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 55699750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132540660000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 132596359750 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1018244 # number of writebacks +system.cpu.l2cache.writebacks::total 1018244 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 957 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1180623 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1181580 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 779448 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 779448 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 957 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1960071 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1961028 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 957 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1960071 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1961028 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 62720750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 88545037500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 88607758250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 58965142500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 58965142500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62720750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 147510180000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 147572900750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62720750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 147510180000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 147572900750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163097 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163208 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412990 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412990 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.412989 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.412989 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214776 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.214859 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214777 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214776 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214859 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58081.074035 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67267.837631 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67260.381430 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68154.174097 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68154.174097 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58081.074035 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67620.301703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67615.636749 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65538.923720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74998.570670 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74990.908995 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75649.873372 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75649.873372 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65538.923720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75257.569751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75252.826961 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7239717 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7239717 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3700624 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1887335 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1887335 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1918 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952810 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 21954728 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820909888 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 820971264 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7239732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7239732 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3700625 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1887334 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1887334 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1914 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21952843 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 21954757 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820910976 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 820972224 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12827676 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12827691 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12827676 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12827691 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12827676 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10114462000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12827691 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10114470500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1635250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1635750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14011262000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14015207750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1181581 # Transaction distribution -system.membus.trans_dist::ReadResp 1181581 # Transaction distribution -system.membus.trans_dist::Writeback 1018242 # Transaction distribution -system.membus.trans_dist::ReadExReq 779450 # Transaction distribution -system.membus.trans_dist::ReadExResp 779450 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940304 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4940304 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190673472 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1181580 # Transaction distribution +system.membus.trans_dist::ReadResp 1181580 # Transaction distribution +system.membus.trans_dist::Writeback 1018244 # Transaction distribution +system.membus.trans_dist::ReadExReq 779448 # Transaction distribution +system.membus.trans_dist::ReadExResp 779448 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4940300 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4940300 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190673408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190673408 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2979273 # Request fanout histogram +system.membus.snoop_fanout::samples 2979272 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2979273 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2979272 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2979273 # Request fanout histogram -system.membus.reqLayer0.occupancy 11833185000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 18446289250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.5 # Layer utilization (%) +system.membus.snoop_fanout::total 2979272 # Request fanout histogram +system.membus.reqLayer0.occupancy 7744840000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 10727612750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt index 9b6ff7bd3..47b73b46e 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt @@ -1,109 +1,109 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.662030 # Number of seconds simulated -sim_ticks 662030381000 # Number of ticks simulated -final_tick 662030381000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.672882 # Number of seconds simulated +sim_ticks 672881519500 # Number of ticks simulated +final_tick 672881519500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173779 # Simulator instruction rate (inst/s) -host_op_rate 173779 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 66269486 # Simulator tick rate (ticks/s) -host_mem_usage 296312 # Number of bytes of host memory used -host_seconds 9989.97 # Real time elapsed on the host +host_inst_rate 171066 # Simulator instruction rate (inst/s) +host_op_rate 171066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66304234 # Simulator tick rate (ticks/s) +host_mem_usage 296744 # Number of bytes of host memory used +host_seconds 10148.39 # Real time elapsed on the host sim_insts 1736043781 # Number of instructions simulated sim_ops 1736043781 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 61824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125964224 # Number of bytes read from this memory -system.physmem.bytes_read::total 126026048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 65301568 # Number of bytes written to this memory -system.physmem.bytes_written::total 65301568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 966 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1968191 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1969157 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1020337 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1020337 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 93385 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 190269552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 190362937 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 93385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 93385 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 98638325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 98638325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 98638325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 93385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 190269552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 289001263 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 1969157 # Number of read requests accepted -system.physmem.writeReqs 1020337 # Number of write requests accepted -system.physmem.readBursts 1969157 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1020337 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 125945216 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 80832 # Total number of bytes read from write queue -system.physmem.bytesWritten 65299584 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 126026048 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 65301568 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1263 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 62400 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125964544 # Number of bytes read from this memory +system.physmem.bytes_read::total 126026944 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 62400 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 62400 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 65296192 # Number of bytes written to this memory +system.physmem.bytes_written::total 65296192 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 975 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1968196 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1969171 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1020253 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1020253 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 92735 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 187201670 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 187294405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 92735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 92735 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 97039657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 97039657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 97039657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 92735 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 187201670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 284334062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 1969171 # Number of read requests accepted +system.physmem.writeReqs 1020253 # Number of write requests accepted +system.physmem.readBursts 1969171 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1020253 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 125945600 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 81344 # Total number of bytes read from write queue +system.physmem.bytesWritten 65294336 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 126026944 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 65296192 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1271 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 119107 # Per bank write bursts -system.physmem.perBankRdBursts::1 114513 # Per bank write bursts -system.physmem.perBankRdBursts::2 116588 # Per bank write bursts -system.physmem.perBankRdBursts::3 118130 # Per bank write bursts -system.physmem.perBankRdBursts::4 118281 # Per bank write bursts -system.physmem.perBankRdBursts::5 117894 # Per bank write bursts -system.physmem.perBankRdBursts::6 120372 # Per bank write bursts -system.physmem.perBankRdBursts::7 125027 # Per bank write bursts -system.physmem.perBankRdBursts::8 127642 # Per bank write bursts -system.physmem.perBankRdBursts::9 130604 # Per bank write bursts -system.physmem.perBankRdBursts::10 129295 # Per bank write bursts -system.physmem.perBankRdBursts::11 130929 # Per bank write bursts -system.physmem.perBankRdBursts::12 126770 # Per bank write bursts -system.physmem.perBankRdBursts::13 125862 # Per bank write bursts -system.physmem.perBankRdBursts::14 123081 # Per bank write bursts -system.physmem.perBankRdBursts::15 123799 # Per bank write bursts -system.physmem.perBankWrBursts::0 61289 # Per bank write bursts -system.physmem.perBankWrBursts::1 61597 # Per bank write bursts -system.physmem.perBankWrBursts::2 60658 # Per bank write bursts -system.physmem.perBankWrBursts::3 61339 # Per bank write bursts -system.physmem.perBankWrBursts::4 61821 # Per bank write bursts -system.physmem.perBankWrBursts::5 63209 # Per bank write bursts -system.physmem.perBankWrBursts::6 64289 # Per bank write bursts -system.physmem.perBankWrBursts::7 65739 # Per bank write bursts -system.physmem.perBankWrBursts::8 65503 # Per bank write bursts -system.physmem.perBankWrBursts::9 65920 # Per bank write bursts -system.physmem.perBankWrBursts::10 65439 # Per bank write bursts -system.physmem.perBankWrBursts::11 65771 # Per bank write bursts -system.physmem.perBankWrBursts::12 64363 # Per bank write bursts -system.physmem.perBankWrBursts::13 64352 # Per bank write bursts -system.physmem.perBankWrBursts::14 64685 # Per bank write bursts -system.physmem.perBankWrBursts::15 64332 # Per bank write bursts +system.physmem.perBankRdBursts::0 119102 # Per bank write bursts +system.physmem.perBankRdBursts::1 114505 # Per bank write bursts +system.physmem.perBankRdBursts::2 116613 # Per bank write bursts +system.physmem.perBankRdBursts::3 118153 # Per bank write bursts +system.physmem.perBankRdBursts::4 118234 # Per bank write bursts +system.physmem.perBankRdBursts::5 117885 # Per bank write bursts +system.physmem.perBankRdBursts::6 120369 # Per bank write bursts +system.physmem.perBankRdBursts::7 125035 # Per bank write bursts +system.physmem.perBankRdBursts::8 127648 # Per bank write bursts +system.physmem.perBankRdBursts::9 130593 # Per bank write bursts +system.physmem.perBankRdBursts::10 129299 # Per bank write bursts +system.physmem.perBankRdBursts::11 130947 # Per bank write bursts +system.physmem.perBankRdBursts::12 126747 # Per bank write bursts +system.physmem.perBankRdBursts::13 125863 # Per bank write bursts +system.physmem.perBankRdBursts::14 123089 # Per bank write bursts +system.physmem.perBankRdBursts::15 123818 # Per bank write bursts +system.physmem.perBankWrBursts::0 61291 # Per bank write bursts +system.physmem.perBankWrBursts::1 61585 # Per bank write bursts +system.physmem.perBankWrBursts::2 60661 # Per bank write bursts +system.physmem.perBankWrBursts::3 61360 # Per bank write bursts +system.physmem.perBankWrBursts::4 61790 # Per bank write bursts +system.physmem.perBankWrBursts::5 63221 # Per bank write bursts +system.physmem.perBankWrBursts::6 64275 # Per bank write bursts +system.physmem.perBankWrBursts::7 65726 # Per bank write bursts +system.physmem.perBankWrBursts::8 65508 # Per bank write bursts +system.physmem.perBankWrBursts::9 65914 # Per bank write bursts +system.physmem.perBankWrBursts::10 65448 # Per bank write bursts +system.physmem.perBankWrBursts::11 65777 # Per bank write bursts +system.physmem.perBankWrBursts::12 64328 # Per bank write bursts +system.physmem.perBankWrBursts::13 64347 # Per bank write bursts +system.physmem.perBankWrBursts::14 64660 # Per bank write bursts +system.physmem.perBankWrBursts::15 64333 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 662030291500 # Total gap between requests +system.physmem.totGap 672881423000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 1969157 # Read request sizes (log2) +system.physmem.readPktSize::6 1969171 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1020337 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1619145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 248303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 76115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 24314 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1020253 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1621016 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 243733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 72507 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 30617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 25 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -144,29 +144,29 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 25811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 27497 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 49263 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 56182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 59042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 60255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 60670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 60945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61157 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61481 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 63086 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 64803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 62190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62948 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61430 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 26054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 27728 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 49537 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 56799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 59190 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 60318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 60638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 60909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61063 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61512 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 62489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 64414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 63055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 173 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see @@ -193,142 +193,143 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1776224 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 107.667141 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 82.863857 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 136.742577 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1381396 77.77% 77.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 271071 15.26% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 53950 3.04% 96.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21226 1.20% 97.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 12955 0.73% 97.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6597 0.37% 98.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5003 0.28% 98.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3759 0.21% 98.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 20267 1.14% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1776224 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 59925 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 32.795728 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 163.660245 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 59887 99.94% 99.94% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 13 0.02% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-5119 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1777587 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 107.583217 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 82.835342 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 136.553801 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1382839 77.79% 77.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 271264 15.26% 93.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53815 3.03% 96.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21128 1.19% 97.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12924 0.73% 98.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6598 0.37% 98.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5024 0.28% 98.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3881 0.22% 98.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 20114 1.13% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1777587 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 59878 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.821905 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 161.087941 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 59840 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 59925 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 59925 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.026383 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.985304 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.212732 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 31950 53.32% 53.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1595 2.66% 55.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 20819 34.74% 90.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 4577 7.64% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 750 1.25% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 154 0.26% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 27 0.05% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 19 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 3 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 4 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32 3 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::33 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::34 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::35 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36 4 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::37 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 59878 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 59878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.038378 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.996376 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.234472 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 31771 53.06% 53.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1453 2.43% 55.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 20992 35.06% 90.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 4585 7.66% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 809 1.35% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 191 0.32% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 31 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 14 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 5 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 1 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::35 5 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::37 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::38 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 3 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 1 0.00% 100.00% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::42 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 59925 # Writes before turning the bus around for reads -system.physmem.totQLat 40790268000 # Total ticks spent queuing -system.physmem.totMemAccLat 77688280500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 9839470000 # Total ticks spent in databus transfers -system.physmem.avgQLat 20727.88 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::52 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 59878 # Writes before turning the bus around for reads +system.physmem.totQLat 40967898000 # Total ticks spent queuing +system.physmem.totMemAccLat 77866023000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 9839500000 # Total ticks spent in databus transfers +system.physmem.avgQLat 20818.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 39477.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 190.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 98.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 190.36 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 98.64 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 39568.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 187.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 97.04 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 187.29 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 97.04 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.26 # Data bus utilization in percentage -system.physmem.busUtilRead 1.49 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.77 # Data bus utilization in percentage for writes +system.physmem.busUtil 2.22 # Data bus utilization in percentage +system.physmem.busUtilRead 1.46 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.76 # Average write queue length when enqueuing -system.physmem.readRowHits 795786 # Number of row buffer hits during reads -system.physmem.writeRowHits 416180 # Number of row buffer hits during writes -system.physmem.readRowHitRate 40.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 40.79 # Row buffer hit rate for writes -system.physmem.avgGap 221452.29 # Average gap between requests -system.physmem.pageHitRate 40.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 6511261680 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3552771750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7409259000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3239617680 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 299928124440 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 134120853750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 498002202300 # Total energy per rank (pJ) -system.physmem_0.averagePower 752.239455 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 221171423750 # Time in different power states -system.physmem_0.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem.avgWrQLen 24.71 # Average write queue length when enqueuing +system.physmem.readRowHits 794560 # Number of row buffer hits during reads +system.physmem.writeRowHits 415972 # Number of row buffer hits during writes +system.physmem.readRowHitRate 40.38 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 40.77 # Row buffer hit rate for writes +system.physmem.avgGap 225087.32 # Average gap between requests +system.physmem.pageHitRate 40.51 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 6515684280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3555184875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7409165400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3239410320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 305964835695 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 135337912500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 505971439710 # Total energy per rank (pJ) +system.physmem_0.averagePower 751.948773 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 223158478000 # Time in different power states +system.physmem_0.memoryStateTime::REF 22468940000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 418748256250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 427253308500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 6916946400 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 3774127500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 7939518600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3371965200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 43240314000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 306633623535 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 128238837000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 500115332235 # Total energy per rank (pJ) -system.physmem_1.averagePower 755.431368 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 211341940750 # Time in different power states -system.physmem_1.memoryStateTime::REF 22106500000 # Time in different power states +system.physmem_1.actEnergy 6922850760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 3777349125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 7940244000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3371641200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 43949246640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 312976099035 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 129187681500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 508125112260 # Total energy per rank (pJ) +system.physmem_1.averagePower 755.149450 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 212887456750 # Time in different power states +system.physmem_1.memoryStateTime::REF 22468940000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 428577885750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 437523815750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 410531758 # Number of BP lookups -system.cpu.branchPred.condPredicted 318847451 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 16269165 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 283137932 # Number of BTB lookups -system.cpu.branchPred.BTBHits 279377578 # Number of BTB hits +system.cpu.branchPred.lookups 410709882 # Number of BP lookups +system.cpu.branchPred.condPredicted 318998342 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 16277823 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 282986544 # Number of BTB lookups +system.cpu.branchPred.BTBHits 279468528 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 98.671900 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 26373623 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 19 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 98.756826 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 26379180 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 17 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 646133385 # DTB read hits -system.cpu.dtb.read_misses 12154937 # DTB read misses -system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 658288322 # DTB read accesses -system.cpu.dtb.write_hits 218173916 # DTB write hits -system.cpu.dtb.write_misses 7514058 # DTB write misses +system.cpu.dtb.read_hits 646309229 # DTB read hits +system.cpu.dtb.read_misses 12154225 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 658463454 # DTB read accesses +system.cpu.dtb.write_hits 218201258 # DTB write hits +system.cpu.dtb.write_misses 7510092 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 225687974 # DTB write accesses -system.cpu.dtb.data_hits 864307301 # DTB hits -system.cpu.dtb.data_misses 19668995 # DTB misses -system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 883976296 # DTB accesses -system.cpu.itb.fetch_hits 422458110 # ITB hits -system.cpu.itb.fetch_misses 45 # ITB misses +system.cpu.dtb.write_accesses 225711350 # DTB write accesses +system.cpu.dtb.data_hits 864510487 # DTB hits +system.cpu.dtb.data_misses 19664317 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 884174804 # DTB accesses +system.cpu.itb.fetch_hits 422619736 # ITB hits +system.cpu.itb.fetch_misses 46 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 422458155 # ITB accesses +system.cpu.itb.fetch_accesses 422619782 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -342,238 +343,238 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 1324060763 # number of cpu cycles simulated +system.cpu.numCycles 1345763040 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 433748906 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 3419441963 # Number of instructions fetch has processed -system.cpu.fetch.Branches 410531758 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 305751201 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 867248304 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 45995858 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 88 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1804 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 39 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 422458110 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 8422260 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1323997070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.582666 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.157790 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 433914332 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 3420599858 # Number of instructions fetch has processed +system.cpu.fetch.Branches 410709882 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 305847708 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 888768265 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 46015780 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1748 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 113 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 422619736 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 8427195 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1345692377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.541888 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.149351 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 696991073 52.64% 52.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48002120 3.63% 56.27% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 24407254 1.84% 58.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 45263157 3.42% 61.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 142993214 10.80% 72.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 66222276 5.00% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 43788088 3.31% 80.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 29616004 2.24% 82.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 226713884 17.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 718495980 53.39% 53.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48031633 3.57% 56.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 24393578 1.81% 58.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 45267643 3.36% 62.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 143041045 10.63% 72.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 66223895 4.92% 77.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 43793513 3.25% 80.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 29627313 2.20% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 226817777 16.86% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1323997070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.310055 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.582542 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 355597650 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 384696746 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 525812607 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 34892959 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 22997108 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 62293389 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 869 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 3264034948 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 2192 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 22997108 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 373957968 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 205165673 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7731 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 538730067 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 183138523 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 3181033284 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 1755579 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18983042 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 140285341 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 27927823 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 2377354751 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 4126620289 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 4126448707 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 171581 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1345692377 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.305187 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.541755 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 355603714 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 406294583 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 525817435 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 34969591 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 23007054 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 62310888 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 895 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 3264812656 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 2282 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 23007054 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 373973816 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 212778142 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 7997 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 538797541 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 197127827 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 3181847820 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1862600 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 20249864 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 150635497 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 31416943 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 2377870821 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 4127617004 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 4127447466 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 169537 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 1001151788 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 192 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 191 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 99207749 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 719206023 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 272877739 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 90880933 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 59162115 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 2889782486 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 178 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 2624016708 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 1570062 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 1139342915 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 505618557 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 149 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1323997070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.981890 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.151111 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 1001667858 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 209 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 206 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 99280769 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 719325488 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 272942348 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 90808423 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 59047660 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 2890368727 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 181 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 2624396643 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 1584497 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 1140831193 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 506084435 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 152 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1345692377 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.950220 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.146970 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 519747645 39.26% 39.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 169377682 12.79% 52.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 158338012 11.96% 64.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 149173722 11.27% 75.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 126185648 9.53% 84.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 84437665 6.38% 91.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 68199937 5.15% 96.33% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 33982775 2.57% 98.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14553984 1.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 540762104 40.18% 40.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 169795677 12.62% 52.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 158437148 11.77% 64.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 149383051 11.10% 75.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 126329288 9.39% 85.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 84501883 6.28% 91.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 68040537 5.06% 96.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 34033784 2.53% 98.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14408905 1.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1323997070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1345692377 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 13171575 35.70% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 19111155 51.80% 87.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 4612971 12.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13165371 35.79% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 19036657 51.75% 87.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 4585623 12.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1719329788 65.52% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 125 0.00% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1719509054 65.52% 65.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 111 0.00% 65.52% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 895316 0.03% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 18 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 165 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 30 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 25 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 672939161 25.65% 91.20% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 230852080 8.80% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 896832 0.03% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 17 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 164 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 25 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 24 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.55% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 673114194 25.65% 91.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 230876222 8.80% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 2624016708 # Type of FU issued -system.cpu.iq.rate 1.981795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 36895701 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.014061 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 6608517036 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 4027973051 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 2521923586 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 1979213 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 1297888 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 892539 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2659929620 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 982789 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69543206 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 2624396643 # Type of FU issued +system.cpu.iq.rate 1.950118 # Inst issue rate +system.cpu.iq.fu_busy_cnt 36787651 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014018 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 6630876089 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 4030049566 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 2522176401 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 1981722 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 1296863 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 893189 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2660200136 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 984158 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 69569005 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 274610360 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 379362 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 147727 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 112149237 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 274729825 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 379855 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 148630 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 112213846 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 353 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6023017 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 321 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6130129 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 22997108 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 147758887 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18474565 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 3040988458 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 6691344 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 719206023 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 272877739 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 178 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 822290 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 17921565 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 147727 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 10901488 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8843129 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 19744617 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 2578330269 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 658288327 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 45686439 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 23007054 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 150994559 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 20053347 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 3041642230 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 6687101 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 719325488 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 272942348 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 181 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 819254 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 19491023 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 148630 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 10888571 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8843177 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 19731748 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 2578706854 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 658463458 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 45689789 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 151205794 # number of nop insts executed -system.cpu.iew.exec_refs 883976375 # number of memory reference insts executed -system.cpu.iew.exec_branches 315983093 # Number of branches executed -system.cpu.iew.exec_stores 225688048 # Number of stores executed -system.cpu.iew.exec_rate 1.947290 # Inst execution rate -system.cpu.iew.wb_sent 2552817971 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 2522816125 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1489246506 # num instructions producing a value -system.cpu.iew.wb_consumers 1920479792 # num instructions consuming a value +system.cpu.iew.exec_nop 151273322 # number of nop insts executed +system.cpu.iew.exec_refs 884174883 # number of memory reference insts executed +system.cpu.iew.exec_branches 315972780 # Number of branches executed +system.cpu.iew.exec_stores 225711425 # Number of stores executed +system.cpu.iew.exec_rate 1.916167 # Inst execution rate +system.cpu.iew.wb_sent 2553063246 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 2523069590 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1489308587 # num instructions producing a value +system.cpu.iew.wb_consumers 1920703402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.905363 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.775455 # average fanout of values written-back +system.cpu.iew.wb_rate 1.874825 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.775397 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 1005136223 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 1005912526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 16268344 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1185116972 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.535528 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.558449 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 16276987 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1206693157 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.508072 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.543192 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 695949152 58.72% 58.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 159874809 13.49% 72.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 79784402 6.73% 78.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 52116706 4.40% 83.34% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 28440614 2.40% 85.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 19407125 1.64% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 20027045 1.69% 89.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 23110908 1.95% 91.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106406211 8.98% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 717446911 59.46% 59.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 159887401 13.25% 72.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 79830197 6.62% 79.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 52027392 4.31% 83.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 28503242 2.36% 85.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 19553290 1.62% 87.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 20023421 1.66% 89.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 23140213 1.92% 91.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 106281090 8.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1185116972 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1206693157 # Number of insts commited each cycle system.cpu.commit.committedInsts 1819780126 # Number of instructions committed system.cpu.commit.committedOps 1819780126 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -619,339 +620,341 @@ system.cpu.commit.op_class_0::MemWrite 160728502 8.83% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1819780126 # Class of committed instruction -system.cpu.commit.bw_lim_events 106406211 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 106281090 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3817847910 # The number of ROB reads -system.cpu.rob.rob_writes 5788846951 # The number of ROB writes -system.cpu.timesIdled 724 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 63693 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3840325519 # The number of ROB reads +system.cpu.rob.rob_writes 5790523687 # The number of ROB writes +system.cpu.timesIdled 690 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 70663 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.762689 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.762689 # CPI: Total CPI of All Threads -system.cpu.ipc 1.311151 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.311151 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 3467581476 # number of integer regfile reads -system.cpu.int_regfile_writes 2022302956 # number of integer regfile writes -system.cpu.fp_regfile_reads 46080 # number of floating regfile reads -system.cpu.fp_regfile_writes 592 # number of floating regfile writes +system.cpu.cpi 0.775190 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.775190 # CPI: Total CPI of All Threads +system.cpu.ipc 1.290007 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.290007 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 3468053564 # number of integer regfile reads +system.cpu.int_regfile_writes 2022530151 # number of integer regfile writes +system.cpu.fp_regfile_reads 45442 # number of floating regfile reads +system.cpu.fp_regfile_writes 563 # number of floating regfile writes system.cpu.misc_regfile_reads 25 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 9209012 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.412521 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 713854428 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9213108 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 77.482477 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 5099544250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.412521 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997903 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997903 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 9208756 # number of replacements +system.cpu.dcache.tags.tagsinuse 4087.479772 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 713775439 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9212852 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 77.476056 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 5132407000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.479772 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997920 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997920 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 751 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 2935 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 406 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 697 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 2970 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 425 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1472845170 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1472845170 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 558341279 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 558341279 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 155513145 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 155513145 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1472909430 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1472909430 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 558274718 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 558274718 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 155500717 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 155500717 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 4 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 4 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 713854424 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 713854424 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 713854424 # number of overall hits -system.cpu.dcache.overall_hits::total 713854424 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 12746245 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 12746245 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 5215357 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 5215357 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 713775435 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 713775435 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 713775435 # number of overall hits +system.cpu.dcache.overall_hits::total 713775435 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 12845064 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 12845064 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 5227785 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 5227785 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 17961602 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 17961602 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 17961602 # number of overall misses -system.cpu.dcache.overall_misses::total 17961602 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 384451562750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 384451562750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 289305166008 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 289305166008 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 69500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 673756728758 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 673756728758 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 673756728758 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 673756728758 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 571087524 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 571087524 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 18072849 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 18072849 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 18072849 # number of overall misses +system.cpu.dcache.overall_misses::total 18072849 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 414536288750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 414536288750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 316664843212 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 316664843212 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 72500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 72500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 731201131962 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 731201131962 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 731201131962 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 731201131962 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 571119782 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 571119782 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 5 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 731816026 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 731816026 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 731816026 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 731816026 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022319 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.022319 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032448 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.032448 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 731848284 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 731848284 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 731848284 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 731848284 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022491 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.022491 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032526 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.032526 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.200000 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.200000 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024544 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024544 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.024544 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.024544 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30161.946734 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30161.946734 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55471.785730 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55471.785730 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37510.948564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37510.948564 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37510.948564 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 14120110 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 8634302 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1055091 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 67341 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.382836 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 128.217609 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.024695 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024695 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.024695 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.024695 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32272.029844 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32272.029844 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60573.425114 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 60573.425114 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40458.542644 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40458.542644 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40458.542644 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 15275634 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 9588635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1068737 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67992 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.293165 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 141.025930 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3742780 # number of writebacks -system.cpu.dcache.writebacks::total 3742780 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5412238 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5412238 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3336257 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3336257 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 8748495 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 8748495 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 8748495 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 8748495 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334007 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7334007 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879100 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1879100 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 3742849 # number of writebacks +system.cpu.dcache.writebacks::total 3742849 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5511228 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 5511228 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3348770 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3348770 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 8859998 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 8859998 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 8859998 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 8859998 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333836 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7333836 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1879015 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1879015 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9213107 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9213107 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9213107 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9213107 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168659488250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168659488250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77208966781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77208966781 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 67500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245868455031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245868455031 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245868455031 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245868455031 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012842 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012842 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 9212851 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9212851 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9212851 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9212851 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180521790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 180521790750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83364623703 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83364623703 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 71000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 71000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 263886414453 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 263886414453 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 263886414453 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 263886414453 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.012841 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.012841 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011691 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011691 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.200000 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.200000 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.012589 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.012589 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22996.908545 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22996.908545 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41088.269268 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41088.269268 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67500 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26686.812064 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26686.812064 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.012588 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.012588 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.012588 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24614.920589 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24614.920589 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44366.129969 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44366.129969 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 71000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 71000 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28643.295594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28643.295594 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28643.295594 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 770.158211 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 422456585 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 966 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 437325.657350 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 773.497223 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 422618194 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 975 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 433454.557949 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 770.158211 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.376054 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.376054 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 773.497223 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.377684 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.377684 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 974 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 899 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.471191 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 844917184 # Number of tag accesses -system.cpu.icache.tags.data_accesses 844917184 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 422456585 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 422456585 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 422456585 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 422456585 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 422456585 # number of overall hits -system.cpu.icache.overall_hits::total 422456585 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1524 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1524 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1524 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1524 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1524 # number of overall misses -system.cpu.icache.overall_misses::total 1524 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 107000999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 107000999 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 107000999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 107000999 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 107000999 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 107000999 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 422458109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 422458109 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 422458109 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 422458109 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 422458109 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 422458109 # number of overall (read+write) accesses +system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 906 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.475586 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 845240447 # Number of tag accesses +system.cpu.icache.tags.data_accesses 845240447 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 422618194 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 422618194 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 422618194 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 422618194 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 422618194 # number of overall hits +system.cpu.icache.overall_hits::total 422618194 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1542 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1542 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1542 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1542 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1542 # number of overall misses +system.cpu.icache.overall_misses::total 1542 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 116278500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 116278500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 116278500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 116278500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 116278500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 116278500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 422619736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 422619736 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 422619736 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 422619736 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 422619736 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 422619736 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70210.629265 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70210.629265 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70210.629265 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70210.629265 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70210.629265 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 469 # number of cycles access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75407.587549 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75407.587549 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75407.587549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75407.587549 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75407.587549 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 435 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 67 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 62.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 558 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 558 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 558 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 558 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 558 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 558 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 966 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 966 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 72141249 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 72141249 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 72141249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 72141249 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 72141249 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 72141249 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 567 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 567 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 567 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 567 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 567 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 567 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 975 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 975 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 79199000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 79199000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 79199000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 79199000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 79199000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 79199000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74680.381988 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74680.381988 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74680.381988 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74680.381988 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 81229.743590 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 81229.743590 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 81229.743590 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 81229.743590 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1936441 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31406.538176 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 9110982 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1966231 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.633729 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 27876136750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14557.398525 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.847630 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16822.292021 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.444257 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000819 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.513376 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.958451 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 29790 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 970 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 611 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17653 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10389 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909119 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107500175 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107500175 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.data 6137091 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6137091 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3742780 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3742780 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1107826 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1107826 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.data 7244917 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7244917 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.data 7244917 # number of overall hits -system.cpu.l2cache.overall_hits::total 7244917 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 966 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1196905 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1197871 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 771286 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 771286 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 966 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1968191 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1969157 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 966 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1968191 # number of overall misses -system.cpu.l2cache.overall_misses::total 1969157 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 71167250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98889965000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 98961132250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 63707909498 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 63707909498 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 71167250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 162597874498 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 162669041748 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 71167250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 162597874498 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 162669041748 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 966 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7333996 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7334962 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3742780 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3742780 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879112 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1879112 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 966 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9213108 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9214074 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 966 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9213108 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9214074 # number of overall (read+write) accesses +system.cpu.l2cache.tags.replacements 1936457 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31413.219008 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 9110872 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1966244 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.633643 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 28158140750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14523.555801 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.886283 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16862.776924 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.443224 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000821 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.514611 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.958655 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 29787 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 973 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 615 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17524 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 10518 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909027 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 107498682 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107498682 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.data 6136947 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6136947 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3742849 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3742849 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1107709 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1107709 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.data 7244656 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7244656 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.data 7244656 # number of overall hits +system.cpu.l2cache.overall_hits::total 7244656 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 975 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1196875 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1197850 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 771321 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 771321 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 975 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1968196 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1969171 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 975 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1968196 # number of overall misses +system.cpu.l2cache.overall_misses::total 1969171 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 78215000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 107761725750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 107839940750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 69308457750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 69308457750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 78215000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 177070183500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 177148398500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 78215000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 177070183500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 177148398500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 975 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7333822 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7334797 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3742849 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3742849 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1879030 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1879030 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 975 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9212852 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9213827 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 975 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9212852 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9213827 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163200 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.163310 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.410452 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.410452 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163199 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.163311 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.410489 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.410489 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.213629 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.213712 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.213636 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.213719 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.213629 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.213712 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73672.101449 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82621.398524 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 82614.181535 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82599.592755 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82599.592755 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 82608.467353 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73672.101449 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 82612.853376 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 82608.467353 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.213636 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.213719 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80220.512821 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 90035.906632 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 90027.917310 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89856.827119 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89856.827119 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80220.512821 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89965.726737 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89960.901567 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80220.512821 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89965.726737 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89960.901567 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -960,105 +963,105 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1020337 # number of writebacks -system.cpu.l2cache.writebacks::total 1020337 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 966 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196905 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1197871 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771286 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 771286 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 966 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1968191 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 1969157 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 966 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1968191 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 1969157 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 58998750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 83895775000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 83954773750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54083955498 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54083955498 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 58998750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137979730498 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138038729248 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 58998750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137979730498 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138038729248 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 1020253 # number of writebacks +system.cpu.l2cache.writebacks::total 1020253 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 975 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1196875 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1197850 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 771321 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 771321 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 975 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1968196 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 1969171 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 975 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1968196 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 1969171 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66029500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 92659024750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 92725054250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 59593481750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 59593481750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66029500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 152252506500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 152318536000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66029500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 152252506500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 152318536000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163200 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163310 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410452 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410452 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163199 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163311 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.410489 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.410489 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.213712 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.213719 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213629 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.213712 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61075.310559 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70093.929761 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70086.656869 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70121.790747 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70121.790747 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61075.310559 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70104.847801 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70100.418224 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.213636 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.213719 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67722.564103 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77417.461932 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77409.570689 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77261.583374 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77261.583374 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67722.564103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77356.374314 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77351.604305 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7334962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7334962 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3742780 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1879112 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1879112 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1932 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168996 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22170928 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61824 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829176832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 829238656 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7334797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7334797 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3742849 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1879030 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1879030 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1950 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22168553 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22170503 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 829164864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 829227264 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12957003 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12956676 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 12957003 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 12956676 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12957003 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10221354853 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 12956676 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10221187000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1610750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1642000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14117356000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14136511250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1197871 # Transaction distribution -system.membus.trans_dist::ReadResp 1197871 # Transaction distribution -system.membus.trans_dist::Writeback 1020337 # Transaction distribution -system.membus.trans_dist::ReadExReq 771286 # Transaction distribution -system.membus.trans_dist::ReadExResp 771286 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958651 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4958651 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191327616 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 191327616 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1197850 # Transaction distribution +system.membus.trans_dist::ReadResp 1197850 # Transaction distribution +system.membus.trans_dist::Writeback 1020253 # Transaction distribution +system.membus.trans_dist::ReadExReq 771321 # Transaction distribution +system.membus.trans_dist::ReadExResp 771321 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4958595 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4958595 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 191323136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 191323136 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2989494 # Request fanout histogram +system.membus.snoop_fanout::samples 2989424 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2989494 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 2989424 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2989494 # Request fanout histogram -system.membus.reqLayer0.occupancy 11823428000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 18423304250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.8 # Layer utilization (%) +system.membus.snoop_fanout::total 2989424 # Request fanout histogram +system.membus.reqLayer0.occupancy 7771933000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 10726595500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt index 2d7afdf8e..6346aa78f 100644 --- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.623386 # Number of seconds simulated -sim_ticks 2623386226000 # Number of ticks simulated -final_tick 2623386226000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.623365 # Number of seconds simulated +sim_ticks 2623365440500 # Number of ticks simulated +final_tick 2623365440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1656263 # Simulator instruction rate (inst/s) -host_op_rate 1656263 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2387660297 # Simulator tick rate (ticks/s) -host_mem_usage 289632 # Number of bytes of host memory used -host_seconds 1098.73 # Real time elapsed on the host +host_inst_rate 1411989 # Simulator instruction rate (inst/s) +host_op_rate 1411989 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2035500124 # Simulator tick rate (ticks/s) +host_mem_usage 294160 # Number of bytes of host memory used +host_seconds 1288.81 # Real time elapsed on the host sim_insts 1819780127 # Number of instructions simulated sim_ops 1819780127 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,40 +26,16 @@ system.physmem.num_reads::total 1959663 # Nu system.physmem.num_writes::writebacks 1018077 # Number of write requests responded to by this memory system.physmem.num_writes::total 1018077 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 19566 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 47788276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 47807841 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 47788654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 47808220 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 19566 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 19566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 24836956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 24836956 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 24836956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 24837153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 24837153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 24837153 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 19566 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 47788276 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 72644797 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1178362 # Transaction distribution -system.membus.trans_dist::ReadResp 1178362 # Transaction distribution -system.membus.trans_dist::Writeback 1018077 # Transaction distribution -system.membus.trans_dist::ReadExReq 781301 # Transaction distribution -system.membus.trans_dist::ReadExResp 781301 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2977740 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2977740 # Request fanout histogram -system.membus.reqLayer0.occupancy 11122356000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 17636967000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.physmem.bw_total::cpu.data 47788654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 72645373 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -94,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 29 # Number of system calls -system.cpu.numCycles 5246772452 # number of cpu cycles simulated +system.cpu.numCycles 5246730881 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1819780127 # Number of instructions committed @@ -113,7 +89,7 @@ system.cpu.num_mem_refs 611922547 # nu system.cpu.num_load_insts 449492741 # Number of load instructions system.cpu.num_store_insts 162429806 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5246772452 # Number of busy cycles +system.cpu.num_busy_cycles 5246730881 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 214632552 # Number of branches fetched @@ -152,13 +128,122 @@ system.cpu.op_class::MemWrite 162429806 8.89% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1826378509 # Class of executed instruction +system.cpu.dcache.tags.replacements 9107638 # number of replacements +system.cpu.dcache.tags.tagsinuse 4079.262739 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 40977437000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262739 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits +system.cpu.dcache.overall_hits::total 596212431 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses +system.cpu.dcache.overall_misses::total 9111734 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143355355000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143355355000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57375808000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57375808000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200731163000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200731163000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200731163000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200731163000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19848.675941 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19848.675941 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30368.496602 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30368.496602 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22029.963013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22029.963013 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22029.963013 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks +system.cpu.dcache.writebacks::total 3693497 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132521734000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 132521734000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54541828000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54541828000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187063562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 187063562000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187063562000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187063562000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18348.675941 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18348.675941 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28868.496602 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28868.496602 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20529.963013 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20529.963013 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 612.458646 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 612.458786 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1826377708 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 802 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2277278.937656 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 612.458646 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 612.458786 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.299052 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.299052 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 801 # Occupied blocks per task id @@ -179,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 802 # n system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.icache.overall_misses::total 802 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 44182000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 44182000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 44182000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 44182000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 44182000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 44182000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 44139500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 44139500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 44139500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 44139500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 44139500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 44139500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1826378510 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1826378510 # number of demand (read+write) accesses @@ -197,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55089.775561 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55089.775561 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55089.775561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55089.775561 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55089.775561 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55036.783042 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55036.783042 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55036.783042 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55036.783042 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55036.783042 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -217,43 +302,43 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 802 system.cpu.icache.demand_mshr_misses::total 802 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 802 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 42578000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 42578000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42578000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 42578000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42936500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 42936500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42936500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 42936500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42936500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 42936500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53089.775561 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53089.775561 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53089.775561 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53089.775561 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.783042 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53536.783042 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.783042 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53536.783042 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926937 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30535.257456 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30535.253333 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8959453 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1956729 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.578791 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 218167128000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15221.890655 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064317 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.302484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.464535 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 218167126000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15221.864156 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 39.064589 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15274.324589 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.464534 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001192 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.466135 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.931862 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29792 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1059 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1254 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1060 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1253 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 27303 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909180 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 106294313 # Number of tag accesses @@ -279,17 +364,17 @@ system.cpu.l2cache.demand_misses::total 1959663 # nu system.cpu.l2cache.overall_misses::cpu.inst 802 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958861 # number of overall misses system.cpu.l2cache.overall_misses::total 1959663 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41776000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61258944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61300720000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40629030000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40629030000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 41776000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101887974000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101929750000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 41776000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101887974000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101929750000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 42134500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61828353000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61870487500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41018308500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41018308500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 42134500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102846661500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102888796000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 42134500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102846661500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102888796000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 802 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222414 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223216 # number of ReadReq accesses(hits+misses) @@ -314,17 +399,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.215051 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214982 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.215051 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52089.775561 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52021.930093 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52021.976269 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52001.763725 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52001.763725 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52013.917699 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52089.775561 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52013.886641 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52013.917699 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52536.783042 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52505.479976 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52505.501281 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007679 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007679 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52503.311028 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52536.783042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52503.297324 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52503.311028 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -346,17 +431,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1959663 system.cpu.l2cache.overall_mshr_misses::cpu.inst 802 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958861 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1959663 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32152000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47128224000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47160376000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31253418000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31253418000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32152000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78381642000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78413794000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32152000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78381642000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78413794000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32510000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47697633000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47730143000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642696500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642696500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32510000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79340329500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 79372839500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32510000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79340329500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79372839500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163042 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163135 # mshr miss rate for ReadReq accesses @@ -368,127 +453,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.215051 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214982 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.215051 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40089.775561 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.930093 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40021.976269 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40001.763725 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40001.763725 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40089.775561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40013.886641 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40013.917699 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40536.159601 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40505.479976 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40505.500856 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007679 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007679 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40536.159601 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40503.297324 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40503.310773 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9107638 # number of replacements -system.cpu.dcache.tags.tagsinuse 4079.262869 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 596212431 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9111734 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.433476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 40977439000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4079.262869 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.995914 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1238 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2584 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 200 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1219760064 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1219760064 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 437373249 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 437373249 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 158839182 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 158839182 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 596212431 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 596212431 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 596212431 # number of overall hits -system.cpu.dcache.overall_hits::total 596212431 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222414 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222414 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889320 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889320 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9111734 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9111734 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9111734 # number of overall misses -system.cpu.dcache.overall_misses::total 9111734 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143374726000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143374726000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57377180000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57377180000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200751906000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200751906000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200751906000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200751906000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.016245 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.011755 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015053 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015053 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015053 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015053 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19851.358009 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19851.358009 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30369.222789 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30369.222789 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22032.239528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22032.239528 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22032.239528 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3693497 # number of writebacks -system.cpu.dcache.writebacks::total 3693497 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222414 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889320 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9111734 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9111734 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9111734 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128929898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128929898000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53598540000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53598540000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182528438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182528438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182528438000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182528438000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011755 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.015053 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.015053 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17851.358009 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17851.358009 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28369.222789 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28369.222789 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20032.239528 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20032.239528 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223216 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3693497 # Transaction distribution @@ -518,5 +494,29 @@ system.cpu.toL2Bus.respLayer0.occupancy 1203000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13667601000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1178362 # Transaction distribution +system.membus.trans_dist::ReadResp 1178362 # Transaction distribution +system.membus.trans_dist::Writeback 1018077 # Transaction distribution +system.membus.trans_dist::ReadExReq 781301 # Transaction distribution +system.membus.trans_dist::ReadExResp 781301 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937403 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4937403 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190575360 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2977740 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2977740 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2977740 # Request fanout histogram +system.membus.reqLayer0.occupancy 7156873500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9798315500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt index 1df40303a..0b1bb03bc 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt @@ -1,105 +1,105 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.108725 # Number of seconds simulated -sim_ticks 1108725388000 # Number of ticks simulated -final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.121241 # Number of seconds simulated +sim_ticks 1121241432500 # Number of ticks simulated +final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160331 # Simulator instruction rate (inst/s) -host_op_rate 172733 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 115089854 # Simulator tick rate (ticks/s) -host_mem_usage 301444 # Number of bytes of host memory used -host_seconds 9633.56 # Real time elapsed on the host +host_inst_rate 243175 # Simulator instruction rate (inst/s) +host_op_rate 261985 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 176527853 # Simulator tick rate (ticks/s) +host_mem_usage 312356 # Number of bytes of host memory used +host_seconds 6351.64 # Real time elapsed on the host sim_insts 1544563087 # Number of instructions simulated sim_ops 1664032480 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 131507968 # Number of bytes read from this memory -system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory -system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2054812 # Number of read requests responded to by this memory -system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 45429 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 118611849 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 45429 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 118611849 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 2055599 # Number of read requests accepted -system.physmem.writeReqs 1046417 # Number of write requests accepted -system.physmem.readBursts 2055599 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1046417 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 131472320 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue -system.physmem.bytesWritten 66969088 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 131558336 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 66970688 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue +system.physmem.bytes_read::cpu.inst 50560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 131525952 # Number of bytes read from this memory +system.physmem.bytes_read::total 131576512 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 50560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 50560 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 66977984 # Number of bytes written to this memory +system.physmem.bytes_written::total 66977984 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 790 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2055093 # Number of read requests responded to by this memory +system.physmem.num_reads::total 2055883 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1046531 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1046531 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 45093 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 117303864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 117348956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 45093 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 45093 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 59735559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 59735559 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 59735559 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 45093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 117303864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 177084516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 2055883 # Number of read requests accepted +system.physmem.writeReqs 1046531 # Number of write requests accepted +system.physmem.readBursts 2055883 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1046531 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 131490688 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 85824 # Total number of bytes read from write queue +system.physmem.bytesWritten 66976384 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 131576512 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 66977984 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1341 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 127971 # Per bank write bursts -system.physmem.perBankRdBursts::1 125115 # Per bank write bursts -system.physmem.perBankRdBursts::2 122192 # Per bank write bursts -system.physmem.perBankRdBursts::3 124223 # Per bank write bursts -system.physmem.perBankRdBursts::4 123351 # Per bank write bursts -system.physmem.perBankRdBursts::5 123340 # Per bank write bursts -system.physmem.perBankRdBursts::6 123758 # Per bank write bursts -system.physmem.perBankRdBursts::7 124120 # Per bank write bursts -system.physmem.perBankRdBursts::8 131994 # Per bank write bursts -system.physmem.perBankRdBursts::9 134060 # Per bank write bursts -system.physmem.perBankRdBursts::10 132574 # Per bank write bursts -system.physmem.perBankRdBursts::11 133683 # Per bank write bursts -system.physmem.perBankRdBursts::12 133864 # Per bank write bursts -system.physmem.perBankRdBursts::13 133891 # Per bank write bursts -system.physmem.perBankRdBursts::14 129793 # Per bank write bursts -system.physmem.perBankRdBursts::15 130326 # Per bank write bursts -system.physmem.perBankWrBursts::0 65785 # Per bank write bursts -system.physmem.perBankWrBursts::1 64106 # Per bank write bursts -system.physmem.perBankWrBursts::2 62369 # Per bank write bursts -system.physmem.perBankWrBursts::3 62872 # Per bank write bursts -system.physmem.perBankWrBursts::4 62855 # Per bank write bursts -system.physmem.perBankWrBursts::5 62943 # Per bank write bursts -system.physmem.perBankWrBursts::6 64256 # Per bank write bursts -system.physmem.perBankWrBursts::7 65177 # Per bank write bursts -system.physmem.perBankWrBursts::8 67064 # Per bank write bursts -system.physmem.perBankWrBursts::9 67603 # Per bank write bursts -system.physmem.perBankWrBursts::10 67361 # Per bank write bursts -system.physmem.perBankWrBursts::11 67637 # Per bank write bursts -system.physmem.perBankWrBursts::12 67067 # Per bank write bursts -system.physmem.perBankWrBursts::13 67487 # Per bank write bursts -system.physmem.perBankWrBursts::14 66154 # Per bank write bursts -system.physmem.perBankWrBursts::15 65656 # Per bank write bursts +system.physmem.perBankRdBursts::0 127988 # Per bank write bursts +system.physmem.perBankRdBursts::1 125250 # Per bank write bursts +system.physmem.perBankRdBursts::2 122092 # Per bank write bursts +system.physmem.perBankRdBursts::3 124158 # Per bank write bursts +system.physmem.perBankRdBursts::4 123330 # Per bank write bursts +system.physmem.perBankRdBursts::5 123315 # Per bank write bursts +system.physmem.perBankRdBursts::6 123951 # Per bank write bursts +system.physmem.perBankRdBursts::7 124319 # Per bank write bursts +system.physmem.perBankRdBursts::8 132052 # Per bank write bursts +system.physmem.perBankRdBursts::9 134015 # Per bank write bursts +system.physmem.perBankRdBursts::10 132327 # Per bank write bursts +system.physmem.perBankRdBursts::11 133706 # Per bank write bursts +system.physmem.perBankRdBursts::12 133817 # Per bank write bursts +system.physmem.perBankRdBursts::13 133969 # Per bank write bursts +system.physmem.perBankRdBursts::14 129938 # Per bank write bursts +system.physmem.perBankRdBursts::15 130315 # Per bank write bursts +system.physmem.perBankWrBursts::0 65788 # Per bank write bursts +system.physmem.perBankWrBursts::1 64148 # Per bank write bursts +system.physmem.perBankWrBursts::2 62323 # Per bank write bursts +system.physmem.perBankWrBursts::3 62858 # Per bank write bursts +system.physmem.perBankWrBursts::4 62842 # Per bank write bursts +system.physmem.perBankWrBursts::5 62926 # Per bank write bursts +system.physmem.perBankWrBursts::6 64344 # Per bank write bursts +system.physmem.perBankWrBursts::7 65270 # Per bank write bursts +system.physmem.perBankWrBursts::8 67114 # Per bank write bursts +system.physmem.perBankWrBursts::9 67597 # Per bank write bursts +system.physmem.perBankWrBursts::10 67253 # Per bank write bursts +system.physmem.perBankWrBursts::11 67655 # Per bank write bursts +system.physmem.perBankWrBursts::12 67032 # Per bank write bursts +system.physmem.perBankWrBursts::13 67505 # Per bank write bursts +system.physmem.perBankWrBursts::14 66189 # Per bank write bursts +system.physmem.perBankWrBursts::15 65662 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1108725299500 # Total gap between requests +system.physmem.totGap 1121241338000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 2055599 # Read request sizes (log2) +system.physmem.readPktSize::6 2055883 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1046417 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1922438 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 131799 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1046531 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1926751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -144,27 +144,27 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 32284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 33556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 57018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 60831 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 61268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 61505 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 61466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 61474 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 61478 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 61526 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 61560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 61560 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 62022 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 62349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 61672 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 62578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 61195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 60970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 32090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 33564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 56918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 60994 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 61458 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 61482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 61483 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 61490 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 61494 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 61503 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 61511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 61551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 62299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 61830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 61881 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 62640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 61233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 60987 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -193,104 +193,105 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1917383 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 103.495400 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 81.766538 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 125.134212 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 1491936 77.81% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 306042 15.96% 93.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 52771 2.75% 96.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21239 1.11% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 13137 0.69% 98.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7295 0.38% 98.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 5316 0.28% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4195 0.22% 99.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 15452 0.81% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1917383 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 60970 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 33.645219 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 157.122880 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 60927 99.93% 99.93% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 1919691 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 103.383938 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 81.729389 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 124.654868 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1494811 77.87% 77.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 305161 15.90% 93.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 53151 2.77% 96.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 21323 1.11% 97.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 13050 0.68% 98.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7398 0.39% 98.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5428 0.28% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5020 0.26% 99.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 14349 0.75% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1919691 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 60985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 33.641650 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 160.664141 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 60945 99.93% 99.93% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 60970 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 60970 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.162408 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.127431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.097398 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 27276 44.74% 44.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1165 1.91% 46.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 28420 46.61% 93.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3653 5.99% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 385 0.63% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 61 0.10% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 7 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 60970 # Writes before turning the bus around for reads -system.physmem.totQLat 38268969000 # Total ticks spent queuing -system.physmem.totMemAccLat 76786250250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 10271275000 # Total ticks spent in databus transfers -system.physmem.avgQLat 18629.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 60985 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 60985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.160056 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.125150 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.096252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 27287 44.74% 44.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1323 2.17% 46.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 28176 46.20% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3806 6.24% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 330 0.54% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 51 0.08% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads +system.physmem.totQLat 38434565750 # Total ticks spent queuing +system.physmem.totMemAccLat 76957228250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers +system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 37379.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 118.58 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 60.40 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 118.66 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 60.40 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 37457.12 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 117.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 59.73 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 117.35 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 59.74 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 1.40 # Data bus utilization in percentage -system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads +system.physmem.busUtil 1.38 # Data bus utilization in percentage +system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing -system.physmem.readRowHits 776845 # Number of row buffer hits during reads -system.physmem.writeRowHits 406412 # Number of row buffer hits during writes -system.physmem.readRowHitRate 37.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 38.84 # Row buffer hit rate for writes -system.physmem.avgGap 357420.88 # Average gap between requests -system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 7070973840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 3858170250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 7753512000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 3307152240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 416204777970 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 300142086750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 810753074250 # Total energy per rank (pJ) -system.physmem_0.averagePower 731.249224 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 496624730250 # Time in different power states -system.physmem_0.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing +system.physmem.readRowHits 774810 # Number of row buffer hits during reads +system.physmem.writeRowHits 406537 # Number of row buffer hits during writes +system.physmem.readRowHitRate 37.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes +system.physmem.avgGap 361409.32 # Average gap between requests +system.physmem.pageHitRate 38.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 7080832080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 3863549250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 7756031400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 3308033520 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 422818284195 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 301848259500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 819908647065 # Total energy per rank (pJ) +system.physmem_0.averagePower 731.254419 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 499427924250 # Time in different power states +system.physmem_0.memoryStateTime::REF 37440520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 575075912250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 584369735750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 7424434080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 4051030500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 8269419600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 3473467920 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 425140731810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 292303530750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 813079015860 # Total energy per rank (pJ) -system.physmem_1.averagePower 733.347080 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 483537101750 # Time in different power states -system.physmem_1.memoryStateTime::REF 37022700000 # Time in different power states +system.physmem_1.actEnergy 7432016760 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 4055167875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 8269029600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 3473325360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 431345081205 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 294368613000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 822176890920 # Total energy per rank (pJ) +system.physmem_1.averagePower 733.277404 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 486933261750 # Time in different power states +system.physmem_1.memoryStateTime::REF 37440520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 588165429250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 240158127 # Number of BP lookups -system.cpu.branchPred.condPredicted 186758642 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14604059 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 133657061 # Number of BTB lookups -system.cpu.branchPred.BTBHits 122306338 # Number of BTB hits +system.cpu.branchPred.lookups 240141363 # Number of BP lookups +system.cpu.branchPred.condPredicted 186745178 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 132286201 # Number of BTB lookups +system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 91.507577 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 15659556 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 92.438530 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -410,90 +411,90 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 2217450776 # number of cpu cycles simulated +system.cpu.numCycles 2242482865 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1544563087 # Number of instructions committed system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed -system.cpu.discardedOps 40093383 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 40063389 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.435649 # CPI: cycles per instruction -system.cpu.ipc 0.696549 # IPC: instructions per cycle -system.cpu.tickCycles 1838812013 # Number of cycles that the object actually ticked -system.cpu.idleCycles 378638763 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 9223724 # number of replacements -system.cpu.dcache.tags.tagsinuse 4085.606596 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 624087400 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4085.606596 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997463 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy +system.cpu.cpi 1.451856 # CPI: cycles per instruction +system.cpu.ipc 0.688774 # IPC: instructions per cycle +system.cpu.tickCycles 1838984641 # Number of cycles that the object actually ticked +system.cpu.idleCycles 403498224 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 9223361 # number of replacements +system.cpu.dcache.tags.tagsinuse 4085.642530 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 624067003 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 67.631527 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642530 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 1296 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2482 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 1217 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 453740634 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 170346644 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 453735354 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 453735354 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 624087278 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 624087278 # number of overall hits -system.cpu.dcache.overall_hits::total 624087278 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7337122 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2239403 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9576525 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9576525 # number of overall misses -system.cpu.dcache.overall_misses::total 9576525 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 183400270746 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 101399706750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 284799977496 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 284799977496 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 461077756 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 624066881 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 624066881 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 624066881 # number of overall hits +system.cpu.dcache.overall_hits::total 624066881 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7336762 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7336762 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9591282 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9591282 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9591282 # number of overall misses +system.cpu.dcache.overall_misses::total 9591282 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442349996 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 192442349996 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711138250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 109711138250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 302153488246 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 302153488246 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 302153488246 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 302153488246 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 461072116 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 461072116 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 633663803 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 633663803 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.015113 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.015113 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24996.213876 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45279.794101 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 633658163 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 633658163 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 633658163 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015912 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.015912 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.015136 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.015136 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.015136 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.015136 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.874977 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.874977 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.747835 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.747835 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 31502.930291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 31502.930291 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -502,101 +503,101 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks -system.cpu.dcache.writebacks::total 3701129 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 221 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 348484 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348705 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348705 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336901 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890919 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9227820 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9227820 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168309061254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77322111500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245631172754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245631172754 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses +system.cpu.dcache.writebacks::writebacks 3701040 # number of writebacks +system.cpu.dcache.writebacks::total 3701040 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 208 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363617 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 363617 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 363825 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 363825 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 363825 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 363825 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336554 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7336554 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890903 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1890903 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9227457 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9227457 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9227457 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9227457 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020888504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020888504 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976849000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976849000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997737504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 264997737504 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997737504 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 264997737504 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22940.075279 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40891.286988 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.830317 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.830317 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.976660 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.976660 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 29 # number of replacements -system.cpu.icache.tags.tagsinuse 661.153981 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 466170177 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 568500.215854 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 32 # number of replacements +system.cpu.icache.tags.tagsinuse 661.433391 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 466139352 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 566390.464156 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 661.153981 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.322829 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.322829 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 661.433391 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.322966 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.322966 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 932342814 # Number of tag accesses -system.cpu.icache.tags.data_accesses 932342814 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 466170177 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 466170177 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 466170177 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 466170177 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 466170177 # number of overall hits -system.cpu.icache.overall_hits::total 466170177 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses -system.cpu.icache.overall_misses::total 820 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 58360249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 58360249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 58360249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 58360249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 58360249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 58360249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 466170997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 466170997 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 466170997 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 466170997 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 466170997 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 466170997 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 932281173 # Number of tag accesses +system.cpu.icache.tags.data_accesses 932281173 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 466139352 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 466139352 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 466139352 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 466139352 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 466139352 # number of overall hits +system.cpu.icache.overall_hits::total 466139352 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses +system.cpu.icache.overall_misses::total 823 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 63715999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 63715999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 63715999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 63715999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 63715999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 63715999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 466140175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 466140175 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 466140175 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 466140175 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 466140175 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 466140175 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71171.035366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 71171.035366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 71171.035366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 71171.035366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77419.196841 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77419.196841 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77419.196841 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77419.196841 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -605,123 +606,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56400751 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 56400751 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56400751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 56400751 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56400751 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 56400751 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62148501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 62148501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62148501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 62148501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62148501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 62148501 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68781.403659 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68781.403659 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75514.582017 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75514.582017 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 2022895 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31254.140512 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8985448 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2052670 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 4.377444 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.862616 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 16227.992121 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.457742 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000820 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.495239 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.953801 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 2023178 # number of replacements +system.cpu.l2cache.tags.tagsinuse 31261.935104 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8984732 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2052953 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 4.376492 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 59841737750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 14973.678994 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.751537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 16261.504573 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.456960 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000816 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.496262 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.954039 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12850 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12852 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15555 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 107381741 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 107381741 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 107378416 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 107378416 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6082181 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 6082213 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 3701129 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 3701129 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1090823 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1090823 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6081604 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 6081636 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 3701040 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 3701040 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1090756 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1090756 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 7173004 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 7173036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 7172360 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 7172392 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 7173004 # number of overall hits -system.cpu.l2cache.overall_hits::total 7173036 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 788 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 1254720 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 1255508 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 800096 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 800096 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2054816 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2055604 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2054816 # number of overall misses -system.cpu.l2cache.overall_misses::total 2055604 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55257250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 100145150750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 100200408000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64467346000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 64467346000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 55257250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 164612496750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 164667754000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 55257250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 164612496750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 164667754000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7336901 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 7337721 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 3701129 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 3701129 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890919 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1890919 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9227820 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9228640 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9227820 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9228640 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960976 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171015 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.171103 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423125 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.423125 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960976 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222676 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.222676 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70123.413706 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79814.740141 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79808.657531 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80574.513558 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80574.513558 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80106.749160 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80106.749160 # average overall miss latency +system.cpu.l2cache.overall_hits::cpu.data 7172360 # number of overall hits +system.cpu.l2cache.overall_hits::total 7172392 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 791 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 1254950 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 1255741 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 800147 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 800147 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 791 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2055097 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2055888 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 791 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2055097 # number of overall misses +system.cpu.l2cache.overall_misses::total 2055888 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60988000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109821544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 109882532000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568051000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 70568051000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 60988000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 180389595000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 180450583000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 60988000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 180389595000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 180450583000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 823 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7336554 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 7337377 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 3701040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 3701040 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890903 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1890903 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 823 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 9227457 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9228280 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 823 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 9227457 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9228280 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961118 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171054 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.171143 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423156 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.423156 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961118 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.222715 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.222781 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961118 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.222715 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.222781 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77102.402023 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87510.692856 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.136601 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.858129 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.858129 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 87772.574673 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 87772.574673 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -730,8 +731,8 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks -system.cpu.l2cache.writebacks::total 1046417 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1046531 # number of writebacks +system.cpu.l2cache.writebacks::total 1046531 # number of writebacks system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits @@ -741,107 +742,105 @@ system.cpu.l2cache.demand_mshr_hits::total 5 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254716 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800096 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2054812 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2054812 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45360250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84287306750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54391877500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45360250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138679184250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45360250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138679184250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171014 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57636.912325 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67176.402270 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67981.689072 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 790 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254946 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 1255736 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800147 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 800147 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2055093 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2055883 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2055093 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51087500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006089500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459125500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51087500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414127500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 154465215000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51087500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414127500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 154465215000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423156 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423156 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.222781 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64667.721519 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.347847 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.022721 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.022721 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 7337721 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 3701129 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1890919 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1890919 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156769 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 22158409 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827452736 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 827505216 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 3701040 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1890903 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1890903 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1646 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155954 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 22157600 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52672 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827423808 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 827476480 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 12929769 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 12929320 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12929769 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 12929320 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 12929769 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 10166013500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1389749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1400999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14186681246 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 1255503 # Transaction distribution -system.membus.trans_dist::ReadResp 1255503 # Transaction distribution -system.membus.trans_dist::Writeback 1046417 # Transaction distribution -system.membus.trans_dist::ReadExReq 800096 # Transaction distribution -system.membus.trans_dist::ReadExResp 800096 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157615 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5157615 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198529024 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 198529024 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 1255736 # Transaction distribution +system.membus.trans_dist::ReadResp 1255736 # Transaction distribution +system.membus.trans_dist::Writeback 1046531 # Transaction distribution +system.membus.trans_dist::ReadExReq 800147 # Transaction distribution +system.membus.trans_dist::ReadExResp 800147 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158297 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5158297 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198554496 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 198554496 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3102016 # Request fanout histogram +system.membus.snoop_fanout::samples 3102414 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3102016 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3102414 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3102016 # Request fanout histogram -system.membus.reqLayer0.occupancy 12126859000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 19430032500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 1.8 # Layer utilization (%) +system.membus.snoop_fanout::total 3102414 # Request fanout histogram +system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 11243795500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt index 2039a5a26..d3007a8e0 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.756343 # Number of seconds simulated -sim_ticks 756342731500 # Number of ticks simulated -final_tick 756342731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.771783 # Number of seconds simulated +sim_ticks 771782683000 # Number of ticks simulated +final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 137786 # Simulator instruction rate (inst/s) -host_op_rate 148444 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67471289 # Simulator tick rate (ticks/s) -host_mem_usage 311496 # Number of bytes of host memory used -host_seconds 11209.85 # Real time elapsed on the host +host_inst_rate 141348 # Simulator instruction rate (inst/s) +host_op_rate 152281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 70628369 # Simulator tick rate (ticks/s) +host_mem_usage 310548 # Number of bytes of host memory used +host_seconds 10927.38 # Real time elapsed on the host sim_insts 1544563023 # Number of instructions simulated sim_ops 1664032415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 238887296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 63148480 # Number of bytes read from this memory -system.physmem.bytes_read::total 302102080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 104863424 # Number of bytes written to this memory -system.physmem.bytes_written::total 104863424 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 3732614 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 986695 # Number of read requests responded to by this memory -system.physmem.num_reads::total 4720345 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1638491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1638491 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 87664 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 315845299 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 83491885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 399424847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 87664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 87664 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 138645378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 138645378 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 138645378 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 87664 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 315845299 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 83491885 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 538070225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 4720345 # Number of read requests accepted -system.physmem.writeReqs 1638491 # Number of write requests accepted -system.physmem.readBursts 4720345 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1638491 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 301644480 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 457600 # Total number of bytes read from write queue -system.physmem.bytesWritten 104860480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 302102080 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 104863424 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 7150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one +system.physmem.bytes_read::cpu.inst 66112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 238756480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 63336128 # Number of bytes read from this memory +system.physmem.bytes_read::total 302158720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 66112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 66112 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 104900608 # Number of bytes written to this memory +system.physmem.bytes_written::total 104900608 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 1033 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 3730570 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 989627 # Number of read requests responded to by this memory +system.physmem.num_reads::total 4721230 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1639072 # Number of write requests responded to by this memory +system.physmem.num_writes::total 1639072 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 85661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309357135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 82064718 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 391507515 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 85661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85661 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 135919878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 135919878 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 135919878 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 85661 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309357135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 82064718 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 527427392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 4721230 # Number of read requests accepted +system.physmem.writeReqs 1639072 # Number of write requests accepted +system.physmem.readBursts 4721230 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1639072 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 301708544 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 450176 # Total number of bytes read from write queue +system.physmem.bytesWritten 104898432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 302158720 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 104900608 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 7034 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 296862 # Per bank write bursts -system.physmem.perBankRdBursts::1 294626 # Per bank write bursts -system.physmem.perBankRdBursts::2 288270 # Per bank write bursts -system.physmem.perBankRdBursts::3 292812 # Per bank write bursts -system.physmem.perBankRdBursts::4 290199 # Per bank write bursts -system.physmem.perBankRdBursts::5 289793 # Per bank write bursts -system.physmem.perBankRdBursts::6 284872 # Per bank write bursts -system.physmem.perBankRdBursts::7 281493 # Per bank write bursts -system.physmem.perBankRdBursts::8 297311 # Per bank write bursts -system.physmem.perBankRdBursts::9 303290 # Per bank write bursts -system.physmem.perBankRdBursts::10 295469 # Per bank write bursts -system.physmem.perBankRdBursts::11 301855 # Per bank write bursts -system.physmem.perBankRdBursts::12 303298 # Per bank write bursts -system.physmem.perBankRdBursts::13 302373 # Per bank write bursts -system.physmem.perBankRdBursts::14 297652 # Per bank write bursts -system.physmem.perBankRdBursts::15 293020 # Per bank write bursts -system.physmem.perBankWrBursts::0 104131 # Per bank write bursts -system.physmem.perBankWrBursts::1 101826 # Per bank write bursts -system.physmem.perBankWrBursts::2 99098 # Per bank write bursts -system.physmem.perBankWrBursts::3 99979 # Per bank write bursts -system.physmem.perBankWrBursts::4 99438 # Per bank write bursts -system.physmem.perBankWrBursts::5 99115 # Per bank write bursts -system.physmem.perBankWrBursts::6 102674 # Per bank write bursts -system.physmem.perBankWrBursts::7 104427 # Per bank write bursts -system.physmem.perBankWrBursts::8 105209 # Per bank write bursts -system.physmem.perBankWrBursts::9 104570 # Per bank write bursts -system.physmem.perBankWrBursts::10 102342 # Per bank write bursts -system.physmem.perBankWrBursts::11 102683 # Per bank write bursts -system.physmem.perBankWrBursts::12 102787 # Per bank write bursts -system.physmem.perBankWrBursts::13 102808 # Per bank write bursts -system.physmem.perBankWrBursts::14 104630 # Per bank write bursts -system.physmem.perBankWrBursts::15 102728 # Per bank write bursts +system.physmem.perBankRdBursts::0 296496 # Per bank write bursts +system.physmem.perBankRdBursts::1 294922 # Per bank write bursts +system.physmem.perBankRdBursts::2 288553 # Per bank write bursts +system.physmem.perBankRdBursts::3 293200 # Per bank write bursts +system.physmem.perBankRdBursts::4 290519 # Per bank write bursts +system.physmem.perBankRdBursts::5 289057 # Per bank write bursts +system.physmem.perBankRdBursts::6 284695 # Per bank write bursts +system.physmem.perBankRdBursts::7 280747 # Per bank write bursts +system.physmem.perBankRdBursts::8 297891 # Per bank write bursts +system.physmem.perBankRdBursts::9 303659 # Per bank write bursts +system.physmem.perBankRdBursts::10 295750 # Per bank write bursts +system.physmem.perBankRdBursts::11 302488 # Per bank write bursts +system.physmem.perBankRdBursts::12 303486 # Per bank write bursts +system.physmem.perBankRdBursts::13 302338 # Per bank write bursts +system.physmem.perBankRdBursts::14 297681 # Per bank write bursts +system.physmem.perBankRdBursts::15 292714 # Per bank write bursts +system.physmem.perBankWrBursts::0 104090 # Per bank write bursts +system.physmem.perBankWrBursts::1 102136 # Per bank write bursts +system.physmem.perBankWrBursts::2 99204 # Per bank write bursts +system.physmem.perBankWrBursts::3 100079 # Per bank write bursts +system.physmem.perBankWrBursts::4 99319 # Per bank write bursts +system.physmem.perBankWrBursts::5 99058 # Per bank write bursts +system.physmem.perBankWrBursts::6 102867 # Per bank write bursts +system.physmem.perBankWrBursts::7 104266 # Per bank write bursts +system.physmem.perBankWrBursts::8 105488 # Per bank write bursts +system.physmem.perBankWrBursts::9 104503 # Per bank write bursts +system.physmem.perBankWrBursts::10 102301 # Per bank write bursts +system.physmem.perBankWrBursts::11 102956 # Per bank write bursts +system.physmem.perBankWrBursts::12 103260 # Per bank write bursts +system.physmem.perBankWrBursts::13 102520 # Per bank write bursts +system.physmem.perBankWrBursts::14 104484 # Per bank write bursts +system.physmem.perBankWrBursts::15 102507 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 756342591500 # Total gap between requests +system.physmem.totGap 771782536000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 4720345 # Read request sizes (log2) +system.physmem.readPktSize::6 4721230 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1638491 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2764600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1036830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 329452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 239558 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 162691 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 91104 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 40419 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 23320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 17706 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4471 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1653 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 733 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 418 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1639072 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 2775597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1044443 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 331745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 234202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 153941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 85295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 39428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 23872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 18360 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 4183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1645 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 788 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -148,38 +148,38 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 22698 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 24488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 59650 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 74848 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 84172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 91913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 98459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 103044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 106253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 107840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 108834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 109988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 110978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 113431 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 107071 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 104798 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 103128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 101631 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3003 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 572 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22873 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 24573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 60114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 75847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 93235 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 99435 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 103341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 105611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 106420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 106485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 107133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 108359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 110847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 113228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 106323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 103422 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 101669 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 2755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 22 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see @@ -197,123 +197,121 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 4285614 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 94.853108 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 78.948636 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 101.693693 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 3410667 79.58% 79.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 676414 15.78% 95.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 97051 2.26% 97.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 35005 0.82% 98.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 22710 0.53% 98.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 12276 0.29% 99.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7200 0.17% 99.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 5155 0.12% 99.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 19136 0.45% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 4285614 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 98802 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 47.703225 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::gmean 32.303831 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 97.301104 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-127 94981 96.13% 96.13% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::128-255 1362 1.38% 97.51% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::256-383 759 0.77% 98.28% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::384-511 434 0.44% 98.72% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::512-639 380 0.38% 99.10% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::640-767 348 0.35% 99.46% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::768-895 273 0.28% 99.73% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::896-1023 148 0.15% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-1151 67 0.07% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1152-1279 20 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1280-1407 9 0.01% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1408-1535 8 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1536-1663 4 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::samples 4289012 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 94.801701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 78.923105 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 101.558340 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 3414847 79.62% 79.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 675748 15.76% 95.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 96615 2.25% 97.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 35482 0.83% 98.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 22807 0.53% 98.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 12154 0.28% 99.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7173 0.17% 99.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5164 0.12% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 19022 0.44% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 4289012 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 98837 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 47.696531 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::gmean 32.309771 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 98.301255 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-127 95044 96.16% 96.16% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::128-255 1344 1.36% 97.52% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::384-511 419 0.42% 98.73% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::512-639 374 0.38% 99.10% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::640-767 356 0.36% 99.46% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::768-895 254 0.26% 99.72% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::896-1023 146 0.15% 99.87% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-1151 62 0.06% 99.93% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1152-1279 41 0.04% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1280-1407 8 0.01% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1536-1663 2 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2560-2687 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2816-2943 2 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 98802 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 98802 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 16.583116 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 16.550078 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.089696 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 73349 74.24% 74.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 1793 1.81% 76.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 18295 18.52% 94.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 3696 3.74% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 920 0.93% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 398 0.40% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 161 0.16% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 94 0.10% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 50 0.05% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 24 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 14 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 5 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 98802 # Writes before turning the bus around for reads -system.physmem.totQLat 132475907765 # Total ticks spent queuing -system.physmem.totMemAccLat 220848314015 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 23565975000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28107.45 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2560-2687 3 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 98837 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 98837 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 16.583243 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 16.550199 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.089458 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 73410 74.27% 74.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 1674 1.69% 75.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 18461 18.68% 94.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 3603 3.65% 98.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 928 0.94% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 388 0.39% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 174 0.18% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 100 0.10% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 61 0.06% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 27 0.03% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 7 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 98837 # Writes before turning the bus around for reads +system.physmem.totQLat 132409571838 # Total ticks spent queuing +system.physmem.totMemAccLat 220800746838 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 23570980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28087.41 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 46857.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 398.82 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 138.64 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 399.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 138.65 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 46837.41 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 390.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 135.92 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 391.51 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 135.92 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 4.20 # Data bus utilization in percentage -system.physmem.busUtilRead 3.12 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 1.08 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing -system.physmem.readRowHits 1712938 # Number of row buffer hits during reads -system.physmem.writeRowHits 353078 # Number of row buffer hits during writes -system.physmem.readRowHitRate 36.34 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 21.55 # Row buffer hit rate for writes -system.physmem.avgGap 118943.56 # Average gap between requests -system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 16066436400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 8766408750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 18087404400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5253193440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 400853320515 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 102178887750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 600606152535 # Total energy per rank (pJ) -system.physmem_0.averagePower 794.094387 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 167492103071 # Time in different power states -system.physmem_0.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem.busUtil 4.12 # Data bus utilization in percentage +system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing +system.physmem.readRowHits 1710867 # Number of row buffer hits during reads +system.physmem.writeRowHits 353347 # Number of row buffer hits during writes +system.physmem.readRowHitRate 36.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 21.56 # Row buffer hit rate for writes +system.physmem.avgGap 121343.69 # Average gap between requests +system.physmem.pageHitRate 32.49 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 16078381200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 8772926250 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 18081671400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5255351280 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 410988240855 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 102552687000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 612138233745 # Total energy per rank (pJ) +system.physmem_0.averagePower 793.150023 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 168058001250 # Time in different power states +system.physmem_0.memoryStateTime::REF 25771460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 563593117929 # Time in different power states +system.physmem_0.memoryStateTime::ACT 577951698750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 16332729840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 8911707750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 18675259200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5363826480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 402415744095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 100808340750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 601908109395 # Total energy per rank (pJ) -system.physmem_1.averagePower 795.815775 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 165215512876 # Time in different power states -system.physmem_1.memoryStateTime::REF 25255880000 # Time in different power states +system.physmem_1.actEnergy 16346489040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 8919215250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 18688846800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5365504800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 412404849315 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 101310048000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 613443928965 # Total energy per rank (pJ) +system.physmem_1.averagePower 794.841817 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 165993972457 # Time in different power states +system.physmem_1.memoryStateTime::REF 25771460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 565869633374 # Time in different power states +system.physmem_1.memoryStateTime::ACT 580015821043 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 286251205 # Number of BP lookups -system.cpu.branchPred.condPredicted 223383370 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 14630986 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 158738952 # Number of BTB lookups -system.cpu.branchPred.BTBHits 150334108 # Number of BTB hits +system.cpu.branchPred.lookups 286268512 # Number of BP lookups +system.cpu.branchPred.condPredicted 223399208 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 14631885 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 157652290 # Number of BTB lookups +system.cpu.branchPred.BTBHits 150341382 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 94.705242 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 16640646 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 95.362638 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 16641174 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -432,233 +430,233 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 1512685464 # number of cpu cycles simulated +system.cpu.numCycles 1543565367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 13925295 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 2067334861 # Number of instructions fetch has processed -system.cpu.fetch.Branches 286251205 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 166974754 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1484044715 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 29286501 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.IcacheWaitRetryStallCycles 1090 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 656878260 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 961 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 1512614520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.464203 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.224459 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 13925779 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 2067423618 # Number of instructions fetch has processed +system.cpu.fetch.Branches 286268512 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 166982556 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1514915602 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 29288421 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 919 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 656914213 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 1543486763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.434983 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.229356 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 430302331 28.45% 28.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 465370544 30.77% 59.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 101420857 6.71% 65.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 515520788 34.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 461116597 29.87% 29.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465422138 30.15% 60.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 101389056 6.57% 66.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 515558972 33.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1512614520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.189234 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.366665 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 74740374 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 515177494 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 849893259 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 58160845 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 14642548 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 42195150 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 2036986769 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 52385989 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 14642548 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 139815435 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 436624028 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 12701 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 837804287 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 83715521 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 1976173031 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 26689335 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 45146280 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 125414 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1394915 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 22818803 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 1985649062 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 9127137269 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 2432583454 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 143 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 1543486763 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.185459 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.339382 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 74615169 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 546131714 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 850052649 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 58043724 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 14643507 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 42202613 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 2037139109 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 52472329 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 14643507 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 139680975 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 464946049 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 837873228 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 86328827 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 1976320354 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 26732336 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 45128593 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 125639 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1500891 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 25518898 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 1985788047 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 9127865226 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 2432787425 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 124 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 310750117 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 155 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 111721700 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 542489680 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 199288909 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 26826914 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28715919 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 1947778041 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 1857580897 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 13541153 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 279193675 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 645796508 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 1512614520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.228060 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.150014 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 310889102 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 151 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 141 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 111344488 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 542536301 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 199301557 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 26908887 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 29198248 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 1947883742 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 279518916 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.203385 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.151093 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 560160519 37.03% 37.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 325201183 21.50% 58.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 378431439 25.02% 83.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 219774852 14.53% 98.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 29040355 1.92% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 6172 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 590762659 38.27% 38.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 325764931 21.11% 59.38% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 378272466 24.51% 83.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 219653351 14.23% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 29027182 1.88% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 6174 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 1512614520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 1543486763 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 166509117 41.02% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 1974 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 191277328 47.12% 88.14% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 48123931 11.86% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 166053840 40.99% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 1992 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 191416352 47.25% 88.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 47630536 11.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 1138363415 61.28% 61.28% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 801029 0.04% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 532094788 28.64% 89.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 186321614 10.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 1138248479 61.28% 61.28% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 801009 0.04% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 26 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 532044411 28.64% 89.97% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 186315567 10.03% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 1857580897 # Type of FU issued -system.cpu.iq.rate 1.228002 # Inst issue rate -system.cpu.iq.fu_busy_cnt 405912350 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.218517 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 5647229580 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 2226984572 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 1805831958 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 2263493115 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 17832338 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 1857409514 # Type of FU issued +system.cpu.iq.rate 1.203324 # Inst issue rate +system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 2227415601 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 2262512110 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 17814082 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 84183346 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 66238 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 13114 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 24441864 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 84229967 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 66402 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 24454512 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 4579390 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 4849629 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 4520775 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4802645 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 14642548 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 25281228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1183865 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 1947778336 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 14643507 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 25316113 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 1330365 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 1947884031 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 542489680 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 199288909 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 158613 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1024253 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 13114 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 7709445 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 8723908 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 16433353 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 1827918594 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 516926976 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 29662303 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 542536301 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 199301557 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 148 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 158933 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1170467 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 7700956 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 8705023 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 16405979 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 1827745758 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 516865735 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 29663756 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 81 # number of nop insts executed -system.cpu.iew.exec_refs 698686621 # number of memory reference insts executed -system.cpu.iew.exec_branches 229598858 # Number of branches executed -system.cpu.iew.exec_stores 181759645 # Number of stores executed -system.cpu.iew.exec_rate 1.208393 # Inst execution rate -system.cpu.iew.wb_sent 1808851456 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 1805832027 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1169265268 # num instructions producing a value -system.cpu.iew.wb_consumers 1689455879 # num instructions consuming a value +system.cpu.iew.exec_nop 79 # number of nop insts executed +system.cpu.iew.exec_refs 698617938 # number of memory reference insts executed +system.cpu.iew.exec_branches 229554698 # Number of branches executed +system.cpu.iew.exec_stores 181752203 # Number of stores executed +system.cpu.iew.exec_rate 1.184106 # Inst execution rate +system.cpu.iew.wb_sent 1808737138 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 1805707322 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1169287953 # num instructions producing a value +system.cpu.iew.wb_consumers 1689671414 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.193792 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back +system.cpu.iew.wb_rate 1.169829 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692021 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 257820227 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 257958644 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 14630284 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 1473146552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.129577 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.040655 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 14631182 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 1504006174 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.106400 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.024308 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 893288218 60.64% 60.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 250810214 17.03% 77.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 109558722 7.44% 85.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 55058301 3.74% 88.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 29206870 1.98% 90.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 33934631 2.30% 93.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 24884814 1.69% 94.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 18117903 1.23% 96.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 58286879 3.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 923727407 61.42% 61.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 250637926 16.66% 78.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 110048306 7.32% 85.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 55269063 3.67% 89.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 29308073 1.95% 91.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 34102690 2.27% 93.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 24713726 1.64% 94.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 18129256 1.21% 96.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 58069727 3.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 1473146552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 1504006174 # Number of insts commited each cycle system.cpu.commit.committedInsts 1544563041 # Number of instructions committed system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -704,77 +702,77 @@ system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction -system.cpu.commit.bw_lim_events 58286879 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 3336711734 # The number of ROB reads -system.cpu.rob.rob_writes 3883178493 # The number of ROB writes -system.cpu.timesIdled 871 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 70944 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 3367926925 # The number of ROB reads +system.cpu.rob.rob_writes 3883468057 # The number of ROB writes +system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 1544563023 # Number of Instructions Simulated system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.979361 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.979361 # CPI: Total CPI of All Threads -system.cpu.ipc 1.021073 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.021073 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 2175874054 # number of integer regfile reads -system.cpu.int_regfile_writes 1261590215 # number of integer regfile writes +system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads +system.cpu.ipc 1.000646 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.000646 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 2175695472 # number of integer regfile reads +system.cpu.int_regfile_writes 1261559121 # number of integer regfile writes system.cpu.fp_regfile_reads 38 # number of floating regfile reads -system.cpu.fp_regfile_writes 51 # number of floating regfile writes -system.cpu.cc_regfile_reads 6966029517 # number of cc regfile reads -system.cpu.cc_regfile_writes 551971474 # number of cc regfile writes -system.cpu.misc_regfile_reads 675853074 # number of misc regfile reads +system.cpu.fp_regfile_writes 48 # number of floating regfile writes +system.cpu.cc_regfile_reads 6965502930 # number of cc regfile reads +system.cpu.cc_regfile_writes 551873305 # number of cc regfile writes +system.cpu.misc_regfile_reads 675842878 # number of misc regfile reads system.cpu.misc_regfile_writes 124 # number of misc regfile writes -system.cpu.dcache.tags.replacements 17007297 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.963762 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 638259274 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 17007809 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 37.527425 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 79888000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.963762 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 17005493 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.964646 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 638183172 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 17006005 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 37.526931 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 79063000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.964646 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1335624835 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1335624835 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 469463783 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 469463783 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 168795373 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 168795373 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 1335677307 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1335677307 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 469397613 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 469397613 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 168785441 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 168785441 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 638259156 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 638259156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 638259156 # number of overall hits -system.cpu.dcache.overall_hits::total 638259156 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 17258559 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 17258559 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3790674 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3790674 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 638183054 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 638183054 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 638183054 # number of overall hits +system.cpu.dcache.overall_hits::total 638183054 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 17351867 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 17351867 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3800606 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3800606 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 21049233 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 21049233 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 21049235 # number of overall misses -system.cpu.dcache.overall_misses::total 21049235 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 392276819281 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 392276819281 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 143202458834 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 143202458834 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 535479278115 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 535479278115 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 535479278115 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 535479278115 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 486722342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 486722342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 21152473 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 21152473 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 21152475 # number of overall misses +system.cpu.dcache.overall_misses::total 21152475 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 417182903209 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 417182903209 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 149917932873 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 149917932873 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358750 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 358750 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 567100836082 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 567100836082 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 567100836082 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 567100836082 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 486749480 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 486749480 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) @@ -783,421 +781,419 @@ system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 659308389 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 659308389 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 659308391 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 659308391 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035459 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.035459 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021964 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.021964 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 659335527 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 659335527 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 659335529 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 659335529 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035648 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.035648 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022022 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.022022 # miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.031926 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.031926 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.031926 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.031926 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22729.407437 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 22729.407437 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37777.571702 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37777.571702 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25439.372452 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25439.372452 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 25439.370035 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 25439.370035 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 19976216 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2938205 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 1014245 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 66761 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.695651 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 44.010800 # average number of cycles each access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.032082 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.032082 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.032082 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.032082 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24042.536933 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24042.536933 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39445.797032 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39445.797032 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 89687.500000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 89687.500000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26810.143480 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26810.143480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26810.140945 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26810.140945 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 20723795 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 3315809 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 944207 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 67033 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.948360 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 49.465323 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 4837992 # number of writebacks -system.cpu.dcache.writebacks::total 4837992 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2988204 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 2988204 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1053221 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 1053221 # number of WriteReq MSHR hits +system.cpu.dcache.writebacks::writebacks 4835251 # number of writebacks +system.cpu.dcache.writebacks::total 4835251 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3083373 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 3083373 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1063096 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 1063096 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 4041425 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 4041425 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 4041425 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 4041425 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270355 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 14270355 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737453 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2737453 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 4146469 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 4146469 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 4146469 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 4146469 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268494 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 14268494 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737510 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2737510 # number of WriteReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 17007808 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 17007808 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 17007809 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 17007809 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 303479537034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 303479537034 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 110174073244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 110174073244 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 413653610278 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 413653610278 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 413653672278 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 413653672278 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029319 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029319 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015861 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015861 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 17006004 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 17006004 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 17006005 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 17006005 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 329072767985 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 329072767985 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115107857313 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 115107857313 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444180625298 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 444180625298 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444180693048 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 444180693048 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025796 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025796 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21266.432197 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21266.432197 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40246.927799 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40246.927799 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24321.394637 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24321.394637 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24321.396852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24321.396852 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23062.894233 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23062.894233 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42048.378750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42048.378750 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26119.047443 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26119.047443 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26119.049891 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26119.049891 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 591 # number of replacements -system.cpu.icache.tags.tagsinuse 445.749905 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 656876635 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1079 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 608782.794254 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 588 # number of replacements +system.cpu.icache.tags.tagsinuse 446.068543 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 656912599 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 610513.567844 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 445.749905 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.870605 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.870605 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 446.068543 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.871228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.871228 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1313757597 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1313757597 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 656876635 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 656876635 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 656876635 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 656876635 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 656876635 # number of overall hits -system.cpu.icache.overall_hits::total 656876635 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1624 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1624 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1624 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1624 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1624 # number of overall misses -system.cpu.icache.overall_misses::total 1624 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 95182738 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 95182738 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 95182738 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 95182738 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 95182738 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 95182738 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 656878259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 656878259 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 656878259 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 656878259 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 656878259 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 656878259 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 1313829498 # Number of tag accesses +system.cpu.icache.tags.data_accesses 1313829498 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 656912599 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 656912599 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 656912599 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 656912599 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 656912599 # number of overall hits +system.cpu.icache.overall_hits::total 656912599 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1612 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1612 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1612 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1612 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1612 # number of overall misses +system.cpu.icache.overall_misses::total 1612 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 102924516 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 102924516 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 102924516 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 102924516 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 102924516 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 102924516 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 656914211 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 656914211 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 656914211 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 656914211 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 656914211 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 656914211 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58610.060345 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 58610.060345 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 58610.060345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 58610.060345 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 15932 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 279 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 82.549223 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 39.857143 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63848.955335 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 63848.955335 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 63848.955335 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 63848.955335 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 17306 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 93.043011 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 38.375000 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 545 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 545 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 545 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 545 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 545 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 545 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1079 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1079 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1079 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1079 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1079 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1079 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69657739 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 69657739 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69657739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 69657739 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69657739 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 69657739 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76203217 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 76203217 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76203217 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 76203217 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76203217 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 76203217 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64557.682113 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64557.682113 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70820.833643 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70820.833643 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 10957108 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 11640584 # number of prefetch candidates identified -system.cpu.l2cache.prefetcher.pfBufferHit 428597 # number of redundant prefetches already in prefetch queue +system.cpu.l2cache.prefetcher.num_hwpf_issued 10941726 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 11630409 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.pfBufferHit 431114 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 4655192 # number of prefetches not generated due to page crossing -system.cpu.l2cache.tags.replacements 4712285 # number of replacements -system.cpu.l2cache.tags.tagsinuse 16126.126522 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 15322460 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 4728219 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 3.240641 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 29457635500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 5257.920148 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.981837 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7532.490537 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3316.734000 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.320918 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001159 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.459747 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.202437 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.984261 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 762 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 15172 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 562 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::3 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 487 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2381 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1270 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1696 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.046509 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.926025 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 357015786 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 357015786 # Number of data accesses +system.cpu.l2cache.prefetcher.pfSpanPage 4654951 # number of prefetches not generated due to page crossing +system.cpu.l2cache.tags.replacements 4713207 # number of replacements +system.cpu.l2cache.tags.tagsinuse 16130.406064 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 15325447 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 4729134 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.240646 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 29468558500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 5233.732135 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.908605 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7574.796716 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3302.968608 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.319442 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001154 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.462329 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.201597 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.984522 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 731 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 15196 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 525 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::3 201 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2455 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1253 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9206 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1816 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.044617 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927490 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 356943997 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 356943997 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 43 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 11478119 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 11478162 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 4837992 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 4837992 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1752292 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1752292 # number of ReadExReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 11484174 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 11484217 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 4835251 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 4835251 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1752141 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1752141 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.inst 43 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 13230411 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 13230454 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 13236315 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 13236358 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 43 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 13230411 # number of overall hits -system.cpu.l2cache.overall_hits::total 13230454 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1036 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 2792203 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2793239 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 985195 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 985195 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1036 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 3777398 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3778434 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1036 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 3777398 # number of overall misses -system.cpu.l2cache.overall_misses::total 3778434 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68850750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 219170127718 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 219238978468 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95974587720 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 95974587720 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 68850750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 315144715438 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 315213566188 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 68850750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 315144715438 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 315213566188 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1079 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 14270322 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 14271401 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 4837992 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 4837992 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2737487 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 1079 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 17007809 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 17008888 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1079 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 17007809 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 17008888 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960148 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195665 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.195723 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359890 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.359890 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960148 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.222098 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.222145 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960148 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.222098 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.222145 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66458.252896 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78493.622318 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 78489.158453 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97416.844097 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97416.844097 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 83424.393859 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 83424.393859 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked +system.cpu.l2cache.overall_hits::cpu.data 13236315 # number of overall hits +system.cpu.l2cache.overall_hits::total 13236358 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 2784280 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2785313 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 985410 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 985410 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 3769690 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 3770723 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1033 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 3769690 # number of overall misses +system.cpu.l2cache.overall_misses::total 3770723 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 75372729 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 239047213138 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 239122585867 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100142345987 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 100142345987 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 75372729 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 339189559125 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 339264931854 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 75372729 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 339189559125 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 339264931854 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 14268454 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 14269530 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 4835251 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 4835251 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737551 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2737551 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 17006005 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 17007081 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 17006005 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 17007081 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960037 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195135 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.195193 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359960 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.359960 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960037 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.221668 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.221715 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960037 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.221668 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.221715 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72964.887706 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.024946 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.243960 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101625.055547 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101625.055547 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 89973.443251 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 89973.443251 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 846 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 211.500000 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1638491 # number of writebacks -system.cpu.l2cache.writebacks::total 1638491 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43338 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 43338 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3740 # number of ReadExReq MSHR hits -system.cpu.l2cache.ReadExReq_mshr_hits::total 3740 # number of ReadExReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 47078 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 47078 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 47078 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 47078 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1036 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748865 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2749901 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993225 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 993225 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981455 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 981455 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1036 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 3730320 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3731356 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1036 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 3730320 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993225 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4724581 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59969750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 193568757616 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 193628727366 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68540364307 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87429015038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87429015038 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59969750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 280997772654 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 281057742404 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59969750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 280997772654 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 349598106711 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192628 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192686 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.writebacks::writebacks 1639072 # number of writebacks +system.cpu.l2cache.writebacks::total 1639072 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 36084 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 36084 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3647 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 3647 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 39731 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 39731 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 39731 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 39731 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1033 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748196 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2749229 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993723 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 993723 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981763 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 981763 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1033 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 3729959 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3730992 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1033 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 3729959 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993723 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4724715 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66585771 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212846915589 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212913501360 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 71046693133 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91372170669 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91372170669 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66585771 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304219086258 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 304285672029 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66585771 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304219086258 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 375332365162 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192664 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358524 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.219377 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358628 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358628 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.219379 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.277771 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57885.859073 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70417.702439 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70412.981182 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69007.892781 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89081.022602 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89081.022602 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75323.218263 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73995.579018 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.277809 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64458.636012 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77449.685390 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77444.804111 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71495.470199 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93069.478753 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93069.478753 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81556.238134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79440.212830 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 14271401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 14271401 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 4837992 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 1352607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2737487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2737487 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2158 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38853610 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 38855768 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398131264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 1398200320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 1352607 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 23199492 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.058303 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.234316 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 14269530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 14269530 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 4835251 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 1300143 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2737551 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2737551 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2152 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38847261 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38849413 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68864 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397840384 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1397909248 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 1300143 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 23142477 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.056180 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.230269 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 21846885 94.17% 94.17% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 1352607 5.83% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 21842334 94.38% 94.38% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 1300143 5.62% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 23199492 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 15761436995 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1798250 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 23142477 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 15756418748 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1812271 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 26002804288 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 26100835834 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3738412 # Transaction distribution -system.membus.trans_dist::ReadResp 3738412 # Transaction distribution -system.membus.trans_dist::Writeback 1638491 # Transaction distribution -system.membus.trans_dist::ReadExReq 981933 # Transaction distribution -system.membus.trans_dist::ReadExResp 981933 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11079181 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11079181 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406965504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 406965504 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3739202 # Transaction distribution +system.membus.trans_dist::ReadResp 3739202 # Transaction distribution +system.membus.trans_dist::Writeback 1639072 # Transaction distribution +system.membus.trans_dist::ReadExReq 982028 # Transaction distribution +system.membus.trans_dist::ReadExResp 982028 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11081532 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11081532 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407059328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 407059328 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6358836 # Request fanout histogram +system.membus.snoop_fanout::samples 6360302 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 6358836 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 6360302 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 6358836 # Request fanout histogram -system.membus.reqLayer0.occupancy 20942586092 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 44003891862 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 5.8 # Layer utilization (%) +system.membus.snoop_fanout::total 6360302 # Request fanout histogram +system.membus.reqLayer0.occupancy 14493239223 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 25671846860 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt index c26ad4c6d..a5246083c 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.832017 # Nu sim_ticks 832017490000 # Number of ticks simulated final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1680600 # Simulator instruction rate (inst/s) -host_op_rate 1810592 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 905297170 # Simulator tick rate (ticks/s) -host_mem_usage 301428 # Number of bytes of host memory used -host_seconds 919.05 # Real time elapsed on the host +host_inst_rate 1937211 # Simulator instruction rate (inst/s) +host_op_rate 2087051 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1043527090 # Simulator tick rate (ticks/s) +host_mem_usage 301332 # Number of bytes of host memory used +host_seconds 797.31 # Real time elapsed on the host sim_insts 1544563041 # Number of instructions simulated sim_ops 1664032433 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram -system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram +system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram -system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram +system.membus.snoop_fanout::3 1544565589 71.11% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 2172060894 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt index 89012dc1c..893b8aa6f 100644 --- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.363671 # Number of seconds simulated -sim_ticks 2363670998000 # Number of ticks simulated -final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.363663 # Number of seconds simulated +sim_ticks 2363662966500 # Number of ticks simulated +final_tick 2363662966500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1113267 # Simulator instruction rate (inst/s) -host_op_rate 1199701 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1710076181 # Simulator tick rate (ticks/s) -host_mem_usage 309628 # Number of bytes of host memory used -host_seconds 1382.20 # Real time elapsed on the host +host_inst_rate 1021163 # Simulator instruction rate (inst/s) +host_op_rate 1100446 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1568591191 # Simulator tick rate (ticks/s) +host_mem_usage 309800 # Number of bytes of host memory used +host_seconds 1506.87 # Real time elapsed on the host sim_insts 1538759601 # Number of instructions simulated sim_ops 1658228914 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -26,16 +26,16 @@ system.physmem.num_reads::total 1958774 # Nu system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 53020297 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53036976 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 27542282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 27542282 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 27542282 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 53020297 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 80579258 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 4727341996 # number of cpu cycles simulated +system.cpu.numCycles 4727325933 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 1538759601 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 633153380 # nu system.cpu.num_load_insts 458306334 # Number of load instructions system.cpu.num_store_insts 174847046 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 4727341995.998000 # Number of busy cycles +system.cpu.num_busy_cycles 4727325932.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 213462426 # Number of branches fetched @@ -215,12 +215,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 1664032480 # Class of executed instruction system.cpu.dcache.tags.replacements 9111140 # number of replacements -system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4083.733675 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 25164658000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733675 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -254,14 +254,14 @@ system.cpu.dcache.demand_misses::cpu.data 9115235 # n system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses system.cpu.dcache.overall_misses::total 9115236 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143400508500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143400508500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57355969000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57355969000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200756477500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200756477500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200756477500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200756477500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) @@ -286,14 +286,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19844.838340 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19844.838340 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30360.743912 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30360.743912 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22024.278858 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22024.278858 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22024.276442 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22024.276442 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132561379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 132561379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54522245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54522245500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187083625000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 187083625000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187083678500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187083678500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18344.838340 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18344.838340 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28860.743912 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28860.743912 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20524.278858 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20524.278858 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20524.282476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20524.282476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 7 # number of replacements -system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 515.012767 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 515.012767 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id @@ -373,12 +373,12 @@ system.cpu.icache.demand_misses::cpu.inst 638 # n system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses system.cpu.icache.overall_misses::total 638 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34207000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34207000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34207000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34207000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34207000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34207000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses @@ -391,12 +391,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53615.987461 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53615.987461 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53615.987461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53615.987461 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53615.987461 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -411,37 +411,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 638 system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 33250000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 33250000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 33250000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 33250000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 33250000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 33250000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52115.987461 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52115.987461 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52115.987461 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52115.987461 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926075 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31008.535045 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy +system.cpu.l2cache.tags.warmup_cycle 150067842000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15658.160488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876098 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.498459 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.477849 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.467728 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id @@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 1958774 # nu system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32381000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61822893500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61855274500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40996230000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 40996230000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 32381000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102819123500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102851504500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 32381000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102819123500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102851504500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) @@ -511,17 +511,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214875 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52566.558442 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52513.241093 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52513.268976 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.307347 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.307347 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52508.101751 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52566.558442 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52508.083362 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52508.101751 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,17 +543,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958774 system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24978000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47681937000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47706915000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31625653000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31625653000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24978000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79307590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 79332568000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24978000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79307590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79332568000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses @@ -565,17 +565,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40548.701299 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40501.712419 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40501.736993 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.224107 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.224107 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40548.701299 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40501.118909 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.133873 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution @@ -590,19 +590,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) @@ -630,9 +628,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 2975972 # Request fanout histogram -system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 7175472500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 9807518500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt index 310a8da1f..9a9ddb0f1 100644 --- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.882581 # Number of seconds simulated -sim_ticks 5882580526000 # Number of ticks simulated -final_tick 5882580526000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.882580 # Number of seconds simulated +sim_ticks 5882580398500 # Number of ticks simulated +final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 912016 # Simulator instruction rate (inst/s) -host_op_rate 1421004 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1783532526 # Simulator tick rate (ticks/s) -host_mem_usage 308940 # Number of bytes of host memory used -host_seconds 3298.27 # Real time elapsed on the host +host_inst_rate 733187 # Simulator instruction rate (inst/s) +host_op_rate 1142372 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1433815394 # Simulator tick rate (ticks/s) +host_mem_usage 313792 # Number of bytes of host memory used +host_seconds 4102.75 # Real time elapsed on the host sim_insts 3008081022 # Number of instructions simulated sim_ops 4686862596 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -27,7 +27,7 @@ system.physmem.num_writes::writebacks 1018421 # Nu system.physmem.num_writes::total 1018421 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 7344 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 21304762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 21312105 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 21312106 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 7344 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 7344 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 11079992 # Write bandwidth from this memory (bytes/s) @@ -35,37 +35,11 @@ system.physmem.bw_write::total 11079992 # Wr system.physmem.bw_total::writebacks 11079992 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 7344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 21304762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 32392097 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 1177614 # Transaction distribution -system.membus.trans_dist::ReadResp 1177614 # Transaction distribution -system.membus.trans_dist::Writeback 1018421 # Transaction distribution -system.membus.trans_dist::ReadExReq 781295 # Transaction distribution -system.membus.trans_dist::ReadExResp 781295 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 2977330 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 2977330 # Request fanout histogram -system.membus.reqLayer0.occupancy 11124698000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 17630181000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.3 # Layer utilization (%) +system.physmem.bw_total::total 32392098 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 46 # Number of system calls -system.cpu.numCycles 11765161052 # number of cpu cycles simulated +system.cpu.numCycles 11765160797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 3008081022 # Number of instructions committed @@ -86,7 +60,7 @@ system.cpu.num_mem_refs 1677713084 # nu system.cpu.num_load_insts 1239184746 # Number of load instructions system.cpu.num_store_insts 438528338 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 11765161051.998001 # Number of busy cycles +system.cpu.num_busy_cycles 11765160796.998001 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 248500691 # Number of branches fetched @@ -125,6 +99,115 @@ system.cpu.op_class::MemWrite 438528338 9.36% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 4686862596 # Class of executed instruction +system.cpu.dcache.tags.replacements 9108581 # number of replacements +system.cpu.dcache.tags.tagsinuse 4084.587033 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 58853917000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587033 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits +system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses +system.cpu.dcache.overall_misses::total 9112677 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328499000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 143328499000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382147000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 57382147000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 200710646000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 200710646000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 200710646000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 200710646000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.759596 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.759596 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.703662 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.703662 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 22025.431824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.431824 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22025.431824 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks +system.cpu.dcache.writebacks::total 3697956 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 132494224000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 132494224000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 54547406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 54547406500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 187041630500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 187041630500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 187041630500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 187041630500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18343.759596 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18343.759596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28863.703662 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28863.703662 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20525.431824 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20525.431824 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10 # number of replacements system.cpu.icache.tags.tagsinuse 555.705054 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4013232207 # Total number of references to valid blocks. @@ -152,12 +235,12 @@ system.cpu.icache.demand_misses::cpu.inst 675 # n system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.icache.overall_misses::total 675 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 37156000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 37156000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 37156000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 37156000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 37156000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 37156000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37138500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37138500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37138500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37138500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37138500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37138500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4013232882 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4013232882 # number of demand (read+write) accesses @@ -170,12 +253,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55045.925926 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55045.925926 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55045.925926 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55045.925926 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55045.925926 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55020 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55020 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55020 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55020 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55020 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -190,34 +273,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 675 system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35806000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 35806000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35806000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 35806000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35806000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 35806000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36126000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 36126000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36126000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 36126000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36126000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 36126000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53045.925926 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53045.925926 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53045.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53045.925926 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53520 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53520 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53520 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53520 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 1926197 # number of replacements -system.cpu.l2cache.tags.tagsinuse 31136.249379 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 31136.249311 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8965026 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 1955980 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 4.583393 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 340768635000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795533 # Average occupied blocks per requestor +system.cpu.l2cache.tags.warmup_cycle 340768621000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 15396.795346 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.641016 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812830 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 15713.812949 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.469873 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.479548 # Average percentage of cache occupancy @@ -252,17 +335,17 @@ system.cpu.l2cache.demand_misses::total 1958909 # nu system.cpu.l2cache.overall_misses::cpu.inst 675 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1958234 # number of overall misses system.cpu.l2cache.overall_misses::total 1958909 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35131000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61200881000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 61236012000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40627414000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 40627414000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 35131000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 101828295000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 101863426000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 35131000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 101828295000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 101863426000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 35451000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61789308500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 61824759500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41017993500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41017993500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 35451000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 102807302000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 102842753000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 35451000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 102807302000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 102842753000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 675 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 7222850 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 7223525 # number of ReadReq accesses(hits+misses) @@ -287,17 +370,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.214949 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.214891 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.214949 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52045.925926 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000.045032 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000.071331 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.094715 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000.094715 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000.080657 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52045.925926 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.064854 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000.080657 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52520 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500.009346 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.020805 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500.007680 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500.007680 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52520 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.015570 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52520 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.008681 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.015570 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,17 +402,17 @@ system.cpu.l2cache.demand_mshr_misses::total 1958909 system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1958234 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 1958909 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27031000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47077613000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47104644000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31251874000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31251874000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27031000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78329487000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 78356518000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27031000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78329487000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 78356518000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27350500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47666040500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47693391000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31642453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31642453500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27350500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 79308494000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 79335844500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27350500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 79308494000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 79335844500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162947 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163025 # mshr miss rate for ReadReq accesses @@ -341,127 +424,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.214949 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214891 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.214949 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40045.925926 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000.045032 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000.071331 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000.094715 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000.094715 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40045.925926 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000.064854 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000.080657 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.259259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500.009346 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500.020380 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.007680 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.007680 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.259259 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.008681 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500.015315 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 9108581 # number of replacements -system.cpu.dcache.tags.tagsinuse 4084.587030 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1668600407 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 9112677 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 183.107599 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 58853922000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4084.587030 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.997214 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 2744 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 320 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 3364538845 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 3364538845 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1231961896 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1231961896 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 436638511 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 436638511 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1668600407 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1668600407 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1668600407 # number of overall hits -system.cpu.dcache.overall_hits::total 1668600407 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 7222850 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 7222850 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1889827 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1889827 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 9112677 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9112677 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9112677 # number of overall misses -system.cpu.dcache.overall_misses::total 9112677 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 143328541000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 143328541000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 57382215000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 57382215000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 200710756000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 200710756000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 200710756000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 200710756000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1239184746 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 438528338 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1677713084 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1677713084 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.005829 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.004309 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.005432 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.005432 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.005432 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.005432 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.765411 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.765411 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30363.739644 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30363.739644 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 22025.443895 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.443895 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 22025.443895 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 3697956 # number of writebacks -system.cpu.dcache.writebacks::total 3697956 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 7222850 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1889827 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 9112677 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 9112677 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 9112677 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128882841000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 128882841000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53602561000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 53602561000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182485402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 182485402000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182485402000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 182485402000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.005829 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004309 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.005432 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.005432 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.765411 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.765411 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28363.739644 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28363.739644 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.443895 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.443895 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 7223525 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 3697956 # Transaction distribution @@ -493,5 +467,31 @@ system.cpu.toL2Bus.respLayer0.occupancy 1012500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 13669015500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.trans_dist::ReadReq 1177614 # Transaction distribution +system.membus.trans_dist::ReadResp 1177614 # Transaction distribution +system.membus.trans_dist::Writeback 1018421 # Transaction distribution +system.membus.trans_dist::ReadExReq 781295 # Transaction distribution +system.membus.trans_dist::ReadExResp 781295 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4936239 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 190549120 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 2977330 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2977330 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 2977330 # Request fanout histogram +system.membus.reqLayer0.occupancy 7158077000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 9794545500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt index ae03186ae..e483ad3f0 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.052167 # Number of seconds simulated -sim_ticks 52167245000 # Number of ticks simulated -final_tick 52167245000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.052202 # Number of seconds simulated +sim_ticks 52201532500 # Number of ticks simulated +final_tick 52201532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 211928 # Simulator instruction rate (inst/s) -host_op_rate 211928 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120297341 # Simulator tick rate (ticks/s) -host_mem_usage 286252 # Number of bytes of host memory used -host_seconds 433.65 # Real time elapsed on the host +host_inst_rate 357575 # Simulator instruction rate (inst/s) +host_op_rate 357575 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 203104604 # Simulator tick rate (ticks/s) +host_mem_usage 300132 # Number of bytes of host memory used +host_seconds 257.02 # Real time elapsed on the host sim_insts 91903089 # Number of instructions simulated sim_ops 91903089 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 202688 # Nu system.physmem.num_reads::cpu.inst 3167 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 2151 # Number of read requests responded to by this memory system.physmem.num_reads::total 5318 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 3885350 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2638897 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 6524247 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3885350 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3885350 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2638897 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6524247 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3882798 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2637164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 6519962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3882798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3882798 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3882798 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2637164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6519962 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 5318 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 5318 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 52167163500 # Total gap between requests +system.physmem.totGap 52201444000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4913 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 386 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4919 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 380 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 348.971193 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 211.834828 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 332.374999 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 320 32.92% 32.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191 19.65% 52.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 96 9.88% 62.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 99 10.19% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 63 6.48% 79.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 36 3.70% 82.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.47% 85.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 26 2.67% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 117 12.04% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 972 # Bytes accessed per row activation -system.physmem.totQLat 32099750 # Total ticks spent queuing -system.physmem.totMemAccLat 131812250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 983 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 345.912513 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 209.979760 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 330.521018 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 325 33.06% 33.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 203 20.65% 53.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 90 9.16% 62.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 89 9.05% 71.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 77 7.83% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 32 3.26% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 28 2.85% 85.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 23 2.34% 88.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 116 11.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 983 # Bytes accessed per row activation +system.physmem.totQLat 33415750 # Total ticks spent queuing +system.physmem.totMemAccLat 133128250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 26590000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6036.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6283.52 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24786.06 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25033.52 # Average memory access latency per DRAM burst system.physmem.avgRdBW 6.52 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 6.52 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.05 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4338 # Number of row buffer hits during reads +system.physmem.readRowHits 4331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.44 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 9809545.60 # Average gap between requests -system.physmem.pageHitRate 81.57 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3530520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1926375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19827600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 9815991.73 # Average gap between requests +system.physmem.pageHitRate 81.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3500280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1909875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 19975800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1740830445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29769165000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34942123380 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.898193 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49520504500 # Time in different power states -system.physmem_0.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_0.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1770933285 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29766117750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34971823230 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.967540 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49515286750 # Time in different power states +system.physmem_0.memoryStateTime::REF 1743040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 898118000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 940967000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3772440 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2058375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 21216000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3908520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2132625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 21301800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3406843440 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1807143390 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29710995750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34952029395 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.088108 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49425818250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1741740000 # Time in different power states +system.physmem_1.refreshEnergy 3409386240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1804216725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29736921750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34977867660 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.083336 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49466733750 # Time in different power states +system.physmem_1.memoryStateTime::REF 1743040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 995309750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 989849750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 11476348 # Number of BP lookups -system.cpu.branchPred.condPredicted 8235349 # Number of conditional branches predicted +system.cpu.branchPred.lookups 11476351 # Number of BP lookups +system.cpu.branchPred.condPredicted 8235351 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 785844 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6672654 # Number of BTB lookups -system.cpu.branchPred.BTBHits 5371509 # Number of BTB hits +system.cpu.branchPred.BTBLookups 6672655 # Number of BTB lookups +system.cpu.branchPred.BTBHits 5371510 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.500338 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1176737 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 80.500341 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1176738 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 216 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 26977004 # DT system.cpu.dtb.data_misses 47407 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 27024411 # DTB accesses -system.cpu.itb.fetch_hits 23068130 # ITB hits +system.cpu.itb.fetch_hits 23068140 # ITB hits system.cpu.itb.fetch_misses 88 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 23068218 # ITB accesses +system.cpu.itb.fetch_accesses 23068228 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,26 +293,26 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 104334490 # number of cpu cycles simulated +system.cpu.numCycles 104403065 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903089 # Number of instructions committed system.cpu.committedOps 91903089 # Number of ops (including micro ops) committed system.cpu.discardedOps 2153944 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.135266 # CPI: cycles per instruction -system.cpu.ipc 0.880851 # IPC: instructions per cycle -system.cpu.tickCycles 102681434 # Number of cycles that the object actually ticked -system.cpu.idleCycles 1653056 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.136013 # CPI: cycles per instruction +system.cpu.ipc 0.880272 # IPC: instructions per cycle +system.cpu.tickCycles 102681380 # Number of cycles that the object actually ticked +system.cpu.idleCycles 1721685 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1448.700214 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26568138 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1448.443915 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26568135 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 2230 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11913.963229 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11913.961883 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1448.700214 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.353687 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.353687 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1448.443915 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.353624 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.353624 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 2073 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id @@ -320,16 +320,16 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 system.cpu.dcache.tags.age_task_id_blocks_1024::3 405 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1380 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.506104 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 53145366 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 53145366 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 20069946 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 20069946 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 53145360 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 53145360 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 20069943 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 20069943 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6498192 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6498192 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26568138 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26568138 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26568138 # number of overall hits -system.cpu.dcache.overall_hits::total 26568138 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 26568135 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26568135 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26568135 # number of overall hits +system.cpu.dcache.overall_hits::total 26568135 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 519 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 519 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 2911 # number of WriteReq misses @@ -338,22 +338,22 @@ system.cpu.dcache.demand_misses::cpu.data 3430 # n system.cpu.dcache.demand_misses::total 3430 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 3430 # number of overall misses system.cpu.dcache.overall_misses::total 3430 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 37684500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 37684500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 195045500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 195045500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 232730000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 232730000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 232730000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 232730000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 20070465 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 20070465 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 40365000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 40365000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 216719250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 216719250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 257084250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 257084250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 257084250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 257084250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 20070462 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 20070462 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26571568 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26571568 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26571568 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26571568 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 26571565 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26571565 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26571565 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26571565 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000026 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000448 # miss rate for WriteReq accesses @@ -362,14 +362,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000129 system.cpu.dcache.demand_miss_rate::total 0.000129 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000129 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000129 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72609.826590 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72609.826590 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67002.919959 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 67002.919959 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67851.311953 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67851.311953 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77774.566474 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 77774.566474 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74448.385435 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74448.385435 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74951.676385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74951.676385 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74951.676385 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -396,14 +396,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 2230 system.cpu.dcache.demand_mshr_misses::total 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 2230 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34103500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34103500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 117640500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 117640500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 151744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 151744000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 151744000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 151744000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 37010250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 37010250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 130741250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 130741250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 167751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 167751500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 167751500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 167751500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000268 # mshr miss rate for WriteReq accesses @@ -412,24 +412,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70316.494845 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70316.494845 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67415.759312 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67415.759312 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68046.636771 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68046.636771 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76309.793814 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76309.793814 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74923.352436 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74923.352436 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75224.887892 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75224.887892 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13871 # number of replacements -system.cpu.icache.tags.tagsinuse 1640.665289 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 23052294 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1640.396029 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 23052304 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 15835 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1455.781118 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 1455.781749 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1640.665289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801106 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801106 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1640.396029 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.800975 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.800975 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1964 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id @@ -437,44 +437,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 669 system.cpu.icache.tags.age_task_id_blocks_1024::3 148 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 948 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.958984 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 46152095 # Number of tag accesses -system.cpu.icache.tags.data_accesses 46152095 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 23052294 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 23052294 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 23052294 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 23052294 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 23052294 # number of overall hits -system.cpu.icache.overall_hits::total 23052294 # number of overall hits +system.cpu.icache.tags.tag_accesses 46152115 # Number of tag accesses +system.cpu.icache.tags.data_accesses 46152115 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 23052304 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 23052304 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 23052304 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 23052304 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 23052304 # number of overall hits +system.cpu.icache.overall_hits::total 23052304 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 15836 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 15836 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 15836 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 15836 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 15836 # number of overall misses system.cpu.icache.overall_misses::total 15836 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 386327750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 386327750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 386327750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 386327750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 386327750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 386327750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 23068130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 23068130 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 23068130 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 23068130 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 23068130 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 23068130 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 409644000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 409644000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 409644000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 409644000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 409644000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 409644000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 23068140 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 23068140 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 23068140 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 23068140 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 23068140 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 23068140 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000686 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000686 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000686 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000686 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000686 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24395.538646 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 24395.538646 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 24395.538646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 24395.538646 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 24395.538646 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25867.895933 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25867.895933 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25867.895933 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25867.895933 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25867.895933 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -489,38 +489,38 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 15836 system.cpu.icache.demand_mshr_misses::total 15836 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 15836 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 15836 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 353292250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 353292250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 353292250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 353292250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 353292250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 353292250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 384517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 384517500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 384517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 384517500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 384517500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 384517500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000686 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000686 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000686 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 22309.437358 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 22309.437358 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 22309.437358 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 22309.437358 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24281.226320 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24281.226320 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24281.226320 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24281.226320 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2479.833240 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2479.394298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12735 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3665 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 3.474761 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.780071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2101.017125 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 361.036043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.779390 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2100.640552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 360.974356 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064118 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011018 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.075679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.064106 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011016 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.075665 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 3665 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 66 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 143 # Occupied blocks per task id @@ -554,17 +554,17 @@ system.cpu.l2cache.demand_misses::total 5318 # nu system.cpu.l2cache.overall_misses::cpu.inst 3167 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2151 # number of overall misses system.cpu.l2cache.overall_misses::total 5318 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210776750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33082500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 243859250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 115635000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 115635000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210776750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 148717500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 359494250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210776750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 148717500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 359494250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 235668000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35962750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 271630750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 128723250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 128723250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 235668000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 164686000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 400354000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 235668000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 164686000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 400354000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 15835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 485 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 16320 # number of ReadReq accesses(hits+misses) @@ -589,17 +589,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.294381 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964574 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.294381 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66554.073255 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76579.861111 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67757.502084 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 67268.760908 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 67268.760908 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67599.520496 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66554.073255 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69138.772664 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67599.520496 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74413.640669 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83247.106481 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75473.951098 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74882.635253 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74882.635253 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75282.813088 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74413.640669 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76562.529056 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75282.813088 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5318 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3167 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2151 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5318 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 170928750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27694500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 198623250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93817500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 170928750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 121512000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 292440750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 170928750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 121512000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 292440750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196043000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30551250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 226594250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 107188750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 107188750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196043000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 137740000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 333783000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196043000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 137740000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 333783000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.890722 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.220527 # mshr miss rate for ReadReq accesses @@ -641,17 +641,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.294381 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.200000 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964574 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.294381 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53971.818756 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64107.638889 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55188.455126 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54576.788831 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53971.818756 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56490.934449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 54990.739000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61901.799811 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70720.486111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62960.336205 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62355.293775 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62355.293775 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61901.799811 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.332404 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62764.761188 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 16320 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 16320 # Transaction distribution @@ -678,9 +678,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 18172 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 9193000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 24435250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 24439500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3734000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3770500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 3599 # Transaction distribution system.membus.trans_dist::ReadResp 3599 # Transaction distribution @@ -701,9 +701,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 5318 # Request fanout histogram -system.membus.reqLayer0.occupancy 6478000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 6453000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 50027750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 28232500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt index fbd001a0c..9c86c55d6 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.022159 # Number of seconds simulated -sim_ticks 22159411000 # Number of ticks simulated -final_tick 22159411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.022229 # Number of seconds simulated +sim_ticks 22228749500 # Number of ticks simulated +final_tick 22228749500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 210811 # Simulator instruction rate (inst/s) -host_op_rate 210811 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 55493646 # Simulator tick rate (ticks/s) -host_mem_usage 299980 # Number of bytes of host memory used -host_seconds 399.31 # Real time elapsed on the host +host_inst_rate 212613 # Simulator instruction rate (inst/s) +host_op_rate 212613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56143360 # Simulator tick rate (ticks/s) +host_mem_usage 300388 # Number of bytes of host memory used +host_seconds 395.93 # Real time elapsed on the host sim_insts 84179709 # Number of instructions simulated sim_ops 84179709 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 196160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 138688 # Number of bytes read from this memory -system.physmem.bytes_read::total 334848 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 196160 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 196160 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 2167 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5232 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 8852221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6258650 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15110871 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 8852221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 8852221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 8852221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6258650 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 15110871 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5232 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 196032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 138560 # Number of bytes read from this memory +system.physmem.bytes_read::total 334592 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 196032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 196032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3063 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 2165 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5228 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 8818850 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6233369 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15052219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 8818850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 8818850 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 8818850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6233369 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 15052219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5228 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5232 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5228 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 334848 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 334592 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 334848 # Total read bytes from the system interface side +system.physmem.bytesReadSys 334592 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 471 # Per bank write bursts -system.physmem.perBankRdBursts::1 289 # Per bank write bursts +system.physmem.perBankRdBursts::0 472 # Per bank write bursts +system.physmem.perBankRdBursts::1 290 # Per bank write bursts system.physmem.perBankRdBursts::2 302 # Per bank write bursts -system.physmem.perBankRdBursts::3 527 # Per bank write bursts -system.physmem.perBankRdBursts::4 218 # Per bank write bursts +system.physmem.perBankRdBursts::3 525 # Per bank write bursts +system.physmem.perBankRdBursts::4 219 # Per bank write bursts system.physmem.perBankRdBursts::5 224 # Per bank write bursts -system.physmem.perBankRdBursts::6 217 # Per bank write bursts -system.physmem.perBankRdBursts::7 287 # Per bank write bursts -system.physmem.perBankRdBursts::8 239 # Per bank write bursts -system.physmem.perBankRdBursts::9 281 # Per bank write bursts -system.physmem.perBankRdBursts::10 249 # Per bank write bursts -system.physmem.perBankRdBursts::11 253 # Per bank write bursts -system.physmem.perBankRdBursts::12 396 # Per bank write bursts +system.physmem.perBankRdBursts::6 218 # Per bank write bursts +system.physmem.perBankRdBursts::7 285 # Per bank write bursts +system.physmem.perBankRdBursts::8 238 # Per bank write bursts +system.physmem.perBankRdBursts::9 279 # Per bank write bursts +system.physmem.perBankRdBursts::10 248 # Per bank write bursts +system.physmem.perBankRdBursts::11 252 # Per bank write bursts +system.physmem.perBankRdBursts::12 398 # Per bank write bursts system.physmem.perBankRdBursts::13 338 # Per bank write bursts -system.physmem.perBankRdBursts::14 493 # Per bank write bursts -system.physmem.perBankRdBursts::15 448 # Per bank write bursts +system.physmem.perBankRdBursts::14 491 # Per bank write bursts +system.physmem.perBankRdBursts::15 449 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 22159321500 # Total gap between requests +system.physmem.totGap 22228653000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5232 # Read request sizes (log2) +system.physmem.readPktSize::6 5228 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,12 +90,12 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 631 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 112 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 15 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3268 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1223 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -188,27 +188,27 @@ system.physmem.wrQLenPdf::62 0 # Wh system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 866 # Bytes accessed per row activation system.physmem.bytesPerActivate::mean 383.630485 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 228.084782 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.284844 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 269 31.06% 31.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 171 19.75% 50.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 88 10.16% 60.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 63 7.27% 68.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 38 4.39% 72.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 33 3.81% 76.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 35 4.04% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 46 5.31% 85.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 123 14.20% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 225.895164 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 361.482180 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 274 31.64% 31.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 174 20.09% 51.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 79 9.12% 60.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 66 7.62% 68.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 29 3.35% 71.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 37 4.27% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 36 4.16% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 45 5.20% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 126 14.55% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 866 # Bytes accessed per row activation -system.physmem.totQLat 41292000 # Total ticks spent queuing -system.physmem.totMemAccLat 139392000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 26160000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7892.20 # Average queueing delay per DRAM burst +system.physmem.totQLat 39875750 # Total ticks spent queuing +system.physmem.totMemAccLat 137900750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 26140000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7627.34 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26642.20 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 15.11 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26377.34 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 15.05 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 15.11 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 15.05 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.12 # Data bus utilization in percentage @@ -216,70 +216,70 @@ system.physmem.busUtilRead 0.12 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4354 # Number of row buffer hits during reads +system.physmem.readRowHits 4353 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.22 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.26 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 4235344.32 # Average gap between requests -system.physmem.pageHitRate 83.22 # Row buffer hit rate, read and write combined +system.physmem.avgGap 4251846.40 # Average gap between requests +system.physmem.pageHitRate 83.26 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 3137400 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 1711875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 19453200 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 19476600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 894020490 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 12507056250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14872232415 # Total energy per rank (pJ) -system.physmem_0.averagePower 671.367713 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 20804380500 # Time in different power states -system.physmem_0.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_0.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 894518100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 12548665500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14918939715 # Total energy per rank (pJ) +system.physmem_0.averagePower 671.352430 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 20873521000 # Time in different power states +system.physmem_0.memoryStateTime::REF 742040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 608242500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 606815000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3341520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1823250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 20802600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3349080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1827375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 20794800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1446853200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 920005650 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 12484262250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14877088470 # Total energy per rank (pJ) -system.physmem_1.averagePower 671.586927 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 20766250250 # Time in different power states -system.physmem_1.memoryStateTime::REF 739700000 # Time in different power states +system.physmem_1.refreshEnergy 1451430240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 919030095 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 12527163750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14923595340 # Total energy per rank (pJ) +system.physmem_1.averagePower 671.561933 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 20841181500 # Time in different power states +system.physmem_1.memoryStateTime::REF 742040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 646430250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 642887000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 16298030 # Number of BP lookups -system.cpu.branchPred.condPredicted 11843884 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 974423 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 8872850 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7618799 # Number of BTB hits +system.cpu.branchPred.lookups 16323961 # Number of BP lookups +system.cpu.branchPred.condPredicted 11865379 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 978310 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9045215 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7641567 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 85.866424 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1608574 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 439 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 84.481872 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1608650 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 453 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 24142171 # DTB read hits -system.cpu.dtb.read_misses 235539 # DTB read misses +system.cpu.dtb.read_hits 24152698 # DTB read hits +system.cpu.dtb.read_misses 236585 # DTB read misses system.cpu.dtb.read_acv 2 # DTB read access violations -system.cpu.dtb.read_accesses 24377710 # DTB read accesses -system.cpu.dtb.write_hits 7161357 # DTB write hits -system.cpu.dtb.write_misses 1208 # DTB write misses -system.cpu.dtb.write_acv 1 # DTB write access violations -system.cpu.dtb.write_accesses 7162565 # DTB write accesses -system.cpu.dtb.data_hits 31303528 # DTB hits -system.cpu.dtb.data_misses 236747 # DTB misses -system.cpu.dtb.data_acv 3 # DTB access violations -system.cpu.dtb.data_accesses 31540275 # DTB accesses -system.cpu.itb.fetch_hits 16127186 # ITB hits -system.cpu.itb.fetch_misses 86 # ITB misses +system.cpu.dtb.read_accesses 24389283 # DTB read accesses +system.cpu.dtb.write_hits 7160578 # DTB write hits +system.cpu.dtb.write_misses 1214 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 7161792 # DTB write accesses +system.cpu.dtb.data_hits 31313276 # DTB hits +system.cpu.dtb.data_misses 237799 # DTB misses +system.cpu.dtb.data_acv 2 # DTB access violations +system.cpu.dtb.data_accesses 31551075 # DTB accesses +system.cpu.itb.fetch_hits 16159751 # ITB hits +system.cpu.itb.fetch_misses 85 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 16127272 # ITB accesses +system.cpu.itb.fetch_accesses 16159836 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,139 +293,140 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 44318823 # number of cpu cycles simulated +system.cpu.numCycles 44457500 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 16859439 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 139373095 # Number of instructions fetch has processed -system.cpu.fetch.Branches 16298030 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9227373 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 26218422 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2029202 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 113 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 2359 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 29 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 16127186 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 380559 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 44094963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 3.160749 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.432020 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 16896881 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 139613933 # Number of instructions fetch has processed +system.cpu.fetch.Branches 16323961 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9250217 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 26293708 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2036816 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 2 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 203 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 2338 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 16159751 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 382144 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 44211553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 3.157861 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.431266 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 19653198 44.57% 44.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2660337 6.03% 50.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1339868 3.04% 53.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1948475 4.42% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3047157 6.91% 64.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1303414 2.96% 67.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1381873 3.13% 71.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 894467 2.03% 73.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 11866174 26.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19722112 44.61% 44.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2663068 6.02% 50.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1345508 3.04% 53.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1957580 4.43% 58.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3052640 6.90% 65.01% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1306785 2.96% 67.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1385791 3.13% 71.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 896674 2.03% 73.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 11881395 26.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 44094963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.367745 # Number of branch fetches per cycle -system.cpu.fetch.rate 3.144783 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 13063435 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8246931 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 19674377 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 2107337 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1002883 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 2678530 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 12053 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 133445502 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 49010 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1002883 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 14206625 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 4728440 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8922 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 20521133 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3626960 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 129917938 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 71936 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1987853 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 1348485 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 46206 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 95420653 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 168813407 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 161260201 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 7553205 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 44211553 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.367181 # Number of branch fetches per cycle +system.cpu.fetch.rate 3.140391 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13076592 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 8324763 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 19681975 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 2121490 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1006733 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 2681054 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 12065 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 133596496 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 48387 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1006733 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 14226924 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 4752424 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9184 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 20532599 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 3683689 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 130038627 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 69797 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 2001155 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 1372929 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 55394 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 95511389 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 168978901 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 161414982 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 7563918 # Number of floating rename lookups system.cpu.rename.CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 26993292 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 764 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 773 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 8204907 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 27105677 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 8747640 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 3541499 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1618929 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 112639456 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1940 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 100102500 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 120259 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 27967887 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 21886191 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 1551 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 44094963 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 2.270157 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 2.096378 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 27084028 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 772 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 782 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 8280120 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 27136625 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 8757663 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3565364 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1670156 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 112744524 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2237 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 100145020 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 122649 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 28075682 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 21979359 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 1848 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 44211553 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 2.265132 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 2.094303 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11535006 26.16% 26.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 7754470 17.59% 43.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7555421 17.13% 60.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5737104 13.01% 73.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 4489384 10.18% 84.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2977388 6.75% 90.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2013844 4.57% 95.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 1160432 2.63% 98.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 871914 1.98% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11585483 26.20% 26.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 7800031 17.64% 43.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7580714 17.15% 60.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5746471 13.00% 73.99% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 4482670 10.14% 84.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2978699 6.74% 90.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2013201 4.55% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 1153505 2.61% 98.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 870779 1.97% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 44094963 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 44211553 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 479018 20.14% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.14% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 443 0.02% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.16% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 33638 1.41% 21.58% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 11723 0.49% 22.07% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 1006429 42.32% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.39% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 686405 28.86% 93.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 160330 6.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 481856 20.25% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 20.25% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 350 0.01% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 34531 1.45% 21.71% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 11644 0.49% 22.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 1006485 42.29% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 64.50% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 687304 28.88% 93.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 157568 6.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 60895268 60.83% 60.83% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 491428 0.49% 61.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 60921013 60.83% 60.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 491088 0.49% 61.32% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2836761 2.83% 64.16% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 115534 0.12% 64.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 2437739 2.44% 66.71% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 313998 0.31% 67.02% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 765483 0.76% 67.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2841000 2.84% 64.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 115643 0.12% 64.28% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 2440640 2.44% 66.71% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 314095 0.31% 67.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 766051 0.76% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 319 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.79% # Type of FU issued @@ -447,84 +448,84 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.79% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.79% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.79% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 24980978 24.96% 92.74% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 7264985 7.26% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 24991126 24.95% 92.75% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 7264038 7.25% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 100102500 # Type of FU issued -system.cpu.iq.rate 2.258690 # Inst issue rate -system.cpu.iq.fu_busy_cnt 2377986 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023756 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 231175586 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 131029945 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 90008848 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 15622622 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 9621224 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 7166740 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 94135370 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 8345109 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1908744 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 100145020 # Type of FU issued +system.cpu.iq.rate 2.252601 # Inst issue rate +system.cpu.iq.fu_busy_cnt 2379738 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023763 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 231363005 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 131215529 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 90039702 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 15640975 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 9648680 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 7175345 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 94170320 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 8354431 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1902679 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 7109479 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 10719 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 42241 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 2246537 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 7140427 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 11100 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 42139 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 2256560 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 42761 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 2468 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 42760 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 1687 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1002883 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 3707612 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 461807 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 123638491 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 278104 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 27105677 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 8747640 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1940 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 39979 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 414885 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 42241 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 554445 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 525545 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1079990 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 98729735 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 24378234 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1372765 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1006733 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3731793 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 447885 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 123749930 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 277756 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 27136625 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 8757663 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2237 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 43684 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 396903 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 42139 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 560048 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 524506 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1084554 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 98770041 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 24389817 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1374979 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 10997095 # number of nop insts executed -system.cpu.iew.exec_refs 31540837 # number of memory reference insts executed -system.cpu.iew.exec_branches 12532490 # Number of branches executed -system.cpu.iew.exec_stores 7162603 # Number of stores executed -system.cpu.iew.exec_rate 2.227716 # Inst execution rate -system.cpu.iew.wb_sent 97918369 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 97175588 # cumulative count of insts written-back -system.cpu.iew.wb_producers 67088120 # num instructions producing a value -system.cpu.iew.wb_consumers 95122376 # num instructions consuming a value +system.cpu.iew.exec_nop 11003169 # number of nop insts executed +system.cpu.iew.exec_refs 31551638 # number of memory reference insts executed +system.cpu.iew.exec_branches 12536484 # Number of branches executed +system.cpu.iew.exec_stores 7161821 # Number of stores executed +system.cpu.iew.exec_rate 2.221673 # Inst execution rate +system.cpu.iew.wb_sent 97959187 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 97215047 # cumulative count of insts written-back +system.cpu.iew.wb_producers 67118954 # num instructions producing a value +system.cpu.iew.wb_consumers 95176065 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 2.192648 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.705282 # average fanout of values written-back +system.cpu.iew.wb_rate 2.186696 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.705208 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 31736961 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 31848480 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 962705 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 39466887 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 2.328612 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 2.908948 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 966635 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 39567002 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 2.322720 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 2.905630 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 14969500 37.93% 37.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 8597582 21.78% 59.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3898491 9.88% 69.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 1956472 4.96% 74.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1378246 3.49% 78.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1028775 2.61% 80.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 694003 1.76% 82.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 732346 1.86% 84.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6211472 15.74% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15032687 37.99% 37.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 8622118 21.79% 59.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3917590 9.90% 69.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 1951695 4.93% 74.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1384336 3.50% 78.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1033619 2.61% 80.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 694183 1.75% 82.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 726057 1.84% 84.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6204717 15.68% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 39466887 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 39567002 # Number of insts commited each cycle system.cpu.commit.committedInsts 91903055 # Number of instructions committed system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -570,345 +571,345 @@ system.cpu.commit.op_class_0::MemWrite 6501103 7.07% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 91903055 # Class of committed instruction -system.cpu.commit.bw_lim_events 6211472 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6204717 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 156894391 # The number of ROB reads -system.cpu.rob.rob_writes 251967276 # The number of ROB writes -system.cpu.timesIdled 4539 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 223860 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 157112780 # The number of ROB reads +system.cpu.rob.rob_writes 252206838 # The number of ROB writes +system.cpu.timesIdled 4633 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 245947 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.526479 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.526479 # CPI: Total CPI of All Threads -system.cpu.ipc 1.899412 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.899412 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 133358103 # number of integer regfile reads -system.cpu.int_regfile_writes 73122882 # number of integer regfile writes -system.cpu.fp_regfile_reads 6250590 # number of floating regfile reads -system.cpu.fp_regfile_writes 6153622 # number of floating regfile writes -system.cpu.misc_regfile_reads 718773 # number of misc regfile reads +system.cpu.cpi 0.528126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.528126 # CPI: Total CPI of All Threads +system.cpu.ipc 1.893487 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.893487 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 133407543 # number of integer regfile reads +system.cpu.int_regfile_writes 73150911 # number of integer regfile writes +system.cpu.fp_regfile_reads 6256040 # number of floating regfile reads +system.cpu.fp_regfile_writes 6161921 # number of floating regfile writes +system.cpu.misc_regfile_reads 718993 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes -system.cpu.dcache.tags.replacements 160 # number of replacements -system.cpu.dcache.tags.tagsinuse 1457.564933 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 28680753 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2248 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12758.342082 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 159 # number of replacements +system.cpu.dcache.tags.tagsinuse 1458.668074 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 28697534 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2246 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12777.174533 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1457.564933 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.355851 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2088 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1458.668074 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.356120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.356120 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2087 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 542 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1388 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.509766 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 57382576 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 57382576 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22187756 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22187756 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6492735 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6492735 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 262 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 262 # number of LoadLockedReq hits -system.cpu.dcache.demand_hits::cpu.data 28680491 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 28680491 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 28680491 # number of overall hits -system.cpu.dcache.overall_hits::total 28680491 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1042 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1042 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 8368 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 8368 # number of WriteReq misses +system.cpu.dcache.tags.age_task_id_blocks_1024::2 541 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1390 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.509521 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 57416312 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 57416312 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 22204643 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22204643 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6492628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6492628 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 263 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 263 # number of LoadLockedReq hits +system.cpu.dcache.demand_hits::cpu.data 28697271 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 28697271 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 28697271 # number of overall hits +system.cpu.dcache.overall_hits::total 28697271 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1023 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1023 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 8475 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 8475 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 9410 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 9410 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 9410 # number of overall misses -system.cpu.dcache.overall_misses::total 9410 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 65475750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 65475750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 523849968 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 523849968 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 92750 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 589325718 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 589325718 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 589325718 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 589325718 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 22188798 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 22188798 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 9498 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 9498 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 9498 # number of overall misses +system.cpu.dcache.overall_misses::total 9498 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 69711000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 69711000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 550954965 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 550954965 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 85000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 620665965 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 620665965 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 620665965 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 620665965 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 22205666 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 22205666 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 263 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 28689901 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 28689901 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 28689901 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 28689901 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000047 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001287 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003802 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000328 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000328 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000328 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000328 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62836.612284 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62836.612284 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62601.573614 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62601.573614 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 92750 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 92750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62627.600213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62627.600213 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62627.600213 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 29227 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 416 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 894 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 32.692394 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 208 # average number of cycles each access was blocked +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 264 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 264 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 28706769 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 28706769 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 28706769 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 28706769 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001304 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.003788 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000331 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000331 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000331 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000331 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68143.695015 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68143.695015 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65009.435398 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 65009.435398 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 85000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 85000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 65347.016740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 65347.016740 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 65347.016740 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 33287 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 426 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.138498 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 110 # number of writebacks -system.cpu.dcache.writebacks::total 110 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 529 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 529 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6634 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 6634 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 7163 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 7163 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 7163 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 513 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 513 # number of ReadReq MSHR misses +system.cpu.dcache.writebacks::writebacks 109 # number of writebacks +system.cpu.dcache.writebacks::total 109 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 512 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6741 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 6741 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 7253 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 7253 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 7253 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 7253 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 511 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 511 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1734 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 1734 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2247 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2247 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2247 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36153000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 36153000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 125731745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 125731745 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 90250 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 161884745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 161884745 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 161884745 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 161884745 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2245 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2245 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2245 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38736500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 38736500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 136484495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 136484495 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 83500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 83500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 175220995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 175220995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 175220995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 175220995 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000267 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000267 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003802 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003802 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.003788 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.003788 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000078 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000078 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000078 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70473.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70473.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72509.656863 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72509.656863 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 90250 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72044.835336 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72044.835336 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75805.283757 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75805.283757 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78710.781430 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78710.781430 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 83500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 83500 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78049.440980 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78049.440980 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 9583 # number of replacements -system.cpu.icache.tags.tagsinuse 1600.631053 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 16112652 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 11519 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1398.789131 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 9845 # number of replacements +system.cpu.icache.tags.tagsinuse 1600.510636 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 16144798 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 11783 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1370.177204 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1600.631053 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.781558 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.781558 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1936 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 763 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 930 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 32265889 # Number of tag accesses -system.cpu.icache.tags.data_accesses 32265889 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 16112652 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 16112652 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 16112652 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 16112652 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 16112652 # number of overall hits -system.cpu.icache.overall_hits::total 16112652 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14533 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14533 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14533 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14533 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14533 # number of overall misses -system.cpu.icache.overall_misses::total 14533 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 419570250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 419570250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 419570250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 419570250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 419570250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 419570250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 16127185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 16127185 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 16127185 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 16127185 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 16127185 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 16127185 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000901 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000901 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000901 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000901 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000901 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000901 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28870.174775 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 28870.174775 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 28870.174775 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 28870.174775 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 28870.174775 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1600.510636 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.781499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.781499 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1938 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 760 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 936 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.946289 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 32331281 # Number of tag accesses +system.cpu.icache.tags.data_accesses 32331281 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 16144798 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 16144798 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 16144798 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 16144798 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 16144798 # number of overall hits +system.cpu.icache.overall_hits::total 16144798 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14951 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14951 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14951 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14951 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14951 # number of overall misses +system.cpu.icache.overall_misses::total 14951 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 446766000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 446766000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 446766000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 446766000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 446766000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 446766000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 16159749 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 16159749 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 16159749 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 16159749 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 16159749 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 16159749 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000925 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000925 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000925 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000925 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000925 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000925 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29882.014581 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 29882.014581 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 29882.014581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 29882.014581 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 29882.014581 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 39.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 55.777778 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3014 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 3014 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 3014 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 3014 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 3014 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11519 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 11519 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 11519 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 11519 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 11519 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 11519 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 306551250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 306551250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 306551250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 306551250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 306551250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 306551250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000714 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000714 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000714 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 26612.661689 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 26612.661689 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26612.661689 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 26612.661689 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3168 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 3168 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 3168 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 3168 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 3168 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 3168 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 11783 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 11783 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 11783 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 11783 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 11783 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 11783 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 332403750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 332403750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 332403750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 332403750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 332403750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 332403750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000729 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000729 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000729 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000729 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28210.451498 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28210.451498 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28210.451498 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 28210.451498 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2401.991328 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 8524 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3591 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 2.373712 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2407.331968 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 8790 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3587 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 2.450516 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.703660 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2007.347225 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 376.940444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.698797 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2011.289043 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 378.344128 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000540 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061259 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.011503 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.073303 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3591 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 915 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2425 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109589 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 116342 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 116342 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 8454 # number of ReadReq hits +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061380 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.011546 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.073466 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3587 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 911 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2430 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.109467 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 118425 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 118425 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 8720 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 55 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 8509 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 110 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 110 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::total 8775 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 109 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 109 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 8454 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 8720 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 81 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 8535 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 8454 # number of overall hits +system.cpu.l2cache.demand_hits::total 8801 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 8720 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 81 # number of overall hits -system.cpu.l2cache.overall_hits::total 8535 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3065 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 458 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3523 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 1709 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 1709 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3065 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 2167 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5232 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3065 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 2167 # number of overall misses -system.cpu.l2cache.overall_misses::total 5232 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 210484500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35100000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 245584500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 123658250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 123658250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 210484500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 158758250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 369242750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 210484500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 158758250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 369242750 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 11519 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 513 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 12032 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 110 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 110 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 1735 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 11519 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2248 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 13767 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 11519 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2248 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 13767 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.266082 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892788 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.292803 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985014 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.985014 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.266082 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.963968 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.380039 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.266082 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.963968 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.380039 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68673.572594 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76637.554585 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69708.912858 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72357.080164 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72357.080164 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70573.920107 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68673.572594 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73261.767420 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70573.920107 # average overall miss latency +system.cpu.l2cache.overall_hits::total 8801 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3063 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 457 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3520 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 1708 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 1708 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 3063 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 2165 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5228 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3063 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 2165 # number of overall misses +system.cpu.l2cache.overall_misses::total 5228 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 229052250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 37709500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 266761750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 134332250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 134332250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 229052250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 172041750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 401094000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 229052250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 172041750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 401094000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 11783 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 512 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 12295 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 109 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 1734 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 1734 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 11783 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2246 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 14029 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 11783 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2246 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 14029 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.259951 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.892578 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.286295 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.985006 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.985006 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.259951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.963936 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.372657 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.259951 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.963936 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.372657 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74780.362390 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82515.317287 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75784.588068 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78648.858314 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78648.858314 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74780.362390 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79465.011547 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76720.351951 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74780.362390 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79465.011547 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76720.351951 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -917,102 +918,102 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3065 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 458 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3523 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1709 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 1709 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3065 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 2167 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5232 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3065 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 2167 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5232 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 171659500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29415000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 201074500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 102798250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 102798250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 171659500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132213250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 303872750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 171659500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132213250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 303872750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892788 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.292803 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985014 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.380039 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.266082 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963968 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.380039 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56006.362153 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64224.890830 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57074.794209 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60151.111761 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60151.111761 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56006.362153 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61012.113521 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58079.654052 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 457 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3520 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1708 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1708 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 2165 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5228 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 2165 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5228 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 190854250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 31997500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 222851750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 113271750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 113271750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 190854250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 145269250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 336123500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 190854250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 145269250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 336123500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.892578 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.286295 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985006 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.372657 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.259951 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.372657 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62309.582109 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70016.411379 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63310.156250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66318.354801 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66318.354801 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62309.582109 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67098.960739 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64292.941852 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 12032 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 110 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 1735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 1735 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23038 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4606 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 27644 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 737216 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150912 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 888128 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 12295 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 109 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1734 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1734 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 23566 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4601 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 28167 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 754112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 150720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 904832 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 13877 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 14138 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 13877 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 14138 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 13877 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7048500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 14138 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7178000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 17856250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 18279750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3547750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3635750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3523 # Transaction distribution -system.membus.trans_dist::ReadResp 3523 # Transaction distribution -system.membus.trans_dist::ReadExReq 1709 # Transaction distribution -system.membus.trans_dist::ReadExResp 1709 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10464 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334848 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 334848 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3520 # Transaction distribution +system.membus.trans_dist::ReadResp 3520 # Transaction distribution +system.membus.trans_dist::ReadExReq 1708 # Transaction distribution +system.membus.trans_dist::ReadExResp 1708 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10456 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 334592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 334592 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5232 # Request fanout histogram +system.membus.snoop_fanout::samples 5228 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5232 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5228 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5232 # Request fanout histogram -system.membus.reqLayer0.occupancy 6529000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5228 # Request fanout histogram +system.membus.reqLayer0.occupancy 6467500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 48920250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 27502000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 4e099442b..85445221a 100644 --- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.118729 # Number of seconds simulated -sim_ticks 118729316000 # Number of ticks simulated -final_tick 118729316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 118729316500 # Number of ticks simulated +final_tick 118729316500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1660785 # Simulator instruction rate (inst/s) -host_op_rate 1660785 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2145562848 # Simulator tick rate (ticks/s) -host_mem_usage 293264 # Number of bytes of host memory used -host_seconds 55.34 # Real time elapsed on the host +host_inst_rate 1507080 # Simulator instruction rate (inst/s) +host_op_rate 1507080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1946992285 # Simulator tick rate (ticks/s) +host_mem_usage 297820 # Number of bytes of host memory used +host_seconds 60.98 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,29 +29,6 @@ system.physmem.bw_inst_read::total 1412827 # In system.physmem.bw_total::cpu.inst 1412827 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155704 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2568532 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3043 # Transaction distribution -system.membus.trans_dist::ReadResp 3043 # Transaction distribution -system.membus.trans_dist::ReadExReq 1722 # Transaction distribution -system.membus.trans_dist::ReadExResp 1722 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4765 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4765 # Request fanout histogram -system.membus.reqLayer0.occupancy 4765000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 42885000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls -system.cpu.numCycles 237458632 # number of cpu cycles simulated +system.cpu.numCycles 237458633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 91903056 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 26497334 # nu system.cpu.num_load_insts 19996208 # Number of load instructions system.cpu.num_store_insts 6501126 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 237458632 # Number of busy cycles +system.cpu.num_busy_cycles 237458633 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 10240685 # Number of branches fetched @@ -144,13 +121,122 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.cpu.dcache.tags.replacements 157 # number of replacements +system.cpu.dcache.tags.tagsinuse 1442.043377 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043377 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits +system.cpu.dcache.overall_hits::total 26495078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses +system.cpu.dcache.overall_misses::total 2223 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 107 # number of writebacks +system.cpu.dcache.writebacks::total 107 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23186500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 92426000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 115612500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 115612500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48813.684211 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52875.286041 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52007.422402 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52007.422402 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 6681 # number of replacements -system.cpu.icache.tags.tagsinuse 1418.052773 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1418.052759 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 8510 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 10798.423032 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052773 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1418.052759 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.692409 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1829 # Occupied blocks per task id @@ -174,12 +260,12 @@ system.cpu.icache.demand_misses::cpu.inst 8510 # n system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses system.cpu.icache.overall_misses::total 8510 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 220712000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 220712000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 220712000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 220712000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 220712500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 220712500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 220712500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 220712500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 220712500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses @@ -192,12 +278,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.605170 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25935.605170 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.605170 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25935.605170 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25935.663925 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25935.663925 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25935.663925 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25935.663925 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -212,34 +298,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 8510 system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 207947500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 207947500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 207947500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 207947500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000093 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000093 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000093 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23935.605170 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23935.605170 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 24435.663925 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 24435.663925 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 24435.663925 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2074.070560 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2074.070538 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 5956 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3109 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 1.915729 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 17.795178 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.018003 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257379 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 17.795177 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1705.017985 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 351.257376 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000543 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.052033 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.010720 # Average percentage of cache occupancy @@ -277,17 +363,17 @@ system.cpu.l2cache.demand_misses::total 4765 # nu system.cpu.l2cache.overall_misses::cpu.inst 2621 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 2144 # number of overall misses system.cpu.l2cache.overall_misses::total 4765 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 136292000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 21944000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 158236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 89544000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 136292000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 111488000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 247780000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 136292000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 111488000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 247780000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137603000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22155000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 159758000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 90405000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137603000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 112560000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 250163000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137603000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 112560000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 250163000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 8510 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 8985 # number of ReadReq accesses(hits+misses) @@ -312,17 +398,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.443958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.307991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.964462 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.443958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.190767 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.164312 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.104932 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.190767 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.104932 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -342,17 +428,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4765 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2621 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 2144 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4765 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104840000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 121720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 68880000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85760000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 190600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104840000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85760000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 190600000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 106150500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 17091000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 123241500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 69741000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 106150500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 86832000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 192982500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 106150500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 86832000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 192982500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.338676 # mshr miss rate for ReadReq accesses @@ -364,127 +450,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.443958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.443958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 157 # number of replacements -system.cpu.dcache.tags.tagsinuse 1442.043392 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11918.613585 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1442.043392 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352061 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 487 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 6499355 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 26495078 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 26495078 # number of overall hits -system.cpu.dcache.overall_hits::total 26495078 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1748 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2223 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 2223 # number of overall misses -system.cpu.dcache.overall_misses::total 2223 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 23899000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 23899000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 95048000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 95048000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 118947000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 118947000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 118947000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 26497301 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000084 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000084 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50313.684211 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50313.684211 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54375.286041 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54375.286041 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53507.422402 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53507.422402 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 107 # number of writebacks -system.cpu.dcache.writebacks::total 107 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 22949000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 91552000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 114501000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 114501000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 48313.684211 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52375.286041 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51507.422402 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution @@ -514,5 +491,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3043 # Transaction distribution +system.membus.trans_dist::ReadResp 3043 # Transaction distribution +system.membus.trans_dist::ReadExReq 1722 # Transaction distribution +system.membus.trans_dist::ReadExResp 1722 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9530 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 304960 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4765 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4765 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4765 # Request fanout histogram +system.membus.reqLayer0.occupancy 4765500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23825500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt index c2d632546..f13570e98 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/minor-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.131746 # Number of seconds simulated -sim_ticks 131745950000 # Number of ticks simulated -final_tick 131745950000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.131756 # Number of seconds simulated +sim_ticks 131756455500 # Number of ticks simulated +final_tick 131756455500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165378 # Simulator instruction rate (inst/s) -host_op_rate 174335 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126440065 # Simulator tick rate (ticks/s) -host_mem_usage 304748 # Number of bytes of host memory used -host_seconds 1041.96 # Real time elapsed on the host +host_inst_rate 249754 # Simulator instruction rate (inst/s) +host_op_rate 263281 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 190965456 # Simulator tick rate (ticks/s) +host_mem_usage 316672 # Number of bytes of host memory used +host_seconds 689.95 # Real time elapsed on the host sim_insts 172317809 # Number of instructions simulated sim_ops 181650742 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 138176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 138304 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 109312 # Number of bytes read from this memory -system.physmem.bytes_read::total 247488 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 138176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 138176 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 2159 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 247616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 138304 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 138304 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 2161 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1708 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3867 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1048806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 829718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1878525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1048806 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1048806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 829718 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1878525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3867 # Number of read requests accepted +system.physmem.num_reads::total 3869 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1049694 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 829652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1879346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1049694 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1049694 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 829652 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1879346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3869 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3867 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3869 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 247488 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 247616 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 247488 # Total read bytes from the system interface side +system.physmem.bytesReadSys 247616 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -45,18 +45,18 @@ system.physmem.perBankRdBursts::0 305 # Pe system.physmem.perBankRdBursts::1 217 # Per bank write bursts system.physmem.perBankRdBursts::2 135 # Per bank write bursts system.physmem.perBankRdBursts::3 313 # Per bank write bursts -system.physmem.perBankRdBursts::4 308 # Per bank write bursts +system.physmem.perBankRdBursts::4 307 # Per bank write bursts system.physmem.perBankRdBursts::5 305 # Per bank write bursts system.physmem.perBankRdBursts::6 273 # Per bank write bursts system.physmem.perBankRdBursts::7 222 # Per bank write bursts system.physmem.perBankRdBursts::8 249 # Per bank write bursts system.physmem.perBankRdBursts::9 218 # Per bank write bursts system.physmem.perBankRdBursts::10 295 # Per bank write bursts -system.physmem.perBankRdBursts::11 199 # Per bank write bursts +system.physmem.perBankRdBursts::11 201 # Per bank write bursts system.physmem.perBankRdBursts::12 183 # Per bank write bursts system.physmem.perBankRdBursts::13 218 # Per bank write bursts system.physmem.perBankRdBursts::14 224 # Per bank write bursts -system.physmem.perBankRdBursts::15 203 # Per bank write bursts +system.physmem.perBankRdBursts::15 204 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 131745861500 # Total gap between requests +system.physmem.totGap 131756361000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3867 # Read request sizes (log2) +system.physmem.readPktSize::6 3869 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,7 +90,7 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 3616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 3618 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 912 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 269.543860 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 178.691365 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 273.658023 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 266 29.17% 29.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 353 38.71% 67.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 82 8.99% 76.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 61 6.69% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 33 3.62% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 27 2.96% 90.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 14 1.54% 91.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 19 2.08% 93.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 57 6.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 912 # Bytes accessed per row activation -system.physmem.totQLat 28130750 # Total ticks spent queuing -system.physmem.totMemAccLat 100637000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19335000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7274.57 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 274.663687 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.028895 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 274.690311 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 245 27.37% 27.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 357 39.89% 67.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 9.05% 76.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 51 5.70% 82.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 43 4.80% 86.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 26 2.91% 89.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 22 2.46% 92.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 1.79% 93.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 54 6.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 895 # Bytes accessed per row activation +system.physmem.totQLat 26801000 # Total ticks spent queuing +system.physmem.totMemAccLat 99344750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19345000 # Total ticks spent in databus transfers +system.physmem.avgQLat 6927.11 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26024.57 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 25677.11 # Average memory access latency per DRAM burst system.physmem.avgRdBW 1.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 1.88 # Average system read bandwidth in MiByte/s @@ -216,48 +216,48 @@ system.physmem.busUtilRead 0.01 # Da system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 2950 # Number of row buffer hits during reads +system.physmem.readRowHits 2968 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.29 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.71 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34069268.55 # Average gap between requests -system.physmem.pageHitRate 76.29 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3092040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1687125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16177200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 34054370.90 # Average gap between requests +system.physmem.pageHitRate 76.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3069360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1674750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16169400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 3575900700 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 75909402750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 88111095015 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.807422 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 126280313250 # Time in different power states -system.physmem_0.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_0.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 3539588850 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 75945927000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 88111773120 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.773044 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 126343733250 # Time in different power states +system.physmem_0.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1064296750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1010942750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3787560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2066625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13767000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3681720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 2008875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13774800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 8604835200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3595739265 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 75892008750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 88112204400 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.815773 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 126251429250 # Time in different power states -system.physmem_1.memoryStateTime::REF 4399200000 # Time in different power states +system.physmem_1.refreshEnergy 8605343760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3587668065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 75903760500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 88116237720 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.806861 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 126271447000 # Time in different power states +system.physmem_1.memoryStateTime::REF 4399460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 1093059250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 1080937500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 49935043 # Number of BP lookups -system.cpu.branchPred.condPredicted 39664695 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 5744224 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 24405530 # Number of BTB lookups -system.cpu.branchPred.BTBHits 23309445 # Number of BTB hits +system.cpu.branchPred.lookups 49934480 # Number of BP lookups +system.cpu.branchPred.condPredicted 39666708 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 5743450 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 24374232 # Number of BTB lookups +system.cpu.branchPred.BTBHits 23299942 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 95.508866 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1908457 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 95.592518 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1908561 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 139 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,75 +377,75 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 263491900 # number of cpu cycles simulated +system.cpu.numCycles 263512911 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 172317809 # Number of instructions committed system.cpu.committedOps 181650742 # Number of ops (including micro ops) committed -system.cpu.discardedOps 11758002 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 11759003 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 1.529104 # CPI: cycles per instruction -system.cpu.ipc 0.653978 # IPC: instructions per cycle -system.cpu.tickCycles 257145198 # Number of cycles that the object actually ticked -system.cpu.idleCycles 6346702 # Total number of cycles that the object has spent stopped +system.cpu.cpi 1.529226 # CPI: cycles per instruction +system.cpu.ipc 0.653925 # IPC: instructions per cycle +system.cpu.tickCycles 257129924 # Number of cycles that the object actually ticked +system.cpu.idleCycles 6382987 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 42 # number of replacements -system.cpu.dcache.tags.tagsinuse 1377.772724 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40762987 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 1377.698544 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40765677 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1810 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22520.987293 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22522.473481 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1377.772724 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.336370 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.336370 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 1377.698544 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.336352 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.336352 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1768 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 83 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1358 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.431641 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 81532656 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 81532656 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28355530 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28355530 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12362643 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12362643 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 81538036 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 81538036 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28358222 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28358222 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12362641 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12362641 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 40718173 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 40718173 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 40718173 # number of overall hits -system.cpu.dcache.overall_hits::total 40718173 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 792 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1644 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1644 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 40720863 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 40720863 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 40720863 # number of overall hits +system.cpu.dcache.overall_hits::total 40720863 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 790 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 790 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1646 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1646 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 2436 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 2436 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 2436 # number of overall misses system.cpu.dcache.overall_misses::total 2436 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 54011984 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 54011984 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 115610250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 115610250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 169622234 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 169622234 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 169622234 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28356322 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28356322 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 57599734 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 57599734 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 127302750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 127302750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 184902484 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 184902484 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 184902484 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28359012 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28359012 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 40720609 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 40720609 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 40720609 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 40720609 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 40723299 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 40723299 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 40723299 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 40723299 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.000028 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000133 # miss rate for WriteReq accesses @@ -454,14 +454,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.000060 system.cpu.dcache.demand_miss_rate::total 0.000060 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.000060 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.000060 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68196.949495 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68196.949495 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70322.536496 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70322.536496 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 69631.458949 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 69631.458949 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72911.055696 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72911.055696 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77340.674362 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 77340.674362 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 75904.139573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 75904.139573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,10 +472,10 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 16 # number of writebacks system.cpu.dcache.writebacks::total 16 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 80 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 546 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 546 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 78 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 78 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 548 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 548 # number of WriteReq MSHR hits system.cpu.dcache.demand_mshr_hits::cpu.data 626 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 626 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::cpu.data 626 # number of overall MSHR hits @@ -488,14 +488,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1810 system.cpu.dcache.demand_mshr_misses::total 1810 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1810 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1810 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 47293264 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 76508500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 123801764 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 123801764 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 123801764 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 51193764 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 85249250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 136443014 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 136443014 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 136443014 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -504,69 +504,69 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000044 system.cpu.dcache.demand_mshr_miss_rate::total 0.000044 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000044 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66423.123596 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69679.872495 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68398.764641 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 68398.764641 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 71901.353933 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77640.482696 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75382.880663 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 75382.880663 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2909 # number of replacements -system.cpu.icache.tags.tagsinuse 1424.880841 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 71614329 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 4705 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 15220.898831 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 2891 # number of replacements +system.cpu.icache.tags.tagsinuse 1424.909254 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 71597357 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 4688 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 15272.473763 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1424.880841 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.695743 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1796 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 1424.909254 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.695756 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1797 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 60 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 492 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 125 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 1068 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.876953 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 143242775 # Number of tag accesses -system.cpu.icache.tags.data_accesses 143242775 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 71614329 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 71614329 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 71614329 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 71614329 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 71614329 # number of overall hits -system.cpu.icache.overall_hits::total 71614329 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 4706 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 4706 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 4706 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 4706 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 4706 # number of overall misses -system.cpu.icache.overall_misses::total 4706 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 186377497 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 186377497 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 186377497 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 186377497 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 186377497 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 71619035 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 71619035 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 71619035 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 71619035 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 71619035 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000066 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000066 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39604.228007 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 39604.228007 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 39604.228007 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 39604.228007 # average overall miss latency +system.cpu.icache.tags.age_task_id_blocks_1024::2 490 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 129 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 1067 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.877441 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 143208780 # Number of tag accesses +system.cpu.icache.tags.data_accesses 143208780 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 71597357 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 71597357 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 71597357 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 71597357 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 71597357 # number of overall hits +system.cpu.icache.overall_hits::total 71597357 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 4689 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 4689 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 4689 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 4689 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 4689 # number of overall misses +system.cpu.icache.overall_misses::total 4689 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 200362248 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 200362248 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 200362248 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 200362248 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 200362248 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 71602046 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 71602046 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 71602046 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 71602046 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 71602046 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000065 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000065 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000065 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000065 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000065 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 42730.272553 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 42730.272553 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 42730.272553 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 42730.272553 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -575,123 +575,123 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4706 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 4706 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 4706 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 4706 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 4706 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 4706 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 176047503 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 176047503 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 176047503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 176047503 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 176047503 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 176047503 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 37409.159159 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 37409.159159 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 37409.159159 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 37409.159159 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4689 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 4689 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 4689 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 4689 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 4689 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 4689 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 192401752 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 192401752 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 192401752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 192401752 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 192401752 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 192401752 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000065 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000065 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000065 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 41032.576669 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 41032.576669 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41032.576669 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 41032.576669 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2001.520471 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2624 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 2785 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.942190 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2001.520500 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2606 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 2787 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.935056 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 3.029184 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.649056 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 490.842232 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 3.029170 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1507.676368 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 490.814962 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000092 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046010 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.014979 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.046011 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.014978 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.061082 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 2785 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 522 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 153 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 2787 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 520 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2005 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.084991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 56139 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 56139 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2543 # number of ReadReq hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.085052 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 56005 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 56005 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 2525 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 80 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2605 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 16 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 16 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2543 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 2525 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.data 88 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2631 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2543 # number of overall hits +system.cpu.l2cache.demand_hits::total 2613 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2525 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 88 # number of overall hits -system.cpu.l2cache.overall_hits::total 2631 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 2163 # number of ReadReq misses +system.cpu.l2cache.overall_hits::total 2613 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 2164 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 632 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2795 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2796 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1090 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1090 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 2163 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 2164 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 1722 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 3885 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 2163 # number of overall misses +system.cpu.l2cache.demand_misses::total 3886 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 2164 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1722 # number of overall misses -system.cpu.l2cache.overall_misses::total 3885 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 145907500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 45776750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 191684250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 75329000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 75329000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 145907500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 121105750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 267013250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 145907500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 121105750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 267013250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 4706 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 3886 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 161201250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 49637250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 210838500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 84065750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 84065750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 161201250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 133703000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 294904250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 161201250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 133703000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 294904250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 4689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 712 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 5418 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 5401 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 16 # number of Writeback accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1098 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1098 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 4706 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 4689 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 1810 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 6516 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 4706 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 6499 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 4689 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 1810 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 6516 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.459626 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 6499 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.461506 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.887640 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.515873 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.517682 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.992714 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.992714 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.459626 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.461506 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.951381 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.596225 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.459626 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.597938 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.461506 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.951381 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.596225 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67456.079519 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72431.566456 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68581.127013 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69109.174312 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69109.174312 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68729.279279 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67456.079519 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70328.542393 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68729.279279 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.597938 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74492.259704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78539.952532 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75407.188841 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77124.541284 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77124.541284 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75888.896037 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74492.259704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77644.018583 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75888.896037 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -700,115 +700,113 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 14 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 14 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 14 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2160 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2162 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 618 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2778 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2780 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1090 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1090 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2160 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 2162 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 1708 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 3868 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2160 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 3870 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 2162 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1708 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 3868 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 118562000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 37228000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 155790000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 61501500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 61501500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 118562000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 98729500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 217291500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 118562000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 98729500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 217291500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 3870 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134008500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 40696500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 174705000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70436750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134008500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 111133250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 245141750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134008500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 111133250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 245141750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.867978 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.512735 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.514719 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992714 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992714 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.593616 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.458989 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.595476 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.461079 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943646 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.593616 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54889.814815 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60239.482201 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56079.913607 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56423.394495 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54889.814815 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57804.156909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56176.706308 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.595476 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61983.580019 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65851.941748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62843.525180 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64620.871560 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61983.580019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65066.305621 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63344.121447 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 5418 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 5417 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 5401 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 5400 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1098 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1098 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9411 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 9377 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3636 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 13047 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 301120 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 13013 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 300032 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 116864 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 417984 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 416896 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 6532 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 6515 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 6532 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 6515 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 6532 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3282000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 6515 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3273500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 7517497 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 7496248 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2996736 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3020486 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 2777 # Transaction distribution -system.membus.trans_dist::ReadResp 2777 # Transaction distribution +system.membus.trans_dist::ReadReq 2779 # Transaction distribution +system.membus.trans_dist::ReadResp 2779 # Transaction distribution system.membus.trans_dist::ReadExReq 1090 # Transaction distribution system.membus.trans_dist::ReadExResp 1090 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7734 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 247488 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7738 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 247616 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 247616 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3867 # Request fanout histogram +system.membus.snoop_fanout::samples 3869 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3867 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3869 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3867 # Request fanout histogram -system.membus.reqLayer0.occupancy 4723500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3869 # Request fanout histogram +system.membus.reqLayer0.occupancy 4526500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36361000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20559250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt index 30df36f38..bc1d643b6 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.085008 # Number of seconds simulated -sim_ticks 85008313500 # Number of ticks simulated -final_tick 85008313500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.085027 # Number of seconds simulated +sim_ticks 85027009000 # Number of ticks simulated +final_tick 85027009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 130085 # Simulator instruction rate (inst/s) -host_op_rate 137131 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 64179279 # Simulator tick rate (ticks/s) -host_mem_usage 313784 # Number of bytes of host memory used -host_seconds 1324.54 # Real time elapsed on the host +host_inst_rate 134467 # Simulator instruction rate (inst/s) +host_op_rate 141751 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66356016 # Simulator tick rate (ticks/s) +host_mem_usage 312828 # Number of bytes of host memory used +host_seconds 1281.38 # Real time elapsed on the host sim_insts 172303021 # Number of instructions simulated sim_ops 181635953 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 127168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 48000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.l2cache.prefetcher 71360 # Number of bytes read from this memory -system.physmem.bytes_read::total 246528 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 127168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 127168 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 1987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 750 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.l2cache.prefetcher 1115 # Number of read requests responded to by this memory -system.physmem.num_reads::total 3852 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1495948 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 564651 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 839447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2900046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1495948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1495948 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1495948 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 564651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 839447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2900046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 3852 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 127040 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 47680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.l2cache.prefetcher 71040 # Number of bytes read from this memory +system.physmem.bytes_read::total 245760 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 127040 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 127040 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 1985 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 745 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.l2cache.prefetcher 1110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 3840 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1494113 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 560763 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 835499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2890376 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1494113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1494113 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1494113 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 560763 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 835499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2890376 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 3840 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 3852 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 3840 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 246528 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 245760 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 246528 # Total read bytes from the system interface side +system.physmem.bytesReadSys 245760 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 309 # Per bank write bursts -system.physmem.perBankRdBursts::1 223 # Per bank write bursts +system.physmem.perBankRdBursts::1 220 # Per bank write bursts system.physmem.perBankRdBursts::2 142 # Per bank write bursts -system.physmem.perBankRdBursts::3 310 # Per bank write bursts +system.physmem.perBankRdBursts::3 304 # Per bank write bursts system.physmem.perBankRdBursts::4 300 # Per bank write bursts system.physmem.perBankRdBursts::5 302 # Per bank write bursts system.physmem.perBankRdBursts::6 262 # Per bank write bursts system.physmem.perBankRdBursts::7 237 # Per bank write bursts system.physmem.perBankRdBursts::8 252 # Per bank write bursts -system.physmem.perBankRdBursts::9 218 # Per bank write bursts -system.physmem.perBankRdBursts::10 293 # Per bank write bursts +system.physmem.perBankRdBursts::9 219 # Per bank write bursts +system.physmem.perBankRdBursts::10 292 # Per bank write bursts system.physmem.perBankRdBursts::11 194 # Per bank write bursts -system.physmem.perBankRdBursts::12 193 # Per bank write bursts -system.physmem.perBankRdBursts::13 212 # Per bank write bursts +system.physmem.perBankRdBursts::12 191 # Per bank write bursts +system.physmem.perBankRdBursts::13 211 # Per bank write bursts system.physmem.perBankRdBursts::14 211 # Per bank write bursts system.physmem.perBankRdBursts::15 194 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 85008170000 # Total gap between requests +system.physmem.totGap 85026865500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 3852 # Read request sizes (log2) +system.physmem.readPktSize::6 3840 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,17 +94,17 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 2522 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 895 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 165 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 83 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 2543 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 162 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 760 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 321.936842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 203.366462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 304.047629 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 237 31.18% 31.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 182 23.95% 55.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 69 9.08% 64.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 96 12.63% 76.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 35 4.61% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 45 5.92% 87.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 18 2.37% 89.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 14 1.84% 91.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 64 8.42% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 760 # Bytes accessed per row activation -system.physmem.totQLat 36289181 # Total ticks spent queuing -system.physmem.totMemAccLat 108514181 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 19260000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9420.87 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 319.332464 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 200.822648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.559029 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 236 30.77% 30.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 188 24.51% 55.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 81 10.56% 65.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 90 11.73% 77.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 32 4.17% 81.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 41 5.35% 87.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 12 1.56% 88.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 16 2.09% 90.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71 9.26% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 767 # Bytes accessed per row activation +system.physmem.totQLat 42919435 # Total ticks spent queuing +system.physmem.totMemAccLat 114919435 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 19200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11176.94 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28170.87 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29926.94 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.89 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.90 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.89 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 3.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 3085 # Number of row buffer hits during reads +system.physmem.readRowHits 3071 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.09 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.97 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22068579.96 # Average gap between requests -system.physmem.pageHitRate 80.09 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2721600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1485000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 16239600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 22142412.89 # Average gap between requests +system.physmem.pageHitRate 79.97 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2691360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1468500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 16192800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 2339255205 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 48949672500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 56861323425 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.935094 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 81434793722 # Time in different power states -system.physmem_0.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_0.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 2327866605 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 48973677750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 56875372215 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.916551 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 81470624236 # Time in different power states +system.physmem_0.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 733662278 # Time in different power states +system.physmem_0.memoryStateTime::ACT 716299514 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3001320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1637625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 13540800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3107160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1695375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 13657800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5551949520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 2301878880 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 48982450500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 56854458645 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.854443 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 81486384408 # Time in different power states -system.physmem_1.memoryStateTime::REF 2838420000 # Time in different power states +system.physmem_1.refreshEnergy 5553475200 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 2285718525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 49010649750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 56868303810 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.833418 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 81532427147 # Time in different power states +system.physmem_1.memoryStateTime::REF 2839200000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 678791592 # Time in different power states +system.physmem_1.memoryStateTime::ACT 654496603 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 85929478 # Number of BP lookups -system.cpu.branchPred.condPredicted 68409655 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 6016514 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 40103730 # Number of BTB lookups -system.cpu.branchPred.BTBHits 39019729 # Number of BTB hits +system.cpu.branchPred.lookups 85926168 # Number of BP lookups +system.cpu.branchPred.condPredicted 68405800 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 6016539 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 40105937 # Number of BTB lookups +system.cpu.branchPred.BTBHits 39014203 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 97.297007 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 3701200 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 81899 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 97.277874 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 3700977 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 81896 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,96 +381,96 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 170016628 # number of cpu cycles simulated +system.cpu.numCycles 170054019 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 5612512 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 349284796 # Number of instructions fetch has processed -system.cpu.fetch.Branches 85929478 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 42720929 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 158258026 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 12046973 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 1522 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 5612946 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 349281739 # Number of instructions fetch has processed +system.cpu.fetch.Branches 85926168 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 42715180 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 158272644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 12047045 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1757 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingQuiesceStallCycles 23 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 2068 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 78953849 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 17938 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 169897637 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.150791 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.046975 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 2232 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 78951619 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 17953 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 169913124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.150597 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.047113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17345965 10.21% 10.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 30201314 17.78% 27.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 31838054 18.74% 46.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 90512304 53.27% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 17360928 10.22% 10.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 30199989 17.77% 27.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31841897 18.74% 46.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 90510310 53.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 169897637 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.505418 # Number of branch fetches per cycle -system.cpu.fetch.rate 2.054416 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 17565023 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 17095500 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 122663721 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 6724834 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 5848559 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 11136257 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 190151 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 306621954 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 27645544 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 5848559 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 37752791 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 8406678 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 578098 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 108929543 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 8381968 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 278665579 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 13416120 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 3045260 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 842372 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 2187359 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 31268 # Number of times rename has blocked due to SQ full -system.cpu.rename.FullRegisterEvents 80203 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 483123422 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 1196973277 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 297590130 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 3005585 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 169913124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.505287 # Number of branch fetches per cycle +system.cpu.fetch.rate 2.053946 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 17565564 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 17109843 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 122664763 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 6724358 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 5848596 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 11135936 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 189930 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 306620744 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 27649027 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 5848596 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37751386 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 8466295 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 579465 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 108929053 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 8338329 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 278664885 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 13415182 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 3050613 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 842331 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 2187361 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 37352 # Number of times rename has blocked due to SQ full +system.cpu.rename.FullRegisterEvents 26454 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 483122463 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 1196977553 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 297589838 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 3006277 # Number of floating rename lookups system.cpu.rename.CommittedMaps 292976929 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 190146493 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 23524 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 23418 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13341047 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 34139788 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 14476953 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2546690 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 1793951 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 264825375 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 45850 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 214906973 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 5192109 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 82644277 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 219958197 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 634 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 169897637 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.264920 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.017502 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 190145534 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 23528 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 23432 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13338171 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 34140942 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 14477069 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 2549253 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 1790153 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 264824262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 45858 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 214907174 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 5191222 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 82643318 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 219950944 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 642 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 169913124 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 1.264806 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.017451 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 52826553 31.09% 31.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 36096362 21.25% 52.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 65782146 38.72% 91.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 13572889 7.99% 99.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1571303 0.92% 99.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 47864 0.03% 100.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 520 0.00% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 52840350 31.10% 31.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 36091754 21.24% 52.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 65793999 38.72% 91.06% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 13568282 7.99% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1571301 0.92% 99.97% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 47256 0.03% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 182 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 169897637 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 169913124 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 35601312 66.11% 66.11% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 152935 0.28% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 35600908 66.11% 66.11% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 152918 0.28% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 66.39% # attempts to use FU when none available @@ -489,22 +489,22 @@ system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 66.39% # at system.cpu.iq.fu_full::SimdShift 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 1069 0.00% 66.39% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 1064 0.00% 66.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 66.39% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 35738 0.07% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 318 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 35736 0.07% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 241 0.00% 66.46% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 201 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 812 0.00% 66.46% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 34382 0.06% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 216 0.00% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 1033 0.00% 66.46% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 34370 0.06% 66.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 4 0.00% 66.53% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 66.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 14078938 26.14% 92.67% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 3947834 7.33% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 14078817 26.14% 92.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 3947857 7.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167350726 77.87% 77.87% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 918985 0.43% 78.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167349433 77.87% 77.87% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 918954 0.43% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.30% # Type of FU issued @@ -523,93 +523,93 @@ system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.30% # Ty system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.30% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.30% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 33019 0.02% 78.31% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 33017 0.02% 78.31% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.31% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 165190 0.08% 78.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 245718 0.11% 78.51% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 165198 0.08% 78.39% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 245711 0.11% 78.50% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 76018 0.04% 78.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 460475 0.21% 78.76% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 460497 0.21% 78.75% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 206696 0.10% 78.85% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 71623 0.03% 78.88% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 319 0.00% 78.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 32004909 14.89% 93.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 13373295 6.22% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 32005154 14.89% 93.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 13374554 6.22% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 214906973 # Type of FU issued -system.cpu.iq.rate 1.264035 # Inst issue rate -system.cpu.iq.fu_busy_cnt 53853755 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.250591 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 654805304 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 345511813 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 204602678 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 3952143 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 2010627 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 1806422 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266627552 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2133176 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 1600193 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 214907174 # Type of FU issued +system.cpu.iq.rate 1.263758 # Inst issue rate +system.cpu.iq.fu_busy_cnt 53853149 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.250588 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 654819591 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 345508564 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 204603377 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 3952252 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 2011834 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 1806382 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266627232 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2133091 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 1600790 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 6243644 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7556 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 7106 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1832319 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 6244798 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 7531 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 7120 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1832435 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 25875 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 661 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 25844 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 768 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 5848559 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 5681569 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 36478 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 264887188 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 5848596 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 5681557 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 36821 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 264886087 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 34139788 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 14476953 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 23442 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3814 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 29479 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 7106 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 3233640 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 3247282 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 6480922 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 207527385 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 30721175 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 7379588 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 34140942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 14477069 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 23450 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3913 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 29719 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 7120 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 3233413 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 3247375 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 6480788 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 207526427 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 30720305 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 7380747 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 15963 # number of nop insts executed -system.cpu.iew.exec_refs 43860513 # number of memory reference insts executed -system.cpu.iew.exec_branches 44937173 # Number of branches executed -system.cpu.iew.exec_stores 13139338 # Number of stores executed -system.cpu.iew.exec_rate 1.220630 # Inst execution rate -system.cpu.iew.wb_sent 206744227 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 206409100 # cumulative count of insts written-back -system.cpu.iew.wb_producers 129466460 # num instructions producing a value -system.cpu.iew.wb_consumers 221676348 # num instructions consuming a value +system.cpu.iew.exec_nop 15967 # number of nop insts executed +system.cpu.iew.exec_refs 43860812 # number of memory reference insts executed +system.cpu.iew.exec_branches 44937004 # Number of branches executed +system.cpu.iew.exec_stores 13140507 # Number of stores executed +system.cpu.iew.exec_rate 1.220356 # Inst execution rate +system.cpu.iew.wb_sent 206744573 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 206409759 # cumulative count of insts written-back +system.cpu.iew.wb_producers 129475490 # num instructions producing a value +system.cpu.iew.wb_consumers 221697589 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 1.214052 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.584034 # average fanout of values written-back +system.cpu.iew.wb_rate 1.213789 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.584018 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 69543087 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 69541306 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 45216 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 5841587 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 158455572 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 1.146380 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.646562 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 5841613 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 158471260 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 1.146267 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.646384 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 73674398 46.50% 46.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 41276379 26.05% 72.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 22551197 14.23% 86.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 9630660 6.08% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 3550983 2.24% 95.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2150131 1.36% 96.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1280461 0.81% 97.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 988669 0.62% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 3352694 2.12% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 73683520 46.50% 46.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 41279039 26.05% 72.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 22557642 14.23% 86.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 9629639 6.08% 92.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 3553008 2.24% 95.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2147976 1.36% 96.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1280790 0.81% 97.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 986719 0.62% 97.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 3352927 2.12% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 158455572 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 158471260 # Number of insts commited each cycle system.cpu.commit.committedInsts 172317409 # Number of instructions committed system.cpu.commit.committedOps 181650341 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -655,186 +655,186 @@ system.cpu.commit.op_class_0::MemWrite 12644634 6.96% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 181650341 # Class of committed instruction -system.cpu.commit.bw_lim_events 3352694 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 3352927 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 406291105 # The number of ROB reads -system.cpu.rob.rob_writes 513842853 # The number of ROB writes -system.cpu.timesIdled 3394 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 118991 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 406304779 # The number of ROB reads +system.cpu.rob.rob_writes 513839131 # The number of ROB writes +system.cpu.timesIdled 3408 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 140895 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 172303021 # Number of Instructions Simulated system.cpu.committedOps 181635953 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 0.986730 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.986730 # CPI: Total CPI of All Threads -system.cpu.ipc 1.013448 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.013448 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 218960053 # number of integer regfile reads -system.cpu.int_regfile_writes 114514072 # number of integer regfile writes -system.cpu.fp_regfile_reads 2904445 # number of floating regfile reads -system.cpu.fp_regfile_writes 2441481 # number of floating regfile writes -system.cpu.cc_regfile_reads 709585079 # number of cc regfile reads -system.cpu.cc_regfile_writes 229544416 # number of cc regfile writes -system.cpu.misc_regfile_reads 59313443 # number of misc regfile reads +system.cpu.cpi 0.986947 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.986947 # CPI: Total CPI of All Threads +system.cpu.ipc 1.013225 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.013225 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 218958782 # number of integer regfile reads +system.cpu.int_regfile_writes 114515411 # number of integer regfile writes +system.cpu.fp_regfile_reads 2904346 # number of floating regfile reads +system.cpu.fp_regfile_writes 2441525 # number of floating regfile writes +system.cpu.cc_regfile_reads 709584302 # number of cc regfile reads +system.cpu.cc_regfile_writes 229541480 # number of cc regfile writes +system.cpu.misc_regfile_reads 59315386 # number of misc regfile reads system.cpu.misc_regfile_writes 820036 # number of misc regfile writes -system.cpu.dcache.tags.replacements 72897 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.439547 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 41117509 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 73409 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 560.115367 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 497141250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.439547 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.998905 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.998905 # Average percentage of cache occupancy +system.cpu.dcache.tags.replacements 72889 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.417696 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 41115745 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 73401 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 560.152382 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 506067250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.417696 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.998863 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.998863 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 222 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 226 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 42 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 22 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 82532283 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 82532283 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 28730746 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 28730746 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 12341850 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 12341850 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 82529901 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 82529901 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 28729389 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 28729389 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 12341441 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 12341441 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 361 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 361 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 22145 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 22145 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 22147 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 22147 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 22407 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 22407 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41072596 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41072596 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41072957 # number of overall hits -system.cpu.dcache.overall_hits::total 41072957 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 89111 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 89111 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 22437 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 22437 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 118 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 118 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 262 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 262 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 111548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 111548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 111666 # number of overall misses -system.cpu.dcache.overall_misses::total 111666 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 835319240 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 835319240 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 222952999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 222952999 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2325000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 2325000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 1058272239 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 1058272239 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 1058272239 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 1058272239 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 28819857 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 28819857 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 41070830 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41070830 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41071191 # number of overall hits +system.cpu.dcache.overall_hits::total 41071191 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 89283 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 89283 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 22846 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 22846 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 116 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 116 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 260 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 260 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 112129 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 112129 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 112245 # number of overall misses +system.cpu.dcache.overall_misses::total 112245 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 853218237 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 853218237 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 244809935 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 244809935 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 2319500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 2319500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 1098028172 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 1098028172 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 1098028172 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 1098028172 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 28818672 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 28818672 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 479 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 479 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 477 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 477 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 22407 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 22407 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 41184144 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 41184144 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 41184623 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 41184623 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003092 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.003092 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001815 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.001815 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.246347 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011693 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.002709 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.002709 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.002711 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.002711 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9373.918371 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 9373.918371 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 9936.845345 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 9936.845345 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8874.045802 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8874.045802 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 9487.146690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 9487.146690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 9477.121407 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 9477.121407 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 122 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 7730 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 41182959 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 41182959 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 41183436 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 41183436 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.003098 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.003098 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001848 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.001848 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.243187 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.011604 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.002723 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.002723 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.002725 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.002725 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 9556.334767 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 9556.334767 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10715.658540 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 10715.658540 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 8921.153846 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 8921.153846 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 9792.544052 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 9792.544052 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 9782.423912 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 9782.423912 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 167 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 10490 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 532 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 61 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14.530075 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 844 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 12.428910 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 64874 # number of writebacks -system.cpu.dcache.writebacks::total 64874 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24383 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 24383 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 13871 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 13871 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 262 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 38254 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 38254 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 38254 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 38254 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64728 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64728 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8566 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 8566 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 115 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 73294 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 73294 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 73409 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 73409 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 491417758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 491417758 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 74043249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 74043249 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 982500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 565461007 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 565461007 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 566443507 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 566443507 # number of overall MSHR miss cycles +system.cpu.dcache.writebacks::writebacks 64871 # number of writebacks +system.cpu.dcache.writebacks::total 64871 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 24560 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 24560 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 14281 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 14281 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 260 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 260 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 38841 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 38841 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 38841 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 38841 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64723 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 64723 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 8565 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 8565 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 113 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 73288 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 73288 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 73401 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 73401 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 526941010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 526941010 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 81775757 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 81775757 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 905500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 905500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 608716767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 608716767 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 609622267 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 609622267 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002246 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000693 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000693 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.240084 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.240084 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.236897 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.236897 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.001780 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001782 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7592.042980 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 7592.042980 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 8643.853491 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 8643.853491 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8543.478261 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8543.478261 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 7714.969943 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 7714.969943 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 7716.267855 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 7716.267855 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 8141.479999 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 8141.479999 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9547.665733 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 9547.665733 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 8013.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 8013.274336 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8305.817692 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 8305.817692 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8305.367325 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 8305.367325 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 54440 # number of replacements -system.cpu.icache.tags.tagsinuse 510.617911 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78896507 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 54952 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1435.734951 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 84258685250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.617911 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997301 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997301 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 54441 # number of replacements +system.cpu.icache.tags.tagsinuse 510.602621 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78893897 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 54953 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 1435.661329 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 84271974250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.602621 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997271 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997271 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id @@ -842,188 +842,188 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 272 system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 48 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 157962600 # Number of tag accesses -system.cpu.icache.tags.data_accesses 157962600 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78896507 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78896507 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78896507 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78896507 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78896507 # number of overall hits -system.cpu.icache.overall_hits::total 78896507 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 57317 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 57317 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 57317 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 57317 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 57317 # number of overall misses -system.cpu.icache.overall_misses::total 57317 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 586515679 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 586515679 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 586515679 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 586515679 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 586515679 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 586515679 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78953824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78953824 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78953824 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78953824 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78953824 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78953824 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000726 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000726 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000726 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000726 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000726 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000726 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10232.839803 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 10232.839803 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 10232.839803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 10232.839803 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 10232.839803 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 47827 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 10 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 2525 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 18.941386 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 10 # average number of cycles each access was blocked +system.cpu.icache.tags.tag_accesses 157958145 # Number of tag accesses +system.cpu.icache.tags.data_accesses 157958145 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78893897 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78893897 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78893897 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78893897 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78893897 # number of overall hits +system.cpu.icache.overall_hits::total 78893897 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 57699 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 57699 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 57699 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 57699 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 57699 # number of overall misses +system.cpu.icache.overall_misses::total 57699 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 607673936 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 607673936 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 607673936 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 607673936 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 607673936 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 607673936 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 78951596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78951596 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78951596 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78951596 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78951596 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78951596 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000731 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000731 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000731 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000731 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000731 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000731 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 10531.793203 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 10531.793203 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 10531.793203 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 10531.793203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 10531.793203 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 10531.793203 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 55459 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 532 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2752 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 20.152253 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 177.333333 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2365 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2365 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2365 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2365 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2365 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2365 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54952 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 54952 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 54952 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 54952 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 54952 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 54952 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 466993997 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 466993997 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 466993997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 466993997 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 466993997 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 466993997 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2746 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2746 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2746 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2746 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2746 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2746 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 54953 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 54953 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 54953 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 54953 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 54953 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 54953 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 509320483 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 509320483 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 509320483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 509320483 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 509320483 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 509320483 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000696 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000696 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000696 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000696 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 8498.216571 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 8498.216571 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 8498.216571 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 8498.216571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 8498.216571 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 8498.216571 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 9268.292595 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 9268.292595 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 9268.292595 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 9268.292595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 9268.292595 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 9268.292595 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.prefetcher.num_hwpf_issued 9345 # number of hwpf issued -system.cpu.l2cache.prefetcher.pfIdentified 9345 # number of prefetch candidates identified +system.cpu.l2cache.prefetcher.num_hwpf_issued 9289 # number of hwpf issued +system.cpu.l2cache.prefetcher.pfIdentified 9289 # number of prefetch candidates identified system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu.l2cache.prefetcher.pfSpanPage 1367 # number of prefetches not generated due to page crossing +system.cpu.l2cache.prefetcher.pfSpanPage 1375 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2661.020186 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 178437 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3588 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 49.731605 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2667.127708 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 178431 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3576 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 49.896812 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 702.071269 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1377.111854 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 421.096641 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 160.740422 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.042851 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.084052 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.025702 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.009811 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.162416 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1022 262 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3326 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::writebacks 701.951887 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1376.042782 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 417.094048 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 172.038991 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.042844 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.083987 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.025457 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.010500 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.162789 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1022 260 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3316 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::1 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::2 86 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::4 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 749 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::2 83 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::4 158 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 751 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::3 37 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2295 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015991 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.203003 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3103985 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3103985 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 52960 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 64249 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 117209 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 64874 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 64874 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 8402 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 8402 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 52960 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 72651 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 125611 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 52960 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 72651 # number of overall hits -system.cpu.l2cache.overall_hits::total 125611 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 1992 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 523 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 2515 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 235 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 235 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 1992 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 758 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 2750 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 1992 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 758 # number of overall misses -system.cpu.l2cache.overall_misses::total 2750 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 121584000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 34631250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 156215250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 15317000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 15317000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 121584000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 49948250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 171532250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 121584000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 49948250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 171532250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 54952 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 64772 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 119724 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 64874 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 64874 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 8637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 8637 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 54952 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 73409 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 128361 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 54952 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 73409 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 128361 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.036250 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.008074 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.021007 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027209 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.027209 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.036250 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.010326 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.021424 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.036250 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.010326 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.021424 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 61036.144578 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 66216.539197 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 62113.419483 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65178.723404 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65178.723404 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 62375.363636 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 61036.144578 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65894.788918 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 62375.363636 # average overall miss latency +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2290 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1022 0.015869 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.202393 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 3103812 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 3103812 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 52962 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 64250 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 117212 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 64871 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 64871 # number of Writeback hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 8396 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 8396 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 52962 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 72646 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 125608 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 52962 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 72646 # number of overall hits +system.cpu.l2cache.overall_hits::total 125608 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 1991 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 515 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 2506 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 240 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 240 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 1991 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 755 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 2746 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 1991 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 755 # number of overall misses +system.cpu.l2cache.overall_misses::total 2746 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 137421241 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 37855250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 175276491 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 18932508 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 18932508 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 137421241 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 56787758 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 194208999 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 137421241 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 56787758 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 194208999 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 54953 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 64765 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 119718 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 64871 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 64871 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 8636 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 8636 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 54953 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 73401 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 128354 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 54953 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 73401 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 128354 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.036231 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.007952 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.020933 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.027791 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.027791 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.036231 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.010286 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.021394 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.036231 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.010286 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.021394 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69021.215972 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73505.339806 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 69942.733839 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 78885.450000 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 78885.450000 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69021.215972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75215.573510 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 70724.325929 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69021.215972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75215.573510 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 70724.325929 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1032,128 +1032,128 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 8 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 8 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 8 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 13 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1987 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 515 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 2502 # number of ReadReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1816 # number of HardPFReq MSHR misses -system.cpu.l2cache.HardPFReq_mshr_misses::total 1816 # number of HardPFReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 235 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 235 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 1987 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 750 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 2737 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 1987 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 750 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1816 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 4553 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104199500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 29901250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134100750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 63393390 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 13328500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 13328500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104199500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 43229750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 147429250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104199500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 43229750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 63393390 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 210822640 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007951 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020898 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 2 # number of ReadExReq MSHR hits +system.cpu.l2cache.ReadExReq_mshr_hits::total 2 # number of ReadExReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1985 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 507 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 2492 # number of ReadReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1808 # number of HardPFReq MSHR misses +system.cpu.l2cache.HardPFReq_mshr_misses::total 1808 # number of HardPFReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 238 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 238 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 1985 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 2730 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 1985 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 745 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1808 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 4538 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 120193759 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33127750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 153321509 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68601184 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68601184 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 16505250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 16505250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 120193759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 49633000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 169826759 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 120193759 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 49633000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68601184 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 238427943 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.007828 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.020816 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027209 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.021323 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036159 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010217 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.027559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.027559 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.010150 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.021269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.036122 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.010150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.035470 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52440.613991 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58060.679612 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 53597.422062 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34908.254405 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56717.021277 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56717.021277 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53865.272196 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52440.613991 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57639.666667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34908.254405 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 46304.115967 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.035355 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60551.012091 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65340.729783 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61525.485152 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37943.132743 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69349.789916 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69349.789916 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62207.604029 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60551.012091 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66621.476510 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37943.132743 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52540.313574 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 119724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 119724 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 64874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 2213 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 8637 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 8637 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211692 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 321596 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8850112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 12367040 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 2213 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 195448 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011323 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105804 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 119718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 119718 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 64871 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 2155 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 8636 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 8636 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 109906 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 211673 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 321579 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3516992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8849408 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 12366400 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 2155 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 195380 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011030 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.104442 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 193235 98.87% 98.87% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 2213 1.13% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 193225 98.90% 98.90% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 2155 1.10% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 195448 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 161491500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 195380 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 161483500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 82814471 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 82836732 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 110208992 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 110205232 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3617 # Transaction distribution -system.membus.trans_dist::ReadResp 3617 # Transaction distribution -system.membus.trans_dist::ReadExReq 235 # Transaction distribution -system.membus.trans_dist::ReadExResp 235 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7704 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 7704 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 246528 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 246528 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 3602 # Transaction distribution +system.membus.trans_dist::ReadResp 3602 # Transaction distribution +system.membus.trans_dist::ReadExReq 238 # Transaction distribution +system.membus.trans_dist::ReadExResp 238 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 7680 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 7680 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 245760 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 245760 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3852 # Request fanout histogram +system.membus.snoop_fanout::samples 3840 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 3852 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 3840 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 3852 # Request fanout histogram -system.membus.reqLayer0.occupancy 5007645 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 3840 # Request fanout histogram +system.membus.reqLayer0.occupancy 4975502 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 36124927 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 20238053 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 7ececc2b6..e6a9622eb 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491000 # Number of ticks simulated final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1699536 # Simulator instruction rate (inst/s) -host_op_rate 1791584 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 982302061 # Simulator tick rate (ticks/s) -host_mem_usage 304728 # Number of bytes of host memory used -host_seconds 101.39 # Real time elapsed on the host +host_inst_rate 1940320 # Simulator instruction rate (inst/s) +host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1121471108 # Simulator tick rate (ticks/s) +host_mem_usage 304628 # Number of bytes of host memory used +host_seconds 88.81 # Real time elapsed on the host sim_insts 172317409 # Number of instructions simulated sim_ops 181650341 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -230,18 +230,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 230024466 # Request fanout histogram -system.membus.snoop_fanout::mean 4.825391 # Request fanout histogram +system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::5 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram +system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 230024466 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 62a10ca2c..6ce1a7f0e 100644 --- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.230173 # Number of seconds simulated -sim_ticks 230173357000 # Number of ticks simulated -final_tick 230173357000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 230173357500 # Number of ticks simulated +final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1229194 # Simulator instruction rate (inst/s) -host_op_rate 1295881 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1646435898 # Simulator tick rate (ticks/s) -host_mem_usage 312932 # Number of bytes of host memory used -host_seconds 139.80 # Real time elapsed on the host +host_inst_rate 1098511 # Simulator instruction rate (inst/s) +host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1471393960 # Simulator tick rate (ticks/s) +host_mem_usage 313104 # Number of bytes of host memory used +host_seconds 156.43 # Real time elapsed on the host sim_insts 171842483 # Number of instructions simulated sim_ops 181165370 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460346714 # number of cpu cycles simulated +system.cpu.numCycles 460346715 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 171842483 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 40540779 # nu system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460346713.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 40300311 # Number of branches fetched @@ -208,12 +208,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650742 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619284 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619284 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id @@ -309,16 +309,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 1788 system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 34093000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57994500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 92087500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 92140500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 92140500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 34437000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 58544500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 92981500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93035000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 93035000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses @@ -329,24 +329,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49553.779070 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52722.272727 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51503.076063 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51503.076063 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51503.912800 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51503.912800 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50053.779070 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53222.272727 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53500 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52003.076063 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52003.076063 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992604 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992604 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id @@ -370,12 +370,12 @@ system.cpu.icache.demand_misses::cpu.inst 3051 # n system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses system.cpu.icache.overall_misses::total 3051 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 112370500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 112370500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 112370500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 112370500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 112370500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 112370500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses @@ -388,12 +388,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.711242 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36830.711242 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36830.711242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.711242 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36830.711242 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -408,34 +408,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 3051 system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 106268500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 106268500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106268500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 106268500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 107794500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 107794500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 107794500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 107794500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34830.711242 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34830.711242 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34830.711242 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34830.711242 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35330.875123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663358 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036759 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588821 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_misses::total 3453 # nu system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses system.cpu.l2cache.overall_misses::total 3453 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 89997500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32887000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 122884500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56814500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56814500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 89997500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 89701500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 179699000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 89997500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 89701500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 179699000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 90862500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 33203000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 124065500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 57360500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 90862500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 90563500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 181426000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 90862500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 90563500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 181426000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 3051 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 689 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 3740 # number of ReadReq accesses(hits+misses) @@ -508,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.713430 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52051.764025 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52036.392405 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52047.649301 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52027.930403 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52027.930403 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52041.413264 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52051.764025 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52031.032483 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52041.413264 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52552.053210 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52536.392405 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52547.861076 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52527.930403 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52541.558065 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52552.053210 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52531.032483 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52541.558065 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 3453 system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 70024500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25596000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 95620500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 44226000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 70024500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 69822000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 139846500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 70024500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 69822000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 139846500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.631283 # mshr miss rate for ReadReq accesses @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution @@ -585,19 +585,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4856 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) @@ -624,9 +622,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 3453 # Request fanout histogram -system.membus.reqLayer0.occupancy 3596000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 3596500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 31220000 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 17408500 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 66a194e38..e9f2af2a4 100644 --- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.270563 # Number of seconds simulated -sim_ticks 270563082000 # Number of ticks simulated -final_tick 270563082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 270563082500 # Number of ticks simulated +final_tick 270563082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1449498 # Simulator instruction rate (inst/s) -host_op_rate 1449499 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2027353723 # Simulator tick rate (ticks/s) -host_mem_usage 294428 # Number of bytes of host memory used -host_seconds 133.46 # Real time elapsed on the host +host_inst_rate 1283602 # Simulator instruction rate (inst/s) +host_op_rate 1283603 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1795321724 # Simulator tick rate (ticks/s) +host_mem_usage 297332 # Number of bytes of host memory used +host_seconds 150.70 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,32 +29,9 @@ system.physmem.bw_inst_read::total 850848 # In system.physmem.bw_total::cpu.inst 850848 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 372793 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223641 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 4095 # Transaction distribution -system.membus.trans_dist::ReadResp 4095 # Transaction distribution -system.membus.trans_dist::ReadExReq 1078 # Transaction distribution -system.membus.trans_dist::ReadExResp 1078 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5173 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5173 # Request fanout histogram -system.membus.reqLayer0.occupancy 5173000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 46557000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls -system.cpu.numCycles 541126164 # number of cpu cycles simulated +system.cpu.numCycles 541126165 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 193444518 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 76733958 # nu system.cpu.num_load_insts 57735091 # Number of load instructions system.cpu.num_store_insts 18998867 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 541126163.998000 # Number of busy cycles +system.cpu.num_busy_cycles 541126164.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 15132745 # Number of branches fetched @@ -112,13 +89,142 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.203936 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203936 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits +system.cpu.dcache.overall_hits::total 76709932 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses +system.cpu.dcache.overall_misses::total 1575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 2 # number of writebacks +system.cpu.dcache.writebacks::total 2 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses +system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26643000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 26643000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57619500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 57619500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 53500 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 84262500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 84262500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 84262500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 84262500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53500 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53500 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 10362 # number of replacements -system.cpu.icache.tags.tagsinuse 1591.579171 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1591.579164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 12288 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15741.638021 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1591.579164 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.777138 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1926 # Occupied blocks per task id @@ -142,12 +248,12 @@ system.cpu.icache.demand_misses::cpu.inst 12288 # n system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses system.cpu.icache.overall_misses::total 12288 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 310818000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 310818000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 310818000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 310818000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 310818000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 310818500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 310818500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 310818500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 310818500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 310818500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 310818500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 193445536 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 193445536 # number of demand (read+write) accesses @@ -160,12 +266,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 system.cpu.icache.demand_miss_rate::total 0.000064 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000064 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.433594 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 25294.433594 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 25294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.433594 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 25294.433594 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25294.474284 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 25294.474284 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 25294.474284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 25294.474284 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 25294.474284 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -180,34 +286,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 12288 system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 286242000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 286242000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 292386500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 292386500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292386500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 292386500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000064 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000064 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000064 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000064 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23294.433594 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 23294.433594 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23794.474284 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 23794.474284 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23794.474284 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 23794.474284 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2678.340865 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2678.340853 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 8691 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 4097 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 2.121308 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.000453 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282924 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057488 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2275.282913 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 403.057487 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000000 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.069436 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.012300 # Average percentage of cache occupancy @@ -240,17 +346,17 @@ system.cpu.l2cache.demand_misses::total 5173 # nu system.cpu.l2cache.overall_misses::cpu.inst 3597 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1576 # number of overall misses system.cpu.l2cache.overall_misses::total 5173 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 187044000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 25896000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 212940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 56056000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 187044000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 81952000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 268996000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 187044000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 81952000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 268996000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 188843000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 26145000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 214988000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 56595000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 56595000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 188843000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 82740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 271583000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 188843000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 82740000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 271583000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 12288 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 498 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 12786 # number of ReadReq accesses(hits+misses) @@ -275,17 +381,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.373125 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.292725 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.373125 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52500.139005 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500.122100 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52500.096656 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52500.139005 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52500.096656 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,17 +411,17 @@ system.cpu.l2cache.demand_mshr_misses::total 5173 system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 145678500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20169000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 165847500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43659000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43659000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 145678500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63828000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 209506500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 145678500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63828000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 209506500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.320272 # mshr miss rate for ReadReq accesses @@ -327,147 +433,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 2 # number of replacements -system.cpu.dcache.tags.tagsinuse 1237.203941 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1237.203941 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.302052 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits -system.cpu.dcache.overall_hits::total 76709932 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses -system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses -system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses -system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses -system.cpu.dcache.overall_misses::total 1575 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 27390000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 27390000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 59235000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 59235000 # number of WriteReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::cpu.data 55000 # number of SwapReq miss cycles -system.cpu.dcache.SwapReq_miss_latency::total 55000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 86625000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 86625000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 86625000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 86625000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 55000 # average SwapReq miss latency -system.cpu.dcache.SwapReq_avg_miss_latency::total 55000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 2 # number of writebacks -system.cpu.dcache.writebacks::total 2 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1077 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1077 # number of WriteReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::cpu.data 1 # number of SwapReq MSHR misses -system.cpu.dcache.SwapReq_mshr_misses::total 1 # number of SwapReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1575 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1575 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1575 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26394000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26394000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 57081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 57081000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 53000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 53000 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 83475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 83475000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 83475000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 83475000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000057 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.SwapReq_mshr_miss_rate::total 0.000045 # mshr miss rate for SwapReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000021 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000021 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 53000 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 53000 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 2 # Transaction distribution @@ -497,5 +474,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 18432000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 4095 # Transaction distribution +system.membus.trans_dist::ReadResp 4095 # Transaction distribution +system.membus.trans_dist::ReadExReq 1078 # Transaction distribution +system.membus.trans_dist::ReadExResp 1078 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5173 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5173 # Request fanout histogram +system.membus.reqLayer0.occupancy 5173500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 25865500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt index 85460c89a..e5c937252 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt @@ -1,62 +1,62 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.148652 # Number of seconds simulated -sim_ticks 148652306000 # Number of ticks simulated -final_tick 148652306000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.148669 # Number of seconds simulated +sim_ticks 148668850500 # Number of ticks simulated +final_tick 148668850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 83185 # Simulator instruction rate (inst/s) -host_op_rate 139426 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 93628996 # Simulator tick rate (ticks/s) -host_mem_usage 346568 # Number of bytes of host memory used -host_seconds 1587.67 # Real time elapsed on the host +host_inst_rate 82634 # Simulator instruction rate (inst/s) +host_op_rate 138502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 93018548 # Simulator tick rate (ticks/s) +host_mem_usage 346916 # Number of bytes of host memory used +host_seconds 1598.27 # Real time elapsed on the host sim_insts 132071192 # Number of instructions simulated sim_ops 221363384 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 224768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 125696 # Number of bytes read from this memory -system.physmem.bytes_read::total 350464 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 224768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 224768 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 3512 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1964 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5476 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1512038 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 845570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2357609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1512038 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1512038 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1512038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 845570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2357609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 5476 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 225344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 125504 # Number of bytes read from this memory +system.physmem.bytes_read::total 350848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 225344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 225344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3521 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1961 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5482 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1515745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 844185 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2359929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1515745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1515745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1515745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 844185 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2359929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 5482 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 5476 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 5482 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 350464 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 350848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 350464 # Total read bytes from the system interface side +system.physmem.bytesReadSys 350848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 324 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 295 # Per bank write bursts -system.physmem.perBankRdBursts::1 363 # Per bank write bursts -system.physmem.perBankRdBursts::2 461 # Per bank write bursts -system.physmem.perBankRdBursts::3 370 # Per bank write bursts -system.physmem.perBankRdBursts::4 335 # Per bank write bursts -system.physmem.perBankRdBursts::5 334 # Per bank write bursts -system.physmem.perBankRdBursts::6 400 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 345 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 294 # Per bank write bursts +system.physmem.perBankRdBursts::1 364 # Per bank write bursts +system.physmem.perBankRdBursts::2 457 # Per bank write bursts +system.physmem.perBankRdBursts::3 371 # Per bank write bursts +system.physmem.perBankRdBursts::4 339 # Per bank write bursts +system.physmem.perBankRdBursts::5 333 # Per bank write bursts +system.physmem.perBankRdBursts::6 398 # Per bank write bursts system.physmem.perBankRdBursts::7 383 # Per bank write bursts -system.physmem.perBankRdBursts::8 340 # Per bank write bursts -system.physmem.perBankRdBursts::9 286 # Per bank write bursts -system.physmem.perBankRdBursts::10 236 # Per bank write bursts -system.physmem.perBankRdBursts::11 261 # Per bank write bursts -system.physmem.perBankRdBursts::12 219 # Per bank write bursts -system.physmem.perBankRdBursts::13 509 # Per bank write bursts -system.physmem.perBankRdBursts::14 392 # Per bank write bursts -system.physmem.perBankRdBursts::15 292 # Per bank write bursts +system.physmem.perBankRdBursts::8 344 # Per bank write bursts +system.physmem.perBankRdBursts::9 280 # Per bank write bursts +system.physmem.perBankRdBursts::10 239 # Per bank write bursts +system.physmem.perBankRdBursts::11 268 # Per bank write bursts +system.physmem.perBankRdBursts::12 225 # Per bank write bursts +system.physmem.perBankRdBursts::13 502 # Per bank write bursts +system.physmem.perBankRdBursts::14 395 # Per bank write bursts +system.physmem.perBankRdBursts::15 290 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts system.physmem.perBankWrBursts::2 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 148652208500 # Total gap between requests +system.physmem.totGap 148668756000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 5476 # Read request sizes (log2) +system.physmem.readPktSize::6 5482 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,11 +90,11 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 4366 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 909 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 4368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 913 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,26 +186,26 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1147 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 304.265039 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 175.960981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.625541 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 464 40.45% 40.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 245 21.36% 61.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 104 9.07% 70.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 57 4.97% 75.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 54 4.71% 80.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 57 4.97% 85.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 24 2.09% 87.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 15 1.31% 88.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 127 11.07% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1147 # Bytes accessed per row activation -system.physmem.totQLat 37377750 # Total ticks spent queuing -system.physmem.totMemAccLat 140052750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 27380000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6825.74 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 1140 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 306.470175 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.641766 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.557853 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 448 39.30% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 255 22.37% 61.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 105 9.21% 70.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 70 6.14% 77.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 38 3.33% 80.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 59 5.18% 85.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 19 1.67% 87.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 18 1.58% 88.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 128 11.23% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1140 # Bytes accessed per row activation +system.physmem.totQLat 40930250 # Total ticks spent queuing +system.physmem.totMemAccLat 143717750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 27410000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7466.30 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25575.74 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 26216.30 # Average memory access latency per DRAM burst system.physmem.avgRdBW 2.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 2.36 # Average system read bandwidth in MiByte/s @@ -214,286 +214,285 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.10 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 4321 # Number of row buffer hits during reads +system.physmem.readRowHits 4334 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.91 # Row buffer hit rate for reads +system.physmem.readRowHitRate 79.06 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 27146130.11 # Average gap between requests -system.physmem.pageHitRate 78.91 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 5072760 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2767875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 22791600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 27119437.43 # Average gap between requests +system.physmem.pageHitRate 79.06 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 5027400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 2743125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 22776000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 4015280925 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 85666359000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 99421191120 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.838371 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 142511183750 # Time in different power states -system.physmem_0.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_0.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 4021675470 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 85670093250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 99432251325 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.842708 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 142518159000 # Time in different power states +system.physmem_0.memoryStateTime::REF 4964180000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 1172773250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 1181750000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3575880 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1951125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 19585800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 3568320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1947000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 19648200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 9708918960 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 3861811845 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 85800972750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 99396816360 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.674456 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 142739163750 # Time in different power states -system.physmem_1.memoryStateTime::REF 4963660000 # Time in different power states +system.physmem_1.refreshEnergy 9709936080 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 3821631120 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 85845562500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 99402293220 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.641253 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 142814554750 # Time in different power states +system.physmem_1.memoryStateTime::REF 4964180000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 947728750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 888260750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 22375930 # Number of BP lookups -system.cpu.branchPred.condPredicted 22375930 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1550820 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 14142904 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13245564 # Number of BTB hits +system.cpu.branchPred.lookups 22385702 # Number of BP lookups +system.cpu.branchPred.condPredicted 22385702 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1554139 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 14132286 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13246709 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 93.655193 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1524021 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 21798 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 93.733661 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1526841 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 22095 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 297304620 # number of cpu cycles simulated +system.cpu.numCycles 297337717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 27866919 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 248846814 # Number of instructions fetch has processed -system.cpu.fetch.Branches 22375930 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 14769585 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 267364531 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3698749 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 56 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 4550 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 42690 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 27888104 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 249064218 # Number of instructions fetch has processed +system.cpu.fetch.Branches 22385702 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 14773550 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 267343346 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3703385 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 34 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 5713 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 48972 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 111 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 26638460 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 257102 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 2 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 297128244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.381645 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.790124 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.IcacheWaitRetryStallCycles 83 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 26656558 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 259176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 297137957 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.382061 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.790607 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 229068376 77.09% 77.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5099613 1.72% 78.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 4127262 1.39% 80.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 4784384 1.61% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4893969 1.65% 83.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 5110538 1.72% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5334476 1.80% 86.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3994023 1.34% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 34715603 11.68% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 229077480 77.09% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5080600 1.71% 78.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 4128062 1.39% 80.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 4791015 1.61% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4884919 1.64% 83.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 5103681 1.72% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5337561 1.80% 86.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 4007445 1.35% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 34727194 11.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 297128244 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.075263 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.837010 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 16329336 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 230975824 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 26113582 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 21860128 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1849374 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 359242894 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1849374 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 24118008 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 162656356 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 38273 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 38263619 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 70202614 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 350538626 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 41453 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 61947521 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 7945702 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 153558 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 405817730 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 972424276 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 641996744 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 4657501 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 297137957 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.075287 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.837648 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 16350382 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 230944995 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 26142980 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 21847908 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1851692 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 359376016 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1851692 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 24144395 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 162574126 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 34810 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 38280834 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 70252100 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 350628030 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 42505 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 62013521 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 7956456 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 170486 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 405834886 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 972854229 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 642281329 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 4678301 # Number of floating rename lookups system.cpu.rename.CommittedMaps 259429450 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 146388280 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2397 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2322 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 128546417 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 89512895 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 32023027 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 63891013 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 21581901 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 341300793 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 5145 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 266928835 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 76764 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 119543073 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 250225997 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3900 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 297128244 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.898362 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.364631 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 146405436 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2386 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2313 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 128573116 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 89639956 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 32032649 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 63973866 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21576036 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 341334735 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 4899 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 266857181 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 74594 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 119571219 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 250511173 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3654 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 297137957 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.898092 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.364162 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 171384973 57.68% 57.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 54250707 18.26% 75.94% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 33605057 11.31% 87.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 19187938 6.46% 93.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 10808168 3.64% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 4369052 1.47% 98.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 2227260 0.75% 99.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 898004 0.30% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 397085 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 171399069 57.68% 57.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 54278133 18.27% 75.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 33575860 11.30% 87.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 19165859 6.45% 93.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 10861721 3.66% 97.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 4344660 1.46% 98.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 2227090 0.75% 99.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 887493 0.30% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 398072 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 297128244 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 297137957 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 240256 7.42% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.42% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 2591676 80.04% 87.46% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 406020 12.54% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 235011 7.30% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.30% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 2578157 80.11% 87.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 405217 12.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 1211341 0.45% 0.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 167360520 62.70% 63.15% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 793230 0.30% 63.45% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7036198 2.64% 66.09% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 1213739 0.45% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 66512723 24.92% 91.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 22801084 8.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 1211344 0.45% 0.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 167292419 62.69% 63.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 790150 0.30% 63.44% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7035672 2.64% 66.08% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 1215098 0.46% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 66512451 24.92% 91.46% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 22800047 8.54% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 266928835 # Type of FU issued -system.cpu.iq.rate 0.897829 # Inst issue rate -system.cpu.iq.fu_busy_cnt 3237952 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012130 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 829304993 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 456859927 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 261005005 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 4995637 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 4315017 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 2397122 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 266441955 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 2513491 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 18899538 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 266857181 # Type of FU issued +system.cpu.iq.rate 0.897488 # Inst issue rate +system.cpu.iq.fu_busy_cnt 3218385 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012060 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 829150425 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 456900250 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 260922611 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 4994873 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 4333463 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 2397328 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 266351243 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 2512979 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 18909810 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 32863308 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 14004 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 331776 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 11507310 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 32990369 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 14136 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 328607 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 11516932 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 52520 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 52167 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1849374 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 126083228 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5521965 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 341305938 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 113234 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 89512895 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 32023027 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 2291 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2224383 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 364956 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 331776 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 682604 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 926974 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1609578 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 264820941 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 65644877 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2107894 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 1851692 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 126137646 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5532810 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 341339634 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 112602 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 89639956 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 32032649 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 2212 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 2223479 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 382778 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 328607 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 684628 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 928175 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1612803 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 264737771 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 65643847 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2119410 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 88243318 # number of memory reference insts executed -system.cpu.iew.exec_branches 14594562 # Number of branches executed -system.cpu.iew.exec_stores 22598441 # Number of stores executed -system.cpu.iew.exec_rate 0.890739 # Inst execution rate -system.cpu.iew.wb_sent 264116022 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 263402127 # cumulative count of insts written-back -system.cpu.iew.wb_producers 208929627 # num instructions producing a value -system.cpu.iew.wb_consumers 376950815 # num instructions consuming a value +system.cpu.iew.exec_refs 88241442 # number of memory reference insts executed +system.cpu.iew.exec_branches 14589088 # Number of branches executed +system.cpu.iew.exec_stores 22597595 # Number of stores executed +system.cpu.iew.exec_rate 0.890361 # Inst execution rate +system.cpu.iew.wb_sent 264036391 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 263319939 # cumulative count of insts written-back +system.cpu.iew.wb_producers 208896510 # num instructions producing a value +system.cpu.iew.wb_consumers 376872402 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.885967 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554262 # average fanout of values written-back +system.cpu.iew.wb_rate 0.885592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554290 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 119991036 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 120026923 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 1245 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1555160 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 280815934 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.788286 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.594389 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1559493 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 280830334 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.788246 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.594394 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 180962849 64.44% 64.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 57749972 20.57% 85.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 14199777 5.06% 90.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 11927311 4.25% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 4203723 1.50% 95.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 2893126 1.03% 96.84% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 916943 0.33% 97.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 1048119 0.37% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 6914114 2.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180946233 64.43% 64.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 57795535 20.58% 85.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 14201408 5.06% 90.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 11929876 4.25% 94.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 4188274 1.49% 95.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 2885386 1.03% 96.84% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 910038 0.32% 97.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 1053521 0.38% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 6920063 2.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 280815934 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 280830334 # Number of insts commited each cycle system.cpu.commit.committedInsts 132071192 # Number of instructions committed system.cpu.commit.committedOps 221363384 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -539,336 +538,336 @@ system.cpu.commit.op_class_0::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 221363384 # Class of committed instruction -system.cpu.commit.bw_lim_events 6914114 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 6920063 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 615256240 # The number of ROB reads -system.cpu.rob.rob_writes 699066092 # The number of ROB writes -system.cpu.timesIdled 3079 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 176376 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 615300578 # The number of ROB reads +system.cpu.rob.rob_writes 699132843 # The number of ROB writes +system.cpu.timesIdled 3156 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 199760 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 132071192 # Number of Instructions Simulated system.cpu.committedOps 221363384 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.251094 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.251094 # CPI: Total CPI of All Threads -system.cpu.ipc 0.444229 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.444229 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 456513966 # number of integer regfile reads -system.cpu.int_regfile_writes 239334814 # number of integer regfile writes -system.cpu.fp_regfile_reads 3274089 # number of floating regfile reads -system.cpu.fp_regfile_writes 2057271 # number of floating regfile writes -system.cpu.cc_regfile_reads 102998380 # number of cc regfile reads -system.cpu.cc_regfile_writes 60202762 # number of cc regfile writes -system.cpu.misc_regfile_reads 136901121 # number of misc regfile reads +system.cpu.cpi 2.251344 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.251344 # CPI: Total CPI of All Threads +system.cpu.ipc 0.444179 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.444179 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 456486870 # number of integer regfile reads +system.cpu.int_regfile_writes 239256029 # number of integer regfile writes +system.cpu.fp_regfile_reads 3277423 # number of floating regfile reads +system.cpu.fp_regfile_writes 2057707 # number of floating regfile writes +system.cpu.cc_regfile_reads 102994410 # number of cc regfile reads +system.cpu.cc_regfile_writes 60201710 # number of cc regfile writes +system.cpu.misc_regfile_reads 136869897 # number of misc regfile reads system.cpu.misc_regfile_writes 1689 # number of misc regfile writes -system.cpu.dcache.tags.replacements 52 # number of replacements -system.cpu.dcache.tags.tagsinuse 1443.647680 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 67095165 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 2013 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33330.931446 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 51 # number of replacements +system.cpu.dcache.tags.tagsinuse 1444.566400 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 67084714 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 2000 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33542.357000 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1443.647680 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.352453 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.352453 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1961 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 441 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 1444.566400 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.352677 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.352677 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1949 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 432 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::4 1405 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.478760 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 134197329 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 134197329 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 46580786 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 46580786 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20513865 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20513865 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 67094651 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 67094651 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 67094651 # number of overall hits -system.cpu.dcache.overall_hits::total 67094651 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1141 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1141 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1866 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1866 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 3007 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3007 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3007 # number of overall misses -system.cpu.dcache.overall_misses::total 3007 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 64283437 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 64283437 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 116004574 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 116004574 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 180288011 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 180288011 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 180288011 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 180288011 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 46581927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 46581927 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_task_id_percent::1024 0.475830 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 134176300 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 134176300 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 46570369 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 46570369 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20513845 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20513845 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 67084214 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 67084214 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 67084214 # number of overall hits +system.cpu.dcache.overall_hits::total 67084214 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1050 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1050 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1886 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1886 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 2936 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 2936 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 2936 # number of overall misses +system.cpu.dcache.overall_misses::total 2936 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 66068903 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 66068903 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 130813345 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 130813345 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 196882248 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 196882248 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 196882248 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 196882248 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 46571419 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 46571419 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 67097658 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 67097658 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 67097658 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 67097658 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000091 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000091 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56339.559159 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 56339.559159 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62167.510182 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62167.510182 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 59956.106086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 59956.106086 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 59956.106086 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 248 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 50 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 67087150 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 67087150 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 67087150 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 67087150 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000023 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000092 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000092 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000044 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000044 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000044 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000044 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62922.764762 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62922.764762 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69360.204136 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69360.204136 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67057.986376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67057.986376 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67057.986376 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 241 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 39 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 49.600000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 50 # average number of cycles each access was blocked +system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 48.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 19.500000 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.writebacks::writebacks 10 # number of writebacks system.cpu.dcache.writebacks::total 10 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 666 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 666 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 588 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 588 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 667 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 667 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 667 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 667 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1865 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1865 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 2340 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 2340 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 2340 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 2340 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 33671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 33671000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 111589176 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 111589176 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 145260176 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 145260176 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 145260176 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 145260176 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_hits::cpu.data 589 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 589 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 589 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 589 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 462 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 462 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1885 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1885 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 2347 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 2347 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 2347 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 2347 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36319250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 36319250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 127241905 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 127241905 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 163561155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 163561155 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 163561155 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 163561155 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000091 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000091 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000092 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000092 # mshr miss rate for WriteReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.000035 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000035 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.000035 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70886.315789 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70886.315789 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59833.338338 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59833.338338 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62076.998291 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 62076.998291 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78613.095238 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78613.095238 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67502.336870 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67502.336870 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69689.456753 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69689.456753 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 5851 # number of replacements -system.cpu.icache.tags.tagsinuse 1641.461746 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 26627917 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 7830 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3400.755683 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements 5861 # number of replacements +system.cpu.icache.tags.tagsinuse 1662.434995 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 26645946 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 7838 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 3399.584843 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1641.461746 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.801495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.801495 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 1979 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 813 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 142 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::4 767 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.966309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 53285074 # Number of tag accesses -system.cpu.icache.tags.data_accesses 53285074 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 26627919 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 26627919 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 26627919 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 26627919 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 26627919 # number of overall hits -system.cpu.icache.overall_hits::total 26627919 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 10540 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 10540 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 10540 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 10540 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 10540 # number of overall misses -system.cpu.icache.overall_misses::total 10540 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 391405749 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 391405749 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 391405749 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 391405749 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 391405749 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 391405749 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 26638459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 26638459 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 26638459 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 26638459 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 26638459 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 26638459 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000396 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.000396 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.000396 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.000396 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.000396 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.000396 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37135.270304 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 37135.270304 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 37135.270304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 37135.270304 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 37135.270304 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 1286 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 1662.434995 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.811736 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.811736 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 1977 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 756 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 135 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::4 777 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.965332 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 53321296 # Number of tag accesses +system.cpu.icache.tags.data_accesses 53321296 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 26645946 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 26645946 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 26645946 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 26645946 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 26645946 # number of overall hits +system.cpu.icache.overall_hits::total 26645946 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 10610 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 10610 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 10610 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 10610 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 10610 # number of overall misses +system.cpu.icache.overall_misses::total 10610 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 431026999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 431026999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 431026999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 431026999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 431026999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 431026999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 26656556 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 26656556 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 26656556 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 26656556 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 26656556 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 26656556 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.000398 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.000398 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.000398 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.000398 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.000398 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40624.599340 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 40624.599340 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 40624.599340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 40624.599340 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 40624.599340 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 1664 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 26 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.461538 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 61.629630 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2383 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 2383 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 2383 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 2383 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 2383 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 2383 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8157 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 8157 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 8157 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 8157 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 8157 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 8157 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 292444251 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 292444251 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 292444251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 292444251 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 292444251 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 292444251 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000306 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.000306 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000306 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.000306 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35851.937109 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35851.937109 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35851.937109 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35851.937109 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35851.937109 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35851.937109 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2425 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 2425 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 2425 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 2425 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 2425 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 2425 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8185 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 8185 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 8185 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 8185 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 8185 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 8185 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 323320999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 323320999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 323320999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 323320999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 323320999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 323320999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000307 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.000307 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000307 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.000307 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39501.649236 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39501.649236 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39501.649236 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 39501.649236 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2637.518864 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4367 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 3944 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.107252 # Average number of references to valid blocks. +system.cpu.l2cache.tags.tagsinuse 2641.798011 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 4354 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 3951 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 1.101999 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 1.637738 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 2323.101405 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 312.779722 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.000050 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.070895 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.009545 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.080491 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 3944 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 161 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2666 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120361 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 86925 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 86925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 4317 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 44 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 4361 # number of ReadReq hits +system.cpu.l2cache.tags.occ_blocks::writebacks 1.181969 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 2328.091219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 312.524822 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.000036 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.071048 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.009538 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.080621 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 3951 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 190 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 894 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2664 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.120575 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 87043 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 87043 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 4315 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 34 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 4349 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 10 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 10 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 3 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 3 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 2 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 5 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 5 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 4317 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 49 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 4366 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 4317 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 49 # number of overall hits -system.cpu.l2cache.overall_hits::total 4366 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 3513 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 431 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 3944 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 324 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 324 # number of UpgradeReq misses +system.cpu.l2cache.demand_hits::cpu.inst 4315 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 39 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 4354 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 4315 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 39 # number of overall hits +system.cpu.l2cache.overall_hits::total 4354 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 3522 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 428 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 3950 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 345 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 345 # number of UpgradeReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 1533 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 1533 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 3513 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1964 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 5477 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 3513 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1964 # number of overall misses -system.cpu.l2cache.overall_misses::total 5477 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 240782500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 32741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 273523500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 102420500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 102420500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 240782500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 135161500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 375944000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 240782500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 135161500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 375944000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 7830 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 475 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 8305 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 3522 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1961 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 5483 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 3522 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1961 # number of overall misses +system.cpu.l2cache.overall_misses::total 5483 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 269302250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 35486250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 304788500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 114514250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 114514250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 269302250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 150000500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 419302750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 269302250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 150000500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 419302750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 7837 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 462 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 8299 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::writebacks 10 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses::total 10 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 327 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 327 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 347 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 347 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 1538 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 1538 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 7830 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 2013 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 9843 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 7830 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 2013 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 9843 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.448659 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.907368 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.474895 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.990826 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.990826 # miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 7837 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 2000 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 9837 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 7837 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 2000 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 9837 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.449407 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.926407 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.475961 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994236 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.994236 # miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.996749 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.996749 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.448659 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.975658 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.556436 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.448659 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.975658 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.556436 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68540.421292 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75965.197216 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69351.800203 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66810.502283 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66810.502283 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68540.421292 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68819.501018 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68640.496622 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68540.421292 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68819.501018 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68640.496622 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.449407 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.980500 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.557385 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.449407 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.980500 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.557385 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76462.876207 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82911.799065 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77161.645570 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74699.445532 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74699.445532 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76473.235455 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76462.876207 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76491.840898 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76473.235455 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -877,118 +876,118 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3513 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 431 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 3944 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 324 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 324 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3522 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 428 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 3950 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 345 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 345 # number of UpgradeReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1533 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 1533 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 3513 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 1964 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 5477 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 3513 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 1964 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 5477 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 196758000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27393000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 224151000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3240823 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3240823 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 83086000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 83086000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 196758000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 110479000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 307237000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 196758000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 110479000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 307237000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.907368 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.474895 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.990826 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.990826 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3522 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1961 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5483 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3522 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1961 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5483 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 225343750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 30127250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 255471000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6111844 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6111844 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 95336750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 95336750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 225343750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125464000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 350807750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 225343750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125464000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 350807750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.926407 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.475961 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994236 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.994236 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.996749 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.996749 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.556436 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.448659 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.975658 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.556436 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56008.539710 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63556.844548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56833.417850 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.540123 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.540123 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 54198.303979 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 54198.303979 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56008.539710 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56252.036660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56095.855395 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.557385 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.449407 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.557385 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63981.757524 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70390.771028 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64676.202532 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17715.489855 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17715.489855 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62189.660796 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62189.660796 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.757524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63979.602244 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63980.986686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 8632 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 8631 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 8647 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 8646 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 10 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 327 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 327 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 347 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 347 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 1538 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 1538 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15986 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4690 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 20676 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501056 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 129472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 630528 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 327 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 10507 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 16021 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4704 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 20725 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 501504 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 128640 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 630144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 348 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 10542 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 10507 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 10542 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 10507 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 5263999 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 10542 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 5281499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 12826749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 12941000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3560824 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3566845 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 3943 # Transaction distribution -system.membus.trans_dist::ReadResp 3943 # Transaction distribution -system.membus.trans_dist::UpgradeReq 324 # Transaction distribution -system.membus.trans_dist::UpgradeResp 324 # Transaction distribution +system.membus.trans_dist::ReadReq 3949 # Transaction distribution +system.membus.trans_dist::ReadResp 3949 # Transaction distribution +system.membus.trans_dist::UpgradeReq 345 # Transaction distribution +system.membus.trans_dist::UpgradeResp 345 # Transaction distribution system.membus.trans_dist::ReadExReq 1533 # Transaction distribution system.membus.trans_dist::ReadExResp 1533 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11600 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 11600 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350464 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 350464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 11654 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 11654 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 350848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 350848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 350848 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 5800 # Request fanout histogram +system.membus.snoop_fanout::samples 5827 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 5800 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 5827 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 5800 # Request fanout histogram -system.membus.reqLayer0.occupancy 7074000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 5827 # Request fanout histogram +system.membus.reqLayer0.occupancy 7212001 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 51890176 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 29752405 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index d20d50993..0e62e6e73 100644 --- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.250954 # Number of seconds simulated -sim_ticks 250953957000 # Number of ticks simulated -final_tick 250953957000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 250953957500 # Number of ticks simulated +final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 881800 # Simulator instruction rate (inst/s) -host_op_rate 1477977 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1675544377 # Simulator tick rate (ticks/s) -host_mem_usage 333860 # Number of bytes of host memory used -host_seconds 149.77 # Real time elapsed on the host +host_inst_rate 722726 # Simulator instruction rate (inst/s) +host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1373280924 # Simulator tick rate (ticks/s) +host_mem_usage 338728 # Number of bytes of host memory used +host_seconds 182.74 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -29,35 +29,10 @@ system.physmem.bw_inst_read::total 724276 # In system.physmem.bw_total::cpu.inst 724276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 483276 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207552 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 3160 # Transaction distribution -system.membus.trans_dist::ReadResp 3160 # Transaction distribution -system.membus.trans_dist::ReadExReq 1575 # Transaction distribution -system.membus.trans_dist::ReadExResp 1575 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4735 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 4735 # Request fanout histogram -system.membus.reqLayer0.occupancy 4753500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 42633500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 501907914 # number of cpu cycles simulated +system.cpu.numCycles 501907915 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 132071193 # Number of instructions committed @@ -78,7 +53,7 @@ system.cpu.num_mem_refs 77165304 # nu system.cpu.num_load_insts 56649587 # Number of load instructions system.cpu.num_store_insts 20515717 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 501907913.998000 # Number of busy cycles +system.cpu.num_busy_cycles 501907914.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12326938 # Number of branches fetched @@ -117,13 +92,122 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.cpu.dcache.tags.replacements 41 # number of replacements +system.cpu.dcache.tags.tagsinuse 1363.457564 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457564 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits +system.cpu.dcache.overall_hits::total 77195831 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses +system.cpu.dcache.overall_misses::total 1905 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.writebacks::writebacks 7 # number of writebacks +system.cpu.dcache.writebacks::total 7 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17202000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 17202000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84297000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 84297000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 101499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 101499000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 101499000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.504587 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.504587 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53420.152091 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53420.152091 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53280.314961 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53280.314961 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2836 # number of replacements -system.cpu.icache.tags.tagsinuse 1455.296642 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1455.296636 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 4694 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 36959.879207 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296642 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1455.296636 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.710594 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1858 # Occupied blocks per task id @@ -147,12 +231,12 @@ system.cpu.icache.demand_misses::cpu.inst 4694 # n system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses system.cpu.icache.overall_misses::total 4694 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 180319000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 180319000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 180319000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 180319000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 180319000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 180319500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 180319500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 180319500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 180319500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 180319500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 180319500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 173494367 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 173494367 # number of demand (read+write) accesses @@ -165,12 +249,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 system.cpu.icache.demand_miss_rate::total 0.000027 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000027 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.784832 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 38414.784832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 38414.784832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.784832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 38414.784832 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 38414.891351 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 38414.891351 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 38414.891351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 38414.891351 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 38414.891351 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -185,34 +269,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 4694 system.cpu.icache.demand_mshr_misses::total 4694 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 4694 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 4694 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 170931000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 170931000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 170931000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 170931000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 170931000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 170931000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 173278500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 173278500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 173278500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 173278500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 173278500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 173278500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000027 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000027 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.784832 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36414.784832 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.784832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 36414.784832 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36914.891351 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36914.891351 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36914.891351 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 36914.891351 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 2058.178686 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 2058.178675 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1862 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 3164 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.588496 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 0.021744 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978580 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178362 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.978570 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 228.178361 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000001 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055847 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.006963 # Average percentage of cache occupancy @@ -250,17 +334,17 @@ system.cpu.l2cache.demand_misses::total 4735 # nu system.cpu.l2cache.overall_misses::cpu.inst 2840 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 1895 # number of overall misses system.cpu.l2cache.overall_misses::total 4735 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 147697000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16641500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 164338500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 81900000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 147697000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 98541500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 246238500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 147697000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 98541500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 246238500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 149117500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16801500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 165919000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 82687500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 149117500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 99489000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 248606500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 149117500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 99489000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 248606500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 4694 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 327 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 5021 # number of ReadReq accesses(hits+misses) @@ -285,17 +369,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.717533 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.717533 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52005.985915 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.854430 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52003.907075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52005.985915 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52003.907075 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52506.161972 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.687500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52506.012658 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52504.012672 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52506.161972 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500.791557 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52504.012672 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -315,17 +399,17 @@ system.cpu.l2cache.demand_mshr_misses::total 4735 system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 115020000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12960000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 127980000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63787500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63787500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 115020000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 76747500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 191767500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 115020000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 76747500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 191767500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.629357 # mshr miss rate for ReadReq accesses @@ -337,127 +421,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 41 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.457571 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1905 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 40522.745932 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.457571 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.332875 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 8 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 471 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 20514153 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 77195831 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 77195831 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 77195831 # number of overall hits -system.cpu.dcache.overall_hits::total 77195831 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 327 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 327 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 1578 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1578 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1905 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1905 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1905 # number of overall misses -system.cpu.dcache.overall_misses::total 1905 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 17692500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 17692500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 86664000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 86664000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 104356500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 104356500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 104356500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 104356500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 56682005 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 20515731 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 77197736 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 77197736 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 77197736 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 77197736 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.000077 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.000025 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.000025 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54105.504587 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54105.504587 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54920.152091 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 54920.152091 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54780.314961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54780.314961 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54780.314961 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7 # number of writebacks -system.cpu.dcache.writebacks::total 7 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 327 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 1578 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1905 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1905 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1905 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 17038500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 83508000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 100546500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 100546500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52105.504587 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52920.152091 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52780.314961 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::Writeback 7 # Transaction distribution @@ -489,5 +464,30 @@ system.cpu.toL2Bus.respLayer0.occupancy 7041000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadReq 3160 # Transaction distribution +system.membus.trans_dist::ReadResp 3160 # Transaction distribution +system.membus.trans_dist::ReadExReq 1575 # Transaction distribution +system.membus.trans_dist::ReadExResp 1575 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 9470 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 303040 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 4735 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 4735 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 4735 # Request fanout histogram +system.membus.reqLayer0.occupancy 4754000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 23694000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index 7159169af..4c75131c1 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.962843 # Number of seconds simulated -sim_ticks 1962842856000 # Number of ticks simulated -final_tick 1962842856000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.962613 # Number of seconds simulated +sim_ticks 1962612686500 # Number of ticks simulated +final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1228880 # Simulator instruction rate (inst/s) -host_op_rate 1228880 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 39594262798 # Simulator tick rate (ticks/s) -host_mem_usage 373652 # Number of bytes of host memory used -host_seconds 49.57 # Real time elapsed on the host -sim_insts 60920382 # Number of instructions simulated -sim_ops 60920382 # Number of ops (including micro ops) simulated +host_inst_rate 1121045 # Simulator instruction rate (inst/s) +host_op_rate 1121044 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36128483856 # Simulator tick rate (ticks/s) +host_mem_usage 373592 # Number of bytes of host memory used +host_seconds 54.32 # Real time elapsed on the host +sim_insts 60898638 # Number of instructions simulated +sim_ops 60898638 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 823232 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 24883392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 41664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 386496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 836288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 24736704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 28736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 435776 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 26135744 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 823232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 41664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 864896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7759040 # Number of bytes written to this memory -system.physmem.bytes_written::total 7759040 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.inst 12863 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 388803 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 651 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 6039 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 26038464 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 836288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 28736 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 865024 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7702400 # Number of bytes written to this memory +system.physmem.bytes_written::total 7702400 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.inst 13067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 386511 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 449 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 6809 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 408371 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 121235 # Number of write requests responded to by this memory -system.physmem.num_writes::total 121235 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.inst 419408 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12677221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 21226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 196906 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 406851 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 120350 # Number of write requests responded to by this memory +system.physmem.num_writes::total 120350 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.inst 426110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12603966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 222039 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 489 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13315250 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 419408 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 21226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 440634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3952960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3952960 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3952960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 419408 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12677221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 21226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 196906 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 13267245 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 426110 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 440751 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3924564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3924564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3924564 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 426110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12603966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 222039 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 489 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17268211 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408371 # Number of read requests accepted -system.physmem.writeReqs 162787 # Number of write requests accepted -system.physmem.readBursts 408371 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 162787 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26128640 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10277440 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26135744 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10418368 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2175 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 7051 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25705 # Per bank write bursts -system.physmem.perBankRdBursts::1 25985 # Per bank write bursts -system.physmem.perBankRdBursts::2 25737 # Per bank write bursts -system.physmem.perBankRdBursts::3 25534 # Per bank write bursts -system.physmem.perBankRdBursts::4 24847 # Per bank write bursts -system.physmem.perBankRdBursts::5 24754 # Per bank write bursts -system.physmem.perBankRdBursts::6 25534 # Per bank write bursts -system.physmem.perBankRdBursts::7 25489 # Per bank write bursts -system.physmem.perBankRdBursts::8 25150 # Per bank write bursts -system.physmem.perBankRdBursts::9 25518 # Per bank write bursts -system.physmem.perBankRdBursts::10 25462 # Per bank write bursts -system.physmem.perBankRdBursts::11 25296 # Per bank write bursts -system.physmem.perBankRdBursts::12 25577 # Per bank write bursts -system.physmem.perBankRdBursts::13 25454 # Per bank write bursts -system.physmem.perBankRdBursts::14 26241 # Per bank write bursts -system.physmem.perBankRdBursts::15 25977 # Per bank write bursts -system.physmem.perBankWrBursts::0 10598 # Per bank write bursts -system.physmem.perBankWrBursts::1 10761 # Per bank write bursts -system.physmem.perBankWrBursts::2 9727 # Per bank write bursts -system.physmem.perBankWrBursts::3 9433 # Per bank write bursts -system.physmem.perBankWrBursts::4 8910 # Per bank write bursts -system.physmem.perBankWrBursts::5 9140 # Per bank write bursts -system.physmem.perBankWrBursts::6 9908 # Per bank write bursts -system.physmem.perBankWrBursts::7 9771 # Per bank write bursts -system.physmem.perBankWrBursts::8 9710 # Per bank write bursts -system.physmem.perBankWrBursts::9 9867 # Per bank write bursts -system.physmem.perBankWrBursts::10 9923 # Per bank write bursts -system.physmem.perBankWrBursts::11 10306 # Per bank write bursts -system.physmem.perBankWrBursts::12 10733 # Per bank write bursts -system.physmem.perBankWrBursts::13 10678 # Per bank write bursts -system.physmem.perBankWrBursts::14 10553 # Per bank write bursts -system.physmem.perBankWrBursts::15 10567 # Per bank write bursts +system.physmem.bw_total::total 17191810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 406851 # Number of read requests accepted +system.physmem.writeReqs 161902 # Number of write requests accepted +system.physmem.readBursts 406851 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 161902 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 26031872 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6592 # Total number of bytes read from write queue +system.physmem.bytesWritten 8721536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 26038464 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10361728 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 103 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 25609 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 6974 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 25141 # Per bank write bursts +system.physmem.perBankRdBursts::1 25398 # Per bank write bursts +system.physmem.perBankRdBursts::2 25524 # Per bank write bursts +system.physmem.perBankRdBursts::3 24918 # Per bank write bursts +system.physmem.perBankRdBursts::4 25169 # Per bank write bursts +system.physmem.perBankRdBursts::5 25258 # Per bank write bursts +system.physmem.perBankRdBursts::6 25808 # Per bank write bursts +system.physmem.perBankRdBursts::7 25541 # Per bank write bursts +system.physmem.perBankRdBursts::8 25675 # Per bank write bursts +system.physmem.perBankRdBursts::9 25330 # Per bank write bursts +system.physmem.perBankRdBursts::10 25284 # Per bank write bursts +system.physmem.perBankRdBursts::11 25615 # Per bank write bursts +system.physmem.perBankRdBursts::12 25647 # Per bank write bursts +system.physmem.perBankRdBursts::13 25653 # Per bank write bursts +system.physmem.perBankRdBursts::14 25754 # Per bank write bursts +system.physmem.perBankRdBursts::15 25033 # Per bank write bursts +system.physmem.perBankWrBursts::0 8965 # Per bank write bursts +system.physmem.perBankWrBursts::1 8625 # Per bank write bursts +system.physmem.perBankWrBursts::2 8456 # Per bank write bursts +system.physmem.perBankWrBursts::3 7799 # Per bank write bursts +system.physmem.perBankWrBursts::4 8065 # Per bank write bursts +system.physmem.perBankWrBursts::5 8041 # Per bank write bursts +system.physmem.perBankWrBursts::6 8610 # Per bank write bursts +system.physmem.perBankWrBursts::7 8172 # Per bank write bursts +system.physmem.perBankWrBursts::8 8465 # Per bank write bursts +system.physmem.perBankWrBursts::9 8053 # Per bank write bursts +system.physmem.perBankWrBursts::10 8222 # Per bank write bursts +system.physmem.perBankWrBursts::11 8481 # Per bank write bursts +system.physmem.perBankWrBursts::12 8850 # Per bank write bursts +system.physmem.perBankWrBursts::13 9510 # Per bank write bursts +system.physmem.perBankWrBursts::14 9309 # Per bank write bursts +system.physmem.perBankWrBursts::15 8651 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1962837817500 # Total gap between requests +system.physmem.numWrRetry 56 # Number of times write queue was full causing retry +system.physmem.totGap 1962566141500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408371 # Read request sizes (log2) +system.physmem.readPktSize::6 406851 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 162787 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 408177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70 # What read queue length does an incoming req see +system.physmem.writePktSize::6 161902 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 406672 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see @@ -158,185 +158,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9433 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11550 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12406 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8581 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6888 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 265 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 202 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 184 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 163 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 69318 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 525.203843 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 317.866807 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 416.347675 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 16137 23.28% 23.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 12161 17.54% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5284 7.62% 48.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3087 4.45% 52.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3309 4.77% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1757 2.53% 60.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1519 2.19% 62.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1296 1.87% 64.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24768 35.73% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 69318 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5881 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 69.418466 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2107.784288 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-4095 5876 99.91% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4096-8191 1 0.02% 99.93% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::40960-45055 1 0.02% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::57344-61439 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::73728-77823 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::122880-126975 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5881 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5881 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.305730 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.811619 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 33.369719 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4828 82.09% 82.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 189 3.21% 85.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 283 4.81% 90.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 60 1.02% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 106 1.80% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 43 0.73% 93.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.29% 93.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 8 0.14% 94.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 22 0.37% 94.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 7 0.12% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 14 0.24% 94.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 3 0.05% 94.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 16 0.27% 95.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 2 0.03% 95.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 15 0.26% 95.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 48 0.82% 96.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 18 0.31% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 12 0.20% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 85 1.45% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 44 0.75% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 9 0.15% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 24 0.41% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.17% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 5 0.09% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 2 0.03% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::264-271 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5881 # Writes before turning the bus around for reads -system.physmem.totQLat 2189518000 # Total ticks spent queuing -system.physmem.totMemAccLat 9844393000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2041300000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5363.05 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6003 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5615 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5716 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5563 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5727 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5644 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7778 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1530 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 943 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1883 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1543 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2742 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2945 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 765 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 520 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 136 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 78 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 98 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 67633 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 513.852823 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 307.797069 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 417.051196 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 16141 23.87% 23.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 12717 18.80% 42.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5311 7.85% 50.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2897 4.28% 54.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2115 3.13% 57.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1690 2.50% 60.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2144 3.17% 63.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1403 2.07% 65.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23215 34.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 67633 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4988 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 81.544306 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 2972.635603 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4985 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 4988 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4988 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.320369 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.529999 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.006905 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4741 95.05% 95.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 52 1.04% 96.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 5 0.10% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 6 0.12% 96.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 4 0.08% 96.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.24% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 26 0.52% 97.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 19 0.38% 97.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 10 0.20% 97.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 13 0.26% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 3 0.06% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.04% 98.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 5 0.10% 98.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 5 0.10% 98.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 12 0.24% 98.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 16 0.32% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 4 0.08% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 10 0.20% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.04% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.02% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 4 0.08% 99.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.04% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 2 0.04% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 10 0.20% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.06% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.04% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 2 0.04% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::816-831 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4988 # Writes before turning the bus around for reads +system.physmem.totQLat 2137453500 # Total ticks spent queuing +system.physmem.totMemAccLat 9763978500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2033740000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5254.98 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24113.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.31 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.24 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.32 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.31 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 24004.98 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.26 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.44 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.27 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.28 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing -system.physmem.readRowHits 365775 # Number of row buffer hits during reads -system.physmem.writeRowHits 133752 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.28 # Row buffer hit rate for writes -system.physmem.avgGap 3436593.41 # Average gap between requests -system.physmem.pageHitRate 87.81 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 258098400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140827500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1587963000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 507047040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 65554579665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1120197596250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1316449002255 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.687203 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1863305388500 # Time in different power states -system.physmem_0.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem.avgWrQLen 25.00 # Average write queue length when enqueuing +system.physmem.readRowHits 364433 # Number of row buffer hits during reads +system.physmem.writeRowHits 110956 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.60 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 81.41 # Row buffer hit rate for writes +system.physmem.avgGap 3450647.54 # Average gap between requests +system.physmem.pageHitRate 87.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 253449000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 138290625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1581504600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 432429840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 66287825100 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1119418909500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1316300550825 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.688732 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1862013795212 # Time in different power states +system.physmem_0.memoryStateTime::REF 65535860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33987247750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35060566038 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 265945680 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 145109250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1596465000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 533543760 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 128202890400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 65970100260 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1119833096250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1316547150600 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.737211 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1862702158750 # Time in different power states -system.physmem_1.memoryStateTime::REF 65543400000 # Time in different power states +system.physmem_1.actEnergy 257856480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 140695500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1591129800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 450625680 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 128188142160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 66523569975 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1119212115750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1316364135345 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.721130 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1861673243216 # Time in different power states +system.physmem_1.memoryStateTime::REF 65535860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34590463750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35401118034 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 7535038 # DTB read hits -system.cpu0.dtb.read_misses 7765 # DTB read misses +system.cpu0.dtb.read_hits 7492205 # DTB read hits +system.cpu0.dtb.read_misses 7443 # DTB read misses system.cpu0.dtb.read_acv 210 # DTB read access violations -system.cpu0.dtb.read_accesses 524069 # DTB read accesses -system.cpu0.dtb.write_hits 5127057 # DTB write hits -system.cpu0.dtb.write_misses 910 # DTB write misses -system.cpu0.dtb.write_acv 133 # DTB write access violations -system.cpu0.dtb.write_accesses 202595 # DTB write accesses -system.cpu0.dtb.data_hits 12662095 # DTB hits -system.cpu0.dtb.data_misses 8675 # DTB misses -system.cpu0.dtb.data_acv 343 # DTB access violations -system.cpu0.dtb.data_accesses 726664 # DTB accesses -system.cpu0.itb.fetch_hits 3654300 # ITB hits -system.cpu0.itb.fetch_misses 3984 # ITB misses +system.cpu0.dtb.read_accesses 490673 # DTB read accesses +system.cpu0.dtb.write_hits 5067323 # DTB write hits +system.cpu0.dtb.write_misses 813 # DTB write misses +system.cpu0.dtb.write_acv 134 # DTB write access violations +system.cpu0.dtb.write_accesses 187452 # DTB write accesses +system.cpu0.dtb.data_hits 12559528 # DTB hits +system.cpu0.dtb.data_misses 8256 # DTB misses +system.cpu0.dtb.data_acv 344 # DTB access violations +system.cpu0.dtb.data_accesses 678125 # DTB accesses +system.cpu0.itb.fetch_hits 3501951 # ITB hits +system.cpu0.itb.fetch_misses 3871 # ITB misses system.cpu0.itb.fetch_acv 184 # ITB acv -system.cpu0.itb.fetch_accesses 3658284 # ITB accesses +system.cpu0.itb.fetch_accesses 3505822 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -349,241 +354,240 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3925685712 # number of cpu cycles simulated +system.cpu0.numCycles 3923838766 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 47981838 # Number of instructions committed -system.cpu0.committedOps 47981838 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 44508329 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 212945 # Number of float alu accesses -system.cpu0.num_func_calls 1202945 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 5633344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 44508329 # number of integer instructions -system.cpu0.num_fp_insts 212945 # number of float instructions -system.cpu0.num_int_register_reads 61205329 # number of times the integer registers were read -system.cpu0.num_int_register_writes 33143507 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 104073 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 105864 # number of times the floating registers were written -system.cpu0.num_mem_refs 12703139 # number of memory refs -system.cpu0.num_load_insts 7562835 # Number of load instructions -system.cpu0.num_store_insts 5140304 # Number of store instructions -system.cpu0.num_idle_cycles 3702094605.998114 # Number of idle cycles -system.cpu0.num_busy_cycles 223591106.001886 # Number of busy cycles -system.cpu0.not_idle_fraction 0.056956 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.943044 # Percentage of idle cycles -system.cpu0.Branches 7224625 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2734428 5.70% 5.70% # Class of executed instruction -system.cpu0.op_class::IntAlu 31547561 65.74% 71.43% # Class of executed instruction -system.cpu0.op_class::IntMult 52422 0.11% 71.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 71.54% # Class of executed instruction -system.cpu0.op_class::FloatAdd 26783 0.06% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatDiv 1883 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.60% # Class of executed instruction -system.cpu0.op_class::MemRead 7738872 16.13% 87.73% # Class of executed instruction -system.cpu0.op_class::MemWrite 5146421 10.72% 98.45% # Class of executed instruction -system.cpu0.op_class::IprAccess 742486 1.55% 100.00% # Class of executed instruction +system.cpu0.committedInsts 47743384 # Number of instructions committed +system.cpu0.committedOps 47743384 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 44279734 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 210698 # Number of float alu accesses +system.cpu0.num_func_calls 1202353 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 5609016 # number of instructions that are conditional controls +system.cpu0.num_int_insts 44279734 # number of integer instructions +system.cpu0.num_fp_insts 210698 # number of float instructions +system.cpu0.num_int_register_reads 60867436 # number of times the integer registers were read +system.cpu0.num_int_register_writes 32999466 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 102334 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 104190 # number of times the floating registers were written +system.cpu0.num_mem_refs 12599731 # number of memory refs +system.cpu0.num_load_insts 7519361 # Number of load instructions +system.cpu0.num_store_insts 5080370 # Number of store instructions +system.cpu0.num_idle_cycles 3698952400.393103 # Number of idle cycles +system.cpu0.num_busy_cycles 224886365.606898 # Number of busy cycles +system.cpu0.not_idle_fraction 0.057313 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.942687 # Percentage of idle cycles +system.cpu0.Branches 7198745 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2727567 5.71% 5.71% # Class of executed instruction +system.cpu0.op_class::IntAlu 31426598 65.81% 71.52% # Class of executed instruction +system.cpu0.op_class::IntMult 52886 0.11% 71.63% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 71.63% # Class of executed instruction +system.cpu0.op_class::FloatAdd 25715 0.05% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatDiv 1656 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 71.69% # Class of executed instruction +system.cpu0.op_class::MemRead 7694830 16.11% 87.81% # Class of executed instruction +system.cpu0.op_class::MemWrite 5086464 10.65% 98.46% # Class of executed instruction +system.cpu0.op_class::IprAccess 736268 1.54% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 47990856 # Class of executed instruction +system.cpu0.op_class::total 47751984 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 6794 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 165589 # number of hwrei instructions executed -system.cpu0.kern.ipl_count::0 56925 40.22% 40.22% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::21 131 0.09% 40.31% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1976 1.40% 41.70% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::30 424 0.30% 42.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 82092 58.00% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 141548 # number of times we switched to this ipl -system.cpu0.kern.ipl_good::0 56392 49.08% 49.08% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.inst.quiesce 6802 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 164994 # number of hwrei instructions executed +system.cpu0.kern.ipl_count::0 56858 40.19% 40.19% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::21 131 0.09% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1973 1.39% 41.68% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::30 421 0.30% 41.97% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 82092 58.03% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 141475 # number of times we switched to this ipl +system.cpu0.kern.ipl_good::0 56322 49.08% 49.08% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.11% 49.20% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::22 1976 1.72% 50.92% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::30 424 0.37% 51.29% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::31 55969 48.71% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good::total 114892 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1903333022000 96.97% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 94388000 0.00% 96.97% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 768238500 0.04% 97.01% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 314332500 0.02% 97.03% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 58332103000 2.97% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1962842084000 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used::0 0.990637 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_good::22 1973 1.72% 50.92% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::30 421 0.37% 51.28% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::31 55901 48.72% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good::total 114748 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_ticks::0 1900658476000 96.88% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 90840500 0.00% 96.88% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 754578500 0.04% 96.92% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 304090000 0.02% 96.94% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 60111368000 3.06% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1961919353000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used::0 0.990573 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.681784 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.811682 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.syscall::2 8 3.42% 3.42% # number of syscalls executed -system.cpu0.kern.syscall::3 20 8.55% 11.97% # number of syscalls executed -system.cpu0.kern.syscall::4 4 1.71% 13.68% # number of syscalls executed -system.cpu0.kern.syscall::6 33 14.10% 27.78% # number of syscalls executed -system.cpu0.kern.syscall::12 1 0.43% 28.21% # number of syscalls executed -system.cpu0.kern.syscall::17 10 4.27% 32.48% # number of syscalls executed -system.cpu0.kern.syscall::19 10 4.27% 36.75% # number of syscalls executed -system.cpu0.kern.syscall::20 6 2.56% 39.32% # number of syscalls executed -system.cpu0.kern.syscall::23 1 0.43% 39.74% # number of syscalls executed -system.cpu0.kern.syscall::24 3 1.28% 41.03% # number of syscalls executed -system.cpu0.kern.syscall::33 8 3.42% 44.44% # number of syscalls executed -system.cpu0.kern.syscall::41 2 0.85% 45.30% # number of syscalls executed -system.cpu0.kern.syscall::45 39 16.67% 61.97% # number of syscalls executed -system.cpu0.kern.syscall::47 3 1.28% 63.25% # number of syscalls executed -system.cpu0.kern.syscall::48 10 4.27% 67.52% # number of syscalls executed -system.cpu0.kern.syscall::54 10 4.27% 71.79% # number of syscalls executed -system.cpu0.kern.syscall::58 1 0.43% 72.22% # number of syscalls executed -system.cpu0.kern.syscall::59 6 2.56% 74.79% # number of syscalls executed -system.cpu0.kern.syscall::71 27 11.54% 86.32% # number of syscalls executed -system.cpu0.kern.syscall::73 3 1.28% 87.61% # number of syscalls executed -system.cpu0.kern.syscall::74 7 2.99% 90.60% # number of syscalls executed -system.cpu0.kern.syscall::87 1 0.43% 91.03% # number of syscalls executed -system.cpu0.kern.syscall::90 3 1.28% 92.31% # number of syscalls executed -system.cpu0.kern.syscall::92 9 3.85% 96.15% # number of syscalls executed -system.cpu0.kern.syscall::97 2 0.85% 97.01% # number of syscalls executed -system.cpu0.kern.syscall::98 2 0.85% 97.86% # number of syscalls executed -system.cpu0.kern.syscall::132 1 0.43% 98.29% # number of syscalls executed -system.cpu0.kern.syscall::144 2 0.85% 99.15% # number of syscalls executed -system.cpu0.kern.syscall::147 2 0.85% 100.00% # number of syscalls executed -system.cpu0.kern.syscall::total 234 # number of syscalls executed +system.cpu0.kern.ipl_used::31 0.680956 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.811083 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.syscall::2 8 3.60% 3.60% # number of syscalls executed +system.cpu0.kern.syscall::3 19 8.56% 12.16% # number of syscalls executed +system.cpu0.kern.syscall::4 4 1.80% 13.96% # number of syscalls executed +system.cpu0.kern.syscall::6 32 14.41% 28.38% # number of syscalls executed +system.cpu0.kern.syscall::12 1 0.45% 28.83% # number of syscalls executed +system.cpu0.kern.syscall::17 9 4.05% 32.88% # number of syscalls executed +system.cpu0.kern.syscall::19 10 4.50% 37.39% # number of syscalls executed +system.cpu0.kern.syscall::20 6 2.70% 40.09% # number of syscalls executed +system.cpu0.kern.syscall::23 1 0.45% 40.54% # number of syscalls executed +system.cpu0.kern.syscall::24 3 1.35% 41.89% # number of syscalls executed +system.cpu0.kern.syscall::33 7 3.15% 45.05% # number of syscalls executed +system.cpu0.kern.syscall::41 2 0.90% 45.95% # number of syscalls executed +system.cpu0.kern.syscall::45 36 16.22% 62.16% # number of syscalls executed +system.cpu0.kern.syscall::47 3 1.35% 63.51% # number of syscalls executed +system.cpu0.kern.syscall::48 10 4.50% 68.02% # number of syscalls executed +system.cpu0.kern.syscall::54 10 4.50% 72.52% # number of syscalls executed +system.cpu0.kern.syscall::58 1 0.45% 72.97% # number of syscalls executed +system.cpu0.kern.syscall::59 6 2.70% 75.68% # number of syscalls executed +system.cpu0.kern.syscall::71 23 10.36% 86.04% # number of syscalls executed +system.cpu0.kern.syscall::73 3 1.35% 87.39% # number of syscalls executed +system.cpu0.kern.syscall::74 6 2.70% 90.09% # number of syscalls executed +system.cpu0.kern.syscall::87 1 0.45% 90.54% # number of syscalls executed +system.cpu0.kern.syscall::90 3 1.35% 91.89% # number of syscalls executed +system.cpu0.kern.syscall::92 9 4.05% 95.95% # number of syscalls executed +system.cpu0.kern.syscall::97 2 0.90% 96.85% # number of syscalls executed +system.cpu0.kern.syscall::98 2 0.90% 97.75% # number of syscalls executed +system.cpu0.kern.syscall::132 1 0.45% 98.20% # number of syscalls executed +system.cpu0.kern.syscall::144 2 0.90% 99.10% # number of syscalls executed +system.cpu0.kern.syscall::147 2 0.90% 100.00% # number of syscalls executed +system.cpu0.kern.syscall::total 222 # number of syscalls executed system.cpu0.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu0.kern.callpal::wripir 512 0.34% 0.34% # number of callpals executed +system.cpu0.kern.callpal::wripir 503 0.34% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrmces 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrfen 1 0.00% 0.34% # number of callpals executed system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.34% # number of callpals executed -system.cpu0.kern.callpal::swpctx 3097 2.07% 2.41% # number of callpals executed -system.cpu0.kern.callpal::tbi 51 0.03% 2.44% # number of callpals executed -system.cpu0.kern.callpal::wrent 7 0.00% 2.45% # number of callpals executed -system.cpu0.kern.callpal::swpipl 134593 89.81% 92.26% # number of callpals executed -system.cpu0.kern.callpal::rdps 6634 4.43% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrkgp 1 0.00% 96.68% # number of callpals executed -system.cpu0.kern.callpal::wrusp 4 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rdusp 9 0.01% 96.69% # number of callpals executed -system.cpu0.kern.callpal::whami 2 0.00% 96.69% # number of callpals executed -system.cpu0.kern.callpal::rti 4424 2.95% 99.64% # number of callpals executed -system.cpu0.kern.callpal::callsys 394 0.26% 99.91% # number of callpals executed -system.cpu0.kern.callpal::imb 139 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 149871 # number of callpals executed -system.cpu0.kern.mode_switch::kernel 7013 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1370 # number of protection mode switches +system.cpu0.kern.callpal::swpctx 3067 2.05% 2.39% # number of callpals executed +system.cpu0.kern.callpal::tbi 51 0.03% 2.42% # number of callpals executed +system.cpu0.kern.callpal::wrent 7 0.00% 2.42% # number of callpals executed +system.cpu0.kern.callpal::swpipl 134616 89.86% 92.28% # number of callpals executed +system.cpu0.kern.callpal::rdps 6699 4.47% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrkgp 1 0.00% 96.75% # number of callpals executed +system.cpu0.kern.callpal::wrusp 3 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rdusp 9 0.01% 96.76% # number of callpals executed +system.cpu0.kern.callpal::whami 2 0.00% 96.76% # number of callpals executed +system.cpu0.kern.callpal::rti 4333 2.89% 99.65% # number of callpals executed +system.cpu0.kern.callpal::callsys 381 0.25% 99.91% # number of callpals executed +system.cpu0.kern.callpal::imb 136 0.09% 100.00% # number of callpals executed +system.cpu0.kern.callpal::total 149812 # number of callpals executed +system.cpu0.kern.mode_switch::kernel 6888 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1282 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1369 -system.cpu0.kern.mode_good::user 1370 +system.cpu0.kern.mode_good::kernel 1282 +system.cpu0.kern.mode_good::user 1282 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.195209 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.186121 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.326733 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1959061538500 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3780541000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.313831 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1958151397500 99.82% 99.82% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3535867500 0.18% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu0.kern.swap_context 3098 # number of times the context was actually changed -system.cpu0.dcache.tags.replacements 1190069 # number of replacements -system.cpu0.dcache.tags.tagsinuse 505.197532 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11466522 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 1190581 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 9.631031 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 108210250 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.197532 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986714 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.986714 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 51892703 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 51892703 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6451021 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6451021 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 4712504 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 4712504 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140772 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 140772 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148353 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 148353 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11163525 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11163525 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11163525 # number of overall hits -system.cpu0.dcache.overall_hits::total 11163525 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 942274 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 942274 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 257633 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 257633 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13709 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 13709 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5579 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 5579 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1199907 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1199907 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1199907 # number of overall misses -system.cpu0.dcache.overall_misses::total 1199907 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 27224956000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 27224956000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10342084186 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 10342084186 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150000000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 150000000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 42703895 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 42703895 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 37567040186 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 37567040186 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 37567040186 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 37567040186 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7393295 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 7393295 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4970137 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4970137 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 154481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 153932 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 12363432 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 12363432 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 12363432 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 12363432 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127450 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.127450 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.051836 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088742 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088742 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.036243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.036243 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097053 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.097053 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097053 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.097053 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28892.823107 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28892.823107 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40142.699833 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 40142.699833 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10941.717120 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10941.717120 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7654.399534 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7654.399534 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 31308.293214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31308.293214 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 31308.293214 # average overall miss latency +system.cpu0.kern.swap_context 3068 # number of times the context was actually changed +system.cpu0.dcache.tags.replacements 1180939 # number of replacements +system.cpu0.dcache.tags.tagsinuse 505.262035 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11368359 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 1181356 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 9.623144 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 505.262035 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.986840 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.986840 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 372 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::3 45 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 51471280 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 51471280 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6411907 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6411907 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 4659091 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 4659091 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 140391 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 140391 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 148074 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 148074 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11070998 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11070998 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11070998 # number of overall hits +system.cpu0.dcache.overall_hits::total 11070998 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 938638 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 938638 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 251661 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 251661 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 13662 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 13662 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 5430 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 5430 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1190299 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1190299 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1190299 # number of overall misses +system.cpu0.dcache.overall_misses::total 1190299 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 29060390999 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 29060390999 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 10906399185 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 10906399185 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 150333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 150333500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 48525392 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 48525392 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 39966790184 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 39966790184 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 39966790184 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 39966790184 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7350545 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 7350545 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4910752 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4910752 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 154053 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 154053 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 153504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 153504 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12261297 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12261297 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12261297 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12261297 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.127696 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.127696 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.051247 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.051247 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.088684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.088684 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.035374 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.035374 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.097078 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.097078 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097078 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.097078 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30960.168882 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30960.168882 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 43337.661318 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 43337.661318 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 11003.769580 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 11003.769580 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8936.536280 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8936.536280 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33577.101370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33577.101370 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33577.101370 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,62 +596,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 685914 # number of writebacks -system.cpu0.dcache.writebacks::total 685914 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 942274 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 942274 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 257633 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 257633 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13709 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13709 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5579 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 5579 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 1199907 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 1199907 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 1199907 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 1199907 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 25214933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 25214933000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9773693814 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9773693814 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 122568000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 122568000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31544105 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31544105 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 34988626814 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 34988626814 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 34988626814 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 34988626814 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1461501000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1461501000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2267119000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2267119000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3728620000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3728620000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127450 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127450 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051836 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051836 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088742 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088742 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.036243 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.036243 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.097053 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097053 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.097053 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26759.661203 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26759.661203 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37936.498096 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37936.498096 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8940.695893 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8940.695893 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5654.078688 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5654.078688 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29159.448869 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29159.448869 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 679102 # number of writebacks +system.cpu0.dcache.writebacks::total 679102 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 938638 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 938638 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 251661 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 251661 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 13662 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 13662 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 5430 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 1190299 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476948315 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 10476948315 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 129828500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 129828500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 40378608 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 40378608 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 38003531316 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 38003531316 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 38003531316 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 38003531316 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1474416000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1474416000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2293895500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2293895500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3768311500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3768311500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127696 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127696 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.051247 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.051247 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088684 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088684 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.035374 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.035374 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.097078 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.097078 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.097078 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29326.090571 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29326.090571 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41631.195596 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41631.195596 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9502.891231 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9502.891231 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 7436.207735 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 7436.207735 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.718427 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.718427 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -655,59 +659,57 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 699791 # number of replacements -system.cpu0.icache.tags.tagsinuse 508.391652 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 47290432 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 700302 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.528626 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 40276505250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.391652 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992952 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.992952 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 436 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 48691282 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 48691282 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 47290432 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 47290432 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 47290432 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 47290432 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 47290432 # number of overall hits -system.cpu0.icache.overall_hits::total 47290432 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 700425 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 700425 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 700425 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 700425 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 700425 # number of overall misses -system.cpu0.icache.overall_misses::total 700425 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 9965953746 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 9965953746 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 9965953746 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 9965953746 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 9965953746 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 9965953746 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 47990857 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 47990857 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 47990857 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 47990857 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 47990857 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 47990857 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014595 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014595 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014595 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014595 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014595 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014595 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14228.438085 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14228.438085 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14228.438085 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14228.438085 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14228.438085 # average overall miss latency +system.cpu0.icache.tags.replacements 698758 # number of replacements +system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 47052596 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 699270 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.288166 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 42435665250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 508.155937 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.992492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.992492 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 356 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::3 156 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 48451372 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 48451372 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 47052596 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 47052596 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 47052596 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 47052596 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 47052596 # number of overall hits +system.cpu0.icache.overall_hits::total 47052596 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 699388 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 699388 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 699388 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 699388 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 699388 # number of overall misses +system.cpu0.icache.overall_misses::total 699388 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10012837997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10012837997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10012837997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10012837997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10012837997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10012837997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 47751984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 47751984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 47751984 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 47751984 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 47751984 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 47751984 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014646 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014646 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014646 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014646 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014646 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014646 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14316.571055 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14316.571055 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14316.571055 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14316.571055 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14316.571055 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -716,51 +718,51 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 700425 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 700425 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 700425 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 700425 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 700425 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 700425 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8560109254 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 8560109254 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8560109254 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 8560109254 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8560109254 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 8560109254 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014595 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014595 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014595 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12221.307426 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12221.307426 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12221.307426 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 699388 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 699388 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 699388 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 699388 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 699388 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 699388 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 8958710003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 8958710003 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 8958710003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 8958710003 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 8958710003 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 8958710003 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014646 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014646 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014646 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014646 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12809.356184 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12809.356184 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12809.356184 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.read_hits 2381610 # DTB read hits -system.cpu1.dtb.read_misses 2620 # DTB read misses +system.cpu1.dtb.read_hits 2419579 # DTB read hits +system.cpu1.dtb.read_misses 2992 # DTB read misses system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_accesses 205337 # DTB read accesses -system.cpu1.dtb.write_hits 1701782 # DTB write hits -system.cpu1.dtb.write_misses 235 # DTB write misses -system.cpu1.dtb.write_acv 24 # DTB write access violations -system.cpu1.dtb.write_accesses 89739 # DTB write accesses -system.cpu1.dtb.data_hits 4083392 # DTB hits -system.cpu1.dtb.data_misses 2855 # DTB misses -system.cpu1.dtb.data_acv 24 # DTB access violations -system.cpu1.dtb.data_accesses 295076 # DTB accesses -system.cpu1.itb.fetch_hits 1808769 # ITB hits -system.cpu1.itb.fetch_misses 1064 # ITB misses +system.cpu1.dtb.read_accesses 239363 # DTB read accesses +system.cpu1.dtb.write_hits 1757217 # DTB write hits +system.cpu1.dtb.write_misses 341 # DTB write misses +system.cpu1.dtb.write_acv 29 # DTB write access violations +system.cpu1.dtb.write_accesses 105247 # DTB write accesses +system.cpu1.dtb.data_hits 4176796 # DTB hits +system.cpu1.dtb.data_misses 3333 # DTB misses +system.cpu1.dtb.data_acv 29 # DTB access violations +system.cpu1.dtb.data_accesses 344610 # DTB accesses +system.cpu1.itb.fetch_hits 1964101 # ITB hits +system.cpu1.itb.fetch_misses 1216 # ITB misses system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_accesses 1809833 # ITB accesses +system.cpu1.itb.fetch_accesses 1965317 # ITB accesses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.read_acv 0 # DTB read access violations @@ -773,219 +775,220 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3923834021 # number of cpu cycles simulated +system.cpu1.numCycles 3925225373 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 12938544 # Number of instructions committed -system.cpu1.committedOps 12938544 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 11924615 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 171199 # Number of float alu accesses -system.cpu1.num_func_calls 411382 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1282019 # number of instructions that are conditional controls -system.cpu1.num_int_insts 11924615 # number of integer instructions -system.cpu1.num_fp_insts 171199 # number of float instructions -system.cpu1.num_int_register_reads 16391744 # number of times the integer registers were read -system.cpu1.num_int_register_writes 8774012 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 88996 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 90942 # number of times the floating registers were written -system.cpu1.num_mem_refs 4106042 # number of memory refs -system.cpu1.num_load_insts 2395192 # Number of load instructions -system.cpu1.num_store_insts 1710850 # Number of store instructions -system.cpu1.num_idle_cycles 3874343491.006502 # Number of idle cycles -system.cpu1.num_busy_cycles 49490529.993498 # Number of busy cycles -system.cpu1.not_idle_fraction 0.012613 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.987387 # Percentage of idle cycles -system.cpu1.Branches 1847277 # Number of branches fetched -system.cpu1.op_class::No_OpClass 699299 5.40% 5.40% # Class of executed instruction -system.cpu1.op_class::IntAlu 7669413 59.26% 64.67% # Class of executed instruction -system.cpu1.op_class::IntMult 22263 0.17% 64.84% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.84% # Class of executed instruction -system.cpu1.op_class::FloatAdd 13113 0.10% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.94% # Class of executed instruction -system.cpu1.op_class::FloatDiv 1759 0.01% 64.95% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.95% # Class of executed instruction -system.cpu1.op_class::MemRead 2466523 19.06% 84.01% # Class of executed instruction -system.cpu1.op_class::MemWrite 1711831 13.23% 97.24% # Class of executed instruction -system.cpu1.op_class::IprAccess 357222 2.76% 100.00% # Class of executed instruction +system.cpu1.committedInsts 13155254 # Number of instructions committed +system.cpu1.committedOps 13155254 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 12132982 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 173111 # Number of float alu accesses +system.cpu1.num_func_calls 411301 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1304865 # number of instructions that are conditional controls +system.cpu1.num_int_insts 12132982 # number of integer instructions +system.cpu1.num_fp_insts 173111 # number of float instructions +system.cpu1.num_int_register_reads 16703630 # number of times the integer registers were read +system.cpu1.num_int_register_writes 8903954 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 90570 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 92446 # number of times the floating registers were written +system.cpu1.num_mem_refs 4200357 # number of memory refs +system.cpu1.num_load_insts 2433886 # Number of load instructions +system.cpu1.num_store_insts 1766471 # Number of store instructions +system.cpu1.num_idle_cycles 3876126897.998025 # Number of idle cycles +system.cpu1.num_busy_cycles 49098475.001975 # Number of busy cycles +system.cpu1.not_idle_fraction 0.012508 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.987492 # Percentage of idle cycles +system.cpu1.Branches 1871330 # Number of branches fetched +system.cpu1.op_class::No_OpClass 704516 5.35% 5.35% # Class of executed instruction +system.cpu1.op_class::IntAlu 7779367 59.12% 64.47% # Class of executed instruction +system.cpu1.op_class::IntMult 21509 0.16% 64.64% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.64% # Class of executed instruction +system.cpu1.op_class::FloatAdd 14171 0.11% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.75% # Class of executed instruction +system.cpu1.op_class::FloatDiv 1986 0.02% 64.76% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.76% # Class of executed instruction +system.cpu1.op_class::MemRead 2505658 19.04% 83.80% # Class of executed instruction +system.cpu1.op_class::MemWrite 1767460 13.43% 97.23% # Class of executed instruction +system.cpu1.op_class::IprAccess 363949 2.77% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 12941423 # Class of executed instruction +system.cpu1.op_class::total 13158616 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed -system.cpu1.kern.inst.hwrei 77895 # number of hwrei instructions executed -system.cpu1.kern.ipl_count::0 26463 38.26% 38.26% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1970 2.85% 41.11% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::30 512 0.74% 41.85% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 40215 58.15% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 69160 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 25619 48.15% 48.15% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1970 3.70% 51.85% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::30 512 0.96% 52.81% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 25107 47.19% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 53208 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1910451046000 97.38% 97.38% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 701160000 0.04% 97.41% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 358891000 0.02% 97.43% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 50405883500 2.57% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1961916980500 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.968106 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.inst.quiesce 2740 # number of quiesce instructions executed +system.cpu1.kern.inst.hwrei 78523 # number of hwrei instructions executed +system.cpu1.kern.ipl_count::0 26526 38.34% 38.34% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1967 2.84% 41.19% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::30 503 0.73% 41.91% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::31 40183 58.09% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 69179 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 25685 48.16% 48.16% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1967 3.69% 51.84% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::30 503 0.94% 52.79% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::31 25182 47.21% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 53337 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1909492808500 97.29% 97.29% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 698045000 0.04% 97.33% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 344048000 0.02% 97.35% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 52077063000 2.65% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1962611964500 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.968295 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.624319 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::total 0.769346 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.syscall::3 10 10.87% 10.87% # number of syscalls executed -system.cpu1.kern.syscall::6 9 9.78% 20.65% # number of syscalls executed -system.cpu1.kern.syscall::15 1 1.09% 21.74% # number of syscalls executed -system.cpu1.kern.syscall::17 5 5.43% 27.17% # number of syscalls executed -system.cpu1.kern.syscall::23 3 3.26% 30.43% # number of syscalls executed -system.cpu1.kern.syscall::24 3 3.26% 33.70% # number of syscalls executed -system.cpu1.kern.syscall::33 3 3.26% 36.96% # number of syscalls executed -system.cpu1.kern.syscall::45 15 16.30% 53.26% # number of syscalls executed -system.cpu1.kern.syscall::47 3 3.26% 56.52% # number of syscalls executed -system.cpu1.kern.syscall::59 1 1.09% 57.61% # number of syscalls executed -system.cpu1.kern.syscall::71 27 29.35% 86.96% # number of syscalls executed -system.cpu1.kern.syscall::74 9 9.78% 96.74% # number of syscalls executed -system.cpu1.kern.syscall::132 3 3.26% 100.00% # number of syscalls executed -system.cpu1.kern.syscall::total 92 # number of syscalls executed +system.cpu1.kern.ipl_used::31 0.626683 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used::total 0.771000 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.syscall::3 11 10.58% 10.58% # number of syscalls executed +system.cpu1.kern.syscall::6 10 9.62% 20.19% # number of syscalls executed +system.cpu1.kern.syscall::15 1 0.96% 21.15% # number of syscalls executed +system.cpu1.kern.syscall::17 6 5.77% 26.92% # number of syscalls executed +system.cpu1.kern.syscall::23 3 2.88% 29.81% # number of syscalls executed +system.cpu1.kern.syscall::24 3 2.88% 32.69% # number of syscalls executed +system.cpu1.kern.syscall::33 4 3.85% 36.54% # number of syscalls executed +system.cpu1.kern.syscall::45 18 17.31% 53.85% # number of syscalls executed +system.cpu1.kern.syscall::47 3 2.88% 56.73% # number of syscalls executed +system.cpu1.kern.syscall::59 1 0.96% 57.69% # number of syscalls executed +system.cpu1.kern.syscall::71 31 29.81% 87.50% # number of syscalls executed +system.cpu1.kern.syscall::74 10 9.62% 97.12% # number of syscalls executed +system.cpu1.kern.syscall::132 3 2.88% 100.00% # number of syscalls executed +system.cpu1.kern.syscall::total 104 # number of syscalls executed system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 424 0.59% 0.59% # number of callpals executed -system.cpu1.kern.callpal::wrmces 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::wrfen 1 0.00% 0.60% # number of callpals executed -system.cpu1.kern.callpal::swpctx 1967 2.75% 3.35% # number of callpals executed -system.cpu1.kern.callpal::tbi 3 0.00% 3.35% # number of callpals executed -system.cpu1.kern.callpal::wrent 7 0.01% 3.36% # number of callpals executed -system.cpu1.kern.callpal::swpipl 62985 88.13% 91.49% # number of callpals executed -system.cpu1.kern.callpal::rdps 2216 3.10% 94.59% # number of callpals executed -system.cpu1.kern.callpal::wrkgp 1 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::wrusp 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::whami 3 0.00% 94.60% # number of callpals executed -system.cpu1.kern.callpal::rti 3692 5.17% 99.77% # number of callpals executed -system.cpu1.kern.callpal::callsys 121 0.17% 99.94% # number of callpals executed -system.cpu1.kern.callpal::imb 42 0.06% 100.00% # number of callpals executed +system.cpu1.kern.callpal::wripir 421 0.59% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrmces 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::wrfen 1 0.00% 0.59% # number of callpals executed +system.cpu1.kern.callpal::swpctx 1997 2.79% 3.39% # number of callpals executed +system.cpu1.kern.callpal::tbi 3 0.00% 3.39% # number of callpals executed +system.cpu1.kern.callpal::wrent 7 0.01% 3.40% # number of callpals executed +system.cpu1.kern.callpal::swpipl 62934 88.05% 91.45% # number of callpals executed +system.cpu1.kern.callpal::rdps 2145 3.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrkgp 1 0.00% 94.46% # number of callpals executed +system.cpu1.kern.callpal::wrusp 4 0.01% 94.46% # number of callpals executed +system.cpu1.kern.callpal::whami 3 0.00% 94.47% # number of callpals executed +system.cpu1.kern.callpal::rti 3774 5.28% 99.75% # number of callpals executed +system.cpu1.kern.callpal::callsys 136 0.19% 99.94% # number of callpals executed +system.cpu1.kern.callpal::imb 44 0.06% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 71468 # number of callpals executed -system.cpu1.kern.mode_switch::kernel 1923 # number of protection mode switches -system.cpu1.kern.mode_switch::user 368 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2902 # number of protection mode switches -system.cpu1.kern.mode_good::kernel 804 -system.cpu1.kern.mode_good::user 368 -system.cpu1.kern.mode_good::idle 436 -system.cpu1.kern.mode_switch_good::kernel 0.418097 # fraction of useful protection mode switches +system.cpu1.kern.callpal::total 71473 # number of callpals executed +system.cpu1.kern.mode_switch::kernel 2064 # number of protection mode switches +system.cpu1.kern.mode_switch::user 463 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2877 # number of protection mode switches +system.cpu1.kern.mode_good::kernel 890 +system.cpu1.kern.mode_good::user 463 +system.cpu1.kern.mode_good::idle 427 +system.cpu1.kern.mode_switch_good::kernel 0.431202 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.150241 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 0.309648 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 17982324500 0.92% 0.92% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1495094500 0.08% 0.99% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1941563117500 99.01% 100.00% # number of ticks spent at the given mode -system.cpu1.kern.swap_context 1968 # number of times the context was actually changed -system.cpu1.dcache.tags.replacements 157282 # number of replacements -system.cpu1.dcache.tags.tagsinuse 486.069018 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 3911225 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157609 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 24.816000 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 1048852201500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 486.069018 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.949354 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.949354 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 327 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 295 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.638672 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 16556980 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 16556980 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 2220683 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 2220683 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 1590246 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1590246 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 47776 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 47776 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50237 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 50237 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 3810929 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 3810929 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 3810929 # number of overall hits -system.cpu1.dcache.overall_hits::total 3810929 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 115097 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 115097 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 57138 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 57138 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8903 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 8903 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5967 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 5967 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 172235 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 172235 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 172235 # number of overall misses -system.cpu1.dcache.overall_misses::total 172235 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1388298999 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1388298999 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1079375302 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1079375302 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 80583500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 80583500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 43835417 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 43835417 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 2467674301 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 2467674301 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 2467674301 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 2467674301 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 2335780 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2335780 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 1647384 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1647384 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 56679 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 56679 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 56204 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 3983164 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3983164 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 3983164 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3983164 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049276 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.049276 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034684 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.034684 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.157078 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.157078 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106167 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106167 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.043241 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.043241 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043241 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043241 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12061.991181 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12061.991181 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18890.673492 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18890.673492 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9051.274851 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9051.274851 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 7346.307525 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7346.307525 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14327.368427 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14327.368427 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14327.368427 # average overall miss latency +system.cpu1.kern.mode_switch_good::idle 0.148418 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 0.329386 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 17700699500 0.90% 0.90% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1706728000 0.09% 0.99% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1943204535000 99.01% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.swap_context 1998 # number of times the context was actually changed +system.cpu1.dcache.tags.replacements 166165 # number of replacements +system.cpu1.dcache.tags.tagsinuse 485.164459 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 4008469 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 166677 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 24.049323 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 79256927000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 485.164459 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.947587 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.947587 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 65 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 16941101 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 16941101 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 2255044 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 2255044 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1640007 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1640007 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 48683 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 48683 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 50718 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 50718 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 3895051 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 3895051 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 3895051 # number of overall hits +system.cpu1.dcache.overall_hits::total 3895051 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 118164 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 118164 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 62534 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 62534 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 8914 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 8914 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 5850 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 5850 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 180698 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 180698 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 180698 # number of overall misses +system.cpu1.dcache.overall_misses::total 180698 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1427964750 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1427964750 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1264688999 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1264688999 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 81194500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 81194500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 50099897 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 50099897 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2692653749 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2692653749 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2692653749 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2692653749 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 2373208 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2373208 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1702541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1702541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 57597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 57597 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 56568 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 56568 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 4075749 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 4075749 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 4075749 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 4075749 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.049791 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.049791 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.036730 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.036730 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.154765 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.154765 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103415 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103415 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044335 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.044335 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044335 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044335 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12084.600640 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12084.600640 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20224.022116 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20224.022116 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9108.649316 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9108.649316 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8564.084957 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8564.084957 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14901.403164 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14901.403164 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 14901.403164 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -994,62 +997,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 107942 # number of writebacks -system.cpu1.dcache.writebacks::total 107942 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 115097 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 57138 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 57138 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8903 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8903 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5967 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 5967 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 172235 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 172235 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 172235 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 172235 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1158014001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1158014001 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 962534698 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 962534698 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 62777500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 62777500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31899583 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31899583 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2120548699 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2120548699 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2120548699 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2120548699 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 22446500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 22446500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 726754500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 726754500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 749201000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 749201000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049276 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049276 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034684 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034684 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.157078 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.157078 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106167 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106167 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.043241 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.043241 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.043241 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10061.200561 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10061.200561 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16845.789107 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16845.789107 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7051.274851 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7051.274851 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5346.000168 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5346.000168 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12311.949946 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12311.949946 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 114146 # number of writebacks +system.cpu1.dcache.writebacks::total 114146 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 118164 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 118164 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 62534 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 62534 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 8914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 8914 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 5850 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 5850 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 180698 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1167915001 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 67823500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 67823500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 41323103 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 41323103 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2418558251 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2418558251 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2418558251 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2418558251 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 18864000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 18864000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 716373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 716373000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 735237000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 735237000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.049791 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.049791 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.036730 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.154765 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.154765 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103415 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103415 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.044335 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.044335 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.044335 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10583.961697 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10583.961697 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18676.480011 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18676.480011 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7608.649316 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7608.649316 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 7063.778291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 7063.778291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1057,58 +1060,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 318148 # number of replacements -system.cpu1.icache.tags.tagsinuse 446.541580 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 12622723 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 318660 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.611884 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 1956986313500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 446.541580 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.872152 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.872152 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 315648 # number of replacements +system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 12842415 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 316160 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.619987 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 1961765828000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 445.931523 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.870960 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.870960 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 72 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 439 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 444 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 13260123 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 13260123 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 12622723 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 12622723 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 12622723 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 12622723 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 12622723 # number of overall hits -system.cpu1.icache.overall_hits::total 12622723 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 318700 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 318700 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 318700 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 318700 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 318700 # number of overall misses -system.cpu1.icache.overall_misses::total 318700 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4202225742 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4202225742 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4202225742 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4202225742 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4202225742 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4202225742 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 12941423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 12941423 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 12941423 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 12941423 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 12941423 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 12941423 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024626 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.024626 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024626 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.024626 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024626 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.024626 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13185.521625 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13185.521625 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13185.521625 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13185.521625 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13185.521625 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 13474819 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 13474819 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 12842415 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 12842415 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 12842415 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 12842415 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 12842415 # number of overall hits +system.cpu1.icache.overall_hits::total 12842415 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 316202 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 316202 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 316202 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 316202 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 316202 # number of overall misses +system.cpu1.icache.overall_misses::total 316202 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4145253739 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4145253739 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4145253739 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4145253739 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4145253739 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4145253739 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 13158617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 13158617 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 13158617 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 13158617 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 13158617 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 13158617 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.024030 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.024030 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.024030 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.024030 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024030 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024030 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13109.511448 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13109.511448 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13109.511448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13109.511448 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13109.511448 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1117,30 +1121,30 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 318700 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 318700 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 318700 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 318700 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 318700 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 318700 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3564575258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3564575258 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3564575258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3564575258 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3564575258 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3564575258 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024626 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024626 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024626 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024626 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11184.735670 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11184.735670 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11184.735670 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 316202 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 316202 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 316202 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 316202 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 316202 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 316202 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3670775261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3670775261 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3670775261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3670775261 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3670775261 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3670775261 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024030 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024030 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024030 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024030 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11608.956493 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11608.956493 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11608.956493 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -1156,11 +1160,11 @@ system.disk2.dma_write_bytes 8192 # Nu system.disk2.dma_write_txs 1 # Number of DMA write transactions. system.iobus.trans_dist::ReadReq 7373 # Transaction distribution system.iobus.trans_dist::ReadResp 7373 # Transaction distribution -system.iobus.trans_dist::WriteReq 55631 # Transaction distribution -system.iobus.trans_dist::WriteResp 14079 # Transaction distribution +system.iobus.trans_dist::WriteReq 55604 # Transaction distribution +system.iobus.trans_dist::WriteResp 14052 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13950 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 13892 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 480 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 180 # Packet count per connected master and slave (bytes) @@ -1171,12 +1175,12 @@ system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 42552 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.tsunami.ide.dma::total 83456 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 126008 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55800 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 42502 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 125954 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 55568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1920 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 160 # Cumulative packet size per connected master and slave (bytes) @@ -1187,13 +1191,13 @@ system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 82034 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.tsunami.ide.dma::total 2661632 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2743666 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 13305000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 81834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2743450 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 13247000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 353000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 359000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1213,52 +1217,52 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406213784 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242106937 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 28473000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 28450000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42016500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42027500 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 41696 # number of replacements -system.iocache.tags.tagsinuse 0.577776 # Cycle average of tags in use +system.iocache.tags.replacements 41694 # number of replacements +system.iocache.tags.tagsinuse 0.567924 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 41712 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 41710 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1755504098000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 0.577776 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.036111 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.036111 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756483552000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 0.567924 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.035495 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.035495 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 375552 # Number of tag accesses -system.iocache.tags.data_accesses 375552 # Number of data accesses -system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses -system.iocache.ReadReq_misses::total 176 # number of ReadReq misses +system.iocache.tags.tag_accesses 375534 # Number of tag accesses +system.iocache.tags.data_accesses 375534 # Number of data accesses +system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses +system.iocache.ReadReq_misses::total 174 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses -system.iocache.demand_misses::tsunami.ide 176 # number of demand (read+write) misses -system.iocache.demand_misses::total 176 # number of demand (read+write) misses -system.iocache.overall_misses::tsunami.ide 176 # number of overall misses -system.iocache.overall_misses::total 176 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 21474383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 21474383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13634467901 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13634467901 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 21474383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 21474383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 21474383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 21474383 # number of overall miss cycles -system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses +system.iocache.demand_misses::total 174 # number of demand (read+write) misses +system.iocache.overall_misses::tsunami.ide 174 # number of overall misses +system.iocache.overall_misses::total 174 # number of overall misses +system.iocache.ReadReq_miss_latency::tsunami.ide 21822883 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21822883 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8775454554 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8775454554 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21822883 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21822883 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21822883 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21822883 # number of overall miss cycles +system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::tsunami.ide 176 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 176 # number of demand (read+write) accesses -system.iocache.overall_accesses::tsunami.ide 176 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 176 # number of overall (read+write) accesses +system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses +system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1267,40 +1271,40 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 122013.539773 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 122013.539773 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328130.244056 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328130.244056 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 122013.539773 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 122013.539773 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206274 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125418.867816 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125418.867816 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 211192.109983 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 211192.109983 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125418.867816 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125418.867816 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125418.867816 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72753 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23554 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9972 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.757493 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.295728 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 41520 # number of writebacks system.iocache.writebacks::total 41520 # number of writebacks -system.iocache.ReadReq_mshr_misses::tsunami.ide 176 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 176 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::tsunami.ide 174 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 174 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::tsunami.ide 41552 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 41552 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::tsunami.ide 176 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::tsunami.ide 176 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12321383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 12321383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11473763901 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11473763901 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 12321383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 12321383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 12321383 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::tsunami.ide 174 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::tsunami.ide 174 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12615883 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12615883 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6614750554 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6614750554 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12615883 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12615883 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12615883 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12615883 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1309,189 +1313,189 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70007.857955 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276130.244056 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276130.244056 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 70007.857955 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70007.857955 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72505.074713 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 159192.109983 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159192.109983 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72505.074713 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72505.074713 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 342765 # number of replacements -system.l2c.tags.tagsinuse 65220.427494 # Cycle average of tags in use -system.l2c.tags.total_refs 2449404 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 407938 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 6.004354 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8652068750 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 55273.007246 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4809.132503 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4932.058830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 161.965185 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 44.263730 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.843399 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.073382 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.075257 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.002471 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000675 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995185 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 65173 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 767 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 5220 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 7222 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 51853 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.994461 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25999302 # Number of tag accesses -system.l2c.tags.data_accesses 25999302 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 687538 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 668153 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 318040 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 105234 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1778965 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 793856 # number of Writeback hits -system.l2c.Writeback_hits::total 793856 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 179 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 542 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 721 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 43 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 23 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 66 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 129887 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 42518 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 172405 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 687538 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 798040 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 318040 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 147752 # number of demand (read+write) hits -system.l2c.demand_hits::total 1951370 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 687538 # number of overall hits -system.l2c.overall_hits::cpu0.data 798040 # number of overall hits -system.l2c.overall_hits::cpu1.inst 318040 # number of overall hits -system.l2c.overall_hits::cpu1.data 147752 # number of overall hits -system.l2c.overall_hits::total 1951370 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 12866 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 271551 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 659 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 293 # number of ReadReq misses -system.l2c.ReadReq_misses::total 285369 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 2958 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 1782 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4740 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 895 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 917 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1812 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 117982 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 5781 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 123763 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 12866 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 389533 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 659 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 6074 # number of demand (read+write) misses -system.l2c.demand_misses::total 409132 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 12866 # number of overall misses -system.l2c.overall_misses::cpu0.data 389533 # number of overall misses -system.l2c.overall_misses::cpu1.inst 659 # number of overall misses -system.l2c.overall_misses::cpu1.data 6074 # number of overall misses -system.l2c.overall_misses::total 409132 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 942533250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 17665276500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 47722250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 21179000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18676711000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 1101962 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 10166561 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 11268523 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 873463 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 278988 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1152451 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 8137748269 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 426449979 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 8564198248 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 942533250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 25803024769 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 47722250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 447628979 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 27240909248 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 942533250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 25803024769 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 47722250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 447628979 # number of overall miss cycles -system.l2c.overall_miss_latency::total 27240909248 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 700404 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 939704 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 318699 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 105527 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2064334 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 793856 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 793856 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 3137 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 2324 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 5461 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 938 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 940 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1878 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 247869 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 48299 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 296168 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 700404 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1187573 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 318699 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 153826 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2360502 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 700404 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1187573 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 318699 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 153826 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2360502 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.018369 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.288975 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.002068 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.002777 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.138238 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.942939 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.766781 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.867973 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.954158 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.975532 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.964856 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.475985 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.119692 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.417881 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.018369 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.328008 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.002068 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.039486 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173324 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.018369 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.328008 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.002068 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.039486 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173324 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73257.675268 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 65053.255190 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72416.160850 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 72283.276451 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 65447.581903 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 372.536173 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5705.140853 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2377.325527 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 975.936313 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 304.239913 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 636.010486 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 68974.489914 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73767.510638 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 69198.373084 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 73257.675268 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 66240.921229 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 72416.160850 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 73695.913566 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 66582.201461 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 73257.675268 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 66240.921229 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 72416.160850 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 73695.913566 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 66582.201461 # average overall miss latency +system.l2c.tags.replacements 341367 # number of replacements +system.l2c.tags.tagsinuse 65207.739778 # Cycle average of tags in use +system.l2c.tags.total_refs 2440642 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 406370 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 6.005960 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9165125750 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 55183.814884 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4854.166492 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 5017.337774 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 113.675354 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 38.745274 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.842038 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.074069 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.076558 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.001735 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000591 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994991 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 65003 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 185 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1104 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 5014 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6093 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 52607 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.991867 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 25960355 # Number of tag accesses +system.l2c.tags.data_accesses 25960355 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 686297 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 664438 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 315744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 108706 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1775185 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 793248 # number of Writeback hits +system.l2c.Writeback_hits::total 793248 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 183 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 524 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 707 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 36 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 60 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 126541 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 47234 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 173775 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 686297 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 790979 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 315744 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 155940 # number of demand (read+write) hits +system.l2c.demand_hits::total 1948960 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 686297 # number of overall hits +system.l2c.overall_hits::cpu0.data 790979 # number of overall hits +system.l2c.overall_hits::cpu1.inst 315744 # number of overall hits +system.l2c.overall_hits::cpu1.data 155940 # number of overall hits +system.l2c.overall_hits::total 1948960 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13070 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 271636 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 457 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 234 # number of ReadReq misses +system.l2c.ReadReq_misses::total 285397 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2949 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 1736 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4685 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 892 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 897 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1789 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 115627 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6589 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 122216 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13070 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 387263 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 457 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 6823 # number of demand (read+write) misses +system.l2c.demand_misses::total 407613 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13070 # number of overall misses +system.l2c.overall_misses::cpu0.data 387263 # number of overall misses +system.l2c.overall_misses::cpu1.inst 457 # number of overall misses +system.l2c.overall_misses::cpu1.data 6823 # number of overall misses +system.l2c.overall_misses::total 407613 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 1052716500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 19700886500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 37366250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 18492250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 20809461500 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 1635455 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 13268077 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 14903532 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1334957 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 185994 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 1520951 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8793297261 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 540094736 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9333391997 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1052716500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 28494183761 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 37366250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 558586986 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30142853497 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1052716500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 28494183761 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 37366250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 558586986 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30142853497 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 699367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 936074 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 316201 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 108940 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2060582 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 793248 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 793248 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 3132 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 2260 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 5392 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 928 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 921 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1849 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 242168 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 53823 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 295991 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 699367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1178242 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 316201 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 162763 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2356573 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 699367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1178242 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 316201 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 162763 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2356573 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.018688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.290186 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.001445 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.002148 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.138503 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.941571 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.768142 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.868880 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.961207 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.973941 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.967550 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.477466 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.122420 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.412904 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.018688 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.328679 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.001445 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.041920 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.172969 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.018688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.328679 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.001445 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.041920 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.172969 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80544.491201 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 72526.787686 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81764.223195 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 79026.709402 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 72914.086343 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 554.579518 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7642.901498 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 3181.116756 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1496.588565 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 207.351171 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 850.168250 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 76048.823034 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81969.151009 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 76368.004165 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 73949.686337 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80544.491201 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 73578.378934 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 81764.223195 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81868.237725 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 73949.686337 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1500,8 +1504,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 79715 # number of writebacks -system.l2c.writebacks::total 79715 # number of writebacks +system.l2c.writebacks::writebacks 78830 # number of writebacks +system.l2c.writebacks::total 78830 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 3 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits @@ -1511,111 +1515,111 @@ system.l2c.demand_mshr_hits::total 11 # nu system.l2c.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 12863 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 271551 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 651 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 293 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 285358 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 2958 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 1782 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 4740 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 895 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 917 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1812 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 117982 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 5781 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 123763 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 12863 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 389533 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 651 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 6074 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 409121 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 12863 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 389533 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 651 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 6074 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 409121 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 778711500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 14270230000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 38887000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 17526500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 15105355000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 29737455 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 17835282 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 47572737 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8983895 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 9183917 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 18167812 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6655812231 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 353576521 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 7009388752 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 778711500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 20926042231 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 38887000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 371103021 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22114743752 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 778711500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 20926042231 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 38887000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 371103021 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22114743752 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1369397500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 20977500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 1390375000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2137899500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 687012000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 2824911500 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3507297000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 707989500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4215286500 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.288975 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002777 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.138232 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.942939 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.766781 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.867973 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.954158 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.975532 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.964856 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.475985 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.119692 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.417881 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173319 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018365 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.328008 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.002043 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.039486 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173319 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 52550.828390 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 59817.406143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 52934.752136 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10053.230223 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10008.575758 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10036.442405 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10037.871508 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10015.176663 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10026.386313 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56413.793892 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61161.826847 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 56635.575673 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60538.871181 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 53720.845810 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59734.254992 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61096.974152 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 54054.286512 # average overall mshr miss latency +system.l2c.ReadReq_mshr_misses::cpu0.inst 13067 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 271636 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 449 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 234 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 285386 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 2949 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 1736 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 4685 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 892 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 897 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1789 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 115627 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6589 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 122216 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 13067 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 387263 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 449 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 6823 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 407602 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 13067 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 387263 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 449 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 6823 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 407602 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 15561750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17240533500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51864446 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 30663235 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 82527681 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15769892 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15706897 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 31476789 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 7347142739 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457723764 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7804866503 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 888765750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 23652210239 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 31138500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 473285514 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 25045400003 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 888765750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 23652210239 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 31138500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 473285514 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 25045400003 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1374876000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 17618000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 1392494000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2153053500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 674538500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2827592000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3527929500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 692156500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4220086000 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.290186 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002148 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.138498 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.941571 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.768142 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.868880 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.961207 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.973941 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.967550 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.477466 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.122420 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.412904 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.172964 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.018684 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.328679 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.001420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.041920 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.172964 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 60025.429251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66503.205128 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 60411.279811 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17587.129875 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17663.153802 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17615.300107 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17679.251121 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17510.476031 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17594.627725 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 63541.757020 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69467.865230 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63861.249779 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68016.051886 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 61075.316359 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61445.724022 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1626,96 +1630,96 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292731 # Transaction distribution -system.membus.trans_dist::ReadResp 292731 # Transaction distribution -system.membus.trans_dist::WriteReq 14079 # Transaction distribution -system.membus.trans_dist::WriteResp 14079 # Transaction distribution -system.membus.trans_dist::Writeback 121235 # Transaction distribution +system.membus.trans_dist::ReadReq 292759 # Transaction distribution +system.membus.trans_dist::ReadResp 292759 # Transaction distribution +system.membus.trans_dist::WriteReq 14052 # Transaction distribution +system.membus.trans_dist::WriteResp 14052 # Transaction distribution +system.membus.trans_dist::Writeback 120350 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution -system.membus.trans_dist::UpgradeReq 16420 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11480 # Transaction distribution -system.membus.trans_dist::UpgradeResp 7054 # Transaction distribution -system.membus.trans_dist::ReadExReq 124107 # Transaction distribution -system.membus.trans_dist::ReadExResp 123261 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 932487 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 975039 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 124815 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1099854 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 82034 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31236544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 31318578 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 16060 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 11220 # Transaction distribution +system.membus.trans_dist::UpgradeResp 6977 # Transaction distribution +system.membus.trans_dist::ReadExReq 122543 # Transaction distribution +system.membus.trans_dist::ReadExResp 121713 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 42502 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 927849 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 970351 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 124813 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1095164 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 81834 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 31082624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 31164458 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317568 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36636146 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 22119 # Total snoops (count) -system.membus.snoop_fanout::samples 600328 # Request fanout histogram +system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 21558 # Total snoops (count) +system.membus.snoop_fanout::samples 597341 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 600328 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 600328 # Request fanout histogram -system.membus.reqLayer0.occupancy 40794500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 597341 # Request fanout histogram +system.membus.reqLayer0.occupancy 40208500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1915022000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3840524699 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43136500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2189522527 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42501500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2106481 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2106466 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 14079 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 14079 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 793856 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 16639 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 11546 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28185 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 298132 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 298132 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1400829 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3132611 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 637399 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 458996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5629835 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44825856 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 119969536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20396736 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 16779122 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 201971250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 99473 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3261009 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 3.012796 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.112394 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 2102341 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2102326 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 14052 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 14052 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 793248 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 41590 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 16264 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 11280 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 27544 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 297931 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 297931 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1398755 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 3106837 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 632403 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 482171 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5620166 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 44759488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 118936680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 20236864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 98552 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 3219281 98.72% 98.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 41728 1.28% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3261009 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 4802800383 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 724500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 3154409746 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 5532665081 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1434275242 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 787817718 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1051604997 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 1901998576 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 474390739 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 282399146 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 5c3a9c7d0..d63246d54 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,107 +1,107 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920419 # Number of seconds simulated -sim_ticks 1920418772000 # Number of ticks simulated -final_tick 1920418772000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.922414 # Number of seconds simulated +sim_ticks 1922413663500 # Number of ticks simulated +final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1235696 # Simulator instruction rate (inst/s) -host_op_rate 1235696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42298287542 # Simulator tick rate (ticks/s) -host_mem_usage 370580 # Number of bytes of host memory used -host_seconds 45.40 # Real time elapsed on the host -sim_insts 56102800 # Number of instructions simulated -sim_ops 56102800 # Number of ops (including micro ops) simulated +host_inst_rate 1122927 # Simulator instruction rate (inst/s) +host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38428929684 # Simulator tick rate (ticks/s) +host_mem_usage 370248 # Number of bytes of host memory used +host_seconds 50.03 # Real time elapsed on the host +sim_insts 56174594 # Number of instructions simulated +sim_ops 56174594 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 850560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 24857984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 850624 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 24859584 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 25709504 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 850560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7403648 # Number of bytes written to this memory -system.physmem.bytes_written::total 7403648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 13290 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 388406 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25711168 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 850624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7404352 # Number of bytes written to this memory +system.physmem.bytes_written::total 7404352 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 13291 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 388431 # Number of read requests responded to by this memory system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401711 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 115682 # Number of write requests responded to by this memory -system.physmem.num_writes::total 115682 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 442903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12944043 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 13387447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 442903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 442903 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3855226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3855226 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3855226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 442903 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12944043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 17242673 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 401711 # Number of read requests accepted -system.physmem.writeReqs 157234 # Number of write requests accepted -system.physmem.readBursts 401711 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 157234 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25703040 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6464 # Total number of bytes read from write queue -system.physmem.bytesWritten 9922432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25709504 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10062976 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2169 # Number of DRAM write bursts merged with an existing one +system.physmem.num_reads::total 401737 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 115693 # Number of write requests responded to by this memory +system.physmem.num_writes::total 115693 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 442477 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12931444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 499 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 13374420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 442477 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 442477 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3851591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3851591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3851591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 442477 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12931444 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 17226012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401737 # Number of read requests accepted +system.physmem.writeReqs 157245 # Number of write requests accepted +system.physmem.readBursts 401737 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 157245 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 25705152 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6016 # Total number of bytes read from write queue +system.physmem.bytesWritten 8387264 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 25711168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10063680 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 94 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26167 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 130 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 25160 # Per bank write bursts -system.physmem.perBankRdBursts::1 25539 # Per bank write bursts -system.physmem.perBankRdBursts::2 25602 # Per bank write bursts +system.physmem.perBankRdBursts::0 25230 # Per bank write bursts +system.physmem.perBankRdBursts::1 25660 # Per bank write bursts +system.physmem.perBankRdBursts::2 25603 # Per bank write bursts system.physmem.perBankRdBursts::3 25523 # Per bank write bursts -system.physmem.perBankRdBursts::4 24974 # Per bank write bursts -system.physmem.perBankRdBursts::5 24969 # Per bank write bursts -system.physmem.perBankRdBursts::6 24210 # Per bank write bursts -system.physmem.perBankRdBursts::7 24487 # Per bank write bursts -system.physmem.perBankRdBursts::8 25140 # Per bank write bursts -system.physmem.perBankRdBursts::9 24800 # Per bank write bursts -system.physmem.perBankRdBursts::10 25360 # Per bank write bursts -system.physmem.perBankRdBursts::11 24834 # Per bank write bursts -system.physmem.perBankRdBursts::12 24395 # Per bank write bursts -system.physmem.perBankRdBursts::13 25368 # Per bank write bursts -system.physmem.perBankRdBursts::14 25772 # Per bank write bursts -system.physmem.perBankRdBursts::15 25477 # Per bank write bursts -system.physmem.perBankWrBursts::0 10048 # Per bank write bursts -system.physmem.perBankWrBursts::1 9910 # Per bank write bursts -system.physmem.perBankWrBursts::2 10442 # Per bank write bursts -system.physmem.perBankWrBursts::3 9959 # Per bank write bursts -system.physmem.perBankWrBursts::4 9552 # Per bank write bursts -system.physmem.perBankWrBursts::5 9342 # Per bank write bursts -system.physmem.perBankWrBursts::6 8789 # Per bank write bursts -system.physmem.perBankWrBursts::7 8561 # Per bank write bursts -system.physmem.perBankWrBursts::8 9905 # Per bank write bursts -system.physmem.perBankWrBursts::9 8742 # Per bank write bursts -system.physmem.perBankWrBursts::10 9526 # Per bank write bursts -system.physmem.perBankWrBursts::11 9262 # Per bank write bursts -system.physmem.perBankWrBursts::12 9811 # Per bank write bursts -system.physmem.perBankWrBursts::13 10568 # Per bank write bursts -system.physmem.perBankWrBursts::14 10305 # Per bank write bursts -system.physmem.perBankWrBursts::15 10316 # Per bank write bursts +system.physmem.perBankRdBursts::4 24970 # Per bank write bursts +system.physmem.perBankRdBursts::5 24976 # Per bank write bursts +system.physmem.perBankRdBursts::6 24206 # Per bank write bursts +system.physmem.perBankRdBursts::7 24492 # Per bank write bursts +system.physmem.perBankRdBursts::8 25173 # Per bank write bursts +system.physmem.perBankRdBursts::9 24777 # Per bank write bursts +system.physmem.perBankRdBursts::10 25267 # Per bank write bursts +system.physmem.perBankRdBursts::11 24875 # Per bank write bursts +system.physmem.perBankRdBursts::12 24505 # Per bank write bursts +system.physmem.perBankRdBursts::13 25378 # Per bank write bursts +system.physmem.perBankRdBursts::14 25651 # Per bank write bursts +system.physmem.perBankRdBursts::15 25357 # Per bank write bursts +system.physmem.perBankWrBursts::0 8677 # Per bank write bursts +system.physmem.perBankWrBursts::1 8490 # Per bank write bursts +system.physmem.perBankWrBursts::2 8972 # Per bank write bursts +system.physmem.perBankWrBursts::3 8549 # Per bank write bursts +system.physmem.perBankWrBursts::4 8030 # Per bank write bursts +system.physmem.perBankWrBursts::5 7962 # Per bank write bursts +system.physmem.perBankWrBursts::6 7256 # Per bank write bursts +system.physmem.perBankWrBursts::7 7133 # Per bank write bursts +system.physmem.perBankWrBursts::8 8241 # Per bank write bursts +system.physmem.perBankWrBursts::9 7447 # Per bank write bursts +system.physmem.perBankWrBursts::10 7887 # Per bank write bursts +system.physmem.perBankWrBursts::11 7738 # Per bank write bursts +system.physmem.perBankWrBursts::12 8187 # Per bank write bursts +system.physmem.perBankWrBursts::13 8962 # Per bank write bursts +system.physmem.perBankWrBursts::14 8876 # Per bank write bursts +system.physmem.perBankWrBursts::15 8644 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1920406851000 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 1922401791500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 401711 # Read request sizes (log2) +system.physmem.readPktSize::6 401737 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 157234 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 401596 # What read queue length does an incoming req see +system.physmem.writePktSize::6 157245 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 401629 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see @@ -148,184 +148,189 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7978 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10585 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11559 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11623 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9597 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7669 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 6479 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 5940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 5895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 365 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 254 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 231 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 173 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 536.116417 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 326.833533 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 417.088244 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15015 22.60% 22.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 11499 17.30% 39.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 4712 7.09% 46.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3144 4.73% 51.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3072 4.62% 56.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1860 2.80% 59.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1297 1.95% 61.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1463 2.20% 63.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 24389 36.70% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66451 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 5539 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 72.502618 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 2835.834060 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-8191 5536 99.95% 99.95% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2050 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5499 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5313 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5522 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 5548 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 6794 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 5788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7612 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6420 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 5573 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 786 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 1489 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 1383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 874 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1604 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1549 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1892 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 2468 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 2834 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 1812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 712 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 482 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 210 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 50 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 64754 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 526.491275 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 319.634857 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 416.364161 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 14682 22.67% 22.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 11626 17.95% 40.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5040 7.78% 48.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3263 5.04% 53.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2595 4.01% 57.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1540 2.38% 59.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1251 1.93% 61.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1707 2.64% 64.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 23050 35.60% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 64754 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 4707 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 85.326110 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 3076.141166 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-8191 4704 99.94% 99.94% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-49151 1 0.02% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::57344-65535 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 5539 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 5539 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 27.990251 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.086567 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 34.704660 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-23 4497 81.19% 81.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-31 178 3.21% 84.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-39 301 5.43% 89.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-47 51 0.92% 90.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-55 99 1.79% 92.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-63 47 0.85% 93.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-71 17 0.31% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-79 11 0.20% 93.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-87 12 0.22% 94.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-95 4 0.07% 94.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-103 17 0.31% 94.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-111 7 0.13% 94.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-119 14 0.25% 94.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-127 6 0.11% 94.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-135 9 0.16% 95.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-143 38 0.69% 95.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-151 16 0.29% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-159 19 0.34% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-167 88 1.59% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-175 43 0.78% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-183 11 0.20% 99.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-191 20 0.36% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-199 10 0.18% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-207 3 0.05% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-215 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-223 4 0.07% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-231 4 0.07% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-239 5 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-247 3 0.05% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-255 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-263 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 5539 # Writes before turning the bus around for reads -system.physmem.totQLat 2115529750 # Total ticks spent queuing -system.physmem.totMemAccLat 9645717250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2008050000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5267.62 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 4707 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 4707 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.841725 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.684188 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 62.214453 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4459 94.73% 94.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 47 1.00% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 10 0.21% 95.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 2 0.04% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 12 0.25% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 3 0.06% 96.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 7 0.15% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.36% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 21 0.45% 97.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 12 0.25% 97.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 17 0.36% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 2 0.04% 97.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 5 0.11% 98.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.06% 98.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 1 0.02% 98.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 2 0.04% 98.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.08% 98.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 11 0.23% 98.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 21 0.45% 98.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 6 0.13% 99.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 6 0.13% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 6 0.13% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 8 0.17% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 2 0.04% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.11% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 3 0.06% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 3 0.06% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.04% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::800-815 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::832-847 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 4707 # Writes before turning the bus around for reads +system.physmem.totQLat 2057087750 # Total ticks spent queuing +system.physmem.totMemAccLat 9587894000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2008215000 # Total ticks spent in databus transfers +system.physmem.avgQLat 5121.68 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24017.62 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 13.38 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 5.17 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 13.39 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 5.24 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 23871.68 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 13.37 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 4.36 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 13.37 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 5.23 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.14 # Data bus utilization in percentage system.physmem.busUtilRead 0.10 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.04 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.84 # Average write queue length when enqueuing -system.physmem.readRowHits 359951 # Number of row buffer hits during reads -system.physmem.writeRowHits 130246 # Number of row buffer hits during writes -system.physmem.readRowHitRate 89.63 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 83.99 # Row buffer hit rate for writes -system.physmem.avgGap 3435770.69 # Average gap between requests -system.physmem.pageHitRate 88.06 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 245601720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134008875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1563619200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 496387440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 64124070615 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1096000726500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1287996669870 # Total energy per rank (pJ) -system.physmem_0.averagePower 670.686102 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1823056528000 # Time in different power states -system.physmem_0.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem.avgWrQLen 25.61 # Average write queue length when enqueuing +system.physmem.readRowHits 360176 # Number of row buffer hits during reads +system.physmem.writeRowHits 107764 # Number of row buffer hits during writes +system.physmem.readRowHitRate 89.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 82.21 # Row buffer hit rate for writes +system.physmem.avgGap 3439112.16 # Average gap between requests +system.physmem.pageHitRate 87.84 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 240309720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131121375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1565148000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 421647120 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 64744742475 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1096652245500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1289317661070 # Total energy per rank (pJ) +system.physmem_0.averagePower 670.677845 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1824141880650 # Time in different power states +system.physmem_0.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33233084500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34074451850 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 256767840 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 140101500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1568938800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 508258800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 125432255520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 64541926215 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1095634186500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1288082435175 # Total energy per rank (pJ) -system.physmem_1.averagePower 670.730762 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1822448681750 # Time in different power states -system.physmem_1.memoryStateTime::REF 64126920000 # Time in different power states +system.physmem_1.actEnergy 249230520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 135988875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1567667400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 427563360 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 125562446880 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 65411599725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1096067283000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1289421779760 # Total energy per rank (pJ) +system.physmem_1.averagePower 670.732006 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1823167298902 # Time in different power states +system.physmem_1.memoryStateTime::REF 64193480000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33840930750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 35049033598 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 9052701 # DTB read hits -system.cpu.dtb.read_misses 10312 # DTB read misses +system.cpu.dtb.read_hits 9063642 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728817 # DTB read accesses -system.cpu.dtb.write_hits 6349364 # DTB write hits -system.cpu.dtb.write_misses 1140 # DTB write misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses +system.cpu.dtb.write_hits 6355525 # DTB write hits +system.cpu.dtb.write_misses 1142 # DTB write misses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 291929 # DTB write accesses -system.cpu.dtb.data_hits 15402065 # DTB hits -system.cpu.dtb.data_misses 11452 # DTB misses +system.cpu.dtb.write_accesses 291931 # DTB write accesses +system.cpu.dtb.data_hits 15419167 # DTB hits +system.cpu.dtb.data_misses 11466 # DTB misses system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1020746 # DTB accesses -system.cpu.itb.fetch_hits 4973977 # ITB hits -system.cpu.itb.fetch_misses 4997 # ITB misses +system.cpu.dtb.data_accesses 1020784 # DTB accesses +system.cpu.itb.fetch_hits 4974414 # ITB hits +system.cpu.itb.fetch_misses 5010 # ITB misses system.cpu.itb.fetch_acv 184 # ITB acv -system.cpu.itb.fetch_accesses 4978974 # ITB accesses +system.cpu.itb.fetch_accesses 4979424 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -338,87 +343,87 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3840837544 # number of cpu cycles simulated +system.cpu.numCycles 3844827327 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 56102800 # Number of instructions committed -system.cpu.committedOps 56102800 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 51978055 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 324393 # Number of float alu accesses -system.cpu.num_func_calls 1481300 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 6461124 # number of instructions that are conditional controls -system.cpu.num_int_insts 51978055 # number of integer instructions -system.cpu.num_fp_insts 324393 # number of float instructions -system.cpu.num_int_register_reads 71208426 # number of times the integer registers were read -system.cpu.num_int_register_writes 38459690 # number of times the integer registers were written -system.cpu.num_fp_register_reads 163609 # number of times the floating registers were read -system.cpu.num_fp_register_writes 166486 # number of times the floating registers were written -system.cpu.num_mem_refs 15454652 # number of memory refs -system.cpu.num_load_insts 9089529 # Number of load instructions -system.cpu.num_store_insts 6365123 # Number of store instructions -system.cpu.num_idle_cycles 3589204507.998131 # Number of idle cycles -system.cpu.num_busy_cycles 251633036.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065515 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934485 # Percentage of idle cycles -system.cpu.Branches 8412940 # Number of branches fetched -system.cpu.op_class::No_OpClass 3197536 5.70% 5.70% # Class of executed instruction -system.cpu.op_class::IntAlu 36173540 64.46% 70.16% # Class of executed instruction -system.cpu.op_class::IntMult 60992 0.11% 70.27% # Class of executed instruction -system.cpu.op_class::IntDiv 0 0.00% 70.27% # Class of executed instruction -system.cpu.op_class::FloatAdd 38085 0.07% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::FloatDiv 3636 0.01% 70.34% # Class of executed instruction -system.cpu.op_class::FloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAddAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShift 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdShiftAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAdd 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatAlu 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCmp 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatCvt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatDiv 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.34% # Class of executed instruction -system.cpu.op_class::MemRead 9316603 16.60% 86.95% # Class of executed instruction -system.cpu.op_class::MemWrite 6371197 11.35% 98.30% # Class of executed instruction -system.cpu.op_class::IprAccess 953030 1.70% 100.00% # Class of executed instruction +system.cpu.committedInsts 56174594 # Number of instructions committed +system.cpu.committedOps 56174594 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 52047018 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses +system.cpu.num_func_calls 1483106 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 6467546 # number of instructions that are conditional controls +system.cpu.num_int_insts 52047018 # number of integer instructions +system.cpu.num_fp_insts 324460 # number of float instructions +system.cpu.num_int_register_reads 71310653 # number of times the integer registers were read +system.cpu.num_int_register_writes 38515122 # number of times the integer registers were written +system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read +system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written +system.cpu.num_mem_refs 15471782 # number of memory refs +system.cpu.num_load_insts 9100493 # Number of load instructions +system.cpu.num_store_insts 6371289 # Number of store instructions +system.cpu.num_idle_cycles 3587399919.998134 # Number of idle cycles +system.cpu.num_busy_cycles 257427407.001866 # Number of busy cycles +system.cpu.not_idle_fraction 0.066954 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.933046 # Percentage of idle cycles +system.cpu.Branches 8421188 # Number of branches fetched +system.cpu.op_class::No_OpClass 3200330 5.70% 5.70% # Class of executed instruction +system.cpu.op_class::IntAlu 36225212 64.47% 70.17% # Class of executed instruction +system.cpu.op_class::IntMult 61016 0.11% 70.28% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 70.28% # Class of executed instruction +system.cpu.op_class::FloatAdd 38087 0.07% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::FloatDiv 3636 0.01% 70.35% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.35% # Class of executed instruction +system.cpu.op_class::MemRead 9327578 16.60% 86.95% # Class of executed instruction +system.cpu.op_class::MemWrite 6377363 11.35% 98.30% # Class of executed instruction +system.cpu.op_class::IprAccess 953205 1.70% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 56114619 # Class of executed instruction +system.cpu.op_class::total 56186427 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 211965 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 74895 40.89% 40.89% # number of times we switched to this ipl +system.cpu.kern.inst.quiesce 6376 # number of quiesce instructions executed +system.cpu.kern.inst.hwrei 211986 # number of hwrei instructions executed +system.cpu.kern.ipl_count::0 74892 40.89% 40.89% # number of times we switched to this ipl system.cpu.kern.ipl_count::21 131 0.07% 40.96% # number of times we switched to this ipl system.cpu.kern.ipl_count::22 1932 1.05% 42.01% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106217 57.99% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183175 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73528 49.31% 49.31% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count::31 106213 57.99% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 183168 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73525 49.31% 49.31% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::21 131 0.09% 49.40% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::22 1932 1.30% 50.69% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73528 49.31% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149119 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1858230927500 96.76% 96.76% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 91348000 0.00% 96.77% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 737130000 0.04% 96.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 61358632500 3.20% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920418038000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981748 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_good::31 73525 49.31% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149113 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1857939859000 96.65% 96.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 91692000 0.00% 96.65% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 740049500 0.04% 96.69% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 63641329000 3.31% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1922412929500 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981747 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.692243 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::total 0.814079 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.692241 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::total 0.814078 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed @@ -454,10 +459,10 @@ system.cpu.kern.callpal::cserve 1 0.00% 0.00% # nu system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed +system.cpu.kern.callpal::swpctx 4177 2.17% 2.17% # number of callpals executed +system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175954 91.22% 93.41% # number of callpals executed +system.cpu.kern.callpal::swpipl 175947 91.21% 93.41% # number of callpals executed system.cpu.kern.callpal::rdps 6833 3.54% 96.96% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.96% # number of callpals executed @@ -466,101 +471,101 @@ system.cpu.kern.callpal::whami 2 0.00% 96.97% # nu system.cpu.kern.callpal::rti 5157 2.67% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192900 # number of callpals executed -system.cpu.kern.mode_switch::kernel 5901 # number of protection mode switches -system.cpu.kern.mode_switch::user 1743 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2098 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1913 -system.cpu.kern.mode_good::user 1743 +system.cpu.kern.callpal::total 192894 # number of callpals executed +system.cpu.kern.mode_switch::kernel 5905 # number of protection mode switches +system.cpu.kern.mode_switch::user 1740 # number of protection mode switches +system.cpu.kern.mode_switch::idle 2095 # number of protection mode switches +system.cpu.kern.mode_good::kernel 1910 +system.cpu.kern.mode_good::user 1740 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch_good::kernel 0.324182 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.323455 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 0.392732 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46109911500 2.40% 2.40% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5189208000 0.27% 2.67% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869118916500 97.33% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed -system.cpu.dcache.tags.replacements 1389979 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.978885 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 14030604 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1390491 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 10.090395 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 107775250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.978885 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999959 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999959 # Average percentage of cache occupancy +system.cpu.kern.mode_switch_good::idle 0.081146 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 0.392197 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 46428613000 2.42% 2.42% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5237727500 0.27% 2.69% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1870746587000 97.31% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4178 # number of times the context was actually changed +system.cpu.dcache.tags.replacements 1391374 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.978196 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 14046325 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1391886 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 10.091577 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 112435250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.978196 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999957 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999957 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 257 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 68 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 63074876 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 63074876 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 7802731 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7802731 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5845607 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5845607 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 183026 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183026 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 199223 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199223 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13648338 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13648338 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13648338 # number of overall hits -system.cpu.dcache.overall_hits::total 13648338 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069103 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069103 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304189 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304189 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 17217 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17217 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373292 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373292 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373292 # number of overall misses -system.cpu.dcache.overall_misses::total 1373292 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 29000817500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 29000817500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10906930630 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10906930630 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228178000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 228178000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 39907748130 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 39907748130 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 39907748130 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 39907748130 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 8871834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 8871834 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 6149796 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6149796 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200243 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199223 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 15021630 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15021630 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 15021630 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15021630 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120505 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120505 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049463 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049463 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085981 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085981 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.091421 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.091421 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.091421 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.091421 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 27126.308223 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 27126.308223 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35855.769374 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35855.769374 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13253.063832 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13253.063832 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29059.914519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29059.914519 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29059.914519 # average overall miss latency +system.cpu.dcache.tags.tag_accesses 63144735 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 63144735 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 7812525 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7812525 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5851580 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5851580 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 182969 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 182969 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 199234 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 199234 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 13664105 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13664105 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13664105 # number of overall hits +system.cpu.dcache.overall_hits::total 13664105 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1070248 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1070248 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304369 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304369 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 17287 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 17287 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 1374617 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1374617 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1374617 # number of overall misses +system.cpu.dcache.overall_misses::total 1374617 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30897353500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30897353500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11699394130 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11699394130 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 229714500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 229714500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 42596747630 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 42596747630 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 42596747630 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 42596747630 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 8882773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 8882773 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 6155949 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6155949 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200256 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 200256 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 199234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 199234 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 15038722 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 15038722 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 15038722 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 15038722 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120486 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120486 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049443 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049443 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086325 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086325 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.091405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.091405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.091405 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.091405 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28869.340097 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 28869.340097 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38438.192227 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38438.192227 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13288.280211 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13288.280211 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30988.084412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30988.084412 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30988.084412 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -569,54 +574,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 834368 # number of writebacks -system.cpu.dcache.writebacks::total 834368 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069103 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069103 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304189 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304189 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17217 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 17217 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373292 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373292 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373292 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373292 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 26736955500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 26736955500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10245884370 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10245884370 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 193732000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 36982839870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 36982839870 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 36982839870 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 36982839870 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1424272500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1424272500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2009399000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2009399000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3433671500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 3433671500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049463 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049463 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.085981 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091421 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091421 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091421 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25008.774178 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25008.774178 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33682.626163 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33682.626163 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11252.366847 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11252.366847 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26930.062849 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26930.062849 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 835634 # number of writebacks +system.cpu.dcache.writebacks::total 835634 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1070248 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1070248 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304369 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304369 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17287 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 17287 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1374617 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11190140370 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 203771000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 203771000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 40356234870 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 40356234870 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 40356234870 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 40356234870 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1432759000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2025445000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2025445000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 3458204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 3458204000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120486 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049443 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086325 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086325 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.091405 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091405 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.091405 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27251.715957 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27251.715957 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36765.046276 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36765.046276 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11787.528200 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11787.528200 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -624,59 +629,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 927664 # number of replacements -system.cpu.icache.tags.tagsinuse 508.305908 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 55186285 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 928175 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 59.456767 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 39853785250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 508.305908 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.992785 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.992785 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 928205 # number of replacements +system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 55257552 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 928716 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 59.498869 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 42087191250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 508.070911 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.992326 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.992326 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 438 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 9 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 57042955 # Number of tag accesses -system.cpu.icache.tags.data_accesses 57042955 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 55186285 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55186285 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55186285 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55186285 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55186285 # number of overall hits -system.cpu.icache.overall_hits::total 55186285 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928335 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928335 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928335 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928335 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928335 # number of overall misses -system.cpu.icache.overall_misses::total 928335 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12909899750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12909899750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12909899750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12909899750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12909899750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12909899750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 56114620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 56114620 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 56114620 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 56114620 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 56114620 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 56114620 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016544 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.016544 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.016544 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.016544 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.016544 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.016544 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13906.509773 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13906.509773 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13906.509773 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13906.509773 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13906.509773 # average overall miss latency +system.cpu.icache.tags.tag_accesses 57115304 # Number of tag accesses +system.cpu.icache.tags.data_accesses 57115304 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 55257552 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55257552 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55257552 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55257552 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55257552 # number of overall hits +system.cpu.icache.overall_hits::total 55257552 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 928876 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 928876 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 928876 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 928876 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 928876 # number of overall misses +system.cpu.icache.overall_misses::total 928876 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13004894000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13004894000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13004894000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13004894000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13004894000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13004894000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 56186428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 56186428 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 56186428 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 56186428 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 56186428 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 56186428 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.016532 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.016532 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.016532 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.016532 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.016532 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14000.678239 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14000.678239 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14000.678239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14000.678239 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14000.678239 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -685,135 +690,135 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928335 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 928335 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 928335 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 928335 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 928335 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 928335 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11048066250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11048066250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11048066250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11048066250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11048066250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11048066250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016544 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.016544 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016544 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.016544 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11900.947664 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11900.947664 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11900.947664 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11900.947664 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 928876 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 928876 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 928876 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 928876 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 928876 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 928876 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11606411000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11606411000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11606411000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11606411000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11606411000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11606411000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016532 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.016532 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.016532 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12495.113449 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12495.113449 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12495.113449 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12495.113449 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 336225 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65295.018505 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2445535 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 401387 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 6.092711 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6784872750 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 55550.770505 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 4768.438466 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4975.809535 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.847637 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072761 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.075925 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.996323 # Average percentage of cache occupancy +system.cpu.l2cache.tags.replacements 336253 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65287.674931 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2448546 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 401415 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 6.099787 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 7245222750 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 55515.781465 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 4753.205077 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5018.688389 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.847104 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.072528 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.076579 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996211 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 65162 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1074 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4873 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3256 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55781 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4937 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3234 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55805 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994293 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 25931322 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 25931322 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 915025 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 814362 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1729387 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 834368 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 834368 # number of Writeback hits +system.cpu.l2cache.tags.tag_accesses 25957144 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 25957144 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.inst 915565 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 815571 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1731136 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 835634 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 835634 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 187334 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 187334 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 915025 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1001696 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1916721 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 915025 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1001696 # number of overall hits -system.cpu.l2cache.overall_hits::total 1916721 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 13290 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 271958 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 285248 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_hits::cpu.data 187495 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 187495 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.inst 915565 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1003066 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1918631 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 915565 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1003066 # number of overall hits +system.cpu.l2cache.overall_hits::total 1918631 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 13291 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 271964 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 285255 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 13 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 13 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 116838 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 116838 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 13290 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 388796 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 402086 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 13290 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 388796 # number of overall misses -system.cpu.l2cache.overall_misses::total 402086 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 969461250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17700747500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18670208750 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 190498 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 190498 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8067922881 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8067922881 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 969461250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 25768670381 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26738131631 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 969461250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 25768670381 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26738131631 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 928315 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1086320 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2014635 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 834368 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 834368 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 116857 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 116857 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 13291 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 388821 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 402112 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 13291 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 388821 # number of overall misses +system.cpu.l2cache.overall_misses::total 402112 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1064072500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 19718835000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20782907500 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 220998 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 220998 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8916531881 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8916531881 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1064072500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 28635366881 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 29699439381 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1064072500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 28635366881 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 29699439381 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 928856 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1087535 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2016391 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 835634 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 835634 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 17 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 17 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 304172 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 928315 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1390492 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2318807 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 928315 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1390492 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2318807 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014316 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250348 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.141588 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 304352 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 304352 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 928856 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1391887 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2320743 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 928856 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1391887 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2320743 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014309 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.250074 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.141468 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.764706 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.764706 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384118 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.384118 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014316 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.279610 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.173402 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014316 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.279610 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.173402 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72946.670429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65086.327668 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 65452.549185 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 14653.692308 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 14653.692308 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69052.216582 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69052.216582 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 66498.539196 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72946.670429 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 66278.126269 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 66498.539196 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.383953 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.383953 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014309 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.279348 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.173269 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014309 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.279348 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.173269 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80059.626815 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72505.313203 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 72857.294351 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 16999.846154 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 16999.846154 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76302.933337 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76302.933337 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 73858.624913 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80059.626815 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73646.657153 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 73858.624913 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -822,66 +827,66 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 74170 # number of writebacks -system.cpu.l2cache.writebacks::total 74170 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13290 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271958 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 285248 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 74181 # number of writebacks +system.cpu.l2cache.writebacks::total 74181 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 13291 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 271964 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 285255 # number of ReadReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 13 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses::total 13 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116838 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 116838 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 13290 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 388796 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 402086 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 13290 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 388796 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 402086 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 802917750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 14300848500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15103766250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 230011 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6607051619 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6607051619 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 802917750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 20907900119 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21710817869 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 802917750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 20907900119 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21710817869 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1334182500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1334182500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1893599000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1893599000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3227781500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3227781500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250348 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141588 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 116857 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 116857 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 13291 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 388821 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 402112 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 327511 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 327511 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7455368119 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7455368119 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 897481500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23773879119 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 24671360619 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 897481500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23773879119 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24671360619 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1335739000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 1335739000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 1899995000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 1899995000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 3235734000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 3235734000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.141468 # mshr miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.764706 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.384118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.384118 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.173402 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014316 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279610 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.173402 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60415.180587 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52584.768604 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52949.595615 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17693.153846 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56548.825031 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56548.825031 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60415.180587 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53776.016520 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53995.458357 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.383953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.383953 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.173269 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.014309 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.279348 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.173269 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67525.505981 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60002.467238 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60352.991183 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 25193.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 25193.153846 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63799.071677 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63799.071677 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -889,41 +894,41 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2021758 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2021741 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 9650 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 9650 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 834368 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 835634 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41588 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 17 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 17 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 304172 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 304172 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1856650 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3648702 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5505352 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59412160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142445588 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 201857748 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 41901 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3194937 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.013060 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.113530 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadExReq 304352 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 304352 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1857732 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3652758 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5510490 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 59446784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 41937 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.113522 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3153212 98.69% 98.69% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 41725 1.31% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 41761 1.31% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3194937 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2424089000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1395084250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1395898500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 2186669630 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 2188894130 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -996,23 +1001,23 @@ system.iobus.reqLayer27.occupancy 76000 # La system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer29.occupancy 406198788 # Layer occupancy (ticks) +system.iobus.reqLayer29.occupancy 242042219 # Layer occupancy (ticks) system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 23510000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 42010500 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 42024000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 41685 # number of replacements -system.iocache.tags.tagsinuse 1.352284 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.342966 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 1753525494000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::tsunami.ide 1.352284 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::tsunami.ide 0.084518 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.084518 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 1756462668000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::tsunami.ide 1.342966 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::tsunami.ide 0.083935 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.083935 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1026,14 +1031,14 @@ system.iocache.demand_misses::tsunami.ide 173 # n system.iocache.demand_misses::total 173 # number of demand (read+write) misses system.iocache.overall_misses::tsunami.ide 173 # number of overall misses system.iocache.overall_misses::total 173 # number of overall misses -system.iocache.ReadReq_miss_latency::tsunami.ide 23338383 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 23338383 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 13635239905 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 13635239905 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 23338383 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 23338383 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 23338383 # number of overall miss cycles -system.iocache.overall_miss_latency::total 23338383 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::tsunami.ide 8755465836 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8755465836 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles +system.iocache.overall_miss_latency::total 21714383 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) @@ -1050,19 +1055,19 @@ system.iocache.demand_miss_rate::tsunami.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::tsunami.ide 134903.947977 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 134903.947977 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 328148.823282 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 328148.823282 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 134903.947977 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 134903.947977 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 134903.947977 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 206255 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::tsunami.ide 210711.056893 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 210711.056893 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 72960 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 23561 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 9989 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.754085 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.304034 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1076,14 +1081,14 @@ system.iocache.demand_mshr_misses::tsunami.ide 173 system.iocache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::tsunami.ide 173 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 14341383 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14341383 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 11474535905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 11474535905 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 14341383 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14341383 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 14341383 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14341383 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::tsunami.ide 6594761836 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6594761836 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 12562383 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1092,57 +1097,57 @@ system.iocache.demand_mshr_miss_rate::tsunami.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82898.167630 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 276148.823282 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 276148.823282 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 82898.167630 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82898.167630 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::tsunami.ide 158711.056893 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 158711.056893 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 292351 # Transaction distribution -system.membus.trans_dist::ReadResp 292351 # Transaction distribution +system.membus.trans_dist::ReadReq 292358 # Transaction distribution +system.membus.trans_dist::ReadResp 292358 # Transaction distribution system.membus.trans_dist::WriteReq 9650 # Transaction distribution system.membus.trans_dist::WriteResp 9650 # Transaction distribution -system.membus.trans_dist::Writeback 115682 # Transaction distribution +system.membus.trans_dist::Writeback 115693 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution system.membus.trans_dist::UpgradeReq 132 # Transaction distribution system.membus.trans_dist::UpgradeResp 132 # Transaction distribution -system.membus.trans_dist::ReadExReq 116719 # Transaction distribution -system.membus.trans_dist::ReadExResp 116719 # Transaction distribution +system.membus.trans_dist::ReadExReq 116738 # Transaction distribution +system.membus.trans_dist::ReadExResp 116738 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33160 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878095 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911255 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 911318 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1036059 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1036122 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44564 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30455424 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30499988 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30457792 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30502356 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5317056 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 35817044 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 431 # Total snoops (count) -system.membus.snoop_fanout::samples 559506 # Request fanout histogram +system.membus.snoop_fanout::samples 559589 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 559506 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 559506 # Request fanout histogram -system.membus.reqLayer0.occupancy 30371500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 559589 # Request fanout histogram +system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 1824515500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3751827620 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 43109500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2144408870 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index def60114c..cb5fe02ce 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.802895 # Number of seconds simulated -sim_ticks 2802895103500 # Number of ticks simulated -final_tick 2802895103500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2802894699500 # Number of ticks simulated +final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 834307 # Simulator instruction rate (inst/s) -host_op_rate 1016590 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 15926512431 # Simulator tick rate (ticks/s) -host_mem_usage 572876 # Number of bytes of host memory used -host_seconds 175.99 # Real time elapsed on the host -sim_insts 146829031 # Number of instructions simulated -sim_ops 178908942 # Number of ops (including micro ops) simulated +host_inst_rate 1337323 # Simulator instruction rate (inst/s) +host_op_rate 1629508 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25528979782 # Simulator tick rate (ticks/s) +host_mem_usage 626168 # Number of bytes of host memory used +host_seconds 109.79 # Real time elapsed on the host +sim_insts 146828240 # Number of instructions simulated +sim_ops 178908039 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1117540 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 9440380 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1117604 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9440956 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 152404 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1082016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 152020 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1081568 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11794004 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1117540 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 152404 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1269944 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8387200 # Number of bytes written to this memory +system.physmem.bytes_read::total 11793812 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1117604 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 152020 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1269624 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8390656 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8404944 # Number of bytes written to this memory +system.physmem.bytes_written::total 8408400 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 25915 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 148031 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 148040 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2536 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16930 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 16923 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193438 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131050 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193435 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131104 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135486 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135540 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 398709 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3368082 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 398732 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3368288 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 386035 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 54237 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 385875 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4207794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 398709 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54374 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 453083 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2992335 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4207726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 398732 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 54237 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 452969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2993568 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2998665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2992335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2999899 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2993568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 398709 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3374398 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 398732 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3374604 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 386049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 54237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 385890 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7206459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7207624 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -142,9 +142,9 @@ system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6573 system.cpu0.dtb.walker.walkRequestOrigin::total 14540 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 20339962 # DTB read hits +system.cpu0.dtb.read_hits 20339720 # DTB read hits system.cpu0.dtb.read_misses 6874 # DTB read misses -system.cpu0.dtb.write_hits 16391171 # DTB write hits +system.cpu0.dtb.write_hits 16391078 # DTB write hits system.cpu0.dtb.write_misses 1093 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -155,12 +155,12 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 20346836 # DTB read accesses -system.cpu0.dtb.write_accesses 16392264 # DTB write accesses +system.cpu0.dtb.read_accesses 20346594 # DTB read accesses +system.cpu0.dtb.write_accesses 16392171 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 36731133 # DTB hits +system.cpu0.dtb.hits 36730798 # DTB hits system.cpu0.dtb.misses 7967 # DTB misses -system.cpu0.dtb.accesses 36739100 # DTB accesses +system.cpu0.dtb.accesses 36738765 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -208,7 +208,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2342 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5700 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 97440315 # ITB inst hits +system.cpu0.itb.inst_hits 97439331 # ITB inst hits system.cpu0.itb.inst_misses 3358 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -225,37 +225,37 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 97443673 # ITB inst accesses -system.cpu0.itb.hits 97440315 # DTB hits +system.cpu0.itb.inst_accesses 97442689 # ITB inst accesses +system.cpu0.itb.hits 97439331 # DTB hits system.cpu0.itb.misses 3358 # DTB misses -system.cpu0.itb.accesses 97443673 # DTB accesses -system.cpu0.numCycles 5605792176 # number of cpu cycles simulated +system.cpu0.itb.accesses 97442689 # DTB accesses +system.cpu0.numCycles 5605791368 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 95427853 # Number of instructions committed -system.cpu0.committedOps 115561498 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 100763618 # Number of integer alu accesses +system.cpu0.committedInsts 95426926 # Number of instructions committed +system.cpu0.committedOps 115560427 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 100762696 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses -system.cpu0.num_func_calls 8000324 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 13204344 # number of instructions that are conditional controls -system.cpu0.num_int_insts 100763618 # number of integer instructions +system.cpu0.num_func_calls 8000180 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13204202 # number of instructions that are conditional controls +system.cpu0.num_int_insts 100762696 # number of integer instructions system.cpu0.num_fp_insts 9755 # number of float instructions -system.cpu0.num_int_register_reads 182459108 # number of times the integer registers were read -system.cpu0.num_int_register_writes 69136203 # number of times the integer registers were written +system.cpu0.num_int_register_reads 182457229 # number of times the integer registers were read +system.cpu0.num_int_register_writes 69135541 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 349974767 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 44907843 # number of times the CC registers were written -system.cpu0.num_mem_refs 37874145 # number of memory refs -system.cpu0.num_load_insts 20597552 # Number of load instructions -system.cpu0.num_store_insts 17276593 # Number of store instructions -system.cpu0.num_idle_cycles 5488206556.246817 # Number of idle cycles -system.cpu0.num_busy_cycles 117585619.753183 # Number of busy cycles +system.cpu0.num_cc_register_reads 349971383 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 44907438 # number of times the CC registers were written +system.cpu0.num_mem_refs 37873810 # number of memory refs +system.cpu0.num_load_insts 20597310 # Number of load instructions +system.cpu0.num_store_insts 17276500 # Number of store instructions +system.cpu0.num_idle_cycles 5488206876.247207 # Number of idle cycles +system.cpu0.num_busy_cycles 117584491.752793 # Number of busy cycles system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles -system.cpu0.Branches 21941792 # Number of branches fetched +system.cpu0.Branches 21941499 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 78888049 67.49% 67.50% # Class of executed instruction +system.cpu0.op_class::IntAlu 78887256 67.49% 67.49% # Class of executed instruction system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction @@ -284,20 +284,20 @@ system.cpu0.op_class::SimdFloatMisc 8087 0.01% 67.60% # Cl system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction -system.cpu0.op_class::MemRead 20597552 17.62% 85.22% # Class of executed instruction -system.cpu0.op_class::MemWrite 17276593 14.78% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 20597310 17.62% 85.22% # Class of executed instruction +system.cpu0.op_class::MemWrite 17276500 14.78% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 116883193 # Class of executed instruction +system.cpu0.op_class::total 116882065 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 693476 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.853661 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 35932684 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 693988 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.777097 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 693477 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.853657 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 35932369 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 693989 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.776569 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853661 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853657 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id @@ -305,50 +305,50 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 74114402 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 74114402 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 19108775 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 19108775 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15690454 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15690454 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 74113775 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 74113775 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 19108539 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 19108539 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15690376 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15690376 # number of WriteReq hits system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363052 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 363052 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 34799229 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 34799229 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 35145322 # number of overall hits -system.cpu0.dcache.overall_hits::total 35145322 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 373098 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 373098 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 295765 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 295765 # number of WriteReq misses +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363049 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 363049 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 34798915 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 34798915 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35145008 # number of overall hits +system.cpu0.dcache.overall_hits::total 35145008 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 373099 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 373099 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 295764 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 295764 # number of WriteReq misses system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18433 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 18433 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18436 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 18436 # number of StoreCondReq misses system.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses system.cpu0.dcache.overall_misses::total 769184 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481873 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 19481873 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986219 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15986219 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481638 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 19481638 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986140 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 15986140 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 35468092 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 35468092 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 35914506 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 35914506 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 35467778 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 35467778 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses @@ -357,8 +357,8 @@ system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048319 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048319 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048327 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048327 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses @@ -371,14 +371,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 511648 # number of writebacks -system.cpu0.dcache.writebacks::total 511648 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 511896 # number of writebacks +system.cpu0.dcache.writebacks::total 511896 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1109742 # number of replacements +system.cpu0.icache.tags.replacements 1109735 # number of replacements system.cpu0.icache.tags.tagsinuse 511.809992 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 96332394 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1110254 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 86.766086 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 96331417 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1110247 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 86.765753 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6345717000 # Cycle when the warmup percentage was hit. system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.809992 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999629 # Average percentage of cache occupancy @@ -388,26 +388,26 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::0 212 system.cpu0.icache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 210 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 195995577 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 195995577 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 96332394 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 96332394 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 96332394 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 96332394 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 96332394 # number of overall hits -system.cpu0.icache.overall_hits::total 96332394 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1110263 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1110263 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1110263 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1110263 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1110263 # number of overall misses -system.cpu0.icache.overall_misses::total 1110263 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 97442657 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 97442657 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 97442657 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 97442657 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 97442657 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 97442657 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 195993602 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 195993602 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 96331417 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 96331417 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 96331417 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 96331417 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 96331417 # number of overall hits +system.cpu0.icache.overall_hits::total 96331417 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1110256 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1110256 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1110256 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1110256 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1110256 # number of overall misses +system.cpu0.icache.overall_misses::total 1110256 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 97441673 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 97441673 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 97441673 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 97441673 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 97441673 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 97441673 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011394 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011394 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011394 # miss rate for demand accesses @@ -429,123 +429,123 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 252403 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16129.283805 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1810262 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 268606 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.739470 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 252330 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16129.294754 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1810154 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 268529 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.741000 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 1814550500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 8068.095549 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.185761 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.086115 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.591048 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.325333 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.492437 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289831 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201985 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.984453 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 8067.926153 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 3.192846 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.094111 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4748.670375 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3309.411269 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.492427 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000195 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.289836 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.201990 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.984454 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1024 16192 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 279 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5587 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7674 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2571 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 5555 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7641 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2632 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000427 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.988281 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39450391 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39450391 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7605 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3248 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065251 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 352125 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1428229 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 511648 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 511648 # number of Writeback hits +system.cpu0.l2cache.tags.tag_accesses 39452382 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39452382 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7540 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3225 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1065497 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 351995 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1428257 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 511896 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 511896 # number of Writeback hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 17 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 17 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94130 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 94130 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7605 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3248 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1065251 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 446255 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1522359 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7605 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3248 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1065251 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 446255 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1522359 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 225 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 134 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 45012 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 128036 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 173407 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26231 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26231 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18433 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18433 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175387 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 175387 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 225 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 134 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 45012 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 303423 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 348794 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 225 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 134 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 45012 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 303423 # number of overall misses -system.cpu0.l2cache.overall_misses::total 348794 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7830 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3382 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110263 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480161 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1601636 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 511648 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 511648 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26248 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 26248 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18433 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 18433 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 94089 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 94089 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7540 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3225 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1065497 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 446084 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1522346 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7540 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3225 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1065497 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 446084 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1522346 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 210 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 124 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 44759 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 128167 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 173260 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26230 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26230 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18436 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 18436 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 175428 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 175428 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 210 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 124 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 44759 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 303595 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 348688 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 210 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 124 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 44759 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 303595 # number of overall misses +system.cpu0.l2cache.overall_misses::total 348688 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7750 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3349 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1110256 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 480162 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1601517 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 511896 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 511896 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 26247 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 26247 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 18436 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 18436 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269517 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 269517 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7830 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3382 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1110263 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 749678 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1871153 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7830 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3382 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1110263 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 749678 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1871153 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.039622 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040542 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266652 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.108269 # miss rate for ReadReq accesses +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7750 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3349 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1110256 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 749679 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1871034 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7750 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3349 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1110256 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 749679 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1871034 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037026 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040314 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.266924 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.108185 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650746 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650746 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.039622 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040542 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404738 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.186406 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.028736 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.039622 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040542 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404738 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.186406 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650898 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650898 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037026 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040314 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404967 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.186361 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.027097 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037026 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040314 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404967 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.186361 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -554,45 +554,43 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192841 # number of writebacks -system.cpu0.l2cache.writebacks::total 192841 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 192974 # number of writebacks +system.cpu0.l2cache.writebacks::total 192974 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1651853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1651853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 511648 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18433 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 44681 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadReq 1651840 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1651840 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28386 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28386 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 511896 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 26247 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18436 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 44683 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238570 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220344 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220556 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4500550 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092920 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80915642 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4500748 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80931536 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 152091834 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 322042 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2656528 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.082604 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.275283 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 152107280 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 322019 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2656743 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.082586 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.275256 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2437088 91.74% 91.74% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 219440 8.26% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 2437332 91.74% 91.74% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 219411 8.26% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2656528 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2656743 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -642,9 +640,9 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2588 system.cpu1.dtb.walker.walkRequestOrigin::total 5946 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 12173884 # DTB read hits +system.cpu1.dtb.read_hits 12173916 # DTB read hits system.cpu1.dtb.read_misses 2852 # DTB read misses -system.cpu1.dtb.write_hits 7587193 # DTB write hits +system.cpu1.dtb.write_hits 7587209 # DTB write hits system.cpu1.dtb.write_misses 506 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -655,12 +653,12 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 12176736 # DTB read accesses -system.cpu1.dtb.write_accesses 7587699 # DTB write accesses +system.cpu1.dtb.read_accesses 12176768 # DTB read accesses +system.cpu1.dtb.write_accesses 7587715 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 19761077 # DTB hits +system.cpu1.dtb.hits 19761125 # DTB hits system.cpu1.dtb.misses 3358 # DTB misses -system.cpu1.dtb.accesses 19764435 # DTB accesses +system.cpu1.dtb.accesses 19764483 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -708,7 +706,7 @@ system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1095 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin::total 2829 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 53671431 # ITB inst hits +system.cpu1.itb.inst_hits 53671575 # ITB inst hits system.cpu1.itb.inst_misses 1734 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -725,37 +723,37 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 53673165 # ITB inst accesses -system.cpu1.itb.hits 53671431 # DTB hits +system.cpu1.itb.inst_accesses 53673309 # ITB inst accesses +system.cpu1.itb.hits 53671575 # DTB hits system.cpu1.itb.misses 1734 # DTB misses -system.cpu1.itb.accesses 53673165 # DTB accesses -system.cpu1.numCycles 5605321082 # number of cpu cycles simulated +system.cpu1.itb.accesses 53673309 # DTB accesses +system.cpu1.numCycles 5605320274 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 51401178 # Number of instructions committed -system.cpu1.committedOps 63347444 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 56984089 # Number of integer alu accesses +system.cpu1.committedInsts 51401314 # Number of instructions committed +system.cpu1.committedOps 63347612 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 56984241 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses -system.cpu1.num_func_calls 9170823 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 5967084 # number of instructions that are conditional controls -system.cpu1.num_int_insts 56984089 # number of integer instructions +system.cpu1.num_func_calls 9170855 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 5967100 # number of instructions that are conditional controls +system.cpu1.num_int_insts 56984241 # number of integer instructions system.cpu1.num_fp_insts 1792 # number of float instructions -system.cpu1.num_int_register_reads 110674435 # number of times the integer registers were read -system.cpu1.num_int_register_writes 41298241 # number of times the integer registers were written +system.cpu1.num_int_register_reads 110674739 # number of times the integer registers were read +system.cpu1.num_int_register_writes 41298353 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 196268127 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 18894317 # number of times the CC registers were written -system.cpu1.num_mem_refs 20026333 # number of memory refs -system.cpu1.num_load_insts 12289505 # Number of load instructions -system.cpu1.num_store_insts 7736828 # Number of store instructions -system.cpu1.num_idle_cycles 5539707743.549846 # Number of idle cycles -system.cpu1.num_busy_cycles 65613338.450155 # Number of busy cycles +system.cpu1.num_cc_register_reads 196268655 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 18894365 # number of times the CC registers were written +system.cpu1.num_mem_refs 20026381 # number of memory refs +system.cpu1.num_load_insts 12289537 # Number of load instructions +system.cpu1.num_store_insts 7736844 # Number of store instructions +system.cpu1.num_idle_cycles 5539706759.565366 # Number of idle cycles +system.cpu1.num_busy_cycles 65613514.434634 # Number of busy cycles system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles -system.cpu1.Branches 15217445 # Number of branches fetched +system.cpu1.Branches 15217493 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 45401182 69.36% 69.36% # Class of executed instruction +system.cpu1.op_class::IntAlu 45401310 69.36% 69.36% # Class of executed instruction system.cpu1.op_class::IntMult 28388 0.04% 69.40% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction @@ -784,70 +782,70 @@ system.cpu1.op_class::SimdFloatMisc 3319 0.01% 69.41% # Cl system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction -system.cpu1.op_class::MemRead 12289505 18.77% 88.18% # Class of executed instruction -system.cpu1.op_class::MemWrite 7736828 11.82% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 12289537 18.77% 88.18% # Class of executed instruction +system.cpu1.op_class::MemWrite 7736844 11.82% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 65459288 # Class of executed instruction +system.cpu1.op_class::total 65459464 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed system.cpu1.dcache.tags.replacements 191938 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.735401 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 19503461 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 472.735415 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19503509 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 192292 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 101.426274 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 101.426523 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735401 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.735415 # Average occupied blocks per requestor system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923311 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.923311 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::3 13 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 39751883 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 39751883 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 11858662 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 11858662 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 7397475 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 7397475 # number of WriteReq hits +system.cpu1.dcache.tags.tag_accesses 39751979 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7397494 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7397494 # number of WriteReq hits system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72435 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 72435 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 19256137 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 19256137 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 19306236 # number of overall hits -system.cpu1.dcache.overall_hits::total 19306236 # number of overall hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72460 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 72460 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19256188 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19256188 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19306287 # number of overall hits +system.cpu1.dcache.overall_hits::total 19306287 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 92471 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 92471 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 92468 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 92468 # number of WriteReq misses system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22544 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 22544 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 229101 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 229101 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 259820 # number of overall misses -system.cpu1.dcache.overall_misses::total 259820 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995292 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11995292 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489946 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7489946 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22519 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 22519 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 229098 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 229098 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses +system.cpu1.dcache.overall_misses::total 259817 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 7489962 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.SoftPFReq_accesses::total 80818 # number of SoftPFReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 96765 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94979 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 94979 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 19485238 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 19485238 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 19566056 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 19566056 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 19485286 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19485286 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19566104 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses @@ -856,10 +854,10 @@ system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237358 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237358 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237095 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237095 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -870,42 +868,42 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 120709 # number of writebacks -system.cpu1.dcache.writebacks::total 120709 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 120855 # number of writebacks +system.cpu1.dcache.writebacks::total 120855 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 523373 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.711131 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 53148636 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 53148780 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 523885 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 101.450960 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 101.451235 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711131 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711129 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975998 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 107868927 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 107868927 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 53148636 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 53148636 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 53148636 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 53148636 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 53148636 # number of overall hits -system.cpu1.icache.overall_hits::total 53148636 # number of overall hits +system.cpu1.icache.tags.tag_accesses 107869215 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 107869215 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 53148780 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 53148780 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 53148780 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 53148780 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 53148780 # number of overall hits +system.cpu1.icache.overall_hits::total 53148780 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 523885 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 523885 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 523885 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 523885 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 523885 # number of overall misses system.cpu1.icache.overall_misses::total 523885 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672521 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 53672521 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 53672521 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 53672521 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 53672521 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 53672521 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 53672665 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 53672665 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 53672665 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 53672665 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 53672665 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 53672665 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses @@ -927,88 +925,88 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 48598 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15305.342188 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 716678 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 63421 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.300326 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 48604 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15305.333897 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 716708 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.298662 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809104 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.085339 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.030831 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.951411 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.465503 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809694 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.091002 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.023143 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.979607 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.430451 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000249 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000124 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200131 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225370 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.934164 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14799 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200133 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225368 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.934163 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14807 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9279 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4981 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903259 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15211446 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15211446 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3145 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1724 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510078 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 99331 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 614278 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 120709 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 120709 # number of Writeback hits +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9357 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4911 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903748 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 15213345 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 15213345 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3151 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1735 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510036 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 99375 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 614297 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 120855 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 120855 # number of Writeback hits system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19802 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 19802 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3145 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1724 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 510078 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 119133 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 634080 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3145 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1724 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 510078 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 119133 # number of overall hits -system.cpu1.l2cache.overall_hits::total 634080 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 344 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 272 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13807 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 73336 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 87759 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28847 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28847 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22544 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22544 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43814 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 43814 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 344 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 272 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13807 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 117150 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 131573 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 344 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 272 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13807 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 117150 # number of overall misses -system.cpu1.l2cache.overall_misses::total 131573 # number of overall misses +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19784 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 19784 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3151 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1735 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 510036 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 119159 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 634081 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3151 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1735 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 510036 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 119159 # number of overall hits +system.cpu1.l2cache.overall_hits::total 634081 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 261 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13849 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 73292 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 87740 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28844 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28844 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22519 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22519 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43832 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 43832 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 261 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13849 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 117124 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 131572 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 261 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13849 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 117124 # number of overall misses +system.cpu1.l2cache.overall_misses::total 131572 # number of overall misses system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3489 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1996 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 523885 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.data 172667 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 702037 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 120709 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 120709 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28855 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 28855 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22544 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 22544 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 120855 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 120855 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 28852 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 28852 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 22519 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 22519 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 63616 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3489 # number of demand (read+write) accesses @@ -1021,27 +1019,27 @@ system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1996 system.cpu1.l2cache.overall_accesses::cpu1.inst 523885 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 765653 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.136273 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026355 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424725 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.125006 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.130762 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026435 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.424470 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.124979 # miss rate for ReadReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.688726 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.688726 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.136273 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026355 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495804 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.171844 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.098596 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.136273 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026355 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495804 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.171844 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.689009 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.689009 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.130762 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026435 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495694 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.171843 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.096876 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.130762 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026435 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495694 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.171843 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1050,51 +1048,49 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 32919 # number of writebacks -system.cpu1.l2cache.writebacks::total 32919 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 32977 # number of writebacks +system.cpu1.l2cache.writebacks::total 32977 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 120709 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 28855 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 51399 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 120855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 28852 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 51371 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707533 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707623 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1774351 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1774441 # Packet count per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866670 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22876014 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 56433406 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 499587 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1371557 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.313464 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.463901 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size::total 56442750 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 499492 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1371571 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.313385 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.463870 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 941623 68.65% 68.65% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 429934 31.35% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 941741 68.66% 68.66% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 429830 31.34% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1371557 # Request fanout histogram -system.iobus.trans_dist::ReadReq 31002 # Transaction distribution -system.iobus.trans_dist::ReadResp 31002 # Transaction distribution -system.iobus.trans_dist::WriteReq 59433 # Transaction distribution -system.iobus.trans_dist::WriteResp 23209 # Transaction distribution +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1371571 # Request fanout histogram +system.iobus.trans_dist::ReadReq 30995 # Transaction distribution +system.iobus.trans_dist::ReadResp 30995 # Transaction distribution +system.iobus.trans_dist::WriteReq 59419 # Transaction distribution +system.iobus.trans_dist::WriteResp 23195 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56582 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1115,11 +1111,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107876 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180828 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71526 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1140,10 +1136,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162766 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484014 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36442 # number of replacements system.iocache.tags.tagsinuse 14.586092 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1193,21 +1189,21 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 107620 # number of replacements -system.l2c.tags.tagsinuse 62052.354763 # Cycle average of tags in use -system.l2c.tags.total_refs 207975 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 168018 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.237814 # Average number of references to valid blocks. +system.l2c.tags.replacements 107683 # number of replacements +system.l2c.tags.tagsinuse 62052.473518 # Cycle average of tags in use +system.l2c.tags.total_refs 207875 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 168125 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.236431 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48595.577563 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.970677 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48595.677496 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972785 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 7329.733330 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3756.722499 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7329.722723 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3756.747244 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.823230 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1654.519056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 710.978017 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.741510 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 1654.505866 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 710.993782 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.741511 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.111843 # Average percentage of cache occupancy @@ -1215,161 +1211,161 @@ system.l2c.tags.occ_percent::cpu0.data 0.057323 # Av system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000028 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.946844 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 60392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1918 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 13006 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 45390 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.921509 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4903951 # Number of tag accesses -system.l2c.tags.data_accesses 4903951 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 85 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 75 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 28112 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 75977 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 41 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 36 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11436 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11429 # number of ReadReq hits -system.l2c.ReadReq_hits::total 127191 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 225760 # number of Writeback hits -system.l2c.Writeback_hits::total 225760 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 516 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 57 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 573 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 52 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 61 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 13918 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 3099 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 17017 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 85 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 75 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 28112 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 89895 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 41 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 36 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11436 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 14528 # number of demand (read+write) hits -system.l2c.demand_hits::total 144208 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 85 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits -system.l2c.overall_hits::cpu0.inst 28112 # number of overall hits -system.l2c.overall_hits::cpu0.data 89895 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 41 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 36 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11436 # number of overall hits -system.l2c.overall_hits::cpu1.data 14528 # number of overall hits -system.l2c.overall_hits::total 144208 # number of overall hits +system.l2c.tags.occ_percent::total 0.946846 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 60435 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1875 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 13095 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.922165 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4904261 # Number of tag accesses +system.l2c.tags.data_accesses 4904261 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 71 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 27858 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 76068 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 39 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 20 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11484 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 11410 # number of ReadReq hits +system.l2c.ReadReq_hits::total 127013 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 225951 # number of Writeback hits +system.l2c.Writeback_hits::total 225951 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 487 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 552 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 64 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 13938 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 3112 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 17050 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 27858 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 90006 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 39 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 20 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 11484 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 14522 # number of demand (read+write) hits +system.l2c.demand_hits::total 144063 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 71 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits +system.l2c.overall_hits::cpu0.inst 27858 # number of overall hits +system.l2c.overall_hits::cpu0.data 90006 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 39 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 20 # number of overall hits +system.l2c.overall_hits::cpu1.inst 11484 # number of overall hits +system.l2c.overall_hits::cpu1.data 14522 # number of overall hits +system.l2c.overall_hits::total 144063 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 16900 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 11311 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 16901 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 11313 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2371 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1120 # number of ReadReq misses -system.l2c.ReadReq_misses::total 31713 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 9991 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3299 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13290 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 771 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1177 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1948 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 136796 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15826 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 152622 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu1.inst 2365 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1118 # number of ReadReq misses +system.l2c.ReadReq_misses::total 31708 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 10019 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3288 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13307 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 752 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1179 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1931 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 136795 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15822 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 152617 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 16900 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 148107 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 16901 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 148108 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2371 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 16946 # number of demand (read+write) misses -system.l2c.demand_misses::total 184335 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2365 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16940 # number of demand (read+write) misses +system.l2c.demand_misses::total 184325 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 16900 # number of overall misses -system.l2c.overall_misses::cpu0.data 148107 # number of overall misses +system.l2c.overall_misses::cpu0.inst 16901 # number of overall misses +system.l2c.overall_misses::cpu0.data 148108 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2371 # number of overall misses -system.l2c.overall_misses::cpu1.data 16946 # number of overall misses -system.l2c.overall_misses::total 184335 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 92 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 77 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 45012 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 87288 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 43 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 36 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 13807 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12549 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 158904 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 225760 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 225760 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 10507 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3356 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13863 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 823 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1186 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2009 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 150714 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 18925 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 169639 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 92 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 77 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 45012 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 238002 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 43 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 36 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 13807 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 31474 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 328543 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 92 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 77 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 45012 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 238002 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 43 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 36 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 13807 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 31474 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 328543 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.025974 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.375455 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.129583 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.171724 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.089250 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.199573 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.950890 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.983015 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.958667 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.936817 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.992411 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.969637 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.907653 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.836248 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.899687 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.025974 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.375455 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.622293 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.171724 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.538413 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.561068 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.076087 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.025974 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.375455 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.622293 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.046512 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.171724 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.538413 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.561068 # miss rate for overall accesses +system.l2c.overall_misses::cpu1.inst 2365 # number of overall misses +system.l2c.overall_misses::cpu1.data 16940 # number of overall misses +system.l2c.overall_misses::total 184325 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 78 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 44759 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 87381 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 41 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 20 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13849 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12528 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 158721 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 225951 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 225951 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10506 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3353 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 13859 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 816 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1189 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2005 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150733 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 18934 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 169667 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 78 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 44759 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 238114 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 41 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 20 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13849 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 31462 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 328388 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 78 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 44759 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 238114 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 41 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 20 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13849 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 31462 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 328388 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.377600 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.129468 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.170770 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.089240 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.199772 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.953646 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980614 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.960170 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.921569 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.991590 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.963092 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.907532 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.835640 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.899509 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.377600 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.622005 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.170770 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.538427 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.561302 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.089744 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.377600 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.622005 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.048780 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.170770 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.538427 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.561302 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1378,49 +1374,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 94860 # number of writebacks -system.l2c.writebacks::total 94860 # number of writebacks +system.l2c.writebacks::writebacks 94914 # number of writebacks +system.l2c.writebacks::total 94914 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 75978 # Transaction distribution -system.membus.trans_dist::ReadResp 75978 # Transaction distribution -system.membus.trans_dist::WriteReq 30905 # Transaction distribution -system.membus.trans_dist::WriteResp 30905 # Transaction distribution -system.membus.trans_dist::Writeback 131050 # Transaction distribution +system.membus.trans_dist::ReadReq 75966 # Transaction distribution +system.membus.trans_dist::ReadResp 75966 # Transaction distribution +system.membus.trans_dist::WriteReq 30891 # Transaction distribution +system.membus.trans_dist::WriteResp 30891 # Transaction distribution +system.membus.trans_dist::Writeback 131104 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 60385 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40916 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15642 # Transaction distribution -system.membus.trans_dist::ReadExReq 196304 # Transaction distribution -system.membus.trans_dist::ReadExResp 152218 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 60393 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40881 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15635 # Transaction distribution +system.membus.trans_dist::ReadExReq 196339 # Transaction distribution +system.membus.trans_dist::ReadExResp 152220 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 773587 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 773592 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 882729 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 882734 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17899556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18089380 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17902820 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18092602 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22740004 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22743226 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 496844 # Request fanout histogram +system.membus.snoop_fanout::samples 496901 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 496844 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 496901 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 496844 # Request fanout histogram +system.membus.snoop_fanout::total 496901 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1452,33 +1448,33 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 305179 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 305179 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 225760 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60554 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40977 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 101531 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 213725 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 213725 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117779 # Packet count per connected master and slave (bytes) +system.toL2Bus.trans_dist::ReadReq 305006 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 305006 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30891 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30891 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 225951 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40955 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 101503 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117662 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1528440 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34662706 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425714 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45088420 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1528323 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664008 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10429874 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 45093882 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36713 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 838658 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.043493 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.203965 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 838716 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.043490 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.203958 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 802182 95.65% 95.65% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 802240 95.65% 95.65% # Request fanout histogram system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 838658 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 838716 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index fb9bec115..20c993e31 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867165000 # Number of ticks simulated -final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783867052000 # Number of ticks simulated +final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1374338 # Simulator instruction rate (inst/s) -host_op_rate 1673035 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 26797569978 # Simulator tick rate (ticks/s) -host_mem_usage 615488 # Number of bytes of host memory used -host_seconds 103.89 # Real time elapsed on the host -sim_insts 142773109 # Number of instructions simulated -sim_ops 173803334 # Number of ops (including micro ops) simulated +host_inst_rate 1378466 # Simulator instruction rate (inst/s) +host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 26878113924 # Simulator tick rate (ticks/s) +host_mem_usage 614624 # Number of bytes of host memory used +host_seconds 103.57 # Real time elapsed on the host +sim_insts 142772879 # Number of instructions simulated +sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1210852 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1210788 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 10328292 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11540680 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1210852 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8837632 # Number of bytes written to this memory +system.physmem.bytes_read::total 11540616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8837568 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8855156 # Number of bytes written to this memory +system.physmem.bytes_written::total 8855092 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27373 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27372 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 161899 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189296 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138088 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189295 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138087 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142469 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142468 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 434953 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 434930 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.data 3710052 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4145557 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 434953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3174588 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145534 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174565 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3180883 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3174588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3180860 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174565 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 434953 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 434930 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3716347 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7326440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326394 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -119,9 +119,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7865 system.cpu.dtb.walker.walkRequestOrigin::total 17894 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 31526301 # DTB read hits +system.cpu.dtb.read_hits 31526223 # DTB read hits system.cpu.dtb.read_misses 8581 # DTB read misses -system.cpu.dtb.write_hits 23124463 # DTB write hits +system.cpu.dtb.write_hits 23124452 # DTB write hits system.cpu.dtb.write_misses 1448 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA @@ -132,12 +132,12 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 31534882 # DTB read accesses -system.cpu.dtb.write_accesses 23125911 # DTB write accesses +system.cpu.dtb.read_accesses 31534804 # DTB read accesses +system.cpu.dtb.write_accesses 23125900 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 54650764 # DTB hits +system.cpu.dtb.hits 54650675 # DTB hits system.cpu.dtb.misses 10029 # DTB misses -system.cpu.dtb.accesses 54660793 # DTB accesses +system.cpu.dtb.accesses 54660704 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -185,7 +185,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 147039592 # ITB inst hits +system.cpu.itb.inst_hits 147039346 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -202,37 +202,37 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 147044354 # ITB inst accesses -system.cpu.itb.hits 147039592 # DTB hits +system.cpu.itb.inst_accesses 147044108 # ITB inst accesses +system.cpu.itb.hits 147039346 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 147044354 # DTB accesses -system.cpu.numCycles 5567737414 # number of cpu cycles simulated +system.cpu.itb.accesses 147044108 # DTB accesses +system.cpu.numCycles 5567737188 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 142773109 # Number of instructions committed -system.cpu.committedOps 173803334 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 153162826 # Number of integer alu accesses +system.cpu.committedInsts 142772879 # Number of instructions committed +system.cpu.committedOps 173803124 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 153162683 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses -system.cpu.num_func_calls 16873879 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 18730390 # number of instructions that are conditional controls -system.cpu.num_int_insts 153162826 # number of integer instructions +system.cpu.num_func_calls 16873899 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 18730330 # number of instructions that are conditional controls +system.cpu.num_int_insts 153162683 # number of integer instructions system.cpu.num_fp_insts 11484 # number of float instructions -system.cpu.num_int_register_reads 285060124 # number of times the integer registers were read -system.cpu.num_int_register_writes 107179564 # number of times the integer registers were written +system.cpu.num_int_register_reads 285059803 # number of times the integer registers were read +system.cpu.num_int_register_writes 107179480 # number of times the integer registers were written system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 530854681 # number of times the CC registers were read -system.cpu.num_cc_register_writes 62364458 # number of times the CC registers were written -system.cpu.num_mem_refs 55939365 # number of memory refs -system.cpu.num_load_insts 31855962 # Number of load instructions -system.cpu.num_store_insts 24083403 # Number of store instructions -system.cpu.num_idle_cycles 5389653746.932553 # Number of idle cycles -system.cpu.num_busy_cycles 178083667.067447 # Number of busy cycles +system.cpu.num_cc_register_reads 530854003 # number of times the CC registers were read +system.cpu.num_cc_register_writes 62364299 # number of times the CC registers were written +system.cpu.num_mem_refs 55939276 # number of memory refs +system.cpu.num_load_insts 31855884 # Number of load instructions +system.cpu.num_store_insts 24083392 # Number of store instructions +system.cpu.num_idle_cycles 5389653746.932674 # Number of idle cycles +system.cpu.num_busy_cycles 178083441.067325 # Number of busy cycles system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles system.cpu.idle_fraction 0.968015 # Percentage of idle cycles -system.cpu.Branches 36397028 # Number of branches fetched +system.cpu.Branches 36396981 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 121152975 68.36% 68.36% # Class of executed instruction +system.cpu.op_class::IntAlu 121152838 68.36% 68.36% # Class of executed instruction system.cpu.op_class::IntMult 116892 0.07% 68.43% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction @@ -261,18 +261,18 @@ system.cpu.op_class::SimdFloatMisc 8569 0.00% 68.44% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction -system.cpu.op_class::MemRead 31855962 17.98% 86.41% # Class of executed instruction -system.cpu.op_class::MemWrite 24083403 13.59% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 31855884 17.98% 86.41% # Class of executed instruction +system.cpu.op_class::MemWrite 24083392 13.59% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 177220138 # Class of executed instruction +system.cpu.op_class::total 177219912 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 819403 # number of replacements +system.cpu.dcache.tags.replacements 819402 # number of replacements system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 53784550 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 65.597714 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 53784483 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 65.597713 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy @@ -282,24 +282,24 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 219237855 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 219237855 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 30129122 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 30129122 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 22340107 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 219237582 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 219237582 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 30129052 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 30129052 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 22340110 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits system.cpu.dcache.SoftPFReq_hits::cpu.data 395080 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 395080 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 457347 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 457347 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 460136 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 52469229 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 52469229 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 52864309 # number of overall hits -system.cpu.dcache.overall_hits::total 52864309 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 396277 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 396277 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 52469162 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 52469162 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 52864242 # number of overall hits +system.cpu.dcache.overall_hits::total 52864242 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 396276 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 396276 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 301678 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 301678 # number of WriteReq misses system.cpu.dcache.SoftPFReq_misses::cpu.data 116120 # number of SoftPFReq misses @@ -308,24 +308,24 @@ system.cpu.dcache.LoadLockedReq_misses::cpu.data 8612 system.cpu.dcache.LoadLockedReq_misses::total 8612 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 697955 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 697955 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 814075 # number of overall misses -system.cpu.dcache.overall_misses::total 814075 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 30525399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 22641785 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 697954 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 697954 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 814074 # number of overall misses +system.cpu.dcache.overall_misses::total 814074 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 30525328 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 22641788 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::cpu.data 511200 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 511200 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465959 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 460138 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 53167184 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 53678384 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 53678384 # number of overall (read+write) accesses +system.cpu.dcache.demand_accesses::cpu.data 53167116 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 53678316 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 53678316 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses @@ -348,14 +348,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 682060 # number of writebacks -system.cpu.dcache.writebacks::total 682060 # number of writebacks +system.cpu.dcache.writebacks::writebacks 682059 # number of writebacks +system.cpu.dcache.writebacks::total 682059 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1699220 # number of replacements +system.cpu.icache.tags.replacements 1699214 # number of replacements system.cpu.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145342961 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 145342721 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.663681 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy @@ -366,26 +366,26 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 77 system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 148742437 # Number of tag accesses -system.cpu.icache.tags.data_accesses 148742437 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145342961 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145342961 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145342961 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145342961 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145342961 # number of overall hits -system.cpu.icache.overall_hits::total 145342961 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1699738 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1699738 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1699738 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1699738 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1699738 # number of overall misses -system.cpu.icache.overall_misses::total 1699738 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 147042699 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 147042699 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 147042699 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses +system.cpu.icache.tags.tag_accesses 148742185 # Number of tag accesses +system.cpu.icache.tags.data_accesses 148742185 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 145342721 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 145342721 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 145342721 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 145342721 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 145342721 # number of overall hits +system.cpu.icache.overall_hits::total 145342721 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699732 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699732 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699732 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699732 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699732 # number of overall misses +system.cpu.icache.overall_misses::total 1699732 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 147042453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 147042453 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 147042453 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011559 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.011559 # miss rate for demand accesses @@ -401,17 +401,17 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 110027 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65155.309065 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2727894 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 175308 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 15.560579 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 110026 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65155.309107 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2727887 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 175307 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 15.560628 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 48893.397928 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 48893.401643 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 2.931998 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.004345 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.659727 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.315067 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9064.654943 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 7194.316179 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.746054 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy @@ -428,34 +428,34 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::3 10700 system.cpu.l2cache.tags.age_task_id_blocks_1024::4 50640 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.996033 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26204409 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26204409 # Number of data accesses +system.cpu.l2cache.tags.tag_accesses 26204344 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26204344 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7601 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3621 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1681362 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 505475 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2198059 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 682060 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 682060 # number of Writeback hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681357 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 505474 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2198053 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 682059 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 682059 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.cpu.l2cache.ReadExReq_hits::cpu.data 151058 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 151058 # number of ReadExReq hits system.cpu.l2cache.demand_hits::cpu.dtb.walker 7601 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::cpu.itb.walker 3621 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1681362 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 656533 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2349117 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681357 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 656532 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2349111 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.dtb.walker 7601 # number of overall hits system.cpu.l2cache.overall_hits::cpu.itb.walker 3621 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1681362 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 656533 # number of overall hits -system.cpu.l2cache.overall_hits::total 2349117 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681357 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 656532 # number of overall hits +system.cpu.l2cache.overall_hits::total 2349111 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 18358 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 18357 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 15534 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 33901 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 33900 # number of ReadReq misses system.cpu.l2cache.UpgradeReq_misses::cpu.data 2728 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses @@ -464,21 +464,21 @@ system.cpu.l2cache.ReadExReq_misses::cpu.data 147864 system.cpu.l2cache.ReadExReq_misses::total 147864 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 18358 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18357 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 163398 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 181765 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 181764 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 18358 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 18357 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 163398 # number of overall misses -system.cpu.l2cache.overall_misses::total 181765 # number of overall misses +system.cpu.l2cache.overall_misses::total 181764 # number of overall misses system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7608 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3623 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699720 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 521009 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2231960 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 682060 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 682060 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699714 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 521008 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2231953 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 682059 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 682059 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) @@ -487,19 +487,19 @@ system.cpu.l2cache.ReadExReq_accesses::cpu.data 298922 system.cpu.l2cache.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7608 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.itb.walker 3623 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1699720 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 819931 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2530882 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699714 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 819930 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530875 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7608 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.itb.walker 3623 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1699720 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 819931 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2530882 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699714 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 819930 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530875 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000920 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010801 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010800 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.029815 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015189 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015188 # miss rate for ReadReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses @@ -508,12 +508,12 @@ system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.494657 system.cpu.l2cache.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000920 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000552 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010801 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010800 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.199283 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.071819 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000920 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000552 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010801 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010800 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.199283 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.071819 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -524,51 +524,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 101898 # number of writebacks -system.cpu.l2cache.writebacks::total 101898 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 101897 # number of writebacks +system.cpu.l2cache.writebacks::total 101897 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2288556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2288556 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 682060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2288542 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 682059 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417520 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444702 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3417508 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2444657 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 37000 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917652 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310219 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5917595 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96310049 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205240399 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 36631 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3268666 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.105029 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3232202 98.88% 98.88% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3268666 # Request fanout histogram -system.iobus.trans_dist::ReadReq 30171 # Transaction distribution -system.iobus.trans_dist::ReadResp 30171 # Transaction distribution -system.iobus.trans_dist::WriteReq 59016 # Transaction distribution -system.iobus.trans_dist::WriteResp 22792 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram +system.iobus.trans_dist::ReadReq 30164 # Transaction distribution +system.iobus.trans_dist::ReadResp 30164 # Transaction distribution +system.iobus.trans_dist::WriteReq 59002 # Transaction distribution +system.iobus.trans_dist::WriteResp 22778 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -589,11 +587,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -614,17 +612,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -667,11 +665,11 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74235 # Transaction distribution -system.membus.trans_dist::ReadResp 74235 # Transaction distribution -system.membus.trans_dist::WriteReq 27560 # Transaction distribution -system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 138088 # Transaction distribution +system.membus.trans_dist::ReadReq 74227 # Transaction distribution +system.membus.trans_dist::ReadResp 74227 # Transaction distribution +system.membus.trans_dist::WriteReq 27546 # Transaction distribution +system.membus.trans_dist::WriteResp 27546 # Transaction distribution +system.membus.trans_dist::Writeback 138087 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -679,34 +677,34 @@ system.membus.trans_dist::SCUpgradeReq 2 # Tr system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606196 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498791 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606151 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 715314 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 715269 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096444 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259459 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259289 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22909315 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 359047 # Request fanout histogram +system.membus.snoop_fanout::samples 359045 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 359047 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 359047 # Request fanout histogram +system.membus.snoop_fanout::total 359045 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index 391769400..64a01b6e7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,160 +1,156 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.868319 # Number of seconds simulated -sim_ticks 2868318696500 # Number of ticks simulated -final_tick 2868318696500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.868581 # Number of seconds simulated +sim_ticks 2868581440500 # Number of ticks simulated +final_tick 2868581440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 534652 # Simulator instruction rate (inst/s) -host_op_rate 646675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11631340017 # Simulator tick rate (ticks/s) -host_mem_usage 586476 # Number of bytes of host memory used -host_seconds 246.60 # Real time elapsed on the host -sim_insts 131846562 # Number of instructions simulated -sim_ops 159471778 # Number of ops (including micro ops) simulated +host_inst_rate 717360 # Simulator instruction rate (inst/s) +host_op_rate 867708 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15647358559 # Simulator tick rate (ticks/s) +host_mem_usage 639748 # Number of bytes of host memory used +host_seconds 183.33 # Real time elapsed on the host +sim_insts 131511324 # Number of instructions simulated +sim_ops 159074269 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1173796 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1283584 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8628800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 156308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 605472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 378048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1161572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1227520 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8321088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 141140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 467936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 345792 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12227608 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1173796 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 156308 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1330104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8654400 # Number of bytes written to this memory +system.physmem.bytes_read::total 11666584 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1161572 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 141140 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1302712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8208384 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8672144 # Number of bytes written to this memory +system.physmem.bytes_written::total 8226128 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26794 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20582 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 134825 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9484 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5907 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26603 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19706 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130017 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 7335 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5403 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200214 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 135225 # Number of write requests responded to by this memory +system.physmem.num_reads::total 191448 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 128256 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139661 # Number of write requests responded to by this memory +system.physmem.num_writes::total 132692 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 409228 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 447504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3008313 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 54495 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 211090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 131801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 404929 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 427919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2900768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 163125 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 120545 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4262988 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 409228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 54495 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 463723 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3017238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4067022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 404929 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49202 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 454131 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2861478 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3023424 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3017238 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2867664 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2861478 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 409228 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 453676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3008313 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 54495 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 211103 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 131801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 404929 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 434091 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2900768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 163138 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 120545 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7286412 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200214 # Number of read requests accepted -system.physmem.writeReqs 175885 # Number of write requests accepted -system.physmem.readBursts 200214 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175885 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12804096 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 10892544 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12227608 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10990480 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5671 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13850 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12188 # Per bank write bursts -system.physmem.perBankRdBursts::1 12046 # Per bank write bursts -system.physmem.perBankRdBursts::2 12591 # Per bank write bursts -system.physmem.perBankRdBursts::3 12330 # Per bank write bursts -system.physmem.perBankRdBursts::4 20750 # Per bank write bursts -system.physmem.perBankRdBursts::5 12582 # Per bank write bursts -system.physmem.perBankRdBursts::6 12043 # Per bank write bursts -system.physmem.perBankRdBursts::7 12246 # Per bank write bursts -system.physmem.perBankRdBursts::8 12442 # Per bank write bursts -system.physmem.perBankRdBursts::9 12402 # Per bank write bursts -system.physmem.perBankRdBursts::10 11722 # Per bank write bursts -system.physmem.perBankRdBursts::11 11146 # Per bank write bursts -system.physmem.perBankRdBursts::12 11467 # Per bank write bursts -system.physmem.perBankRdBursts::13 11916 # Per bank write bursts -system.physmem.perBankRdBursts::14 10852 # Per bank write bursts -system.physmem.perBankRdBursts::15 11341 # Per bank write bursts -system.physmem.perBankWrBursts::0 10835 # Per bank write bursts -system.physmem.perBankWrBursts::1 11264 # Per bank write bursts -system.physmem.perBankWrBursts::2 11493 # Per bank write bursts -system.physmem.perBankWrBursts::3 10899 # Per bank write bursts -system.physmem.perBankWrBursts::4 10487 # Per bank write bursts -system.physmem.perBankWrBursts::5 11152 # Per bank write bursts -system.physmem.perBankWrBursts::6 11024 # Per bank write bursts -system.physmem.perBankWrBursts::7 10595 # Per bank write bursts -system.physmem.perBankWrBursts::8 10782 # Per bank write bursts -system.physmem.perBankWrBursts::9 10958 # Per bank write bursts -system.physmem.perBankWrBursts::10 10716 # Per bank write bursts -system.physmem.perBankWrBursts::11 10408 # Per bank write bursts -system.physmem.perBankWrBursts::12 10444 # Per bank write bursts -system.physmem.perBankWrBursts::13 9906 # Per bank write bursts -system.physmem.perBankWrBursts::14 9416 # Per bank write bursts -system.physmem.perBankWrBursts::15 9817 # Per bank write bursts +system.physmem.bw_total::total 6934686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 191448 # Number of read requests accepted +system.physmem.writeReqs 168916 # Number of write requests accepted +system.physmem.readBursts 191448 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 168916 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12244160 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue +system.physmem.bytesWritten 9286016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11666584 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10544464 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23799 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13043 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11402 # Per bank write bursts +system.physmem.perBankRdBursts::1 11523 # Per bank write bursts +system.physmem.perBankRdBursts::2 11617 # Per bank write bursts +system.physmem.perBankRdBursts::3 11771 # Per bank write bursts +system.physmem.perBankRdBursts::4 20348 # Per bank write bursts +system.physmem.perBankRdBursts::5 12097 # Per bank write bursts +system.physmem.perBankRdBursts::6 11123 # Per bank write bursts +system.physmem.perBankRdBursts::7 11241 # Per bank write bursts +system.physmem.perBankRdBursts::8 11419 # Per bank write bursts +system.physmem.perBankRdBursts::9 11532 # Per bank write bursts +system.physmem.perBankRdBursts::10 11480 # Per bank write bursts +system.physmem.perBankRdBursts::11 10715 # Per bank write bursts +system.physmem.perBankRdBursts::12 11252 # Per bank write bursts +system.physmem.perBankRdBursts::13 11225 # Per bank write bursts +system.physmem.perBankRdBursts::14 11052 # Per bank write bursts +system.physmem.perBankRdBursts::15 11518 # Per bank write bursts +system.physmem.perBankWrBursts::0 9249 # Per bank write bursts +system.physmem.perBankWrBursts::1 9496 # Per bank write bursts +system.physmem.perBankWrBursts::2 9535 # Per bank write bursts +system.physmem.perBankWrBursts::3 9435 # Per bank write bursts +system.physmem.perBankWrBursts::4 8870 # Per bank write bursts +system.physmem.perBankWrBursts::5 9467 # Per bank write bursts +system.physmem.perBankWrBursts::6 9116 # Per bank write bursts +system.physmem.perBankWrBursts::7 8737 # Per bank write bursts +system.physmem.perBankWrBursts::8 8796 # Per bank write bursts +system.physmem.perBankWrBursts::9 9230 # Per bank write bursts +system.physmem.perBankWrBursts::10 9164 # Per bank write bursts +system.physmem.perBankWrBursts::11 8822 # Per bank write bursts +system.physmem.perBankWrBursts::12 9029 # Per bank write bursts +system.physmem.perBankWrBursts::13 8642 # Per bank write bursts +system.physmem.perBankWrBursts::14 8756 # Per bank write bursts +system.physmem.perBankWrBursts::15 8750 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 2868318254500 # Total gap between requests +system.physmem.numWrRetry 83 # Number of times write queue was full causing retry +system.physmem.totGap 2868581033500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9742 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 190444 # Read request sizes (log2) +system.physmem.readPktSize::6 181678 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 171449 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 138850 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16077 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 10399 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7297 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 5697 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 4782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4036 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 88 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 52 # What read queue length does an incoming req see +system.physmem.writePktSize::6 164480 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 134188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 15248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 9686 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6807 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 5320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4456 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 3748 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 74 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 47 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -184,178 +180,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10239 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11771 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10810 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8741 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 533 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 391 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 65 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90415 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.086778 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 144.561031 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 323.181928 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46335 51.25% 51.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17813 19.70% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6067 6.71% 77.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3600 3.98% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2534 2.80% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 1.73% 86.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1031 1.14% 87.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 985 1.09% 88.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10482 11.59% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90415 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7120 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.098736 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 516.724228 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7117 99.96% 99.96% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7120 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7120 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.903933 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.122109 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.073987 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5764 80.96% 80.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 237 3.33% 84.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 43 0.60% 84.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 234 3.29% 88.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 121 1.70% 89.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 62 0.87% 90.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 31 0.44% 91.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 36 0.51% 91.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 117 1.64% 93.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 18 0.25% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 25 0.35% 93.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.22% 94.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 40 0.56% 94.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 10 0.14% 94.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 17 0.24% 95.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 28 0.39% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 58 0.81% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.20% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.10% 96.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 6 0.08% 96.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 88 1.24% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 12 0.17% 98.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 98.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.21% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 6 0.08% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 14 0.20% 98.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 9 0.13% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 35 0.49% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 6 0.08% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.11% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 2 0.03% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.04% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 8 0.11% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.04% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.04% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7120 # Writes before turning the bus around for reads -system.physmem.totQLat 4855930250 # Total ticks spent queuing -system.physmem.totMemAccLat 8607130250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1000320000 # Total ticks spent in databus transfers -system.physmem.avgQLat 24271.88 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2292 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5539 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8828 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7470 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10447 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7437 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1222 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1623 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1629 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1406 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 804 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 81717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 263.471640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 146.531290 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.110863 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 41089 50.28% 50.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16342 20.00% 70.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5746 7.03% 77.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3516 4.30% 81.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2447 2.99% 84.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1416 1.73% 86.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 997 1.22% 87.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 891 1.09% 88.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9273 11.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81717 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5972 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 32.034494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 599.214233 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5970 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5972 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5972 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.295713 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.853114 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 39.858214 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5595 93.69% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 97 1.62% 95.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 24 0.40% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 14 0.23% 95.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 35 0.59% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 43 0.72% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 25 0.42% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.20% 97.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 18 0.30% 98.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 5 0.08% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 30 0.50% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 15 0.25% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.12% 99.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.07% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.05% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.12% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 2 0.03% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 6 0.10% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 7 0.12% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5972 # Writes before turning the bus around for reads +system.physmem.totQLat 4538980935 # Total ticks spent queuing +system.physmem.totMemAccLat 8126137185 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 956575000 # Total ticks spent in databus transfers +system.physmem.avgQLat 23725.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 43021.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.46 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.80 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.26 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.83 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 42475.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.27 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.24 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.07 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.68 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.69 # Average write queue length when enqueuing -system.physmem.readRowHits 167229 # Number of row buffer hits during reads -system.physmem.writeRowHits 112615 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 66.16 # Row buffer hit rate for writes -system.physmem.avgGap 7626497.96 # Average gap between requests -system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 354707640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 193540875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 832845000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 568613520 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 84727272375 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1646666587500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1920687916830 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.622475 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2739235632500 # Time in different power states -system.physmem_0.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing +system.physmem.readRowHits 160412 # Number of row buffer hits during reads +system.physmem.writeRowHits 94279 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.85 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 64.97 # Row buffer hit rate for writes +system.physmem.avgGap 7960231.97 # Average gap between requests +system.physmem.pageHitRate 75.70 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 319183200 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 174157500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 788743800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 478904400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83526196590 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1647879002250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1920527828700 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.504870 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2741264066617 # Time in different power states +system.physmem_0.memoryStateTime::REF 95788160000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 33303656000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31529102383 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328829760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179421000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 727646400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 534256560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 187344349920 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83962556955 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1647337390500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1920414451095 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.527135 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2740355751000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95779320000 # Time in different power states +system.physmem_1.actEnergy 298597320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 162925125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 703505400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 461304720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82377359595 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1648886754000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1920252087120 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.408745 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2742945725805 # Time in different power states +system.physmem_1.memoryStateTime::REF 95788160000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32179536500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29845454195 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory @@ -411,57 +391,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 7749 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 7749 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1459 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6290 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 7749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 7749 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 7749 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 8363.375452 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7097.000757 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 5454.838397 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6203 97.61% 97.61% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 142 2.23% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.94% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 7634 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 7634 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1372 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 7634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 7634 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 7634 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6240 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9567.588141 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8440.173252 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 5686.595019 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6084 97.50% 97.50% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 143 2.29% 99.79% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 8 0.13% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6355 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 987959000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 987959000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 987959000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 4935 77.66% 77.66% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1420 22.34% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6355 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7749 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6240 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 4907 78.64% 78.64% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1333 21.36% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6240 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7634 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7749 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6355 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7634 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6240 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6355 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 14104 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6240 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 13874 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 19044092 # DTB read hits -system.cpu0.dtb.read_misses 6608 # DTB read misses -system.cpu0.dtb.write_hits 15688894 # DTB write hits -system.cpu0.dtb.write_misses 1141 # DTB write misses +system.cpu0.dtb.read_hits 25111402 # DTB read hits +system.cpu0.dtb.read_misses 6533 # DTB read misses +system.cpu0.dtb.write_hits 18719047 # DTB write hits +system.cpu0.dtb.write_misses 1101 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3442 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1734 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 1785 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 19050700 # DTB read accesses -system.cpu0.dtb.write_accesses 15690035 # DTB write accesses +system.cpu0.dtb.read_accesses 25117935 # DTB read accesses +system.cpu0.dtb.write_accesses 18720148 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 34732986 # DTB hits -system.cpu0.dtb.misses 7749 # DTB misses -system.cpu0.dtb.accesses 34740735 # DTB accesses +system.cpu0.dtb.hits 43830449 # DTB hits +system.cpu0.dtb.misses 7634 # DTB misses +system.cpu0.dtb.accesses 43838083 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -499,20 +480,20 @@ system.cpu0.itb.walker.walkWaitTime::samples 3348 system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 8781.732419 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 7396.194245 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5559.104899 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1469 62.99% 62.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 817 35.03% 98.03% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 4 0.17% 98.20% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.67% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9914.451115 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8640.132285 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5844.480359 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 848 36.36% 36.36% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1427 61.19% 97.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.68% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 51 2.19% 99.87% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 987617000 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 987617000 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 987617000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::samples 1120687000 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 1120687000 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 1120687000 # Table walker pending requests distribution system.cpu0.itb.walker.walkPageSizes::4K 2034 87.22% 87.22% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::1M 298 12.78% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2332 # Table walker page sizes translated @@ -523,7 +504,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 91510827 # ITB inst hits +system.cpu0.itb.inst_hits 118783416 # ITB inst hits system.cpu0.itb.inst_misses 3348 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -540,172 +521,172 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 91514175 # ITB inst accesses -system.cpu0.itb.hits 91510827 # DTB hits +system.cpu0.itb.inst_accesses 118786764 # ITB inst accesses +system.cpu0.itb.hits 118783416 # DTB hits system.cpu0.itb.misses 3348 # DTB misses -system.cpu0.itb.accesses 91514175 # DTB accesses -system.cpu0.numCycles 5736637393 # number of cpu cycles simulated +system.cpu0.itb.accesses 118786764 # DTB accesses +system.cpu0.numCycles 5737162881 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 89363678 # Number of instructions committed -system.cpu0.committedOps 107297883 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 94350928 # Number of integer alu accesses +system.cpu0.committedInsts 115118664 # Number of instructions committed +system.cpu0.committedOps 139117689 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 123147620 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses -system.cpu0.num_func_calls 6606472 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 12627044 # number of instructions that are conditional controls -system.cpu0.num_int_insts 94350928 # number of integer instructions +system.cpu0.num_func_calls 12673072 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 15652345 # number of instructions that are conditional controls +system.cpu0.num_int_insts 123147620 # number of integer instructions system.cpu0.num_fp_insts 9820 # number of float instructions -system.cpu0.num_int_register_reads 169124164 # number of times the integer registers were read -system.cpu0.num_int_register_writes 64348180 # number of times the integer registers were written +system.cpu0.num_int_register_reads 226729132 # number of times the integer registers were read +system.cpu0.num_int_register_writes 85574900 # number of times the integer registers were written system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 385798415 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 43074064 # number of times the CC registers were written -system.cpu0.num_mem_refs 35866705 # number of memory refs -system.cpu0.num_load_insts 19295047 # Number of load instructions -system.cpu0.num_store_insts 16571658 # Number of store instructions -system.cpu0.num_idle_cycles 5512519658.266078 # Number of idle cycles -system.cpu0.num_busy_cycles 224117734.733922 # Number of busy cycles -system.cpu0.not_idle_fraction 0.039068 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.960932 # Percentage of idle cycles -system.cpu0.Branches 19970568 # Number of branches fetched +system.cpu0.num_cc_register_reads 504016583 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 52146919 # number of times the CC registers were written +system.cpu0.num_mem_refs 44965604 # number of memory refs +system.cpu0.num_load_insts 25362826 # Number of load instructions +system.cpu0.num_store_insts 19602778 # Number of store instructions +system.cpu0.num_idle_cycles 5466015382.984095 # Number of idle cycles +system.cpu0.num_busy_cycles 271147498.015905 # Number of busy cycles +system.cpu0.not_idle_fraction 0.047262 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.952738 # Percentage of idle cycles +system.cpu0.Branches 29061799 # Number of branches fetched system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 73557669 67.15% 67.15% # Class of executed instruction -system.cpu0.op_class::IntMult 108302 0.10% 67.25% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.25% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 8177 0.01% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu0.op_class::MemRead 19295047 17.61% 84.87% # Class of executed instruction -system.cpu0.op_class::MemWrite 16571658 15.13% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 97796607 68.45% 68.45% # Class of executed instruction +system.cpu0.op_class::IntMult 109233 0.08% 68.52% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 8187 0.01% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction +system.cpu0.op_class::MemRead 25362826 17.75% 86.28% # Class of executed instruction +system.cpu0.op_class::MemWrite 19602778 13.72% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 109543126 # Class of executed instruction +system.cpu0.op_class::total 142881904 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 690539 # number of replacements -system.cpu0.dcache.tags.tagsinuse 487.185772 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 33864824 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 691051 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 49.004812 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 1015908000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 487.185772 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.951535 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.951535 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 688886 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.817079 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 42962889 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 689398 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 62.319428 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 1149671500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.817079 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966440 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.966440 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 126 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 70103571 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 70103571 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 17785791 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 17785791 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14958877 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14958877 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318525 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 318525 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364927 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 364927 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361705 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361705 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 32744668 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 32744668 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 33063193 # number of overall hits -system.cpu0.dcache.overall_hits::total 33063193 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 394905 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 394905 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 324481 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 324481 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127732 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 127732 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21710 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21710 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20007 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20007 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 719386 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 719386 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 847118 # number of overall misses -system.cpu0.dcache.overall_misses::total 847118 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4990872752 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4990872752 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4944330313 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4944330313 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 327573000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 327573000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 444426745 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 444426745 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1572500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1572500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 9935203065 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 9935203065 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 9935203065 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 9935203065 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 18180696 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 18180696 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 15283358 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 15283358 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446257 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 446257 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386637 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386637 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381712 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381712 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 33464054 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 33464054 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 33910311 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 33910311 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.021721 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.021721 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.021231 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.021231 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.286230 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.286230 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056151 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052414 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052414 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.021497 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.021497 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.024981 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.024981 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12638.160449 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12638.160449 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15237.657407 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15237.657407 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15088.576693 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15088.576693 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22213.562503 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22213.562503 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 88293922 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 88293922 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 23854264 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 23854264 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 17989541 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 17989541 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318725 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 318725 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364533 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 364533 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361797 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361797 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 41843805 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 41843805 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 42162530 # number of overall hits +system.cpu0.dcache.overall_hits::total 42162530 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 393288 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 393288 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 323540 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 323540 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127427 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 127427 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21927 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21927 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19722 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 19722 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 716828 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 716828 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 844255 # number of overall misses +system.cpu0.dcache.overall_misses::total 844255 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5012719236 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5012719236 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 5098069375 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 5098069375 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332035250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 332035250 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 435652050 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 435652050 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1835500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1835500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 10110788611 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 10110788611 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 10110788611 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 10110788611 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 24247552 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 24247552 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 18313081 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 18313081 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446152 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 446152 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386460 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386460 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 42560633 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 42560633 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 43006785 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 43006785 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016220 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.016220 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017667 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017667 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285613 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285613 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056738 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056738 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051693 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051693 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016843 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.016843 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019631 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.019631 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12745.670440 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12745.670440 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15757.153289 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15757.153289 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15142.757787 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15142.757787 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22089.648616 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22089.648616 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13810.670579 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13810.670579 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11728.239826 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 11728.239826 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14104.901889 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14104.901889 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11975.989021 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 11975.989021 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -714,82 +695,82 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 504116 # number of writebacks -system.cpu0.dcache.writebacks::total 504116 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25128 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 25128 # number of ReadReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15248 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15248 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 25128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 25128 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 25128 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 25128 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 369777 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 369777 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 324481 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 324481 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100470 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 100470 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6462 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20007 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20007 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 694258 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 694258 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 794728 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 794728 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3859056498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3859056498 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4283066685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4283066685 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1502769500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1502769500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90797250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90797250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 403751255 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 403751255 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1480500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8142123183 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 8142123183 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9644892683 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9644892683 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5991645999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5991645999 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4628507500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4628507500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10620153499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10620153499 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.020339 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.020339 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021231 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.021231 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225139 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016713 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016713 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052414 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052414 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.020746 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.020746 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.023436 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.023436 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10436.172336 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10436.172336 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 13199.745702 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13199.745702 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 14957.395242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14957.395242 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14050.951718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14050.951718 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20180.499575 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20180.499575 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 504121 # number of writebacks +system.cpu0.dcache.writebacks::total 504121 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 25265 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 25265 # number of ReadReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15169 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15169 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 25265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 25265 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 25265 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 25265 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368023 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 368023 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323540 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323540 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 100320 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 100320 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6758 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19722 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 19722 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 691563 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 691563 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 791883 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 791883 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4066612315 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4066612315 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4601719625 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4601719625 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1548565203 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1548565203 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97840500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97840500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 405700950 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 405700950 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1754500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1754500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8668331940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8668331940 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10216897143 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10216897143 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6181726750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6181726750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4820424000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4820424000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11002150750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11002150750 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015178 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017667 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224856 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224856 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017487 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051693 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051693 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.016249 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.018413 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.018413 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11049.886325 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11049.886325 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14223.031542 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14223.031542 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15436.256011 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15436.256011 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14477.730098 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14477.730098 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20570.984180 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20570.984180 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11727.806065 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11727.806065 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12136.092705 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12136.092705 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 12534.406757 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 12534.406757 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 12902.028637 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 12902.028637 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -797,58 +778,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1099798 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.479276 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 90410508 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1100310 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 82.168214 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 13323414750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.479276 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998983 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998983 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1101309 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.453846 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 117681586 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1101821 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 106.806447 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 13496302250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.453846 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998933 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998933 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 215 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 184121973 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 184121973 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 90410508 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 90410508 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 90410508 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 90410508 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 90410508 # number of overall hits -system.cpu0.icache.overall_hits::total 90410508 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1100319 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1100319 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1100319 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1100319 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1100319 # number of overall misses -system.cpu0.icache.overall_misses::total 1100319 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10739818993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 10739818993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 10739818993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 10739818993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 10739818993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 10739818993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 91510827 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 91510827 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 91510827 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 91510827 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 91510827 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 91510827 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012024 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.012024 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012024 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.012024 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012024 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.012024 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9760.641226 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9760.641226 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9760.641226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9760.641226 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9760.641226 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 238668662 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 238668662 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 117681586 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 117681586 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 117681586 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 117681586 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 117681586 # number of overall hits +system.cpu0.icache.overall_hits::total 117681586 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1101830 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1101830 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1101830 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1101830 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1101830 # number of overall misses +system.cpu0.icache.overall_misses::total 1101830 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 10869872254 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 10869872254 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 10869872254 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 10869872254 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 10869872254 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 10869872254 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 118783416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 118783416 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 118783416 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 118783416 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 118783416 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 118783416 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.009276 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.009276 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.009276 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.009276 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.009276 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9865.289794 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9865.289794 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9865.289794 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9865.289794 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9865.289794 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -857,223 +838,224 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1100319 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1100319 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1100319 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1100319 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1100319 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1100319 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9082830507 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 9082830507 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9082830507 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 9082830507 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9082830507 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 9082830507 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 719096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 719096500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 719096500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012024 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.012024 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.012024 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.012024 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8254.724773 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8254.724773 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8254.724773 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1101830 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1101830 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1101830 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1101830 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1101830 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1101830 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9761619746 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 9761619746 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9761619746 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 9761619746 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9761619746 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 9761619746 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 802157500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 802157500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 802157500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 802157500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009276 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009276 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009276 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8859.460848 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8859.460848 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 8859.460848 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1853283 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1853292 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1839936 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1839962 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 22 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 238164 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 268426 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16093.899190 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1968322 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 284663 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.914569 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 237006 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 267761 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16103.938258 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1970214 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 284001 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.937349 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7921.036071 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 2.357121 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.109776 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4473.771805 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1953.197848 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1743.426570 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.483462 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000144 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.273057 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.119214 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.106410 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982294 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1127 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15106 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 288 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 7915.761025 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 0.539297 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.155291 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4574.741605 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1897.934094 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1714.806946 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.483140 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000033 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000009 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.279220 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.115841 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.104664 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.982906 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1117 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15115 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 13 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 261 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 418 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 412 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 118 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 425 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3213 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7809 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3908 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068787 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921997 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 39654154 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 39654154 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 7774 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3610 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1053168 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 381762 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1446314 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 504114 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 504114 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28406 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28406 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1700 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1700 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 227802 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 227802 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 7774 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3610 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1053168 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 609564 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1674116 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 7774 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3610 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1053168 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 609564 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1674116 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 215 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 122 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47151 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 94947 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 142435 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26586 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 26586 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18299 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 18299 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 41687 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 41687 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 215 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 122 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 47151 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 136634 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 184122 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 215 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 122 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 47151 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 136634 # number of overall misses -system.cpu0.l2cache.overall_misses::total 184122 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 4899750 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2713500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2213649997 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2684439955 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 4905703202 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 458226521 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 458226521 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 356750783 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 356750783 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1434495 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1434495 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1789174823 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1789174823 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 4899750 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2713500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2213649997 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 4473614778 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 6694878025 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 4899750 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2713500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2213649997 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 4473614778 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 6694878025 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 7989 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3732 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1100319 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 476709 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1588749 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 504114 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 504114 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54992 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 54992 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19999 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 19999 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269489 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269489 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 7989 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3732 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1100319 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 746198 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1858238 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 7989 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3732 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1100319 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 746198 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1858238 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.032690 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042852 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.199172 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.089652 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.483452 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.483452 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.914996 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.914996 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8038 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3680 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.068176 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.922546 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 39636813 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 39636813 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 8046 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 3668 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1054676 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 380878 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 1447268 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 504119 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 504119 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28198 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28198 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1754 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1754 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 225223 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 225223 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 8046 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 3668 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1054676 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 606101 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1672491 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 8046 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 3668 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1054676 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 606101 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1672491 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 223 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 133 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 47154 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 94223 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 141733 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26109 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 26109 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 17961 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 17961 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 7 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44010 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 44010 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 223 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 133 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 47154 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 138233 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 185743 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 223 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 133 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 47154 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 138233 # number of overall misses +system.cpu0.l2cache.overall_misses::total 185743 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 5218750 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3033000 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2351090746 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2761351258 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 5120693754 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 483042430 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 483042430 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 364663752 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 364663752 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1698997 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1698997 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 1948619833 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1948619833 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 5218750 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3033000 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2351090746 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4709971091 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7069313587 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 5218750 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3033000 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2351090746 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4709971091 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7069313587 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 8269 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 3801 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1101830 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 475101 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 1589001 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 504119 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 504119 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 54307 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 54307 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19715 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 19715 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 7 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269233 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269233 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 8269 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 3801 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1101830 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 744334 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 1858234 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 8269 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 3801 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1101830 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 744334 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1858234 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.034991 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.042796 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.198322 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.089196 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.480767 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.480767 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.911032 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.911032 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.154689 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.154689 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.032690 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042852 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.183107 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.099084 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026912 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.032690 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042852 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.183107 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.099084 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22241.803279 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 46948.102840 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28273.036062 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 34441.697630 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17235.632325 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17235.632325 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19495.643642 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19495.643642 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 179311.875000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 179311.875000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 42919.251157 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 42919.251157 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 36361.097669 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 22789.534884 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22241.803279 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 46948.102840 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 32741.592708 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 36361.097669 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.163464 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.163464 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.034991 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.042796 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.185714 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.099957 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026968 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.034991 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.042796 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.185714 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.099957 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22804.511278 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49859.836833 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 29306.552094 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 36129.156611 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18500.993144 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18500.993144 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20303.087356 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20303.087356 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 242713.857143 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 242713.857143 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 44276.751488 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 44276.751488 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22804.511278 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49859.836833 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34072.696758 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 38059.650092 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 23402.466368 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22804.511278 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49859.836833 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34072.696758 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 38059.650092 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1082,128 +1064,128 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 196247 # number of writebacks -system.cpu0.l2cache.writebacks::total 196247 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 195381 # number of writebacks +system.cpu0.l2cache.writebacks::total 195381 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 32 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1210 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 1210 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1242 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 1242 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1242 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 1242 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 215 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 122 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47151 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94915 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 142403 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 246323 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26586 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26586 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18299 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18299 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40477 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 40477 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 215 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 122 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47151 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 135392 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 182880 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 215 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 122 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47151 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 135392 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 246323 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 429203 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1859500 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 1877090003 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2013208709 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 3895552462 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13906201830 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 448274629 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 448274629 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 246009723 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 246009723 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1112495 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1112495 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1381066645 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1381066645 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1859500 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 1877090003 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3394275354 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 5276619107 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3394250 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1859500 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 1877090003 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3394275354 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13906201830 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 19182820937 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 647209500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5743013251 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6390222751 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4419325000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4419325000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 647209500 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10162338251 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10809547751 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.199105 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089632 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 1212 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 1212 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 1244 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 1244 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 1244 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 1244 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 223 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 133 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 47154 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 94191 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 141701 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 243995 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 243995 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26109 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26109 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 17961 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17961 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 7 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 42798 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 42798 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 223 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 133 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 47154 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 136989 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 184499 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 223 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 133 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 47154 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 136989 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 243995 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 428494 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2168500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2038167254 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2142124308 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4186228812 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13497828640 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 13497828640 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 512289208 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 512289208 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 258190050 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 258190050 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1347997 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1347997 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1547245660 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1547245660 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2168500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2038167254 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3689369968 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5733474472 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 3768750 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2168500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2038167254 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3689369968 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13497828640 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 19231303112 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 730253500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5927208500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6657462000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4606674000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4606674000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 730253500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10533882500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11264136000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.198255 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.089176 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.483452 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.483452 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.914996 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.914996 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.480767 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.480767 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911032 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911032 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150199 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150199 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.098416 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026912 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.032690 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042852 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.181442 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158963 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158963 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.099287 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230973 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 21210.648570 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27355.831422 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 56455.149661 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16861.304032 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16861.304032 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13443.888901 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13443.888901 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 139061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 139061.875000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 34119.787657 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 34119.787657 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28852.904128 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 15787.209302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15241.803279 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39810.184365 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 25069.984593 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 56455.149661 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44694.051386 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.230592 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22742.345957 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29542.690680 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55320.103445 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19621.173082 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19621.173082 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14375.037581 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14375.037581 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 192571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192571 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36152.288892 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36152.288892 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31075.910829 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44881.149122 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1213,57 +1195,55 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1737767 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1686227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 27891 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 27891 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 504114 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 316054 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 89164 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112407 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 298764 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 285064 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2218682 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2366147 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10130 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22028 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4616987 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70456504 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84324454 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14928 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31956 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 154827842 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 648932 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2984532 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.180419 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.384536 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1733379 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1686259 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28500 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28500 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 504119 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 307885 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 88136 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42217 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 111625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297195 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284749 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2221704 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2362865 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10199 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22165 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 4616933 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70553208 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84179104 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 15204 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 33076 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 154780592 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 633519 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2968459 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.176473 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.381222 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 2446067 81.96% 81.96% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 538465 18.04% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 2444606 82.35% 82.35% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 523853 17.65% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2984532 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1775358935 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 2968459 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1775328997 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115165999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114507000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1664866493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1667097754 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1209535062 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1206509407 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 14039749 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 13896250 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1294,59 +1274,62 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 3332 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 3332 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 642 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2690 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 3332 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 3332 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 3332 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 8324.355972 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7260.502547 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 4990.324891 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 2067 80.68% 80.68% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 375 14.64% 95.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.42% 97.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 50 1.95% 99.69% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 4 0.16% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.12% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::81920-90111 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2562 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1455144968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1455144968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1455144968 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1928 75.25% 75.25% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 634 24.75% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2562 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3332 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 3283 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 3283 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 611 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2672 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 3283 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 3283 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 3283 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2513 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9027.258257 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8086.769918 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 4736.776885 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-4095 485 19.30% 19.30% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-8191 533 21.21% 40.51% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1045 41.58% 82.09% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-16383 324 12.89% 94.99% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-20479 44 1.75% 96.74% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::20480-24575 19 0.76% 97.49% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-28671 51 2.03% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::28672-32767 8 0.32% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2513 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1651557968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1651557968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1651557968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1910 76.00% 76.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 603 24.00% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2513 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3283 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3332 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2562 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3283 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2513 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2562 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 5894 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2513 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 5796 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 10115566 # DTB read hits -system.cpu1.dtb.read_misses 2828 # DTB read misses -system.cpu1.dtb.write_hits 6544640 # DTB write hits -system.cpu1.dtb.write_misses 504 # DTB write misses +system.cpu1.dtb.read_hits 3974119 # DTB read hits +system.cpu1.dtb.read_misses 2776 # DTB read misses +system.cpu1.dtb.write_hits 3444686 # DTB write hits +system.cpu1.dtb.write_misses 507 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2029 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 346 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 362 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 10118394 # DTB read accesses -system.cpu1.dtb.write_accesses 6545144 # DTB write accesses +system.cpu1.dtb.read_accesses 3976895 # DTB read accesses +system.cpu1.dtb.write_accesses 3445193 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 16660206 # DTB hits -system.cpu1.dtb.misses 3332 # DTB misses -system.cpu1.dtb.accesses 16663538 # DTB accesses +system.cpu1.dtb.hits 7418805 # DTB hits +system.cpu1.dtb.misses 3283 # DTB misses +system.cpu1.dtb.accesses 7422088 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1376,42 +1359,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1746 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1746 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 168 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1578 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1746 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1746 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 8955.736224 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 7685.889357 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5645.921496 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 191 17.25% 17.25% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 643 58.08% 75.34% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 217 19.60% 94.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.03% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 95.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 27 2.44% 97.74% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.72% 99.46% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1107 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1454651968 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1454651968 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1454651968 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 939 84.82% 84.82% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 168 15.18% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1107 # Table walker page sizes translated +system.cpu1.itb.walker.walks 1740 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1740 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 164 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1576 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1740 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9655.767484 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 8490.755174 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5670.300287 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 219 19.89% 19.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 163 14.80% 34.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 463 42.05% 76.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.28% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.37% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 25 2.27% 97.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.91% 99.55% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1651010968 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1651010968 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1651010968 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1746 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1746 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1740 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1740 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1107 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2853 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 44359905 # ITB inst hits -system.cpu1.itb.inst_misses 1746 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 16749094 # ITB inst hits +system.cpu1.itb.inst_misses 1740 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1420,178 +1404,178 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1148 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1142 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 44361651 # ITB inst accesses -system.cpu1.itb.hits 44359905 # DTB hits -system.cpu1.itb.misses 1746 # DTB misses -system.cpu1.itb.accesses 44361651 # DTB accesses -system.cpu1.numCycles 5735725430 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 16750834 # ITB inst accesses +system.cpu1.itb.hits 16749094 # DTB hits +system.cpu1.itb.misses 1740 # DTB misses +system.cpu1.itb.accesses 16750834 # DTB accesses +system.cpu1.numCycles 5736248293 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 42482884 # Number of instructions committed -system.cpu1.committedOps 52173895 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 47161467 # Number of integer alu accesses +system.cpu1.committedInsts 16392660 # Number of instructions committed +system.cpu1.committedOps 19956580 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 17976734 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses -system.cpu1.num_func_calls 7121857 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 4915281 # number of instructions that are conditional controls -system.cpu1.num_int_insts 47161467 # number of integer instructions +system.cpu1.num_func_calls 1033061 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1853914 # number of instructions that are conditional controls +system.cpu1.num_int_insts 17976734 # number of integer instructions system.cpu1.num_fp_insts 1857 # number of float instructions -system.cpu1.num_int_register_reads 90906541 # number of times the integer registers were read -system.cpu1.num_int_register_writes 34070734 # number of times the integer registers were written +system.cpu1.num_int_register_reads 32611379 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12600410 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 192636366 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 15749934 # number of times the CC registers were written -system.cpu1.num_mem_refs 16924073 # number of memory refs -system.cpu1.num_load_insts 10229886 # Number of load instructions -system.cpu1.num_store_insts 6694187 # Number of store instructions -system.cpu1.num_idle_cycles 5637554126.704413 # Number of idle cycles -system.cpu1.num_busy_cycles 98171303.295587 # Number of busy cycles -system.cpu1.not_idle_fraction 0.017116 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.982884 # Percentage of idle cycles -system.cpu1.Branches 12116511 # Number of branches fetched +system.cpu1.num_cc_register_reads 72918750 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 6543930 # number of times the CC registers were written +system.cpu1.num_mem_refs 7653523 # number of memory refs +system.cpu1.num_load_insts 4085696 # Number of load instructions +system.cpu1.num_store_insts 3567827 # Number of store instructions +system.cpu1.num_idle_cycles 5685220667.433728 # Number of idle cycles +system.cpu1.num_busy_cycles 51027625.566272 # Number of busy cycles +system.cpu1.not_idle_fraction 0.008896 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.991104 # Percentage of idle cycles +system.cpu1.Branches 2968133 # Number of branches fetched system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 37117349 68.64% 68.64% # Class of executed instruction -system.cpu1.op_class::IntMult 29132 0.05% 68.70% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 3361 0.01% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.70% # Class of executed instruction -system.cpu1.op_class::MemRead 10229886 18.92% 87.62% # Class of executed instruction -system.cpu1.op_class::MemWrite 6694187 12.38% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 12626391 62.17% 62.17% # Class of executed instruction +system.cpu1.op_class::IntMult 25909 0.13% 62.30% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 3321 0.02% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction +system.cpu1.op_class::MemRead 4085696 20.12% 82.43% # Class of executed instruction +system.cpu1.op_class::MemWrite 3567827 17.57% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 54073981 # Class of executed instruction +system.cpu1.op_class::total 20309210 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2789 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 191058 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.360308 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 16390617 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 191421 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 85.626013 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 104654883500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.360308 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922579 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922579 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 363 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 312 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.708984 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 33541448 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 33541448 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 9797337 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 9797337 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6353174 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6353174 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49731 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 49731 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79655 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 79655 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71640 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71640 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 16150511 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 16150511 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 16200242 # number of overall hits -system.cpu1.dcache.overall_hits::total 16200242 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 137366 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 137366 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 93147 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 93147 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30426 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30426 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17223 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17223 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23379 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23379 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 230513 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 230513 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 260939 # number of overall misses -system.cpu1.dcache.overall_misses::total 260939 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1997360003 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 1997360003 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2352005341 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2352005341 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 320800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 320800000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539390293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 539390293 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1691000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1691000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4349365344 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4349365344 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4349365344 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4349365344 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9934703 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9934703 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6446321 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6446321 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80157 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 80157 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96878 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96878 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95019 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95019 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 16381024 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 16381024 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 16461181 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 16461181 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013827 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013827 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.014450 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.014450 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.379580 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.379580 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177780 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177780 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246046 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246046 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014072 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.014072 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.015852 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.015852 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14540.424872 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14540.424872 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25250.467981 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25250.467981 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18626.255588 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18626.255588 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23071.572480 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23071.572480 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2726 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 187627 # number of replacements +system.cpu1.dcache.tags.tagsinuse 465.215072 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 7146939 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187994 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.016846 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104853894000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.215072 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.908623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.908623 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 52 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 15057330 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15057330 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3659340 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3659340 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3255921 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3255921 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49714 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 49714 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79782 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 79782 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71812 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 71812 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6915261 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6915261 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6964975 # number of overall hits +system.cpu1.dcache.overall_hits::total 6964975 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 134401 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 134401 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 90853 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 90853 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30496 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30496 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17326 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23466 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23466 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 225254 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 225254 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 255750 # number of overall misses +system.cpu1.dcache.overall_misses::total 255750 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1931922000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1931922000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2253615359 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2253615359 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317972750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 317972750 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 552026738 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 552026738 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2980000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2980000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4185537359 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4185537359 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4185537359 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4185537359 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3793741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3793741 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3346774 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3346774 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 80210 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 80210 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97108 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 97108 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95278 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 95278 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7140515 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7140515 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7220725 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7220725 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035427 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.035427 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027146 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027146 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380202 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380202 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.178420 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178420 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.246290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.246290 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031546 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.031546 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035419 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.035419 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14374.312691 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14374.312691 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24805.073679 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24805.073679 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18352.346185 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18352.346185 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23524.534987 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23524.534987 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18868.199815 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18868.199815 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16668.130651 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16668.130651 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18581.411913 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18581.411913 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16365.737474 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16365.737474 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1600,82 +1584,82 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 118649 # number of writebacks -system.cpu1.dcache.writebacks::total 118649 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 239 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 239 # number of ReadReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12076 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12076 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 239 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 239 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 239 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 239 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 137127 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 137127 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93147 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 93147 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29658 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29658 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5147 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23379 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23379 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 230274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 230274 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 259932 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 259932 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1715737747 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1715737747 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2159697659 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2159697659 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 467259500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 467259500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82226250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82226250 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491497707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491497707 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1621000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1621000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3875435406 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3875435406 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4342694906 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4342694906 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 525084500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 525084500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 379956000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 379956000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 905040500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 905040500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013803 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013803 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014450 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369999 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369999 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053129 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053129 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246046 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246046 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014057 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.014057 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015791 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.015791 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.034443 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.034443 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23185.906782 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23185.906782 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15754.922786 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15754.922786 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15975.568292 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15975.568292 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21023.042346 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21023.042346 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 117066 # number of writebacks +system.cpu1.dcache.writebacks::total 117066 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 249 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12071 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12071 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 249 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 249 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 249 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134152 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 134152 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90853 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 90853 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29793 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29793 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5255 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5255 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23466 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23466 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 225005 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 225005 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 254798 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 254798 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724213250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724213250 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2112235141 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2112235141 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 459472252 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 459472252 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82571000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82571000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 515647762 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 515647762 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2900500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2900500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3836448391 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3836448391 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4295920643 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4295920643 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406973750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406973750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 280407500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 280407500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 687381250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 687381250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035361 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027146 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.371437 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.371437 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054115 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246290 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246290 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031511 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031511 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035287 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035287 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12852.683896 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12852.683896 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23248.931142 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23248.931142 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.154600 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15422.154600 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15712.844910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15712.844910 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21974.250490 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21974.250490 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16829.669898 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16829.669898 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16707.042250 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16707.042250 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17050.502838 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17050.502838 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16860.103466 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16860.103466 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1683,58 +1667,58 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 526723 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.608741 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 43832665 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 527235 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 83.136865 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 84507534000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.608741 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973845 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973845 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 506368 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.574535 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 16242209 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 506880 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 32.043499 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 84702777500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.574535 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973778 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973778 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 387 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 122 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 89247035 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 89247035 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 43832665 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 43832665 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 43832665 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 43832665 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 43832665 # number of overall hits -system.cpu1.icache.overall_hits::total 43832665 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 527235 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 527235 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 527235 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 527235 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 527235 # number of overall misses -system.cpu1.icache.overall_misses::total 527235 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4617960760 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 4617960760 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 4617960760 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 4617960760 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 4617960760 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 4617960760 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 44359900 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 44359900 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 44359900 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 44359900 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 44359900 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 44359900 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011885 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011885 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011885 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011885 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011885 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011885 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8758.828151 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8758.828151 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8758.828151 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8758.828151 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8758.828151 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 34005058 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 34005058 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 16242209 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16242209 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16242209 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16242209 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16242209 # number of overall hits +system.cpu1.icache.overall_hits::total 16242209 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 506880 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 506880 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 506880 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 506880 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 506880 # number of overall misses +system.cpu1.icache.overall_misses::total 506880 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4441098014 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 4441098014 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 4441098014 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 4441098014 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 4441098014 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 4441098014 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16749089 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16749089 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16749089 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16749089 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16749089 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16749089 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030263 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.030263 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030263 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.030263 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030263 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.030263 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8761.635918 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8761.635918 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8761.635918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8761.635918 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1743,219 +1727,220 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 527235 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 527235 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 527235 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 527235 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 527235 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 527235 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3826248740 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 3826248740 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3826248740 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 3826248740 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3826248740 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 3826248740 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 13994500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 13994500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 13994500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 13994500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011885 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011885 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011885 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011885 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7257.197910 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7257.197910 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 7257.197910 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 506880 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 506880 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 506880 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 506880 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 506880 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 506880 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 3933409986 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933409986 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933409986 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 3933409986 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3933409986 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 3933409986 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15446750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15446750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15446750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 15446750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030263 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.030263 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.030263 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7760.041797 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 199846 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 199846 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 194594 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 194618 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59474 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 47689 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15083.724459 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 731618 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 62301 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.743279 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 58318 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 39568 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14853.795199 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 710508 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 54174 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 13.115295 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 8757.920968 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.140482 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.100736 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3269.623984 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2111.182929 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 939.755359 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.534541 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000128 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.199562 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.128856 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.057358 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.920637 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1198 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 23 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13391 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 29 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1169 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 8945.748297 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.024093 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.068283 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3300.044649 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1917.167815 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 684.742061 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.546005 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000246 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000126 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.201419 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.117015 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.041793 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.906604 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1123 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13469 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 10 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 38 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 1075 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1514 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11595 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.073120 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001404 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.817322 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 15244499 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 15244499 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3091 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1729 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 513133 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 102720 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 620673 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 118649 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 118649 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1485 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1485 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 867 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 867 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 28139 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 28139 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3091 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1729 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 513133 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 130859 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 648812 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3091 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1729 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 513133 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 130859 # number of overall hits -system.cpu1.l2cache.overall_hits::total 648812 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 321 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 14102 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 69212 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 83911 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28339 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28339 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22509 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22509 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35184 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35184 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 321 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 14102 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 104396 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 119095 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 321 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 14102 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 104396 # number of overall misses -system.cpu1.l2cache.overall_misses::total 119095 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6369000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5421000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 483830740 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1476489366 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1972110106 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 522569379 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 522569379 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 435248439 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 435248439 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1586000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1586000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1289152696 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1289152696 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6369000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5421000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 483830740 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 2765642062 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3261262802 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6369000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5421000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 483830740 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 2765642062 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3261262802 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3412 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2005 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 527235 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171932 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 704584 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 118649 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 118649 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29824 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29824 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23376 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23376 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63323 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 63323 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3412 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2005 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 527235 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 235255 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 767907 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3412 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2005 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 527235 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 235255 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 767907 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.137656 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026747 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.402554 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.119093 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.950208 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.950208 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962911 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962911 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1497 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11681 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.068542 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.822083 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 14802624 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 14802624 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 2949 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1668 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 493694 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 102403 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 600714 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 117066 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 117066 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1062 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1062 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 911 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 911 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27911 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27911 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 2949 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1668 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 493694 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 130314 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 628625 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 2949 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1668 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 493694 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 130314 # number of overall hits +system.cpu1.l2cache.overall_hits::total 628625 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 319 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 267 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13186 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 66797 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 80569 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 27938 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 27938 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22546 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22546 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 33942 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 33942 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 319 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 267 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 13186 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 100739 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 114511 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 319 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 267 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 13186 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 100739 # number of overall misses +system.cpu1.l2cache.overall_misses::total 114511 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 6370500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5365500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 469517986 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1430715000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1911968986 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 536455892 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 536455892 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 454234073 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 454234073 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2847500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2847500 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1211409437 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1211409437 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 6370500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5365500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 469517986 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2642124437 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 3123378423 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 6370500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5365500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 469517986 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2642124437 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 3123378423 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 3268 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 1935 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 506880 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 169200 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 681283 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 117066 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 117066 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29000 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29000 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23457 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23457 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 61853 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 61853 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 3268 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 1935 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 506880 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 231053 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 743136 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 3268 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 1935 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 506880 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 231053 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 743136 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.137984 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.026014 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.394781 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.118261 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.963379 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.963379 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.961163 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.961163 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.555627 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.555627 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.137656 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026747 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.443757 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.155090 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.094080 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.137656 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026747 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.443757 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.155090 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19641.304348 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 34309.370302 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21332.852193 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23502.402617 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18439.937154 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18439.937154 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19336.640411 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19336.640411 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 528666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 528666.666667 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 36640.310823 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 36640.310823 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 27383.708821 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19841.121495 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19641.304348 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 34309.370302 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26491.839362 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 27383.708821 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.548753 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.548753 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.137984 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.026014 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.436000 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.154092 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.097613 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.137984 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.026014 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.436000 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.154092 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20095.505618 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 35607.309722 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21418.851146 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23730.826819 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19201.656955 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19201.656955 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20146.991617 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20146.991617 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 316388.888889 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 316388.888889 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 35690.573243 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35690.573243 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20095.505618 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 35607.309722 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 26227.423709 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 27275.793793 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 19970.219436 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20095.505618 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 35607.309722 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 26227.423709 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 27275.793793 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1964,126 +1949,126 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 31472 # number of writebacks -system.cpu1.l2cache.writebacks::total 31472 # number of writebacks -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 76 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 76 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 76 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 76 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 76 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 321 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 276 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 14102 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 69212 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 83911 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 24018 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28339 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28339 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22509 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22509 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 35108 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 35108 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 321 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 276 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 14102 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 104320 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 119019 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 321 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 276 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 14102 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 104320 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 24018 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 143037 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3489000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 384250260 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 991800372 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1383661632 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 814752860 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 402368047 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 402368047 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306023777 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306023777 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1341000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1341000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1031661014 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1031661014 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3489000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 384250260 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2023461386 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 2415322646 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4122000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3489000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 384250260 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2023461386 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 814752860 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 3230075506 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 12590000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 494236499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 506826499 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 356773500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 356773500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 12590000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 851009999 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 863599999 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.402554 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.119093 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 25242 # number of writebacks +system.cpu1.l2cache.writebacks::total 25242 # number of writebacks +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 89 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 89 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 89 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 89 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 89 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 319 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 267 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 13186 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66797 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 80569 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 22684 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 22684 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 27938 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 27938 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22546 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22546 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 33853 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 33853 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 319 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 267 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 13186 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 100650 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 114422 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 319 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 267 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 13186 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 100650 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 22684 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 137106 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3630000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 382998014 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 996392500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1387317514 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 708613533 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 708613533 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 439996296 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 439996296 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 340047738 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 340047738 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2503000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2503000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 980626782 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 980626782 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3630000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 382998014 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 1977019282 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 2367944296 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 4297000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3630000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 382998014 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 1977019282 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 708613533 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 3076557829 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14041750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 382270250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 396312000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 262085000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 262085000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 14041750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 644355250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 658397000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.394781 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.118261 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.950208 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.950208 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962911 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962911 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.963379 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.963379 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.961163 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.961163 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.554427 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.554427 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154991 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.094080 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137656 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026747 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.443434 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.547314 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.547314 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153972 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.097613 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.137984 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.026014 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.435614 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.186269 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14329.890366 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16489.633445 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33922.593888 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14198.385511 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14198.385511 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13595.618508 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13595.618508 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 447000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 447000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29385.354164 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29385.354164 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20293.588805 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 12841.121495 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12641.304348 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27247.926535 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19396.677396 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33922.593888 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22582.097681 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.184497 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14916.725302 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17218.998796 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31238.473506 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15749.026272 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15749.026272 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15082.397676 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15082.397676 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 278111.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 278111.111111 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 28967.204738 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 28967.204738 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20694.834000 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22439.264722 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2093,64 +2078,62 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1051189 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 750269 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 3091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 3091 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 118649 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 33325 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 74679 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41637 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85827 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 85544 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 68027 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1054824 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 784590 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5329 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9434 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 1854177 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33743748 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25394480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8020 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13648 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 59159896 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 572639 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1437265 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.343414 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.474848 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1026038 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 726618 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2443 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 117066 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 27637 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75553 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41371 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85405 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 84221 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66421 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1014114 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 770781 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5251 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9223 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 1799369 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32441028 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25029390 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7740 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13072 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 57491230 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 567913 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1404964 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.347502 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.476177 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 943688 65.66% 65.66% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 493577 34.34% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 916736 65.25% 65.25% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 488228 34.75% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1437265 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 595732734 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 1404964 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 579509000 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80038500 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80431999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 791497760 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 760939764 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 388635637 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 380431845 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3324000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 6022000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 5955000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31024 # Transaction distribution -system.iobus.trans_dist::ReadResp 31024 # Transaction distribution -system.iobus.trans_dist::WriteReq 59440 # Transaction distribution -system.iobus.trans_dist::WriteResp 23216 # Transaction distribution +system.iobus.trans_dist::ReadReq 31015 # Transaction distribution +system.iobus.trans_dist::ReadResp 31015 # Transaction distribution +system.iobus.trans_dist::WriteReq 59423 # Transaction distribution +system.iobus.trans_dist::WriteResp 23199 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -2171,11 +2154,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -2196,11 +2179,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2240,23 +2223,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347109131 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198981721 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36846525 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36787516 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36445 # number of replacements -system.iocache.tags.tagsinuse 14.387294 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.385318 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 287959539000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.387294 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.899206 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.899206 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 288337625000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.385318 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.899082 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.899082 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2270,14 +2253,14 @@ system.iocache.demand_misses::realview.ide 255 # system.iocache.demand_misses::total 255 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 255 # number of overall misses system.iocache.overall_misses::total 255 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31782377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31782377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9599974229 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9599974229 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31782377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31782377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31782377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31782377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32669377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32669377 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649988828 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6649988828 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32669377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32669377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32669377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32669377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -2294,19 +2277,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124636.772549 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124636.772549 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265016.956410 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265016.956410 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124636.772549 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124636.772549 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124636.772549 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55555 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128115.203922 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128115.203922 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183579.638582 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183579.638582 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128115.203922 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128115.203922 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128115.203922 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22637 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7160 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3456 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.759078 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.550058 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2320,14 +2303,14 @@ system.iocache.demand_mshr_misses::realview.ide 255 system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 18521377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 18521377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7716276279 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7716276279 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 18521377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 18521377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 18521377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 18521377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19398377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19398377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4766308860 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4766308860 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19398377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19398377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19398377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19398377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2336,303 +2319,290 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72632.850980 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 72632.850980 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213015.577490 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213015.577490 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 72632.850980 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 72632.850980 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76072.066667 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76072.066667 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131578.756073 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131578.756073 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76072.066667 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76072.066667 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 130735 # number of replacements -system.l2c.tags.tagsinuse 63966.604731 # Cycle average of tags in use -system.l2c.tags.total_refs 343053 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195063 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.758678 # Average number of references to valid blocks. +system.l2c.tags.replacements 120296 # number of replacements +system.l2c.tags.tagsinuse 63905.436039 # Cycle average of tags in use +system.l2c.tags.total_refs 339434 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 184689 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.837868 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12083.139597 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.938906 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.007553 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6678.027236 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2760.487108 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38360.306045 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.955640 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1552.248405 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 535.801693 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1990.692549 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.184374 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000060 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.101899 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042122 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.585332 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.023685 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008176 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030376 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.976053 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 32989 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 31331 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 170 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4524 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 28295 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1895 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 29170 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.503372 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.478073 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 4931105 # Number of tag accesses -system.l2c.tags.data_accesses 4931105 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 82 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 29372 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 45566 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 45492 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 34 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 41 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11667 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 8537 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 5785 # number of ReadReq hits -system.l2c.ReadReq_hits::total 146639 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 227719 # number of Writeback hits -system.l2c.Writeback_hits::total 227719 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 770 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3132 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 164 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3862 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1497 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5359 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 82 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 29372 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49428 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 45492 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 34 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 41 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 11667 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 10034 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 5785 # number of demand (read+write) hits -system.l2c.demand_hits::total 151998 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 82 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 29372 # number of overall hits -system.l2c.overall_hits::cpu0.data 49428 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 45492 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 34 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 41 # number of overall hits -system.l2c.overall_hits::cpu1.inst 11667 # number of overall hits -system.l2c.overall_hits::cpu1.data 10034 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5785 # number of overall hits -system.l2c.overall_hits::total 151998 # number of overall hits +system.l2c.tags.occ_blocks::writebacks 11082.113172 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.011404 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.058569 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7219.690376 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2883.100910 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39595.862719 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1402.790170 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 257.162663 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1460.646056 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.169100 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000061 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.110164 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043993 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.604185 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.021405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.003924 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.022288 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.975120 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33682 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 30706 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 154 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4910 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 28614 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 227 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1859 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 28608 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.513947 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.468536 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 4789457 # Number of tag accesses +system.l2c.tags.data_accesses 4789457 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 83 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 70 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 29564 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 45272 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 47744 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 28 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 10986 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 7565 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 4624 # number of ReadReq hits +system.l2c.ReadReq_hits::total 145969 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 220623 # number of Writeback hits +system.l2c.Writeback_hits::total 220623 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2700 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 726 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3426 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 152 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 169 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 321 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4139 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 2014 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 6153 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 83 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 70 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 29564 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49411 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 47744 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 28 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 10986 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9579 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 4624 # number of demand (read+write) hits +system.l2c.demand_hits::total 152122 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 83 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 70 # number of overall hits +system.l2c.overall_hits::cpu0.inst 29564 # number of overall hits +system.l2c.overall_hits::cpu0.data 49411 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 47744 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 28 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits +system.l2c.overall_hits::cpu1.inst 10986 # number of overall hits +system.l2c.overall_hits::cpu1.data 9579 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 4624 # number of overall hits +system.l2c.overall_hits::total 152122 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 17779 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8894 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 2435 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 924 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq misses -system.l2c.ReadReq_misses::total 170945 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8889 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2898 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11787 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 758 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1209 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1967 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11387 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8562 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19949 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu0.inst 17590 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8761 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 130188 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2200 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 584 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 5403 # number of ReadReq misses +system.l2c.ReadReq_misses::total 164735 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8579 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2656 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11235 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 453 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1262 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 10640 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 6753 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 17393 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17779 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 20281 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 2435 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9486 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) misses -system.l2c.demand_misses::total 190894 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17590 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19401 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 130188 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2200 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 7337 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5403 # number of demand (read+write) misses +system.l2c.demand_misses::total 182128 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 7 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17779 # number of overall misses -system.l2c.overall_misses::cpu0.data 20281 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 134996 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 2435 # number of overall misses -system.l2c.overall_misses::cpu1.data 9486 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5907 # number of overall misses -system.l2c.overall_misses::total 190894 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 494750 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 149500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1299838245 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 708631748 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 182647247 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 78676500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 16020624042 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 5423319 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2108409 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 7531728 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 679977 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 605974 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 1285951 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 888864663 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 627516972 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1516381635 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 494750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 149500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1299838245 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1597496411 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 182647247 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 706193472 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 17537005677 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 494750 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 149500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1299838245 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1597496411 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 13069199153 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 182647247 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 706193472 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 680911899 # number of overall miss cycles -system.l2c.overall_miss_latency::total 17537005677 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 89 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 65 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 47151 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 54460 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 180488 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 35 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 41 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 14102 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 9461 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 11692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 317584 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 227719 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 227719 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 11251 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 3668 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 14919 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 922 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1373 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2295 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 15249 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10059 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 25308 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 89 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 65 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 47151 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 69709 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 180488 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 35 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 41 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 14102 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 19520 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 11692 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 342892 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 89 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 65 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 47151 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 69709 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 180488 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 35 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 41 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 14102 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 19520 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 11692 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 342892 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.030769 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.377065 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.163313 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.172671 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.097664 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.538267 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.790063 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.790076 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.790066 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822126 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.880554 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.857081 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.746737 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.851178 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.788249 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.030769 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.377065 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.290938 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.172671 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.485963 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.556718 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.078652 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.030769 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.377065 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.290938 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.747950 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.028571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.172671 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.485963 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.505217 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.556718 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73110.874909 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 79675.258376 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75009.136345 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 85147.727273 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 93718.003112 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 610.115761 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 727.539337 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 638.986002 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 897.067282 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 501.219189 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 653.762583 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 78059.599807 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73290.933427 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 76012.914682 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 91867.767855 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 70678.571429 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 74750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 73110.874909 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 78768.128347 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 96811.751111 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 75009.136345 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 74445.864643 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 115272.033012 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 91867.767855 # average overall miss latency +system.l2c.overall_misses::cpu0.inst 17590 # number of overall misses +system.l2c.overall_misses::cpu0.data 19401 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 130188 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2200 # number of overall misses +system.l2c.overall_misses::cpu1.data 7337 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 5403 # number of overall misses +system.l2c.overall_misses::total 182128 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 549750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 165000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1421225252 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 758301308 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 181920507 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 52732500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 15758293199 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 14082590 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2976406 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 17058996 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1006973 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1562950 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2569923 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 947359927 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 541992722 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1489352649 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 549750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 165000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1421225252 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1705661235 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 181920507 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 594725222 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 17247645848 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 549750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 165000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1421225252 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1705661235 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 12728769957 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 181920507 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 594725222 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 614628925 # number of overall miss cycles +system.l2c.overall_miss_latency::total 17247645848 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 90 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 72 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 47154 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 54033 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 177932 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 28 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 33 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13186 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 8149 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 10027 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 310704 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 220623 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 220623 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11279 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3382 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 14661 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 605 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1431 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2036 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 14779 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 8767 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 23546 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 90 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 72 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 47154 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 68812 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 177932 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 28 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 33 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 13186 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 16916 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 10027 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 334250 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 90 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 72 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 47154 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 68812 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 177932 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 28 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 33 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 13186 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 16916 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 10027 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 334250 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.027778 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.373033 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.162142 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.166844 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.071665 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.530199 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.760617 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.785334 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.766319 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.748760 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.881901 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.842338 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.719940 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.770275 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.738682 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.027778 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.373033 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.281942 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.166844 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.433731 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.544886 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.077778 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.027778 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.373033 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.281942 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.731673 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.166844 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.433731 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.538845 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.544886 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 80797.342354 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 86554.195640 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 82691.139545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 90295.376712 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 95658.440520 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1641.518825 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1120.634789 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1518.379706 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2222.898455 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 1238.470681 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1498.497376 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 89037.587124 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80259.547164 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 85629.428448 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 80797.342354 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 87916.150456 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 82691.139545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 81058.364727 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 94700.682202 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 78535.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 82500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 80797.342354 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 87916.150456 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 97772.221380 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 82691.139545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 81058.364727 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 113756.972978 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 94700.682202 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2641,186 +2611,174 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 99035 # number of writebacks -system.l2c.writebacks::total 99035 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 4 # number of overall MSHR hits +system.l2c.writebacks::writebacks 92066 # number of writebacks +system.l2c.writebacks::total 92066 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 7 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 17779 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8894 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 2432 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 923 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 170941 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8889 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 2898 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11787 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 758 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1209 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1967 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 11387 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8562 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 19949 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 17588 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8761 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 2195 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 584 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 164728 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8579 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2656 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11235 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 453 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1262 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1715 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 10640 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 6753 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 17393 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 7 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17779 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 20281 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 2432 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 9485 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 190890 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17588 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19401 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2195 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 7337 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 182121 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 7 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17779 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 20281 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 134996 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 2432 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 9485 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5907 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 190890 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 408750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1075716745 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 597785248 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 151904497 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 67178000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 13890498792 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 90106352 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 29086385 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 119192737 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7710755 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12095707 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 19806462 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 746306335 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 519227026 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1265533361 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1075716745 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1344091583 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 151904497 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 586405026 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 15156032153 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 408750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 125000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1075716745 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1344091583 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11388842153 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 151904497 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 586405026 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 608475899 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 15156032153 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 476665000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5183212748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 9260500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 424539000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 6093677248 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3944737000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 304049000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4248786000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476665000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9127949748 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9260500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 728588000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10342463248 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.163313 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.097558 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.538254 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.790063 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.790076 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.790066 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.822126 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.880554 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.857081 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.746737 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.851178 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.788249 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.556706 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.078652 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.030769 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.377065 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.290938 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.747950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.028571 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.172458 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.485912 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.505217 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.556706 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67212.193389 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72782.231853 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 81259.023827 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10136.837890 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.709800 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10112.219988 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10172.500000 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10004.720430 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10069.375699 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 65540.206815 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60643.193880 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63438.436062 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 58392.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60504.907194 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 66273.437355 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84364.293409 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62460.730674 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 61824.462414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 103009.293889 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 79396.679517 # average overall mshr miss latency +system.l2c.overall_mshr_misses::cpu0.inst 17588 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19401 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130188 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2195 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 7337 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 5403 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 182121 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 462250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 140000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1200652248 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 648693692 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 154097993 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 45421500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 13719540491 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 153128559 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 47338644 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 200467203 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 8146450 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 22467762 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 30614212 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 815815573 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 457532278 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1273347851 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 462250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 140000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1200652248 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1464509265 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 154097993 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 502953778 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 14992888342 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 462250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 140000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1200652248 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1464509265 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 11121813439 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 154097993 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 502953778 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 548259369 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 14992888342 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 549810500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5306549000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 10505750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 321692750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 6188558000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4079142000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 216691500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4295833500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 549810500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9385691000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 10505750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 538384250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10484391500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.162142 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071665 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.530177 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.760617 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.785334 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.766319 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.748760 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.881901 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.842338 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.719940 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.770275 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.738682 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.544865 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.077778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.027778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.372991 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.281942 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.731673 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.166464 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.433731 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.538845 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.544865 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74043.338888 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77776.541096 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 83286.026000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17849.231729 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17823.284639 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17843.097730 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17983.333333 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17803.297940 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17850.852478 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 76674.395959 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67752.447505 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 73210.363422 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -2835,58 +2793,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 215303 # Transaction distribution -system.membus.trans_dist::ReadResp 215303 # Transaction distribution -system.membus.trans_dist::WriteReq 30982 # Transaction distribution -system.membus.trans_dist::WriteResp 30982 # Transaction distribution -system.membus.trans_dist::Writeback 135225 # Transaction distribution +system.membus.trans_dist::ReadReq 209058 # Transaction distribution +system.membus.trans_dist::ReadResp 209058 # Transaction distribution +system.membus.trans_dist::WriteReq 30943 # Transaction distribution +system.membus.trans_dist::WriteResp 30943 # Transaction distribution +system.membus.trans_dist::Writeback 128256 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 76008 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40410 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13867 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution -system.membus.trans_dist::ReadExReq 40350 # Transaction distribution -system.membus.trans_dist::ReadExResp 19836 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40095 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13060 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution +system.membus.trans_dist::ReadExReq 37613 # Transaction distribution +system.membus.trans_dist::ReadExResp 17283 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13762 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659440 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 781206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13672 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 634735 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 756359 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 890114 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 865267 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27524 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18582632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18773074 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17575592 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17765802 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23408530 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123675 # Total snoops (count) -system.membus.snoop_fanout::samples 499419 # Request fanout histogram +system.membus.pkt_size::total 22401258 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125085 # Total snoops (count) +system.membus.snoop_fanout::samples 484369 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 499419 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 484369 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 499419 # Request fanout histogram -system.membus.reqLayer0.occupancy 88165000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 484369 # Request fanout histogram +system.membus.reqLayer0.occupancy 88115000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11453500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1828859499 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1931425684 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38544475 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1105573957 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1100453088 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37520484 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2919,44 +2877,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 482729 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 482714 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30982 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30982 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 227719 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 79027 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40738 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 119765 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 81 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 81 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51496 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51496 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1065854 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 282098 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1347952 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31837086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4944756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 36781842 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 286323 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 873908 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.041744 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.200003 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 476594 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 476579 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30943 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30943 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 220623 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80382 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40416 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 120798 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 107 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50330 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50330 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1064234 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 261111 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1325345 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31566808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4207570 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 35774378 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 289326 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 860656 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.042449 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.201611 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 837428 95.83% 95.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36480 4.17% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 824122 95.76% 95.76% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36534 4.24% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 873908 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1446151615 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 860656 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 750507689 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1735034184 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 618323353 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 653714719 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 219646363 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index b3648bdab..08c475a80 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.902862 # Number of seconds simulated -sim_ticks 2902861767000 # Number of ticks simulated -final_tick 2902861767000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.903548 # Number of seconds simulated +sim_ticks 2903547931500 # Number of ticks simulated +final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 747193 # Simulator instruction rate (inst/s) -host_op_rate 900893 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 19275657141 # Simulator tick rate (ticks/s) -host_mem_usage 615228 # Number of bytes of host memory used -host_seconds 150.60 # Real time elapsed on the host -sim_insts 112525269 # Number of instructions simulated -sim_ops 135672104 # Number of ops (including micro ops) simulated +host_inst_rate 732027 # Simulator instruction rate (inst/s) +host_op_rate 882601 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18897780106 # Simulator tick rate (ticks/s) +host_mem_usage 614620 # Number of bytes of host memory used +host_seconds 153.65 # Real time elapsed on the host +sim_insts 112472279 # Number of instructions simulated +sim_ops 135607130 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1191332 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8985828 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1191972 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9040292 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10178696 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1191332 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1191332 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7576000 # Number of bytes written to this memory +system.physmem.bytes_read::total 10233800 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1191972 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1191972 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7641920 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7593524 # Number of bytes written to this memory +system.physmem.bytes_written::total 7659444 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 27068 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 140923 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 27078 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141774 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 168015 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 118375 # Number of write requests responded to by this memory +system.physmem.num_reads::total 168876 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 119405 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 122756 # Number of write requests responded to by this memory +system.physmem.num_writes::total 123786 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 410399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3095507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 410523 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3113533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3506435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 410399 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 410399 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2609838 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2615875 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2609838 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3524584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 410523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 410523 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2631925 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6035 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2637960 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2631925 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 410399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3101543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 410523 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3119568 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 331 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6122310 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 168015 # Number of read requests accepted -system.physmem.writeReqs 158980 # Number of write requests accepted -system.physmem.readBursts 168015 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 158980 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10745280 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7680 # Total number of bytes read from write queue -system.physmem.bytesWritten 9814400 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10178696 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9911860 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 120 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5603 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4500 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 9689 # Per bank write bursts -system.physmem.perBankRdBursts::1 9230 # Per bank write bursts -system.physmem.perBankRdBursts::2 10198 # Per bank write bursts -system.physmem.perBankRdBursts::3 10267 # Per bank write bursts -system.physmem.perBankRdBursts::4 18984 # Per bank write bursts -system.physmem.perBankRdBursts::5 10226 # Per bank write bursts -system.physmem.perBankRdBursts::6 10551 # Per bank write bursts -system.physmem.perBankRdBursts::7 10350 # Per bank write bursts -system.physmem.perBankRdBursts::8 9702 # Per bank write bursts -system.physmem.perBankRdBursts::9 9930 # Per bank write bursts -system.physmem.perBankRdBursts::10 9908 # Per bank write bursts -system.physmem.perBankRdBursts::11 8848 # Per bank write bursts -system.physmem.perBankRdBursts::12 9929 # Per bank write bursts -system.physmem.perBankRdBursts::13 10408 # Per bank write bursts -system.physmem.perBankRdBursts::14 9925 # Per bank write bursts -system.physmem.perBankRdBursts::15 9750 # Per bank write bursts -system.physmem.perBankWrBursts::0 9389 # Per bank write bursts -system.physmem.perBankWrBursts::1 8975 # Per bank write bursts -system.physmem.perBankWrBursts::2 10251 # Per bank write bursts -system.physmem.perBankWrBursts::3 9953 # Per bank write bursts -system.physmem.perBankWrBursts::4 9418 # Per bank write bursts -system.physmem.perBankWrBursts::5 9499 # Per bank write bursts -system.physmem.perBankWrBursts::6 9770 # Per bank write bursts -system.physmem.perBankWrBursts::7 9764 # Per bank write bursts -system.physmem.perBankWrBursts::8 9682 # Per bank write bursts -system.physmem.perBankWrBursts::9 9836 # Per bank write bursts -system.physmem.perBankWrBursts::10 9791 # Per bank write bursts -system.physmem.perBankWrBursts::11 9091 # Per bank write bursts -system.physmem.perBankWrBursts::12 9681 # Per bank write bursts -system.physmem.perBankWrBursts::13 9852 # Per bank write bursts -system.physmem.perBankWrBursts::14 9372 # Per bank write bursts -system.physmem.perBankWrBursts::15 9026 # Per bank write bursts +system.physmem.bw_total::total 6162545 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 168876 # Number of read requests accepted +system.physmem.writeReqs 160010 # Number of write requests accepted +system.physmem.readBursts 168876 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 160010 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10798592 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue +system.physmem.bytesWritten 8731520 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10233800 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9977780 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23557 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4508 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10030 # Per bank write bursts +system.physmem.perBankRdBursts::1 9665 # Per bank write bursts +system.physmem.perBankRdBursts::2 10302 # Per bank write bursts +system.physmem.perBankRdBursts::3 9920 # Per bank write bursts +system.physmem.perBankRdBursts::4 18863 # Per bank write bursts +system.physmem.perBankRdBursts::5 10093 # Per bank write bursts +system.physmem.perBankRdBursts::6 10296 # Per bank write bursts +system.physmem.perBankRdBursts::7 10601 # Per bank write bursts +system.physmem.perBankRdBursts::8 9928 # Per bank write bursts +system.physmem.perBankRdBursts::9 10198 # Per bank write bursts +system.physmem.perBankRdBursts::10 9956 # Per bank write bursts +system.physmem.perBankRdBursts::11 9036 # Per bank write bursts +system.physmem.perBankRdBursts::12 9857 # Per bank write bursts +system.physmem.perBankRdBursts::13 10481 # Per bank write bursts +system.physmem.perBankRdBursts::14 9974 # Per bank write bursts +system.physmem.perBankRdBursts::15 9528 # Per bank write bursts +system.physmem.perBankWrBursts::0 8313 # Per bank write bursts +system.physmem.perBankWrBursts::1 8253 # Per bank write bursts +system.physmem.perBankWrBursts::2 9067 # Per bank write bursts +system.physmem.perBankWrBursts::3 8494 # Per bank write bursts +system.physmem.perBankWrBursts::4 8419 # Per bank write bursts +system.physmem.perBankWrBursts::5 8394 # Per bank write bursts +system.physmem.perBankWrBursts::6 8676 # Per bank write bursts +system.physmem.perBankWrBursts::7 8975 # Per bank write bursts +system.physmem.perBankWrBursts::8 8824 # Per bank write bursts +system.physmem.perBankWrBursts::9 8984 # Per bank write bursts +system.physmem.perBankWrBursts::10 8586 # Per bank write bursts +system.physmem.perBankWrBursts::11 8136 # Per bank write bursts +system.physmem.perBankWrBursts::12 8548 # Per bank write bursts +system.physmem.perBankWrBursts::13 8715 # Per bank write bursts +system.physmem.perBankWrBursts::14 8203 # Per bank write bursts +system.physmem.perBankWrBursts::15 7843 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2902861390500 # Total gap between requests +system.physmem.numWrRetry 46 # Number of times write queue was full causing retry +system.physmem.totGap 2903547607000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 9558 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 158443 # Read request sizes (log2) +system.physmem.readPktSize::6 159304 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 154599 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 167093 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 544 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 246 # What read queue length does an incoming req see +system.physmem.writePktSize::6 155629 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 167922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 552 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 242 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,178 +159,163 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4056 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 8985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9766 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 10902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 10695 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10360 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9893 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7190 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 6866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6730 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6660 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 241 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 181 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 10 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 60962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 337.252977 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.461800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.629111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 21587 35.41% 35.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14795 24.27% 59.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5550 9.10% 68.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3419 5.61% 74.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2349 3.85% 78.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1576 2.59% 80.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1011 1.66% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1092 1.79% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9583 15.72% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 60962 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6214 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 27.016254 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 542.923852 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6212 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1595 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1890 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5752 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5724 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 5981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6318 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8094 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 6968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6571 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1258 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2331 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2401 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2576 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1933 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1707 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1648 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1310 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 998 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 170 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 63 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 60277 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 324.004977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 188.393020 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.651376 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 21725 36.04% 36.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14933 24.77% 60.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5631 9.34% 70.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3281 5.44% 75.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2561 4.25% 79.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1497 2.48% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1055 1.75% 84.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1109 1.84% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8485 14.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 60277 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5494 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.709319 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 577.316613 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5492 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::40960-43007 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6214 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6214 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 24.678146 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 20.366342 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 23.738225 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5089 81.90% 81.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 32 0.51% 82.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.39% 82.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 212 3.41% 86.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 128 2.06% 88.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 65 1.05% 89.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 41 0.66% 89.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 30 0.48% 90.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 138 2.22% 92.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 16 0.26% 92.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 13 0.21% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 16 0.26% 93.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 29 0.47% 93.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 17 0.27% 94.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 11 0.18% 94.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 29 0.47% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 66 1.06% 95.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 8 0.13% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 3 0.05% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 17 0.27% 96.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 91 1.46% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.02% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 15 0.24% 98.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 8 0.13% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 6 0.10% 98.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 11 0.18% 98.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.02% 98.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 39 0.63% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 7 0.11% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.14% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 3 0.05% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.02% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 5 0.08% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.05% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 5 0.08% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 4 0.06% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6214 # Writes before turning the bus around for reads -system.physmem.totQLat 1487834250 # Total ticks spent queuing -system.physmem.totMemAccLat 4635865500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 839475000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8861.69 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5494 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5494 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.832545 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.556239 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 46.623010 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5170 94.10% 94.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 87 1.58% 95.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.31% 96.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 12 0.22% 96.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 19 0.35% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 28 0.51% 97.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 22 0.40% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 14 0.25% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 9 0.16% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 4 0.07% 97.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 29 0.53% 98.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 12 0.22% 98.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 6 0.11% 98.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 2 0.04% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.04% 98.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.13% 99.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 8 0.15% 99.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 4 0.07% 99.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 4 0.07% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 10 0.18% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.07% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 6 0.11% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5494 # Writes before turning the bus around for reads +system.physmem.totQLat 1499821694 # Total ticks spent queuing +system.physmem.totMemAccLat 4663471694 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 843640000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8888.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27611.69 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.70 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.38 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.41 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 27638.99 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.01 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.07 # Average write queue length when enqueuing -system.physmem.readRowHits 138089 # Number of row buffer hits during reads -system.physmem.writeRowHits 122193 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.25 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.67 # Row buffer hit rate for writes -system.physmem.avgGap 8877387.70 # Average gap between requests -system.physmem.pageHitRate 81.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 235320120 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 128398875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 698061000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 499083120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 86740865775 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1665624160500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1943526211470 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.522458 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2770750790000 # Time in different power states -system.physmem_0.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing +system.physmem.readRowHits 138826 # Number of row buffer hits during reads +system.physmem.writeRowHits 106054 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.72 # Row buffer hit rate for writes +system.physmem.avgGap 8828431.76 # Average gap between requests +system.physmem.pageHitRate 80.24 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 233551080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127433625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 700206000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 444469680 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 87280455420 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1665566622000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1943998321725 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.525264 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2770655896974 # Time in different power states +system.physmem_0.memoryStateTime::REF 96955820000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 35170942500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35935671776 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 225552600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 123069375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 611512200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 494624880 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 189600322080 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85548905145 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1666669740000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1943273726280 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.435479 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2772511956000 # Time in different power states -system.physmem_1.memoryStateTime::REF 96932680000 # Time in different power states +system.physmem_1.actEnergy 222143040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 121209000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 615864600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 439596720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 189645583920 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85782200445 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1666880880750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1943707478475 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.425095 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2772857314224 # Time in different power states +system.physmem_1.memoryStateTime::REF 96955820000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 33417040500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33734699276 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -380,57 +365,57 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 9552 # Table walker walks requested -system.cpu.dtb.walker.walksShort 9552 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1261 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8291 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 9552 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 9552 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 9552 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7388 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9945.756632 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7345.780525 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7322.338006 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 5745 77.76% 77.76% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 1639 22.18% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-81919 2 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::147456-163839 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7388 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 809108000 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 809108000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 809108000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6174 83.57% 83.57% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1214 16.43% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7388 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9552 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 9545 # Table walker walks requested +system.cpu.dtb.walker.walksShort 9545 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 1267 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 8278 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 9545 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 9545 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 9545 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7381 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10696.619699 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8418.408390 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7914.312600 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7376 99.93% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-65535 1 0.01% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7381 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 937449500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 937449500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 937449500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6161 83.47% 83.47% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1220 16.53% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7381 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 9545 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9552 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7388 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 9545 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7381 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7388 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 16940 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7381 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 16926 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24537663 # DTB read hits -system.cpu.dtb.read_misses 8142 # DTB read misses -system.cpu.dtb.write_hits 19618927 # DTB write hits -system.cpu.dtb.write_misses 1410 # DTB write misses +system.cpu.dtb.read_hits 24524755 # DTB read hits +system.cpu.dtb.read_misses 8132 # DTB read misses +system.cpu.dtb.write_hits 19610055 # DTB write hits +system.cpu.dtb.write_misses 1413 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4273 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 4269 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1664 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 1678 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24545805 # DTB read accesses -system.cpu.dtb.write_accesses 19620337 # DTB write accesses +system.cpu.dtb.read_accesses 24532887 # DTB read accesses +system.cpu.dtb.write_accesses 19611468 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44156590 # DTB hits -system.cpu.dtb.misses 9552 # DTB misses -system.cpu.dtb.accesses 44166142 # DTB accesses +system.cpu.dtb.hits 44134810 # DTB hits +system.cpu.dtb.misses 9545 # DTB misses +system.cpu.dtb.accesses 44144355 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,18 +453,18 @@ system.cpu.itb.walker.walkWaitTime::samples 4762 # system.cpu.itb.walker.walkWaitTime::0 4762 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::total 4762 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkCompletionTime::samples 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 9893.949147 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7210.941913 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7351.443657 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1400 45.06% 45.06% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1004 32.31% 77.37% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 701 22.56% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10683.778565 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8326.699765 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7409.739384 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1442 46.41% 46.41% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 985 31.70% 78.11% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 678 21.82% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::total 3107 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 808810000 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 808810000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 808810000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::samples 937122000 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 937122000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 937122000 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 2798 90.05% 90.05% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 309 9.95% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3107 # Table walker page sizes translated @@ -490,7 +475,7 @@ system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3107 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 7869 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 115624412 # ITB inst hits +system.cpu.itb.inst_hits 115569545 # ITB inst hits system.cpu.itb.inst_misses 4762 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -507,38 +492,38 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 115629174 # ITB inst accesses -system.cpu.itb.hits 115624412 # DTB hits +system.cpu.itb.inst_accesses 115574307 # ITB inst accesses +system.cpu.itb.hits 115569545 # DTB hits system.cpu.itb.misses 4762 # DTB misses -system.cpu.itb.accesses 115629174 # DTB accesses -system.cpu.numCycles 5805723534 # number of cpu cycles simulated +system.cpu.itb.accesses 115574307 # DTB accesses +system.cpu.numCycles 5807095863 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112525269 # Number of instructions committed -system.cpu.committedOps 135672104 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 119969678 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 11290 # Number of float alu accesses -system.cpu.num_func_calls 9899985 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 15238216 # number of instructions that are conditional controls -system.cpu.num_int_insts 119969678 # number of integer instructions -system.cpu.num_fp_insts 11290 # number of float instructions -system.cpu.num_int_register_reads 218203287 # number of times the integer registers were read -system.cpu.num_int_register_writes 82701548 # number of times the integer registers were written -system.cpu.num_fp_register_reads 8578 # number of times the floating registers were read +system.cpu.committedInsts 112472279 # Number of instructions committed +system.cpu.committedOps 135607130 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 119910547 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses +system.cpu.num_func_calls 9892504 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 15232384 # number of instructions that are conditional controls +system.cpu.num_int_insts 119910547 # number of integer instructions +system.cpu.num_fp_insts 11161 # number of float instructions +system.cpu.num_int_register_reads 218091200 # number of times the integer registers were read +system.cpu.num_int_register_writes 82658465 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written -system.cpu.num_cc_register_reads 490054820 # number of times the CC registers were read -system.cpu.num_cc_register_writes 51921339 # number of times the CC registers were written -system.cpu.num_mem_refs 45438019 # number of memory refs -system.cpu.num_load_insts 24860597 # Number of load instructions -system.cpu.num_store_insts 20577422 # Number of store instructions -system.cpu.num_idle_cycles 5386825418.146145 # Number of idle cycles -system.cpu.num_busy_cycles 418898115.853856 # Number of busy cycles -system.cpu.not_idle_fraction 0.072153 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.927847 # Percentage of idle cycles -system.cpu.Branches 25932360 # Number of branches fetched +system.cpu.num_cc_register_reads 489812948 # number of times the CC registers were read +system.cpu.num_cc_register_writes 51900975 # number of times the CC registers were written +system.cpu.num_mem_refs 45415290 # number of memory refs +system.cpu.num_load_insts 24846976 # Number of load instructions +system.cpu.num_store_insts 20568314 # Number of store instructions +system.cpu.num_idle_cycles 5385642355.670145 # Number of idle cycles +system.cpu.num_busy_cycles 421453507.329855 # Number of busy cycles +system.cpu.not_idle_fraction 0.072576 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.927424 # Percentage of idle cycles +system.cpu.Branches 25918910 # Number of branches fetched system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 93231199 67.17% 67.17% # Class of executed instruction -system.cpu.op_class::IntMult 114517 0.08% 67.26% # Class of executed instruction +system.cpu.op_class::IntAlu 93186875 67.17% 67.17% # Class of executed instruction +system.cpu.op_class::IntMult 114498 0.08% 67.26% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction @@ -562,194 +547,194 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 67.26% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 8515 0.01% 67.26% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 8463 0.01% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction -system.cpu.op_class::MemRead 24860597 17.91% 85.17% # Class of executed instruction -system.cpu.op_class::MemWrite 20577422 14.83% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 24846976 17.91% 85.17% # Class of executed instruction +system.cpu.op_class::MemWrite 20568314 14.83% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 138794587 # Class of executed instruction +system.cpu.op_class::total 138727463 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3037 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 823321 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.850573 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 43261398 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 823833 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 52.512339 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.850573 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 820494 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.827736 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 43242693 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 821006 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 52.670374 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1008712250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.827736 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999664 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999664 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 369 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 177233078 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 177233078 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23126684 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23126684 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18835651 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18835651 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 392122 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 392122 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443636 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443636 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460570 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460570 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41962335 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41962335 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42354457 # number of overall hits -system.cpu.dcache.overall_hits::total 42354457 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 402703 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 402703 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 299019 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 299019 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 119172 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 119172 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22743 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22743 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 177143306 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 177143306 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23115915 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23115915 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18827300 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18827300 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 392830 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 392830 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443506 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443506 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460403 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460403 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41943215 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41943215 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42336045 # number of overall hits +system.cpu.dcache.overall_hits::total 42336045 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 400875 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 400875 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 298693 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 298693 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 118357 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 118357 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22685 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22685 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 701722 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 701722 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 820894 # number of overall misses -system.cpu.dcache.overall_misses::total 820894 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916458250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5916458250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11650381750 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11650381750 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280295250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 280295250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17566840000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17566840000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17566840000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17566840000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 23529387 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 23529387 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19134670 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19134670 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 511294 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 511294 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466379 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466379 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460572 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460572 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 42664057 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42664057 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43175351 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43175351 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017115 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.017115 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015627 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015627 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233079 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.233079 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048765 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048765 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 699568 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 699568 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 817925 # number of overall misses +system.cpu.dcache.overall_misses::total 817925 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5965444702 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5965444702 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12639649008 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12639649008 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 280760500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 280760500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18605093710 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18605093710 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18605093710 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18605093710 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 23516790 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 23516790 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19125993 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19125993 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 511187 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 511187 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466191 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 466191 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 460405 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 460405 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 42642783 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 42642783 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43153970 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43153970 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017046 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.017046 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015617 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.231534 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.231534 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048660 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048660 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.016448 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.016448 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.019013 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.019013 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14691.865345 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14691.865345 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38962.011611 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 38962.011611 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12324.462472 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12324.462472 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 25033.902315 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 25033.902315 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 21399.644778 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 21399.644778 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 78 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.016405 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.016405 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.018954 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.018954 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14881.059437 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14881.059437 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42316.522342 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42316.522342 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12376.482257 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12376.482257 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26595.118287 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26595.118287 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 22746.698915 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 22746.698915 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 19 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 2.294118 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 686487 # number of writebacks -system.cpu.dcache.writebacks::total 686487 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 629 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 629 # number of ReadReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14254 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 14254 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 629 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 629 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 629 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 629 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 402074 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 402074 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299019 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 299019 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117021 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 117021 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8489 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8489 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 683915 # number of writebacks +system.cpu.dcache.writebacks::total 683915 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 674 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 674 # number of ReadReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14143 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 14143 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 674 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 674 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 674 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 674 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 400201 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 400201 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298693 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 298693 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 116343 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 116343 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8542 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8542 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 701093 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 701093 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 818114 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 818114 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5098164750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5098164750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10994871250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10994871250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411142000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411142000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 100012000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 100012000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16093036000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 16093036000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17504178000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 17504178000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791398250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791398250 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429682000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429682000 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080250 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017088 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017088 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228872 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228872 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018202 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018202 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 698894 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12133728492 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1470377548 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1470377548 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 105335000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 105335000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17483461242 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 17483461242 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18953838790 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18953838790 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5833129500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5833129500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4513032000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4513032000 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346161500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346161500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017018 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227594 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227594 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018323 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018323 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016433 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016433 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018949 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.018949 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12679.667797 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12679.667797 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36769.808106 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36769.808106 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12058.878321 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12058.878321 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11781.364118 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11781.364118 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22954.210069 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 22954.210069 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21395.768805 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21395.768805 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016390 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016390 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018891 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.018891 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13367.614649 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13367.614649 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40622.741383 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40622.741383 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12638.298376 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12638.298376 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12331.421213 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12331.421213 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25015.898322 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -757,59 +742,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1701491 # number of replacements -system.cpu.icache.tags.tagsinuse 510.782044 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 113922403 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1702003 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 66.934314 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.782044 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.997621 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1698619 # number of replacements +system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 113870408 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1699131 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.016850 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 25693423250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.734312 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.997528 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.997528 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 117326421 # Number of tag accesses -system.cpu.icache.tags.data_accesses 117326421 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 113922403 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 113922403 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 113922403 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 113922403 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 113922403 # number of overall hits -system.cpu.icache.overall_hits::total 113922403 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1702009 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1702009 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1702009 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1702009 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1702009 # number of overall misses -system.cpu.icache.overall_misses::total 1702009 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23268250500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23268250500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23268250500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23268250500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23268250500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23268250500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 115624412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 115624412 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 115624412 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 115624412 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 115624412 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 115624412 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014720 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014720 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014720 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014720 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014720 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014720 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13671.050212 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13671.050212 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13671.050212 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13671.050212 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13671.050212 # average overall miss latency +system.cpu.icache.tags.tag_accesses 117268682 # Number of tag accesses +system.cpu.icache.tags.data_accesses 117268682 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 113870408 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 113870408 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 113870408 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 113870408 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 113870408 # number of overall hits +system.cpu.icache.overall_hits::total 113870408 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1699137 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1699137 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1699137 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1699137 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1699137 # number of overall misses +system.cpu.icache.overall_misses::total 1699137 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23363194999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23363194999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23363194999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23363194999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23363194999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23363194999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 115569545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 115569545 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 115569545 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 115569545 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 115569545 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 115569545 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014702 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014702 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014702 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014702 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014702 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014702 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13750.036047 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13750.036047 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13750.036047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13750.036047 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13750.036047 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -818,196 +803,196 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1702009 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1702009 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1702009 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1702009 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1702009 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1702009 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19857660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19857660500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19857660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19857660500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19857660500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19857660500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 597905000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014720 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.014720 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014720 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.014720 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11667.188893 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11667.188893 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11667.188893 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11667.188893 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1699137 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1699137 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1699137 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 20807922501 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20807922501 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 20807922501 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 677067750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 677067750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 677067750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.014702 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.014702 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.014702 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.014702 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12246.171145 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12246.171145 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 88884 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64931.599128 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2763158 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 154151 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 17.925009 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 89783 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 2753164 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 155016 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 17.760515 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50668.289778 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.809348 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012227 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 9584.205539 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 4675.282236 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.773137 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50459.043234 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 3.807659 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.012269 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 9560.730853 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 4902.381289 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.769944 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000058 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.146243 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.071339 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.990778 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.145885 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.074804 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.990692 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1023 5 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65262 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65228 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2127 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6961 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56128 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2129 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6958 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56095 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000076 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995819 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 26260695 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 26260695 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6986 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3658 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1683931 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 515395 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2209970 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 686487 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 686487 # number of Writeback hits +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.995300 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 26192754 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 26192754 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6798 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3551 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 1681053 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 512833 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2204235 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 683915 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 683915 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 23 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 166042 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 166042 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6986 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 3658 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1683931 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 681437 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2376012 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6986 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 3658 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1683931 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 681437 # number of overall hits -system.cpu.l2cache.overall_hits::total 2376012 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 164921 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 164921 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 6798 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3551 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1681053 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 677754 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2369156 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 6798 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3551 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1681053 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 677754 # number of overall hits +system.cpu.l2cache.overall_hits::total 2369156 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 7 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 18053 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 12189 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 30251 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2710 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2710 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 18063 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 12253 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 30325 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2714 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2714 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 130244 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 130244 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 131035 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 131035 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 7 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 18053 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142433 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 160495 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 18063 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143288 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 161360 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 7 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 18053 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 142433 # number of overall misses -system.cpu.l2cache.overall_misses::total 160495 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 495250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 149500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1316295500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 927332750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2244273000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 444481 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 444481 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8974834460 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 8974834460 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 495250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 149500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1316295500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9902167210 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 11219107460 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 495250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 149500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1316295500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9902167210 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 11219107460 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6993 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3660 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1701984 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 527584 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2240221 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 686487 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 686487 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2733 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2733 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.inst 18063 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143288 # number of overall misses +system.cpu.l2cache.overall_misses::total 161360 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 722250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 165500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1457697500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1014855798 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2473441048 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 528483 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 528483 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 10018114706 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 10018114706 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 722250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 165500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1457697500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11032970504 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12491555754 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 722250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 165500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1457697500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11032970504 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12491555754 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6805 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3553 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 1699116 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 525086 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2234560 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 683915 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 683915 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2737 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2737 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 296286 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 296286 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6993 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 3660 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1701984 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 823870 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2536507 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6993 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 3660 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1701984 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 823870 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2536507 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001001 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000546 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010607 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023103 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013504 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991584 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991584 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 295956 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 295956 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6805 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3553 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1699116 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 821042 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2530516 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6805 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3553 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1699116 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 821042 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2530516 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.001029 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000563 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010631 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.023335 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.013571 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991597 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991597 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.439589 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.439589 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001001 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000546 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010607 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.172883 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063274 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001001 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000546 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010607 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.172883 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063274 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 70750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 74750 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72912.839971 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76079.477398 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74188.390466 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 164.015129 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 164.015129 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68907.853414 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68907.853414 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 70750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72912.839971 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69521.580041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69903.158728 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 70750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 74750 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72912.839971 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69521.580041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69903.158728 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.442752 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.442752 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.001029 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000563 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010631 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.174520 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063766 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.001029 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000563 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010631 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.174520 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063766 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 103178.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82750 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80700.741848 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82825.087570 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81564.420379 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 194.724761 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 194.724761 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76453.731492 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76453.731492 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77414.202739 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 103178.571429 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82750 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80700.741848 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76998.565853 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77414.202739 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1016,100 +1001,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 82185 # number of writebacks -system.cpu.l2cache.writebacks::total 82185 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 83215 # number of writebacks +system.cpu.l2cache.writebacks::total 83215 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 7 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18053 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12189 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 30251 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2710 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2710 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 18063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 12253 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 30325 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2714 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2714 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130244 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130244 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131035 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 131035 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 7 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 18053 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 142433 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 160495 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 18063 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143288 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 161360 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 7 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 18053 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 142433 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 160495 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 408750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 125000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1090271000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 775288750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1866093500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 27282710 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 27282710 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7345006540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7345006540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 408750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 125000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1090271000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8120295290 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9211100040 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 408750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 125000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1090271000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8120295290 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9211100040 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 474215000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5385925500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5860140500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4098165500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4098165500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 474215000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9484091000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9958306000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023103 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013504 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991584 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991584 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 861613702 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2093755952 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48365714 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48365714 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8377798294 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8377798294 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 635250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 140500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1231366500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9239411996 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10471554246 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 635250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 140500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1231366500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9239411996 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10471554246 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 546237750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5396778750 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5943016500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4154268500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4154268500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 546237750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9551047250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 10097285000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.023335 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013571 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991597 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991597 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.439589 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.439589 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063274 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001001 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000546 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010607 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172883 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063274 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60392.787902 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63605.607515 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61687.002083 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10067.420664 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10067.420664 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56394.202727 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56394.202727 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 58392.857143 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60392.787902 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57011.333680 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57391.819309 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442752 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442752 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063766 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001029 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000563 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010631 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.174520 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063766 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 70250 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68170.652715 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70318.591529 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69043.889596 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17820.823139 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17820.823139 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63935.576709 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63935.576709 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 90750 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70250 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1119,61 +1104,59 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2297061 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2297046 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 686487 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2733 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27589 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 683915 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36259 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2737 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2735 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296286 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296286 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3422037 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2457460 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12875 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24836 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 5917208 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108963064 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96860105 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 205865781 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53107 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3278617 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.011120 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.104863 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295956 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3416297 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2449150 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12768 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24628 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 5902843 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108779512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96514397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14212 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 53413 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 3242159 98.89% 98.89% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36458 1.11% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3278617 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2355272500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2567431500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2563126749 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1312657000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1308606460 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 17843250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 17823250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1194,11 +1177,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1219,11 +1202,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1263,23 +1246,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347060139 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198904691 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804507 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36849506 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.134613 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.079220 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 298400039000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.134613 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.070913 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.070913 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 309085643000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.079220 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.067451 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.067451 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1293,14 +1276,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28034377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28034377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9587408255 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9587408255 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28034377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28034377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28034377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28034377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28886876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28886876 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649316309 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6649316309 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28886876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28886876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28886876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28886876 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1317,19 +1300,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119805.029915 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119805.029915 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264670.060043 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264670.060043 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119805.029915 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119805.029915 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55358 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123448.188034 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123448.188034 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183561.073018 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183561.073018 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123448.188034 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123448.188034 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123448.188034 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22762 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7146 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.746711 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.636152 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1343,14 +1326,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15865377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15865377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7703746269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7703746269 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15865377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15865377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15865377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16499876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16499876 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4765656321 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4765656321 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16499876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16499876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16499876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16499876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1359,66 +1342,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67800.756410 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67800.756410 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212669.673945 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212669.673945 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67800.756410 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67800.756410 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70512.290598 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70512.290598 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131560.742077 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131560.742077 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70512.290598 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70512.290598 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 70661 # Transaction distribution -system.membus.trans_dist::ReadResp 70661 # Transaction distribution -system.membus.trans_dist::WriteReq 27618 # Transaction distribution -system.membus.trans_dist::WriteResp 27618 # Transaction distribution -system.membus.trans_dist::Writeback 118375 # Transaction distribution +system.membus.trans_dist::ReadReq 70719 # Transaction distribution +system.membus.trans_dist::ReadResp 70719 # Transaction distribution +system.membus.trans_dist::WriteReq 27589 # Transaction distribution +system.membus.trans_dist::WriteResp 27589 # Transaction distribution +system.membus.trans_dist::Writeback 119405 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4500 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4508 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4502 # Transaction distribution -system.membus.trans_dist::ReadExReq 128454 # Transaction distribution -system.membus.trans_dist::ReadExResp 128454 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4510 # Transaction distribution +system.membus.trans_dist::ReadExReq 129241 # Transaction distribution +system.membus.trans_dist::ReadExResp 129241 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436226 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 543908 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 438994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 546586 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 652795 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 655473 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15455100 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15618561 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15576124 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15739477 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20254017 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 498 # Total snoops (count) -system.membus.snoop_fanout::samples 318040 # Request fanout histogram +system.membus.snoop_fanout::samples 319985 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 318040 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 318040 # Request fanout histogram -system.membus.reqLayer0.occupancy 86773500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 319985 # Request fanout histogram +system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1758500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1700000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1589750000 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1594947750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38337493 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 980923653 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 964658040 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37509494 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt index f0c87683a..33aa26eaf 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/stats.txt @@ -1,73 +1,73 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 2.783867 # Number of seconds simulated -sim_ticks 2783867165000 # Number of ticks simulated -final_tick 2783867165000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2783867052000 # Number of ticks simulated +final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1311458 # Simulator instruction rate (inst/s) -host_op_rate 1596489 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25571502260 # Simulator tick rate (ticks/s) -host_mem_usage 616488 # Number of bytes of host memory used -host_seconds 108.87 # Real time elapsed on the host -sim_insts 142773109 # Number of instructions simulated -sim_ops 173803334 # Number of ops (including micro ops) simulated +host_inst_rate 1291395 # Simulator instruction rate (inst/s) +host_op_rate 1572066 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25180347721 # Simulator tick rate (ticks/s) +host_mem_usage 616688 # Number of bytes of host memory used +host_seconds 110.56 # Real time elapsed on the host +sim_insts 142772879 # Number of instructions simulated +sim_ops 173803124 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 728420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 728356 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 4660384 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 482432 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 5667588 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11540296 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 728420 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 11540232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 728356 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 482432 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1210852 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8837248 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 1210788 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8837184 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory -system.physmem.bytes_written::total 8854772 # Number of bytes written to this memory +system.physmem.bytes_written::total 8854708 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 19835 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 19834 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 73337 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 7538 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 88557 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 189290 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138082 # Number of write requests responded to by this memory +system.physmem.num_reads::total 189289 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138081 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142463 # Number of write requests responded to by this memory +system.physmem.num_writes::total 142462 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 261658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 261635 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.data 1674068 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 173296 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 2035869 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4145419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 261658 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4145396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 261635 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 173296 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 434953 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3174450 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 434930 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3174427 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3180745 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3174450 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3180722 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3174427 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 261658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 261635 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.data 1680360 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 173296 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 2035872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7326164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7326119 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -116,45 +116,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5682 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5682 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5682 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5682 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5682 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 5683 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5683 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5683 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5683 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5683 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 6705500 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 6705500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 6705500 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.42% 65.42% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1612 34.58% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4661 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5682 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 3049 65.40% 65.40% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1613 34.60% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4662 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5683 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5682 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4661 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5683 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4662 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4661 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 10343 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4662 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 10345 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 15994592 # DTB read hits -system.cpu0.dtb.read_misses 4787 # DTB read misses -system.cpu0.dtb.write_hits 11285776 # DTB write hits +system.cpu0.dtb.read_hits 15994593 # DTB read hits +system.cpu0.dtb.read_misses 4788 # DTB read misses +system.cpu0.dtb.write_hits 11285810 # DTB write hits system.cpu0.dtb.write_misses 895 # DTB write misses system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 394 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3233 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 3234 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 774 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 773 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 200 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 15999379 # DTB read accesses -system.cpu0.dtb.write_accesses 11286671 # DTB write accesses +system.cpu0.dtb.read_accesses 15999381 # DTB read accesses +system.cpu0.dtb.write_accesses 11286705 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 27280368 # DTB hits -system.cpu0.dtb.misses 5682 # DTB misses -system.cpu0.dtb.accesses 27286050 # DTB accesses +system.cpu0.dtb.hits 27280403 # DTB hits +system.cpu0.dtb.misses 5683 # DTB misses +system.cpu0.dtb.accesses 27286086 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -202,7 +202,7 @@ system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1886 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1886 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin::total 4497 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74779253 # ITB inst hits +system.cpu0.itb.inst_hits 74779098 # ITB inst hits system.cpu0.itb.inst_misses 2611 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -219,38 +219,38 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74781864 # ITB inst accesses -system.cpu0.itb.hits 74779253 # DTB hits +system.cpu0.itb.inst_accesses 74781709 # ITB inst accesses +system.cpu0.itb.hits 74779098 # DTB hits system.cpu0.itb.misses 2611 # DTB misses -system.cpu0.itb.accesses 74781864 # DTB accesses -system.cpu0.numCycles 5536444795 # number of cpu cycles simulated +system.cpu0.itb.accesses 74781709 # DTB accesses +system.cpu0.numCycles 5536444792 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 72626511 # Number of instructions committed -system.cpu0.committedOps 87972361 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 77485845 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5272 # Number of float alu accesses -system.cpu0.num_func_calls 8692455 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 9458284 # number of instructions that are conditional controls -system.cpu0.num_int_insts 77485845 # number of integer instructions -system.cpu0.num_fp_insts 5272 # number of float instructions -system.cpu0.num_int_register_reads 144065543 # number of times the integer registers were read -system.cpu0.num_int_register_writes 54441741 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 4114 # number of times the floating registers were read +system.cpu0.committedInsts 72626333 # Number of instructions committed +system.cpu0.committedOps 87972335 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 77485858 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5256 # Number of float alu accesses +system.cpu0.num_func_calls 8692525 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 9458276 # number of instructions that are conditional controls +system.cpu0.num_int_insts 77485858 # number of integer instructions +system.cpu0.num_fp_insts 5256 # number of float instructions +system.cpu0.num_int_register_reads 144065688 # number of times the integer registers were read +system.cpu0.num_int_register_writes 54441738 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4098 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1160 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 268855206 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 31825195 # number of times the CC registers were written -system.cpu0.num_mem_refs 27911692 # number of memory refs -system.cpu0.num_load_insts 16162187 # Number of load instructions -system.cpu0.num_store_insts 11749505 # Number of store instructions -system.cpu0.num_idle_cycles 5353607103.050808 # Number of idle cycles -system.cpu0.num_busy_cycles 182837691.949192 # Number of busy cycles +system.cpu0.num_cc_register_reads 268855171 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 31825079 # number of times the CC registers were written +system.cpu0.num_mem_refs 27911721 # number of memory refs +system.cpu0.num_load_insts 16162181 # Number of load instructions +system.cpu0.num_store_insts 11749540 # Number of store instructions +system.cpu0.num_idle_cycles 5353607317.458248 # Number of idle cycles +system.cpu0.num_busy_cycles 182837474.541752 # Number of busy cycles system.cpu0.not_idle_fraction 0.033024 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.966976 # Percentage of idle cycles -system.cpu0.Branches 18597060 # Number of branches fetched +system.cpu0.Branches 18597106 # Number of branches fetched system.cpu0.op_class::No_OpClass 2189 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 61764761 68.82% 68.83% # Class of executed instruction -system.cpu0.op_class::IntMult 59661 0.07% 68.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 61764727 68.82% 68.83% # Class of executed instruction +system.cpu0.op_class::IntMult 59660 0.07% 68.89% # Class of executed instruction system.cpu0.op_class::IntDiv 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::FloatAdd 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::FloatCmp 0 0.00% 68.89% # Class of executed instruction @@ -274,25 +274,25 @@ system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.89% # Cl system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.89% # Class of executed instruction system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.89% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 4406 0.00% 68.90% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 4403 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction -system.cpu0.op_class::MemRead 16162187 18.01% 86.91% # Class of executed instruction -system.cpu0.op_class::MemWrite 11749505 13.09% 100.00% # Class of executed instruction +system.cpu0.op_class::MemRead 16162181 18.01% 86.91% # Class of executed instruction +system.cpu0.op_class::MemWrite 11749540 13.09% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 89742709 # Class of executed instruction +system.cpu0.op_class::total 89742700 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3083 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 819403 # number of replacements +system.cpu0.dcache.tags.replacements 819402 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 53784478 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 819915 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 65.597627 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 53784414 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 819914 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 65.597629 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821680 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175494 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu0.data 475.821817 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 36.175357 # Average occupied blocks per requestor system.cpu0.dcache.tags.occ_percent::cpu0.data 0.929339 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::cpu1.data 0.070655 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy @@ -301,86 +301,86 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::0 286 system.cpu0.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 219237567 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 219237567 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 15302739 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 14826353 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 30129092 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 10898468 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 11441639 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 22340107 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186053 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209002 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 395055 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235062 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222268 # number of LoadLockedReq hits +system.cpu0.dcache.tags.tag_accesses 219237306 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 219237306 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15302738 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 14826284 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 30129022 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 10898497 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 11441613 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 22340110 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186051 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 209007 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 395058 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235059 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 222271 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 457330 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236768 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223368 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236765 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 223371 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 460136 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26201207 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 26267992 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 52469199 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26387260 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 26476994 # number of overall hits -system.cpu0.dcache.overall_hits::total 52864254 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 197067 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 199240 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 396307 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 137729 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 163949 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 26201235 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 26267897 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 52469132 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 26387286 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 26476904 # number of overall hits +system.cpu0.dcache.overall_hits::total 52864190 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197065 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 199241 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 396306 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 137741 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 163937 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 301678 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54389 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61684 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54401 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 61672 # number of SoftPFReq misses system.cpu0.dcache.SoftPFReq_misses::total 116073 # number of SoftPFReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4662 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3967 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 8629 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 2 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 334796 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 363189 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 697985 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 389185 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 424873 # number of overall misses -system.cpu0.dcache.overall_misses::total 814058 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15499806 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 15025593 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 30525399 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 11036197 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 11605588 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 22641785 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240442 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270686 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 511128 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239724 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226235 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 334806 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 363178 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 697984 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 389207 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 424850 # number of overall misses +system.cpu0.dcache.overall_misses::total 814057 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15499803 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 15025525 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 30525328 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 11036238 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 11605550 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 22641788 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 240452 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 270679 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 511131 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239721 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 226238 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 465959 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236768 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223370 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236765 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 223373 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 460138 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 26536003 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 26631181 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 53167184 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 26776445 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 26901867 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 53678312 # number of overall (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 26536041 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 26631075 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 53167116 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 26776493 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 26901754 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 53678247 # number of overall (read+write) accesses system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012714 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013260 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.012983 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012480 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014127 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012481 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014126 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226204 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227880 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227092 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019447 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.226245 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.227842 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.227091 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.019448 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.017535 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.018519 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000009 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses system.cpu0.dcache.demand_miss_rate::cpu0.data 0.012617 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013638 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013637 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.014535 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015793 # miss rate for overall accesses @@ -393,19 +393,19 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 682284 # number of writebacks -system.cpu0.dcache.writebacks::total 682284 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 682283 # number of writebacks +system.cpu0.dcache.writebacks::total 682283 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1699220 # number of replacements +system.cpu0.icache.tags.replacements 1699214 # number of replacements system.cpu0.icache.tags.tagsinuse 511.663681 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 145342961 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1699732 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.509340 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 145342721 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1699726 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 85.509500 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127365 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536315 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.127325 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.536356 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888921 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110422 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110423 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id @@ -413,43 +413,43 @@ system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 148742437 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 148742437 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 73936562 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 71406399 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 145342961 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 73936562 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 71406399 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 145342961 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 73936562 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 71406399 # number of overall hits -system.cpu0.icache.overall_hits::total 145342961 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 844577 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 855161 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1699738 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 844577 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 855161 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1699738 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 844577 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 855161 # number of overall misses -system.cpu0.icache.overall_misses::total 1699738 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 74781139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261560 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 147042699 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74781139 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 72261560 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 147042699 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74781139 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 72261560 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 147042699 # number of overall (read+write) accesses +system.cpu0.icache.tags.tag_accesses 148742185 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 148742185 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 73936444 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 71406277 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 145342721 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 73936444 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 71406277 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 145342721 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 73936444 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 71406277 # number of overall hits +system.cpu0.icache.overall_hits::total 145342721 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 844540 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 855192 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1699732 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 844540 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 855192 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1699732 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 844540 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 855192 # number of overall misses +system.cpu0.icache.overall_misses::total 1699732 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74780984 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 72261469 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 147042453 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74780984 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 72261469 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 147042453 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74780984 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 72261469 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 147042453 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011294 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011834 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011835 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.011559 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011294 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011834 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011835 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.011559 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011294 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011834 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011835 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.011559 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -509,25 +509,25 @@ system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 5060 system.cpu1.dtb.walker.walkRequestOrigin::total 11263 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 15530019 # DTB read hits -system.cpu1.dtb.read_misses 5412 # DTB read misses -system.cpu1.dtb.write_hits 11838449 # DTB write hits -system.cpu1.dtb.write_misses 791 # DTB write misses +system.cpu1.dtb.read_hits 15529940 # DTB read hits +system.cpu1.dtb.read_misses 5414 # DTB read misses +system.cpu1.dtb.write_hits 11838406 # DTB write hits +system.cpu1.dtb.write_misses 789 # DTB write misses system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 3183 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 911 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 909 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 245 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 15535431 # DTB read accesses -system.cpu1.dtb.write_accesses 11839240 # DTB write accesses +system.cpu1.dtb.read_accesses 15535354 # DTB read accesses +system.cpu1.dtb.write_accesses 11839195 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 27368468 # DTB hits +system.cpu1.dtb.hits 27368346 # DTB hits system.cpu1.dtb.misses 6203 # DTB misses -system.cpu1.dtb.accesses 27374671 # DTB accesses +system.cpu1.dtb.accesses 27374549 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -557,26 +557,26 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 3040 # Table walker walks requested -system.cpu1.itb.walker.walksShort 3040 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walkWaitTime::samples 3040 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 3040 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 3040 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 3041 # Table walker walks requested +system.cpu1.itb.walker.walksShort 3041 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walkWaitTime::samples 3041 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 3041 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 3041 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 1720 81.52% 81.52% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 390 18.48% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 2110 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 1721 81.53% 81.53% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 390 18.47% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 2111 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3040 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3040 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 3041 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 3041 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2110 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 5150 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 72259450 # ITB inst hits -system.cpu1.itb.inst_misses 3040 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 2111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 2111 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 5152 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 72259358 # ITB inst hits +system.cpu1.itb.inst_misses 3041 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -585,45 +585,45 @@ system.cpu1.itb.flush_tlb 2817 # Nu system.cpu1.itb.flush_tlb_mva 523 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2022 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 72262490 # ITB inst accesses -system.cpu1.itb.hits 72259450 # DTB hits -system.cpu1.itb.misses 3040 # DTB misses -system.cpu1.itb.accesses 72262490 # DTB accesses -system.cpu1.numCycles 88040872 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 72262399 # ITB inst accesses +system.cpu1.itb.hits 72259358 # DTB hits +system.cpu1.itb.misses 3041 # DTB misses +system.cpu1.itb.accesses 72262399 # DTB accesses +system.cpu1.numCycles 88040649 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 70146598 # Number of instructions committed -system.cpu1.committedOps 85830973 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 75676981 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 6212 # Number of float alu accesses -system.cpu1.num_func_calls 8181424 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 9272106 # number of instructions that are conditional controls -system.cpu1.num_int_insts 75676981 # number of integer instructions -system.cpu1.num_fp_insts 6212 # number of float instructions -system.cpu1.num_int_register_reads 140994581 # number of times the integer registers were read -system.cpu1.num_int_register_writes 52737823 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 4658 # number of times the floating registers were read +system.cpu1.committedInsts 70146546 # Number of instructions committed +system.cpu1.committedOps 85830789 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 75676825 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 6228 # Number of float alu accesses +system.cpu1.num_func_calls 8181374 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 9272054 # number of instructions that are conditional controls +system.cpu1.num_int_insts 75676825 # number of integer instructions +system.cpu1.num_fp_insts 6228 # number of float instructions +system.cpu1.num_int_register_reads 140994115 # number of times the integer registers were read +system.cpu1.num_int_register_writes 52737742 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 4674 # number of times the floating registers were read system.cpu1.num_fp_register_writes 1556 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 261999475 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 30539263 # number of times the CC registers were written -system.cpu1.num_mem_refs 28027673 # number of memory refs -system.cpu1.num_load_insts 15693775 # Number of load instructions -system.cpu1.num_store_insts 12333898 # Number of store instructions -system.cpu1.num_idle_cycles 85385179.520823 # Number of idle cycles -system.cpu1.num_busy_cycles 2655692.479177 # Number of busy cycles +system.cpu1.num_cc_register_reads 261998832 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 30539220 # number of times the CC registers were written +system.cpu1.num_mem_refs 28027555 # number of memory refs +system.cpu1.num_load_insts 15693703 # Number of load instructions +system.cpu1.num_store_insts 12333852 # Number of store instructions +system.cpu1.num_idle_cycles 85384966.713327 # Number of idle cycles +system.cpu1.num_busy_cycles 2655682.286673 # Number of busy cycles system.cpu1.not_idle_fraction 0.030164 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.969836 # Percentage of idle cycles -system.cpu1.Branches 17799968 # Number of branches fetched +system.cpu1.Branches 17799875 # Number of branches fetched system.cpu1.op_class::No_OpClass 148 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 59388214 67.89% 67.89% # Class of executed instruction -system.cpu1.op_class::IntMult 57231 0.07% 67.96% # Class of executed instruction +system.cpu1.op_class::IntAlu 59388111 67.89% 67.89% # Class of executed instruction +system.cpu1.op_class::IntMult 57232 0.07% 67.96% # Class of executed instruction system.cpu1.op_class::IntDiv 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::FloatAdd 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::FloatCmp 0 0.00% 67.96% # Class of executed instruction @@ -647,23 +647,23 @@ system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.96% # Cl system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 4163 0.00% 67.96% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 4166 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatMult 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.96% # Class of executed instruction system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.96% # Class of executed instruction -system.cpu1.op_class::MemRead 15693775 17.94% 85.90% # Class of executed instruction -system.cpu1.op_class::MemWrite 12333898 14.10% 100.00% # Class of executed instruction +system.cpu1.op_class::MemRead 15693703 17.94% 85.90% # Class of executed instruction +system.cpu1.op_class::MemWrite 12333852 14.10% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 87477429 # Class of executed instruction +system.cpu1.op_class::total 87477212 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 30171 # Transaction distribution -system.iobus.trans_dist::ReadResp 30171 # Transaction distribution -system.iobus.trans_dist::WriteReq 59016 # Transaction distribution -system.iobus.trans_dist::WriteResp 22792 # Transaction distribution +system.iobus.trans_dist::ReadReq 30164 # Transaction distribution +system.iobus.trans_dist::ReadResp 30164 # Transaction distribution +system.iobus.trans_dist::WriteReq 59002 # Transaction distribution +system.iobus.trans_dist::WriteResp 22778 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -684,11 +684,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105404 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178332 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67833 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -709,17 +709,17 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159061 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480213 # Cumulative packet size per connected master and slave (bytes) system.iocache.tags.replacements 36430 # number of replacements -system.iocache.tags.tagsinuse 0.909962 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.909961 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.909962 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 0.909961 # Average occupied blocks per requestor system.iocache.tags.occ_percent::realview.ide 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.056873 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id @@ -762,20 +762,20 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 110021 # number of replacements -system.l2c.tags.tagsinuse 65155.309065 # Cycle average of tags in use -system.l2c.tags.total_refs 2731330 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 15.580712 # Average number of references to valid blocks. +system.l2c.tags.replacements 110020 # number of replacements +system.l2c.tags.tagsinuse 65155.309107 # Cycle average of tags in use +system.l2c.tags.total_refs 2731325 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 175301 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 15.580772 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 48893.434420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 48893.438134 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924326 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5044.359026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 4729.332054 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5044.354241 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 4729.333214 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.inst 4020.194257 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 2464.086185 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 2464.086137 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy @@ -795,143 +795,143 @@ system.l2c.tags.age_task_id_blocks_1024::3 10700 # system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 26231923 # Number of tag accesses -system.l2c.tags.data_accesses 26231923 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4699 # number of ReadReq hits +system.l2c.tags.tag_accesses 26231874 # Number of tag accesses +system.l2c.tags.data_accesses 26231874 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4700 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 2287 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 833747 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 246348 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5000 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 833711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 246358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5001 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 847615 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 259132 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2201281 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 682284 # number of Writeback hits -system.l2c.Writeback_hits::total 682284 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 847646 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 259121 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2201277 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 682283 # number of Writeback hits +system.l2c.Writeback_hits::total 682283 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 15 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 72504 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 78554 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 72515 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 78543 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 151058 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 4699 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.dtb.walker 4700 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 2287 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 833747 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 318852 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5000 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 833711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 318873 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5001 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 2453 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 847615 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 337686 # number of demand (read+write) hits -system.l2c.demand_hits::total 2352339 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 4699 # number of overall hits +system.l2c.demand_hits::cpu1.inst 847646 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 337664 # number of demand (read+write) hits +system.l2c.demand_hits::total 2352335 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 4700 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 2287 # number of overall hits -system.l2c.overall_hits::cpu0.inst 833747 # number of overall hits -system.l2c.overall_hits::cpu0.data 318852 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5000 # number of overall hits +system.l2c.overall_hits::cpu0.inst 833711 # number of overall hits +system.l2c.overall_hits::cpu0.data 318873 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5001 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 2453 # number of overall hits -system.l2c.overall_hits::cpu1.inst 847615 # number of overall hits -system.l2c.overall_hits::cpu1.data 337686 # number of overall hits -system.l2c.overall_hits::total 2352339 # number of overall hits +system.l2c.overall_hits::cpu1.inst 847646 # number of overall hits +system.l2c.overall_hits::cpu1.data 337664 # number of overall hits +system.l2c.overall_hits::total 2352335 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 10820 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 10819 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 9770 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 7538 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 5759 # number of ReadReq misses -system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses +system.l2c.ReadReq_misses::total 33894 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63963 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 83901 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 63964 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 83900 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 10820 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 73733 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 10819 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 73734 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 7538 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 89660 # number of demand (read+write) misses -system.l2c.demand_misses::total 181759 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 89659 # number of demand (read+write) misses +system.l2c.demand_misses::total 181758 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 10820 # number of overall misses -system.l2c.overall_misses::cpu0.data 73733 # number of overall misses +system.l2c.overall_misses::cpu0.inst 10819 # number of overall misses +system.l2c.overall_misses::cpu0.data 73734 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses system.l2c.overall_misses::cpu1.inst 7538 # number of overall misses -system.l2c.overall_misses::cpu1.data 89660 # number of overall misses -system.l2c.overall_misses::total 181759 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 4704 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::cpu1.data 89659 # number of overall misses +system.l2c.overall_misses::total 181758 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 4705 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 2288 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 844567 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 256118 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5002 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 844530 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 256128 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5003 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 2453 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 855153 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 264891 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2235176 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 682284 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 682284 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 855184 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 264880 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2235171 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 682283 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 682283 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1262 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 1494 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 136467 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 162455 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 136479 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 162443 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 298922 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 4704 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.dtb.walker 4705 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 2288 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 844567 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 392585 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5002 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 844530 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 392607 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5003 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 2453 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 855153 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 427346 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2534098 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 4704 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 855184 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 427323 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2534093 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 4705 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 2288 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 844567 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 392585 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5002 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 844530 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 392607 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5003 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 2453 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 855153 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 427346 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2534098 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 855184 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 427323 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2534093 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.012811 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.038146 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.038145 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.008815 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.021741 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008814 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.021742 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.015164 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989699 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989960 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.468707 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.516457 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.468673 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.516489 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.494657 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.012811 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.187814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.187806 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.008815 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.209807 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.209816 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.071725 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001063 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.012811 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.187814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.187806 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000400 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.008815 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.209807 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.209816 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.071725 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -941,14 +941,14 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 101892 # number of writebacks -system.l2c.writebacks::total 101892 # number of writebacks +system.l2c.writebacks::writebacks 101891 # number of writebacks +system.l2c.writebacks::total 101891 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 74229 # Transaction distribution -system.membus.trans_dist::ReadResp 74229 # Transaction distribution -system.membus.trans_dist::WriteReq 27560 # Transaction distribution -system.membus.trans_dist::WriteResp 27560 # Transaction distribution -system.membus.trans_dist::Writeback 138082 # Transaction distribution +system.membus.trans_dist::ReadReq 74221 # Transaction distribution +system.membus.trans_dist::ReadResp 74221 # Transaction distribution +system.membus.trans_dist::WriteReq 27546 # Transaction distribution +system.membus.trans_dist::WriteResp 27546 # Transaction distribution +system.membus.trans_dist::Writeback 138081 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution @@ -956,34 +956,34 @@ system.membus.trans_dist::SCUpgradeReq 2 # Tr system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution system.membus.trans_dist::ReadExReq 146085 # Transaction distribution system.membus.trans_dist::ReadExResp 146085 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105404 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498776 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 606178 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498773 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 606133 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109118 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109118 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 715296 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 715251 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159061 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095676 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18258691 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095548 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18258521 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4649856 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22908547 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22908377 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 359035 # Request fanout histogram +system.membus.snoop_fanout::samples 359033 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 359035 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 359033 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 359035 # Request fanout histogram +system.membus.snoop_fanout::total 359033 # Request fanout histogram system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -1015,41 +1015,39 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 2291995 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2291995 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 682284 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 2291984 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2291984 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 27546 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 27546 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 682283 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 298922 # Transaction distribution system.toL2Bus.trans_dist::ReadExResp 298922 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417520 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444926 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20800 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41508 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5924754 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108819320 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324555 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83016 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 205268491 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417508 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444881 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20804 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41510 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5924703 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108818936 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96324385 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 205267949 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 36631 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3272329 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.011143 # Request fanout histogram +system.toL2Bus.snoop_fanout::samples 3272324 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.011143 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0.104971 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 3235865 98.89% 98.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 3235860 98.89% 98.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 36464 1.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3272329 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 3272324 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt index 83b8a4ab7..b412f009d 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic-dual/stats.txt @@ -1,77 +1,77 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.177080 # Number of seconds simulated -sim_ticks 47177080006500 # Number of ticks simulated -final_tick 47177080006500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.216814 # Number of seconds simulated +sim_ticks 47216814145000 # Number of ticks simulated +final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1049876 # Simulator instruction rate (inst/s) -host_op_rate 1235062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50706899360 # Simulator tick rate (ticks/s) -host_mem_usage 670076 # Number of bytes of host memory used -host_seconds 930.39 # Real time elapsed on the host -sim_insts 976792036 # Number of instructions simulated -sim_ops 1149086878 # Number of ops (including micro ops) simulated +host_inst_rate 1225013 # Simulator instruction rate (inst/s) +host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59296512316 # Simulator tick rate (ticks/s) +host_mem_usage 723320 # Number of bytes of host memory used +host_seconds 796.28 # Real time elapsed on the host +sim_insts 975457230 # Number of instructions simulated +sim_ops 1147538415 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 149696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 124032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3867700 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 35125336 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 224640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 222848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2692808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 38798848 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 404992 # Number of bytes read from this memory -system.physmem.bytes_read::total 81610900 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3867700 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2692808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6560508 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 100759808 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3911220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 221184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2638152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 38475968 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 412928 # Number of bytes read from this memory +system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3911220 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2638152 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 100780624 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2339 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 1938 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 100840 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 548855 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3510 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 3482 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 42182 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 606250 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6328 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1315724 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1574372 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 100583888 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 101520 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 550562 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3483 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 3456 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 41328 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 601205 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6452 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1312424 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1571298 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1576975 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3173 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 2629 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 81983 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 744542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4762 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 4724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 57079 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 822409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1729885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 81983 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 57079 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 139061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2135779 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1573901 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3263 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 82835 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4721 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 4684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 55873 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2136220 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2135779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 2629 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 81983 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 744984 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4762 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 4724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 57079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 822409 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3866105 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2130256 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2129815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3263 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory @@ -134,45 +134,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 123914 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 123914 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 123914 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 123914 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 123914 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 125229 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 125229 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 125229 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 125229 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 125229 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 95376 89.74% 89.74% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 10905 10.26% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 106281 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 123914 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 96746 89.71% 89.71% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 11103 10.29% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 107849 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 125229 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 123914 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 106281 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 125229 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 107849 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 106281 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 230195 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 107849 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 233078 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91355479 # DTB read hits -system.cpu0.dtb.read_misses 87819 # DTB read misses -system.cpu0.dtb.write_hits 84601943 # DTB write hits -system.cpu0.dtb.write_misses 36095 # DTB write misses +system.cpu0.dtb.read_hits 92662773 # DTB read hits +system.cpu0.dtb.read_misses 88786 # DTB read misses +system.cpu0.dtb.write_hits 85694958 # DTB write hits +system.cpu0.dtb.write_misses 36443 # DTB write misses system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 36260 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 36354 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 5461 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5600 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10344 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 91443298 # DTB read accesses -system.cpu0.dtb.write_accesses 84638038 # DTB write accesses +system.cpu0.dtb.perms_faults 10503 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 92751559 # DTB read accesses +system.cpu0.dtb.write_accesses 85731401 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 175957422 # DTB hits -system.cpu0.dtb.misses 123914 # DTB misses -system.cpu0.dtb.accesses 176081336 # DTB accesses +system.cpu0.dtb.hits 178357731 # DTB hits +system.cpu0.dtb.misses 125229 # DTB misses +system.cpu0.dtb.accesses 178482960 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -202,187 +202,187 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 60226 # Table walker walks requested -system.cpu0.itb.walker.walksLong 60226 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 60226 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 60226 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 60226 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 61377 # Table walker walks requested +system.cpu0.itb.walker.walksLong 61377 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 61377 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 61377 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 61377 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 54190 98.81% 98.81% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 654 1.19% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 54844 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 55424 98.80% 98.80% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 672 1.20% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 56096 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 60226 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 60226 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 61377 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 61377 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 54844 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 54844 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 115070 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 491372488 # ITB inst hits -system.cpu0.itb.inst_misses 60226 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 56096 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 56096 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 117473 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 497696393 # ITB inst hits +system.cpu0.itb.inst_misses 61377 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 25015 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 25032 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 491432714 # ITB inst accesses -system.cpu0.itb.hits 491372488 # DTB hits -system.cpu0.itb.misses 60226 # DTB misses -system.cpu0.itb.accesses 491432714 # DTB accesses -system.cpu0.numCycles 94354173207 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 497757770 # ITB inst accesses +system.cpu0.itb.hits 497696393 # DTB hits +system.cpu0.itb.misses 61377 # DTB misses +system.cpu0.itb.accesses 497757770 # DTB accesses +system.cpu0.numCycles 94433641544 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 491139120 # Number of instructions committed -system.cpu0.committedOps 577575160 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 529301791 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 523058 # Number of float alu accesses -system.cpu0.num_func_calls 28573576 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 75495865 # number of instructions that are conditional controls -system.cpu0.num_int_insts 529301791 # number of integer instructions -system.cpu0.num_fp_insts 523058 # number of float instructions -system.cpu0.num_int_register_reads 775565033 # number of times the integer registers were read -system.cpu0.num_int_register_writes 419986522 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 843711 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 444676 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132153354 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 131825344 # number of times the CC registers were written -system.cpu0.num_mem_refs 176058068 # number of memory refs -system.cpu0.num_load_insts 91428761 # Number of load instructions -system.cpu0.num_store_insts 84629307 # Number of store instructions -system.cpu0.num_idle_cycles 93776262262.183929 # Number of idle cycles -system.cpu0.num_busy_cycles 577910944.816068 # Number of busy cycles -system.cpu0.not_idle_fraction 0.006125 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.993875 # Percentage of idle cycles -system.cpu0.Branches 109891880 # Number of branches fetched +system.cpu0.committedInsts 497466384 # Number of instructions committed +system.cpu0.committedOps 584970773 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 536103359 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 526132 # Number of float alu accesses +system.cpu0.num_func_calls 28869117 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76496594 # number of instructions that are conditional controls +system.cpu0.num_int_insts 536103359 # number of integer instructions +system.cpu0.num_fp_insts 526132 # number of float instructions +system.cpu0.num_int_register_reads 784958858 # number of times the integer registers were read +system.cpu0.num_int_register_writes 425337843 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 849923 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 443780 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133878831 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 133531045 # number of times the CC registers were written +system.cpu0.num_mem_refs 178459396 # number of memory refs +system.cpu0.num_load_insts 92737001 # Number of load instructions +system.cpu0.num_store_insts 85722395 # Number of store instructions +system.cpu0.num_idle_cycles 93848337191.325058 # Number of idle cycles +system.cpu0.num_busy_cycles 585304352.674931 # Number of busy cycles +system.cpu0.not_idle_fraction 0.006198 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.993802 # Percentage of idle cycles +system.cpu0.Branches 111287587 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 400497126 69.30% 69.30% # Class of executed instruction -system.cpu0.op_class::IntMult 1218559 0.21% 69.51% # Class of executed instruction -system.cpu0.op_class::IntDiv 59561 0.01% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 73140 0.01% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.54% # Class of executed instruction -system.cpu0.op_class::MemRead 91428761 15.82% 85.36% # Class of executed instruction -system.cpu0.op_class::MemWrite 84629307 14.64% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 405476023 69.28% 69.28% # Class of executed instruction +system.cpu0.op_class::IntMult 1232194 0.21% 69.49% # Class of executed instruction +system.cpu0.op_class::IntDiv 59840 0.01% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.50% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 72507 0.01% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu0.op_class::MemRead 92737001 15.84% 85.35% # Class of executed instruction +system.cpu0.op_class::MemWrite 85722395 14.65% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 577906497 # Class of executed instruction +system.cpu0.op_class::total 585300003 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 13193 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 6189405 # number of replacements -system.cpu0.dcache.tags.tagsinuse 506.263112 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 169698310 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 6189917 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 27.415280 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 6272759 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.885315 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 172015744 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 6273271 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 27.420423 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 35630500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 506.263112 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.988795 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.988795 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.885315 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978292 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978292 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 11 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 358274198 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 358274198 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 84971856 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 84971856 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79868150 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 79868150 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 214674 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 214674 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 260533 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 260533 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2068908 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 2068908 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2028668 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 2028668 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 164840006 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 164840006 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165054680 # number of overall hits -system.cpu0.dcache.overall_hits::total 165054680 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3260277 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3260277 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1458399 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1458399 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 767112 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 767112 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 819206 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 819206 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 116959 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 116959 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 156094 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 156094 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4718676 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4718676 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5485788 # number of overall misses -system.cpu0.dcache.overall_misses::total 5485788 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88232133 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 88232133 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81326549 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81326549 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 981786 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 981786 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1079739 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1079739 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2185867 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 2185867 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2184762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 2184762 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169558682 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 169558682 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170540468 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 170540468 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036951 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036951 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017933 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.017933 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781343 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.758707 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.758707 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053507 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053507 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.071447 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.071447 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027829 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.027829 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032167 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.032167 # miss rate for overall accesses +system.cpu0.dcache.tags.tag_accesses 363162158 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 363162158 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 86214905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 86214905 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80919887 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80919887 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 215655 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 215655 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 262024 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 262024 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2076466 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 2076466 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2036774 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 2036774 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 167134792 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 167134792 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 167350447 # number of overall hits +system.cpu0.dcache.overall_hits::total 167350447 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3309378 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 3309378 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1475526 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1475526 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 772138 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 772138 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 831696 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 831696 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 119816 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 119816 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 158369 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 158369 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4784904 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4784904 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5557042 # number of overall misses +system.cpu0.dcache.overall_misses::total 5557042 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 89524283 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 89524283 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 82395413 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 82395413 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 987793 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 987793 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 1093720 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1093720 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2196282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 2196282 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2195143 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 2195143 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 171919696 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 171919696 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 172907489 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 172907489 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017908 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.017908 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781680 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.072145 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.072145 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027832 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027832 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032139 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,50 +391,50 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 4407988 # number of writebacks -system.cpu0.dcache.writebacks::total 4407988 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 4469723 # number of writebacks +system.cpu0.dcache.writebacks::total 4469723 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5467768 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.988996 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 485959047 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5468280 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 88.868721 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 5539081 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.989005 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 492212891 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 5539593 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 88.853620 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.988996 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.989005 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999979 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 202 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 988322949 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 988322949 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 485959047 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 485959047 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 485959047 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 485959047 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 485959047 # number of overall hits -system.cpu0.icache.overall_hits::total 485959047 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5468285 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5468285 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5468285 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5468285 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5468285 # number of overall misses -system.cpu0.icache.overall_misses::total 5468285 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 491427332 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 491427332 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 491427332 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 491427332 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 491427332 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 491427332 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011127 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011127 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011127 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011127 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011127 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011127 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 1001044576 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 1001044576 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 492212891 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 492212891 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 492212891 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 492212891 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 492212891 # number of overall hits +system.cpu0.icache.overall_hits::total 492212891 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 5539598 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 5539598 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 5539598 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 5539598 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 5539598 # number of overall misses +system.cpu0.icache.overall_misses::total 5539598 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 497752489 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 497752489 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 497752489 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 497752489 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 497752489 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011129 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.011129 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011129 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.011129 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011129 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.011129 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -450,132 +450,132 @@ system.cpu0.l2cache.prefetcher.pfBufferHit 0 # system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2648971 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16219.904236 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 11415809 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2665005 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.283598 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.replacements 2710840 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16208.843540 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 11548798 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2726836 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.235237 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 5428.449185 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 50.127041 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 51.911966 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4608.843039 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 6080.573004 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.331326 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003060 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003168 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.281301 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.371129 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.989984 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15969 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 5735.641953 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 53.550576 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 55.046098 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4528.763909 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 5835.841004 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.350076 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003268 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.003360 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.276414 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.356191 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.989309 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15944 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 50 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1130 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4626 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5485 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4547 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.974670 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 274915962 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 274915962 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 266204 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 139155 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4917807 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2910870 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 8234036 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 4407988 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 4407988 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 219663 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 219663 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3562 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 3562 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 630387 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 630387 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 266204 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 139155 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4917807 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3541257 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8864423 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 266204 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 139155 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4917807 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3541257 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8864423 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10959 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8288 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 550478 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 1233478 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1803203 # number of ReadReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 599179 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 599179 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 125865 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 125865 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 156094 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 156094 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 698949 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 698949 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10959 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8288 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 550478 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1932427 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 2502152 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10959 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8288 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 550478 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1932427 # number of overall misses -system.cpu0.l2cache.overall_misses::total 2502152 # number of overall misses -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 277163 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 147443 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5468285 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4144348 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 10037239 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 4407988 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 4407988 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 818842 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 818842 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 129427 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 129427 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 156094 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 156094 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1329336 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1329336 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 277163 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 147443 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5468285 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5473684 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 11366575 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 277163 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 147443 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5468285 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5473684 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 11366575 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056212 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.100667 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.297629 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.179651 # miss rate for ReadReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.731739 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.731739 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.972479 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.972479 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 40 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 233 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1162 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4591 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5299 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 4659 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003174 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.973145 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 278654950 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 278654950 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 269350 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 141753 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4971397 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2944075 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 8326575 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 4469723 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 4469723 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 222737 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 222737 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 3521 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 3521 # number of UpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 634814 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 634814 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 269350 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 141753 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 4971397 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3578889 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 8961389 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 269350 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 141753 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 4971397 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3578889 # number of overall hits +system.cpu0.l2cache.overall_hits::total 8961389 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 11316 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8593 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 568201 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 1257257 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1845367 # number of ReadReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 608598 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 608598 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 128143 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 128143 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 158369 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 158369 # number of SCUpgradeReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 709409 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 709409 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 11316 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8593 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 568201 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1966666 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 2554776 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 11316 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8593 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 568201 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1966666 # number of overall misses +system.cpu0.l2cache.overall_misses::total 2554776 # number of overall misses +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 280666 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 150346 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5539598 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 4201332 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 10171942 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 4469723 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 4469723 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 831335 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 831335 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 131664 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 131664 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 158369 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 158369 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1344223 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1344223 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 280666 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 150346 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 5539598 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 5545555 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 11516165 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 280666 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 150346 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 5539598 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 5545555 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 11516165 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.057155 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102571 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.299252 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.181417 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.732073 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.732073 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.973258 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.973258 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.525788 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.525788 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056212 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100667 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.353040 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.220132 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.039540 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056212 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100667 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.353040 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.220132 # miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.527747 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.527747 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.057155 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102571 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.354638 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.221843 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.040318 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.057155 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102571 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.354638 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.221843 # miss rate for overall accesses system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -584,47 +584,45 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1542533 # number of writebacks -system.cpu0.l2cache.writebacks::total 1542533 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 1573452 # number of writebacks +system.cpu0.l2cache.writebacks::total 1573452 # number of writebacks system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 10228504 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 10228504 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 32523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 32523 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 4407988 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 818842 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 818842 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 129427 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 156094 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 285521 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1329336 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1329336 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11022820 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17694214 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 359792 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 720614 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 29797440 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 350142740 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 685026670 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1439168 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2882456 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 1039491034 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 3383860 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 20196192 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.158528 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.365236 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 10363949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 10363949 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 32448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 32448 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 4469723 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 831335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 831335 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 131664 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 158369 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 290033 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1344223 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1344223 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 11165446 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17933523 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 16994523 84.15% 84.15% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 3201669 15.85% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 20196192 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -654,45 +652,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 144852 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 144852 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 144852 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 144852 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 144852 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 144041 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 144041 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 144041 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 144041 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 144041 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples -274403872 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -274403872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -274403872 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 112422 89.02% 89.02% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 13865 10.98% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 126287 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144852 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 111414 88.97% 88.97% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 13807 11.03% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 125221 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 144041 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144852 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 126287 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 144041 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 125221 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 126287 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 271139 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 125221 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 269262 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 91720002 # DTB read hits -system.cpu1.dtb.read_misses 112244 # DTB read misses -system.cpu1.dtb.write_hits 82499013 # DTB write hits -system.cpu1.dtb.write_misses 32608 # DTB write misses +system.cpu1.dtb.read_hits 90153061 # DTB read hits +system.cpu1.dtb.read_misses 111753 # DTB read misses +system.cpu1.dtb.write_hits 81132787 # DTB write hits +system.cpu1.dtb.write_misses 32288 # DTB write misses system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 45118 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 44587 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4542 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4554 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 11534 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 91832246 # DTB read accesses -system.cpu1.dtb.write_accesses 82531621 # DTB write accesses +system.cpu1.dtb.perms_faults 11374 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 90264814 # DTB read accesses +system.cpu1.dtb.write_accesses 81165075 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 174219015 # DTB hits -system.cpu1.dtb.misses 144852 # DTB misses -system.cpu1.dtb.accesses 174363867 # DTB accesses +system.cpu1.dtb.hits 171285848 # DTB hits +system.cpu1.dtb.misses 144041 # DTB misses +system.cpu1.dtb.accesses 171429889 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -722,186 +720,187 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 61939 # Table walker walks requested -system.cpu1.itb.walker.walksLong 61939 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 61939 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 61939 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 61939 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 60885 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60885 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 60885 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60885 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60885 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples -274404872 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -274404872 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -274404872 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 54929 99.06% 99.06% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 521 0.94% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 55450 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 53790 99.07% 99.07% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 505 0.93% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 54295 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 61939 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 61939 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60885 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60885 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55450 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 117389 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 485906850 # ITB inst hits -system.cpu1.itb.inst_misses 61939 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 54295 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 54295 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115180 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 478248118 # ITB inst hits +system.cpu1.itb.inst_misses 60885 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 49428 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 49427 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 1118 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 31863 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 31530 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 485968789 # ITB inst accesses -system.cpu1.itb.hits 485906850 # DTB hits -system.cpu1.itb.misses 61939 # DTB misses -system.cpu1.itb.accesses 485968789 # DTB accesses -system.cpu1.numCycles 94354166192 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 478309003 # ITB inst accesses +system.cpu1.itb.hits 478248118 # DTB hits +system.cpu1.itb.misses 60885 # DTB misses +system.cpu1.itb.accesses 478309003 # DTB accesses +system.cpu1.numCycles 94433634550 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 485652916 # Number of instructions committed -system.cpu1.committedOps 571511718 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 524558211 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 375128 # Number of float alu accesses -system.cpu1.num_func_calls 28666071 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 74347572 # number of instructions that are conditional controls -system.cpu1.num_int_insts 524558211 # number of integer instructions -system.cpu1.num_fp_insts 375128 # number of float instructions -system.cpu1.num_int_register_reads 774388464 # number of times the integer registers were read -system.cpu1.num_int_register_writes 417530639 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 610571 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 303256 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 128278137 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 127991607 # number of times the CC registers were written -system.cpu1.num_mem_refs 174340371 # number of memory refs -system.cpu1.num_load_insts 91819242 # Number of load instructions -system.cpu1.num_store_insts 82521129 # Number of store instructions -system.cpu1.num_idle_cycles 93782340058.888657 # Number of idle cycles -system.cpu1.num_busy_cycles 571826133.111340 # Number of busy cycles -system.cpu1.not_idle_fraction 0.006060 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.993940 # Percentage of idle cycles -system.cpu1.Branches 108195111 # Number of branches fetched +system.cpu1.committedInsts 477990846 # Number of instructions committed +system.cpu1.committedOps 562567642 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 516282159 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 374678 # Number of float alu accesses +system.cpu1.num_func_calls 28237407 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 73185792 # number of instructions that are conditional controls +system.cpu1.num_int_insts 516282159 # number of integer instructions +system.cpu1.num_fp_insts 374678 # number of float instructions +system.cpu1.num_int_register_reads 763231058 # number of times the integer registers were read +system.cpu1.num_int_register_writes 411079626 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 608455 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 306456 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 126379788 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 126112608 # number of times the CC registers were written +system.cpu1.num_mem_refs 171406825 # number of memory refs +system.cpu1.num_load_insts 90251973 # Number of load instructions +system.cpu1.num_store_insts 81154852 # Number of store instructions +system.cpu1.num_idle_cycles 93870750285.000458 # Number of idle cycles +system.cpu1.num_busy_cycles 562884264.999552 # Number of busy cycles +system.cpu1.not_idle_fraction 0.005961 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.994039 # Percentage of idle cycles +system.cpu1.Branches 106497601 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 396230726 69.29% 69.29% # Class of executed instruction -system.cpu1.op_class::IntMult 1151823 0.20% 69.49% # Class of executed instruction -system.cpu1.op_class::IntDiv 61886 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 36426 0.01% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.51% # Class of executed instruction -system.cpu1.op_class::MemRead 91819242 16.06% 85.57% # Class of executed instruction -system.cpu1.op_class::MemWrite 82521129 14.43% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 390236864 69.33% 69.33% # Class of executed instruction +system.cpu1.op_class::IntMult 1137629 0.20% 69.53% # Class of executed instruction +system.cpu1.op_class::IntDiv 60962 0.01% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.54% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 37059 0.01% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction +system.cpu1.op_class::MemRead 90251973 16.03% 85.58% # Class of executed instruction +system.cpu1.op_class::MemWrite 81154852 14.42% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 571821232 # Class of executed instruction +system.cpu1.op_class::total 562879339 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 6178 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 6025220 # number of replacements -system.cpu1.dcache.tags.tagsinuse 443.938244 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 168203685 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 6025731 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 27.914237 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 6259 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 5945049 # number of replacements +system.cpu1.dcache.tags.tagsinuse 438.290639 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 165346662 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 5945561 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 27.810103 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 8470277778500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 443.938244 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.867067 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.867067 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 354758936 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 354758936 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 85201700 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 85201700 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 78314445 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 78314445 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188411 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 188411 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 65692 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 65692 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2073864 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 2073864 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2064069 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 2064069 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 163516145 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 163516145 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 163704556 # number of overall hits -system.cpu1.dcache.overall_hits::total 163704556 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 3403274 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 3403274 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1467363 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1467363 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 796168 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 796168 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 438523 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 438523 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 149383 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 149383 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 157982 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 157982 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4870637 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4870637 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 5666805 # number of overall misses -system.cpu1.dcache.overall_misses::total 5666805 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 88604974 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 88604974 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 79781808 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 79781808 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 984579 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 984579 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 504215 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 504215 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2223247 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 2223247 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2222051 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 2222051 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 168386782 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 168386782 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 169371361 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 169371361 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038410 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.038410 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018392 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.018392 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808638 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808638 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.869714 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.869714 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.067191 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.067191 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071097 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071097 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028925 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.028925 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033458 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.033458 # miss rate for overall accesses +system.cpu1.dcache.tags.occ_blocks::cpu1.data 438.290639 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.856036 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.856036 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 348813711 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 76990336 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 76990336 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63447 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 63447 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048907 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 2048907 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 160687900 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 160687900 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 160875754 # number of overall hits +system.cpu1.dcache.overall_hits::total 160875754 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1453140 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1453140 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427052 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 427052 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158842 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 158842 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 4811362 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 4811362 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 5603713 # number of overall misses +system.cpu1.dcache.overall_misses::total 5603713 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 78443476 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 980205 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 980205 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 490499 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 490499 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2209076 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 2209076 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2207749 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 2207749 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 165499262 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 165499262 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 166479467 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 166479467 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.038576 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.038576 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018525 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870648 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870648 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071947 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.033660 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -910,49 +909,49 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 4091318 # number of writebacks -system.cpu1.dcache.writebacks::total 4091318 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 4030826 # number of writebacks +system.cpu1.dcache.writebacks::total 4030826 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4818195 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.412963 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 481143593 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4818707 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 99.849107 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 4741297 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 473560604 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 4741809 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 99.869186 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 8470205816000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.412963 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969557 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969557 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.426080 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969582 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969582 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 976743307 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 976743307 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 481143593 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 481143593 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 481143593 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 481143593 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 481143593 # number of overall hits -system.cpu1.icache.overall_hits::total 481143593 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4818707 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4818707 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4818707 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4818707 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4818707 # number of overall misses -system.cpu1.icache.overall_misses::total 4818707 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 485962300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 485962300 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 485962300 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 485962300 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 485962300 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 485962300 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009916 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.009916 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009916 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.009916 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009916 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.009916 # miss rate for overall accesses +system.cpu1.icache.tags.tag_accesses 961346635 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 961346635 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 473560604 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 473560604 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 473560604 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 473560604 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 473560604 # number of overall hits +system.cpu1.icache.overall_hits::total 473560604 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 4741809 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 4741809 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 4741809 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 4741809 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 4741809 # number of overall misses +system.cpu1.icache.overall_misses::total 4741809 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 478302413 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 478302413 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 478302413 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 478302413 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 478302413 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 478302413 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.009914 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.009914 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009914 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.009914 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.009914 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.009914 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -968,133 +967,132 @@ system.cpu1.l2cache.prefetcher.pfBufferHit 0 # system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 2333825 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13484.024344 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 11006559 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 2349876 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 4.683889 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9726491548000 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5253.379361 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 67.604678 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 75.064726 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2656.476360 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5431.499219 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.320641 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004126 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004582 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.162138 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.331512 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.823000 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 103 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15948 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 59 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 78 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1580 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5821 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4453 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4016 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006287 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.973389 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 257480243 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 257480243 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 323221 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141798 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4279723 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 3095607 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7840349 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 4091318 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 4091318 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 167179 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 167179 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3859 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 3859 # number of UpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 621347 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 621347 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 323221 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141798 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4279723 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3716954 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8461696 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 323221 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141798 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4279723 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3716954 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8461696 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12537 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9802 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 538984 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 1253218 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1814541 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 271117 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 271117 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133664 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 133664 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 157982 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 157982 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 708720 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 708720 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12537 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9802 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 538984 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1961938 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 2523261 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12537 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9802 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 538984 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1961938 # number of overall misses -system.cpu1.l2cache.overall_misses::total 2523261 # number of overall misses -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 335758 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 151600 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4818707 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4348825 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 9654890 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 4091318 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 4091318 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 438296 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 438296 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137523 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 137523 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 157982 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 157982 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1330067 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1330067 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 335758 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 151600 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4818707 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 5678892 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 10984957 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 335758 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 151600 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4818707 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 5678892 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 10984957 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064657 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.111852 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288174 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.187940 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.618571 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.618571 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971939 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971939 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.tags.replacements 2278914 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13451.937852 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10861278 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 2294953 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 4.732680 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5180.760257 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.434503 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.707533 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2828.453932 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5282.581627 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.316209 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004177 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005597 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.172635 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.322423 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.821041 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1583 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5963 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4534 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3771 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 254019378 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 254019378 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 325118 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141158 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4217165 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 3057891 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 7741332 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 4030826 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 4030826 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161366 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 161366 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3865 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 3865 # number of UpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614191 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 614191 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 325118 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141158 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 4217165 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3672082 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8355523 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 325118 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141158 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 4217165 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3672082 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8355523 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 12489 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9780 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 524644 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 1239502 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1786415 # number of ReadReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 265480 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 265480 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 133591 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 133591 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 158842 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 158842 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 701699 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 701699 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 12489 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9780 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 524644 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 1941201 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 2488114 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 12489 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9780 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 524644 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 1941201 # number of overall misses +system.cpu1.l2cache.overall_misses::total 2488114 # number of overall misses +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 337607 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 150938 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4741809 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 4297393 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 9527747 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 4030826 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 4030826 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 426846 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 426846 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 137456 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 137456 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 158842 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 158842 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1315890 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 1315890 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 337607 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 150938 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 4741809 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 5613283 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10843637 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 337607 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 150938 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 4741809 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 5613283 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10843637 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.064795 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.110642 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.288431 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.187496 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.621957 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.621957 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.971882 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.971882 # miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.532845 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.532845 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064657 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.111852 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345479 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.229701 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037339 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064657 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.111852 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345479 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.229701 # miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.533250 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.533250 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.064795 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.110642 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.345823 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.229454 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.036993 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.064795 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.110642 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.345823 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.229454 # miss rate for overall accesses system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1103,53 +1101,51 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 1212706 # number of writebacks -system.cpu1.l2cache.writebacks::total 1212706 # number of writebacks +system.cpu1.l2cache.writebacks::writebacks 1183487 # number of writebacks +system.cpu1.l2cache.writebacks::total 1183487 # number of writebacks system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 9779239 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9779239 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 6380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 6380 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 4091318 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 438296 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 438296 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 137523 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 157982 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 295505 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1330067 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1330067 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9637674 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16942172 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370292 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 840154 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 27790292 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 308397768 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 653382681 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1481168 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3360616 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 966622233 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 3659793 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 19426876 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.180108 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.384277 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 137456 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1315890 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9483878 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 16729164 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 27412486 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 644579516 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 19274314 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 15927941 81.99% 81.99% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 3498935 18.01% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 19426876 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40346 # Transaction distribution -system.iobus.trans_dist::ReadResp 40346 # Transaction distribution -system.iobus.trans_dist::WriteReq 136741 # Transaction distribution -system.iobus.trans_dist::WriteResp 30013 # Transaction distribution +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40295 # Transaction distribution +system.iobus.trans_dist::ReadResp 40295 # Transaction distribution +system.iobus.trans_dist::WriteReq 136634 # Transaction distribution +system.iobus.trans_dist::WriteResp 29906 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47950 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47636 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1164,13 +1160,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122884 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122570 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231208 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231208 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354174 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47970 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353858 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47656 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1185,54 +1181,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155991 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338848 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7496933 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115586 # number of replacements -system.iocache.tags.tagsinuse 11.286927 # Cycle average of tags in use +system.iobus.pkt_size::total 7496611 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115585 # number of replacements +system.iocache.tags.tagsinuse 11.290896 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115602 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115601 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 9107775783009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.855232 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.431695 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.240952 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.464481 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705433 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.851982 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 7.438915 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.240749 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.464932 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705681 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1040802 # Number of tag accesses -system.iocache.tags.data_accesses 1040802 # Number of data accesses +system.iocache.tags.tag_accesses 1040793 # Number of tag accesses +system.iocache.tags.data_accesses 1040793 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8876 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8913 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses -system.iocache.demand_misses::total 8917 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8876 # number of demand (read+write) misses +system.iocache.demand_misses::total 8916 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8877 # number of overall misses -system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.overall_misses::realview.ide 8876 # number of overall misses +system.iocache.overall_misses::total 8916 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8876 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8913 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8876 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8916 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8876 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8916 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1257,205 +1253,205 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106694 # number of writebacks system.iocache.writebacks::total 106694 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1764050 # number of replacements -system.l2c.tags.tagsinuse 62893.103184 # Cycle average of tags in use -system.l2c.tags.total_refs 3693923 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1823047 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.026236 # Average number of references to valid blocks. +system.l2c.tags.replacements 1759966 # number of replacements +system.l2c.tags.tagsinuse 62842.185631 # Cycle average of tags in use +system.l2c.tags.total_refs 3707512 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1818705 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.038545 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 482634500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 35252.715261 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 32.297168 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 36.889266 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3199.431904 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6870.253722 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 308.072507 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 447.332489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2890.642136 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 13855.468731 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.537914 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000493 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000563 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.048819 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.104832 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004701 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.006826 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.044108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.211418 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.959673 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 209 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 58788 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 35219.340736 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 46.907098 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 57.886687 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3338.956610 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6965.181537 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.496433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 430.211698 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2959.236338 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 13514.968494 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.537404 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000716 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000883 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.050948 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.106280 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004723 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.006565 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.045154 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.206222 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.958896 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 231 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 58508 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 204 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 542 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 3602 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 5588 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 49009 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003189 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.897034 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 66315846 # Number of tag accesses -system.l2c.tags.data_accesses 66315846 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5920 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4325 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 492739 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 723130 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3764 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 496903 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 707011 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2439522 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2755239 # number of Writeback hits -system.l2c.Writeback_hits::total 2755239 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 115462 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 102925 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 218387 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 13978 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 10743 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 24721 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 1494 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 1282 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2776 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 196550 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 177871 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 374421 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5920 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4325 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 492739 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 919680 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 5730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 496903 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 884882 # number of demand (read+write) hits -system.l2c.demand_hits::total 2813943 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5920 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4325 # number of overall hits -system.l2c.overall_hits::cpu0.inst 492739 # number of overall hits -system.l2c.overall_hits::cpu0.data 919680 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 5730 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3764 # number of overall hits -system.l2c.overall_hits::cpu1.inst 496903 # number of overall hits -system.l2c.overall_hits::cpu1.data 884882 # number of overall hits -system.l2c.overall_hits::total 2813943 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2339 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1938 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 57739 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 182657 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3510 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 3482 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 42081 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 192722 # number of ReadReq misses -system.l2c.ReadReq_misses::total 486468 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 475939 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 161383 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 637322 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 57732 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 55051 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 112783 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 7557 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 7409 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 14966 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 376574 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 420815 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 797389 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2339 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1938 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 57739 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 559231 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3510 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 3482 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 42081 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 613537 # number of demand (read+write) misses -system.l2c.demand_misses::total 1283857 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2339 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1938 # number of overall misses -system.l2c.overall_misses::cpu0.inst 57739 # number of overall misses -system.l2c.overall_misses::cpu0.data 559231 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3510 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 3482 # number of overall misses -system.l2c.overall_misses::cpu1.inst 42081 # number of overall misses -system.l2c.overall_misses::cpu1.data 613537 # number of overall misses -system.l2c.overall_misses::total 1283857 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8259 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 6263 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 550478 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 905787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 9240 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 7246 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 538984 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 899733 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2925990 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2755239 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2755239 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 591401 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 264308 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 855709 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 71710 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 65794 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 137504 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 9051 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 8691 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 17742 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 573124 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 598686 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 1171810 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8259 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 6263 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 550478 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1478911 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 9240 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 7246 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 538984 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 1498419 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 4097800 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8259 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 6263 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 550478 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1478911 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 9240 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 7246 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 538984 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 1498419 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 4097800 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309436 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.104889 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.201656 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.480541 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.078075 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.214199 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.166258 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.804765 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.610587 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.744788 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805076 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.836718 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.820216 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.834935 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.852491 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.843535 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.657055 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.702898 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.680476 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.309436 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.104889 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.378137 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.480541 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.078075 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.409456 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.313304 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.283206 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.309436 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.104889 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.378137 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.379870 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.480541 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.078075 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.409456 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.313304 # miss rate for overall accesses +system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 549 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 3406 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5650 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 48840 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.003525 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.892761 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 66406004 # Number of tag accesses +system.l2c.tags.data_accesses 66406004 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 6334 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4677 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 509782 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 744386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5569 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3610 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 483417 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 692017 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2449792 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2756939 # number of Writeback hits +system.l2c.Writeback_hits::total 2756939 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 121538 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 97977 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 219515 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 13827 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 10932 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 24759 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 1566 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 1304 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 2870 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 202688 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 171255 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 373943 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 6334 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4677 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 509782 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 947074 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 5569 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3610 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 483417 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 863272 # number of demand (read+write) hits +system.l2c.demand_hits::total 2823735 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 6334 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4677 # number of overall hits +system.l2c.overall_hits::cpu0.inst 509782 # number of overall hits +system.l2c.overall_hits::cpu0.data 947074 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 5569 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3610 # number of overall hits +system.l2c.overall_hits::cpu1.inst 483417 # number of overall hits +system.l2c.overall_hits::cpu1.data 863272 # number of overall hits +system.l2c.overall_hits::total 2823735 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 2407 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2011 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 58419 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 184134 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3483 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 3456 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 41227 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 189746 # number of ReadReq misses +system.l2c.ReadReq_misses::total 484883 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 479213 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 160846 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 640059 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 58018 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 53853 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 111871 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 7722 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7423 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 15145 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 377543 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 418309 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 795852 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 2407 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2011 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 58419 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 561677 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3483 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 3456 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 41227 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 608055 # number of demand (read+write) misses +system.l2c.demand_misses::total 1280735 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 2407 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2011 # number of overall misses +system.l2c.overall_misses::cpu0.inst 58419 # number of overall misses +system.l2c.overall_misses::cpu0.data 561677 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3483 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 3456 # number of overall misses +system.l2c.overall_misses::cpu1.inst 41227 # number of overall misses +system.l2c.overall_misses::cpu1.data 608055 # number of overall misses +system.l2c.overall_misses::total 1280735 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8741 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 6688 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 568201 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 928520 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 9052 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 7066 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 524644 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 881763 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2934675 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2756939 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2756939 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 600751 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 258823 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 859574 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 71845 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 64785 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 136630 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 9288 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 8727 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 18015 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 580231 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 589564 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 1169795 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8741 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 6688 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 568201 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1508751 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 9052 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 7066 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 524644 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 1471327 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 4104470 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8741 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 6688 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 568201 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1508751 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 9052 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 7066 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 524644 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 1471327 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 4104470 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.300688 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.102814 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.198309 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.489103 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.078581 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.215189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.165225 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.797690 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.621452 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.744623 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.807544 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.831257 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.818788 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.831395 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.850579 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.840688 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.650677 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.709523 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.680335 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.300688 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.102814 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.372279 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.489103 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.078581 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.413270 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.312034 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275369 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.300688 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.102814 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.372279 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.384777 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.489103 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.078581 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.413270 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.312034 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1464,49 +1460,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1467678 # number of writebacks -system.l2c.writebacks::total 1467678 # number of writebacks +system.l2c.writebacks::writebacks 1464604 # number of writebacks +system.l2c.writebacks::total 1464604 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 577534 # Transaction distribution -system.membus.trans_dist::ReadResp 577534 # Transaction distribution -system.membus.trans_dist::WriteReq 38903 # Transaction distribution -system.membus.trans_dist::WriteResp 38903 # Transaction distribution -system.membus.trans_dist::Writeback 1574372 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 739425 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 739425 # Transaction distribution -system.membus.trans_dist::UpgradeReq 325897 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 311300 # Transaction distribution -system.membus.trans_dist::UpgradeResp 149445 # Transaction distribution -system.membus.trans_dist::ReadExReq 961374 # Transaction distribution -system.membus.trans_dist::ReadExResp 780321 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122884 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 575939 # Transaction distribution +system.membus.trans_dist::ReadResp 575939 # Transaction distribution +system.membus.trans_dist::WriteReq 38831 # Transaction distribution +system.membus.trans_dist::WriteResp 38831 # Transaction distribution +system.membus.trans_dist::Writeback 1571298 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 742240 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 742240 # Transaction distribution +system.membus.trans_dist::UpgradeReq 327418 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 314341 # Transaction distribution +system.membus.trans_dist::UpgradeResp 148936 # Transaction distribution +system.membus.trans_dist::ReadExReq 965776 # Transaction distribution +system.membus.trans_dist::ReadExResp 778482 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27406 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6326067 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 6476449 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337984 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337984 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6814433 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155991 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6332069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 6482289 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6820271 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215692580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 215903587 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14229504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 230133091 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215456868 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 215667865 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 229897305 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 4407750 # Request fanout histogram +system.membus.snoop_fanout::samples 4414869 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 4407750 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 4414869 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 4407750 # Request fanout histogram +system.membus.snoop_fanout::total 4414869 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1549,35 +1545,35 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 3699896 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 3699896 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38903 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38903 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2755239 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 855709 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 855709 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 328922 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 314076 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 642998 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 1352863 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 1352863 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8525495 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7410482 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 15935977 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 295216066 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 254408545 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 549624611 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 117315 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 9340198 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.012381 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.110581 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 117306 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 9224553 98.76% 98.76% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115645 1.24% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 9340198 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt index 70b8700c6..b381100ef 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-atomic/stats.txt @@ -1,56 +1,56 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111151 # Number of seconds simulated -sim_ticks 51111150553500 # Number of ticks simulated -final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111153 # Number of seconds simulated +sim_ticks 51111152682000 # Number of ticks simulated +final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1336104 # Simulator instruction rate (inst/s) -host_op_rate 1570142 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 69344550867 # Simulator tick rate (ticks/s) -host_mem_usage 712616 # Number of bytes of host memory used -host_seconds 737.06 # Real time elapsed on the host -sim_insts 984789519 # Number of instructions simulated -sim_ops 1157289961 # Number of ops (including micro ops) simulated +host_inst_rate 1276359 # Simulator instruction rate (inst/s) +host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66258489115 # Simulator tick rate (ticks/s) +host_mem_usage 712024 # Number of bytes of host memory used +host_seconds 771.39 # Real time elapsed on the host +sim_insts 984570519 # Number of instructions simulated +sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 411136 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 373504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5556020 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 75320200 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory -system.physmem.bytes_read::total 82098556 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5556020 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5556020 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 412352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 376512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5562740 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 74833672 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory +system.physmem.bytes_read::total 81627068 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103042944 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298148 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 6424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 5836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 127220 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1176891 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1323210 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613712 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103063524 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 6443 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 5883 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 127325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1169289 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315843 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610046 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616285 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 8044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 7308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 108705 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1473655 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1606275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 108705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108705 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020647 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1612619 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 8068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 7367 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 108836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1464136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1597050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016056 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 8044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 7308 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 108705 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1474058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3627324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2016459 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 8068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 7367 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 108836 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1464539 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3613509 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -103,45 +103,45 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 265618 # Table walker walks requested -system.cpu.dtb.walker.walksLong 265618 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walkWaitTime::samples 265618 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 265618 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 265618 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 265715 # Table walker walks requested +system.cpu.dtb.walker.walksLong 265715 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walkWaitTime::samples 265715 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 265715 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 265715 # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 204344 89.54% 89.54% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 23878 10.46% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 228222 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265618 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 204282 89.47% 89.47% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 24037 10.53% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 228319 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 265715 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265618 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228222 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 265715 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 228319 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228222 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 493840 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 228319 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 494034 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 184057973 # DTB read hits -system.cpu.dtb.read_misses 194269 # DTB read misses -system.cpu.dtb.write_hits 168276300 # DTB write hits -system.cpu.dtb.write_misses 71349 # DTB write misses +system.cpu.dtb.read_hits 184014035 # DTB read hits +system.cpu.dtb.read_misses 194198 # DTB read misses +system.cpu.dtb.write_hits 168232768 # DTB write hits +system.cpu.dtb.write_misses 71517 # DTB write misses system.cpu.dtb.flush_tlb 11 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 81439 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 82353 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 9105 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 9303 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 21651 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 184252242 # DTB read accesses -system.cpu.dtb.write_accesses 168347649 # DTB write accesses +system.cpu.dtb.read_accesses 184208233 # DTB read accesses +system.cpu.dtb.write_accesses 168304285 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 352334273 # DTB hits -system.cpu.dtb.misses 265618 # DTB misses -system.cpu.dtb.accesses 352599891 # DTB accesses +system.cpu.dtb.hits 352246803 # DTB hits +system.cpu.dtb.misses 265715 # DTB misses +system.cpu.dtb.accesses 352512518 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -171,26 +171,26 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 126829 # Table walker walks requested -system.cpu.itb.walker.walksLong 126829 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walkWaitTime::samples 126829 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 126829 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 126829 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 126837 # Table walker walks requested +system.cpu.itb.walker.walksLong 126837 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walkWaitTime::samples 126837 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 126837 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 126837 # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 113566 99.02% 99.02% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1125 0.98% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 114691 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 113576 99.02% 99.02% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1123 0.98% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 114699 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126829 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 126829 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 126837 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 126837 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114691 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 114691 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 241520 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 985266544 # ITB inst hits -system.cpu.itb.inst_misses 126829 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 114699 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 114699 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 241536 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 985047321 # ITB inst hits +system.cpu.itb.inst_misses 126837 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -199,46 +199,46 @@ system.cpu.itb.flush_tlb 11 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 49771 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 1139 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 57079 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 58174 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 985393373 # ITB inst accesses -system.cpu.itb.hits 985266544 # DTB hits -system.cpu.itb.misses 126829 # DTB misses -system.cpu.itb.accesses 985393373 # DTB accesses -system.cpu.numCycles 102222317883 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 985174158 # ITB inst accesses +system.cpu.itb.hits 985047321 # DTB hits +system.cpu.itb.misses 126837 # DTB misses +system.cpu.itb.accesses 985174158 # DTB accesses +system.cpu.numCycles 102222322140 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 984789519 # Number of instructions committed -system.cpu.committedOps 1157289961 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 1060698532 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 880773 # Number of float alu accesses -system.cpu.num_func_calls 57075493 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 151966445 # number of instructions that are conditional controls -system.cpu.num_int_insts 1060698532 # number of integer instructions -system.cpu.num_fp_insts 880773 # number of float instructions -system.cpu.num_int_register_reads 1564314393 # number of times the integer registers were read -system.cpu.num_int_register_writes 842633326 # number of times the integer registers were written +system.cpu.committedInsts 984570519 # Number of instructions committed +system.cpu.committedOps 1157031967 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 1060455466 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 880805 # Number of float alu accesses +system.cpu.num_func_calls 57056367 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 151940834 # number of instructions that are conditional controls +system.cpu.num_int_insts 1060455466 # number of integer instructions +system.cpu.num_fp_insts 880805 # number of float instructions +system.cpu.num_int_register_reads 1564002170 # number of times the integer registers were read +system.cpu.num_int_register_writes 842444791 # number of times the integer registers were written system.cpu.num_fp_register_reads 1418999 # number of times the floating registers were read -system.cpu.num_fp_register_writes 747792 # number of times the floating registers were written -system.cpu.num_cc_register_reads 264443211 # number of times the CC registers were read -system.cpu.num_cc_register_writes 263865511 # number of times the CC registers were written -system.cpu.num_mem_refs 352552781 # number of memory refs -system.cpu.num_load_insts 184224242 # Number of load instructions -system.cpu.num_store_insts 168328539 # Number of store instructions -system.cpu.num_idle_cycles 101064381138.333679 # Number of idle cycles -system.cpu.num_busy_cycles 1157936744.666323 # Number of busy cycles -system.cpu.not_idle_fraction 0.011328 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.988672 # Percentage of idle cycles -system.cpu.Branches 220135160 # Number of branches fetched +system.cpu.num_fp_register_writes 747920 # number of times the floating registers were written +system.cpu.num_cc_register_reads 264407058 # number of times the CC registers were read +system.cpu.num_cc_register_writes 263829403 # number of times the CC registers were written +system.cpu.num_mem_refs 352465606 # number of memory refs +system.cpu.num_load_insts 184180431 # Number of load instructions +system.cpu.num_store_insts 168285175 # Number of store instructions +system.cpu.num_idle_cycles 101064643603.520065 # Number of idle cycles +system.cpu.num_busy_cycles 1157678536.479939 # Number of busy cycles +system.cpu.not_idle_fraction 0.011325 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.988675 # Percentage of idle cycles +system.cpu.Branches 220088562 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 802806903 69.33% 69.33% # Class of executed instruction -system.cpu.op_class::IntMult 2355402 0.20% 69.53% # Class of executed instruction -system.cpu.op_class::IntDiv 101851 0.01% 69.54% # Class of executed instruction +system.cpu.op_class::IntAlu 802636616 69.33% 69.33% # Class of executed instruction +system.cpu.op_class::IntMult 2354747 0.20% 69.54% # Class of executed instruction +system.cpu.op_class::IntDiv 101759 0.01% 69.54% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.54% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.54% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.54% # Class of executed instruction @@ -265,93 +265,93 @@ system.cpu.op_class::SimdFloatMisc 107822 0.01% 69.55% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.55% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu.op_class::MemRead 184224242 15.91% 85.46% # Class of executed instruction -system.cpu.op_class::MemWrite 168328539 14.54% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 184180431 15.91% 85.46% # Class of executed instruction +system.cpu.op_class::MemWrite 168285175 14.54% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1157924802 # Class of executed instruction +system.cpu.op_class::total 1157666593 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 11615783 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 340859576 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 11616295 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 29.343227 # Average number of references to valid blocks. +system.cpu.dcache.tags.replacements 11612141 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 340776008 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 29.345233 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.999718 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.999719 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1421519854 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1421519854 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 171606610 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 171606610 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 159566138 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 159566138 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 424146 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 424146 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337798 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 337798 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310377 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 4310377 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4563246 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4563246 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 331172748 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 331172748 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 331596894 # number of overall hits -system.cpu.dcache.overall_hits::total 331596894 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 6013361 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 6013361 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2569466 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2569466 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1584813 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1584813 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245259 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1245259 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 254671 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 254671 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1421167352 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1421167352 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 171567259 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 171567259 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 159522870 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 159522870 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 424020 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 424020 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 337709 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 4310545 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 4310545 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 4562464 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 331090129 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 331090129 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 331514149 # number of overall hits +system.cpu.dcache.overall_hits::total 331514149 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 6010080 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 6010080 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2570257 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2570257 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1584397 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1584397 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1245349 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 253721 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 253721 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 1 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 8582827 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 8582827 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 10167640 # number of overall misses -system.cpu.dcache.overall_misses::total 10167640 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 177619971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 177619971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 162135604 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 162135604 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008959 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 2008959 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583057 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1583057 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4565048 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4565048 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4563247 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4563247 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 339755575 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 339755575 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 341764534 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 341764534 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.033855 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015848 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015848 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788873 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.788873 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786617 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786617 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055787 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.data 8580337 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 8580337 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 10164734 # number of overall misses +system.cpu.dcache.overall_misses::total 10164734 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 177577339 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 162093127 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 2008417 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 2008417 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4564266 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 339670466 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 341678883 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 341678883 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.033845 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.033845 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015857 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.788879 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.788879 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.055589 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.055589 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.025262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.029750 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.029750 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.025261 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.029749 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -360,49 +360,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 8923646 # number of writebacks -system.cpu.dcache.writebacks::total 8923646 # number of writebacks +system.cpu.dcache.writebacks::writebacks 8921315 # number of writebacks +system.cpu.dcache.writebacks::total 8921315 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 14287218 # number of replacements +system.cpu.icache.tags.replacements 14295641 # number of replacements system.cpu.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 971093500 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 14287730 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 67.966955 # Average number of references to valid blocks. +system.cpu.icache.tags.total_refs 970865862 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::cpu.inst 511.984599 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 999668970 # Number of tag accesses -system.cpu.icache.tags.data_accesses 999668970 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 971093500 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 971093500 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 971093500 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 971093500 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 971093500 # number of overall hits -system.cpu.icache.overall_hits::total 971093500 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 14287735 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 14287735 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 14287735 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 14287735 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 14287735 # number of overall misses -system.cpu.icache.overall_misses::total 14287735 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 985381235 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 985381235 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 985381235 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 985381235 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 985381235 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 985381235 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014500 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014500 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014500 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014500 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014500 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses +system.cpu.icache.tags.tag_accesses 999458178 # Number of tag accesses +system.cpu.icache.tags.data_accesses 999458178 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 970865862 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 970865862 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 970865862 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 970865862 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 970865862 # number of overall hits +system.cpu.icache.overall_hits::total 970865862 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 14296158 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 14296158 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 14296158 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 14296158 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 14296158 # number of overall misses +system.cpu.icache.overall_misses::total 14296158 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 985162020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 985162020 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 985162020 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014511 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.014511 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.014511 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,130 +412,129 @@ system.cpu.icache.avg_blocked_cycles::no_targets nan system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1726949 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65261.456081 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 29978708 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1789688 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 16.750801 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 1722692 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65341.862502 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 29983424 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1785989 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 16.788135 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 37844.065183 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 274.121350 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 368.710071 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6273.950851 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 20500.608627 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.577455 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004183 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.005626 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095733 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.312814 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 248 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62491 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 241 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54019 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003784 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.953537 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 290358067 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 290358067 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 511193 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 258912 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 14203603 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 7508372 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 22482080 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 8923646 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 8923646 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 697316 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 697316 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 11232 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 11232 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1684603 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1684603 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 511193 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 258912 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 14203603 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 9192975 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 24166683 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 511193 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 258912 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 14203603 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 9192975 # number of overall hits -system.cpu.l2cache.overall_hits::total 24166683 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6424 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5836 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 84132 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 344473 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 440865 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 547943 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 547943 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 40028 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 40028 # number of UpgradeReq misses +system.cpu.l2cache.tags.occ_blocks::writebacks 37141.715219 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 310.196824 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 443.735041 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6261.263092 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 21184.952326 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.566738 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004733 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006771 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.095539 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.323257 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 278 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 63019 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 278 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54669 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004242 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.961594 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 290307620 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 290307620 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 506612 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 255623 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 14211921 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 7504232 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 22478388 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 8921315 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 8921315 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 694333 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 694333 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 11223 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 11223 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1692610 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1692610 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 506612 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 255623 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 14211921 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 9196842 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 24170998 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 506612 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 255623 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 14211921 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 9196842 # number of overall hits +system.cpu.l2cache.overall_hits::total 24170998 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 6443 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5883 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 84237 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 343966 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 440529 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 551016 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 551016 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 39917 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 39917 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 1 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 833603 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 833603 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 6424 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 5836 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 84132 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 1178076 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 1274468 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 6424 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 5836 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 84132 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 1178076 # number of overall misses -system.cpu.l2cache.overall_misses::total 1274468 # number of overall misses -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 517617 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 264748 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 14287735 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 7852845 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 22922945 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 8923646 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 8923646 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245259 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245259 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51260 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 51260 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 826507 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 826507 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 6443 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 5883 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 84237 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 1170473 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 1267036 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 6443 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 5883 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 84237 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 1170473 # number of overall misses +system.cpu.l2cache.overall_misses::total 1267036 # number of overall misses +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 513055 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 261506 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 14296158 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 7848198 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 22918917 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 51140 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 51140 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 1 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2518206 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2518206 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 517617 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 264748 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 14287735 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 10371051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 25441151 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 517617 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 264748 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 14287735 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 10371051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 25441151 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012411 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022044 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005888 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043866 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019232 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.440023 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.440023 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780882 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780882 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2519117 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 513055 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 261506 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 14296158 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 10367315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 25438034 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 513055 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 261506 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 14296158 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 10367315 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 25438034 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.012558 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.022497 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005892 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.043827 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019221 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.442459 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.442459 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780544 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780544 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.331031 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.331031 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012411 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022044 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005888 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.113593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.050095 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012411 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022044 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005888 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.113593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.050095 # miss rate for overall accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.328094 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.012558 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.022497 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005892 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.112900 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.049809 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.012558 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.022497 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005892 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.112900 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.049809 # miss rate for overall accesses system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -544,53 +543,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1507081 # number of writebacks -system.cpu.l2cache.writebacks::total 1507081 # number of writebacks +system.cpu.l2cache.writebacks::writebacks 1503415 # number of writebacks +system.cpu.l2cache.writebacks::total 1503415 # number of writebacks system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 23368238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 23368238 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 8923646 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245259 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 51260 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 23372119 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 51140 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 51261 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28661720 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32393426 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758172 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543680 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 63356998 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032688 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6174720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2238542120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 116335 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 36145396 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003196 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.056442 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 51141 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 28678566 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 32383245 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 758224 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1543944 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 63363979 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 3032896 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 116338 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 36029878 99.68% 99.68% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 36145396 # Request fanout histogram -system.iobus.trans_dist::ReadReq 40296 # Transaction distribution -system.iobus.trans_dist::ReadResp 40296 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 29957 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram +system.iobus.trans_dist::ReadReq 40246 # Transaction distribution +system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.iobus.trans_dist::WriteReq 136515 # Transaction distribution +system.iobus.trans_dist::WriteResp 29851 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -605,13 +602,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -626,54 +623,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115460 # number of replacements +system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115463 # number of replacements system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses +system.iocache.tags.tag_accesses 1039686 # Number of tag accesses +system.iocache.tags.data_accesses 1039686 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses -system.iocache.demand_misses::total 8854 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses +system.iocache.demand_misses::total 8857 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8814 # number of overall misses -system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.overall_misses::realview.ide 8817 # number of overall misses +system.iocache.overall_misses::total 8857 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -698,46 +695,46 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 526448 # Transaction distribution -system.membus.trans_dist::ReadResp 526448 # Transaction distribution -system.membus.trans_dist::WriteReq 33712 # Transaction distribution -system.membus.trans_dist::WriteResp 33712 # Transaction distribution -system.membus.trans_dist::Writeback 1613712 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 654602 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 654602 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40596 # Transaction distribution +system.membus.trans_dist::ReadReq 526062 # Transaction distribution +system.membus.trans_dist::ReadResp 526062 # Transaction distribution +system.membus.trans_dist::WriteReq 33606 # Transaction distribution +system.membus.trans_dist::WriteResp 33606 # Transaction distribution +system.membus.trans_dist::Writeback 1610046 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 657675 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 657675 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40484 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40597 # Transaction distribution -system.membus.trans_dist::ReadExReq 833043 # Transaction distribution -system.membus.trans_dist::ReadExResp 833043 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 40485 # Transaction distribution +system.membus.trans_dist::ReadExReq 825948 # Transaction distribution +system.membus.trans_dist::ReadExResp 825948 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5323339 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5452849 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5790516 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5310733 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 5439925 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5777598 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 213244448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 213413816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 227631160 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 212730912 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 212899962 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3591670 # Request fanout histogram +system.membus.snoop_fanout::samples 3583537 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3591670 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3591670 # Request fanout histogram +system.membus.snoop_fanout::total 3583537 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt index cd0cb8f17..fb0fbc4a7 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing-dual/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 47.410782 # Number of seconds simulated -sim_ticks 47410781652000 # Number of ticks simulated -final_tick 47410781652000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 47.367818 # Number of seconds simulated +sim_ticks 47367817574000 # Number of ticks simulated +final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 787433 # Simulator instruction rate (inst/s) -host_op_rate 926573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 41969003911 # Simulator tick rate (ticks/s) -host_mem_usage 699232 # Number of bytes of host memory used -host_seconds 1129.66 # Real time elapsed on the host -sim_insts 889532971 # Number of instructions simulated -sim_ops 1046714541 # Number of ops (including micro ops) simulated +host_inst_rate 678056 # Simulator instruction rate (inst/s) +host_op_rate 798173 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38043399524 # Simulator tick rate (ticks/s) +host_mem_usage 751768 # Number of bytes of host memory used +host_seconds 1245.10 # Real time elapsed on the host +sim_insts 844246943 # Number of instructions simulated +sim_ops 993804803 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 154432 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 156800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3551860 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 14084888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 14587840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 66560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 59904 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2809592 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 8562400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 11943680 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 428992 # Number of bytes read from this memory -system.physmem.bytes_read::total 56406948 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3551860 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2809592 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 6361452 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 74353408 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 36928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 40576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 2794548 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 9993048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 9568064 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 72256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 86016 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2509048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 8105888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 7582272 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 437184 # Number of bytes read from this memory +system.physmem.bytes_read::total 41225828 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 2794548 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2509048 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5303596 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 61292480 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory -system.physmem.bytes_written::total 74374224 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 2413 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2450 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 95905 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 220098 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 227935 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 1040 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 43988 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 133802 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 186620 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6703 # Number of read requests responded to by this memory -system.physmem.num_reads::total 921890 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1161772 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 61313296 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 634 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 84072 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 156163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 149501 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1129 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1344 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 39292 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 126669 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 118473 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6831 # Number of read requests responded to by this memory +system.physmem.num_reads::total 684685 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 957695 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1164375 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3307 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 74917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 297082 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 307690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1404 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 1264 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 59261 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 180600 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 251919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 9048 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1189749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 74917 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 59261 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 134177 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1568281 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 960298 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 857 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 58997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 210967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 201995 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1525 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 1816 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 52969 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 171126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 160072 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 9230 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 870334 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 58997 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 52969 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 111966 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1293969 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 439 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1568720 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1568281 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3307 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 74917 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 297521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 307690 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 1264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 59261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 180600 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 251919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 9048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2758469 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 921890 # Number of read requests accepted -system.physmem.writeReqs 1829645 # Number of write requests accepted -system.physmem.readBursts 921890 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1829645 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 58978368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue -system.physmem.bytesWritten 116660480 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 56406948 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 116951504 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6803 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 114603 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 54393 # Per bank write bursts -system.physmem.perBankRdBursts::1 56084 # Per bank write bursts -system.physmem.perBankRdBursts::2 54659 # Per bank write bursts -system.physmem.perBankRdBursts::3 58883 # Per bank write bursts -system.physmem.perBankRdBursts::4 54974 # Per bank write bursts -system.physmem.perBankRdBursts::5 58047 # Per bank write bursts -system.physmem.perBankRdBursts::6 51881 # Per bank write bursts -system.physmem.perBankRdBursts::7 58759 # Per bank write bursts -system.physmem.perBankRdBursts::8 52533 # Per bank write bursts -system.physmem.perBankRdBursts::9 95950 # Per bank write bursts -system.physmem.perBankRdBursts::10 53815 # Per bank write bursts -system.physmem.perBankRdBursts::11 56993 # Per bank write bursts -system.physmem.perBankRdBursts::12 52328 # Per bank write bursts -system.physmem.perBankRdBursts::13 55917 # Per bank write bursts -system.physmem.perBankRdBursts::14 52932 # Per bank write bursts -system.physmem.perBankRdBursts::15 53389 # Per bank write bursts -system.physmem.perBankWrBursts::0 113787 # Per bank write bursts -system.physmem.perBankWrBursts::1 117144 # Per bank write bursts -system.physmem.perBankWrBursts::2 115098 # Per bank write bursts -system.physmem.perBankWrBursts::3 118536 # Per bank write bursts -system.physmem.perBankWrBursts::4 116769 # Per bank write bursts -system.physmem.perBankWrBursts::5 120895 # Per bank write bursts -system.physmem.perBankWrBursts::6 109520 # Per bank write bursts -system.physmem.perBankWrBursts::7 112924 # Per bank write bursts -system.physmem.perBankWrBursts::8 111914 # Per bank write bursts -system.physmem.perBankWrBursts::9 117541 # Per bank write bursts -system.physmem.perBankWrBursts::10 111832 # Per bank write bursts -system.physmem.perBankWrBursts::11 116807 # Per bank write bursts -system.physmem.perBankWrBursts::12 108182 # Per bank write bursts -system.physmem.perBankWrBursts::13 109739 # Per bank write bursts -system.physmem.perBankWrBursts::14 110202 # Per bank write bursts -system.physmem.perBankWrBursts::15 111930 # Per bank write bursts +system.physmem.bw_write::total 1294408 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1293969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 780 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 857 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 58997 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 211406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 201995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 1816 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 52969 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 171127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 160072 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 9230 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2164742 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 684685 # Number of read requests accepted +system.physmem.writeReqs 1596629 # Number of write requests accepted +system.physmem.readBursts 684685 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1596629 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 43802304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 17536 # Total number of bytes read from write queue +system.physmem.bytesWritten 99044160 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 41225828 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 102038480 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 274 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 49035 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 111704 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 42136 # Per bank write bursts +system.physmem.perBankRdBursts::1 44080 # Per bank write bursts +system.physmem.perBankRdBursts::2 34958 # Per bank write bursts +system.physmem.perBankRdBursts::3 41288 # Per bank write bursts +system.physmem.perBankRdBursts::4 39326 # Per bank write bursts +system.physmem.perBankRdBursts::5 49165 # Per bank write bursts +system.physmem.perBankRdBursts::6 40428 # Per bank write bursts +system.physmem.perBankRdBursts::7 47118 # Per bank write bursts +system.physmem.perBankRdBursts::8 36254 # Per bank write bursts +system.physmem.perBankRdBursts::9 81044 # Per bank write bursts +system.physmem.perBankRdBursts::10 36070 # Per bank write bursts +system.physmem.perBankRdBursts::11 40557 # Per bank write bursts +system.physmem.perBankRdBursts::12 34453 # Per bank write bursts +system.physmem.perBankRdBursts::13 38158 # Per bank write bursts +system.physmem.perBankRdBursts::14 37145 # Per bank write bursts +system.physmem.perBankRdBursts::15 42231 # Per bank write bursts +system.physmem.perBankWrBursts::0 97165 # Per bank write bursts +system.physmem.perBankWrBursts::1 99476 # Per bank write bursts +system.physmem.perBankWrBursts::2 95543 # Per bank write bursts +system.physmem.perBankWrBursts::3 98326 # Per bank write bursts +system.physmem.perBankWrBursts::4 92692 # Per bank write bursts +system.physmem.perBankWrBursts::5 102230 # Per bank write bursts +system.physmem.perBankWrBursts::6 96747 # Per bank write bursts +system.physmem.perBankWrBursts::7 98806 # Per bank write bursts +system.physmem.perBankWrBursts::8 93672 # Per bank write bursts +system.physmem.perBankWrBursts::9 100275 # Per bank write bursts +system.physmem.perBankWrBursts::10 92352 # Per bank write bursts +system.physmem.perBankWrBursts::11 96579 # Per bank write bursts +system.physmem.perBankWrBursts::12 94667 # Per bank write bursts +system.physmem.perBankWrBursts::13 97213 # Per bank write bursts +system.physmem.perBankWrBursts::14 92658 # Per bank write bursts +system.physmem.perBankWrBursts::15 99164 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 47410778671000 # Total gap between requests +system.physmem.numWrRetry 352 # Number of times write queue was full causing retry +system.physmem.totGap 47367814519500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43195 # Read request sizes (log2) system.physmem.readPktSize::3 37 # Read request sizes (log2) system.physmem.readPktSize::4 5 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 878653 # Read request sizes (log2) +system.physmem.readPktSize::6 641448 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 2 # Write request sizes (log2) system.physmem.writePktSize::3 2601 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1827042 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 652905 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 75815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40303 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 33479 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29162 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 25818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 22543 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 19321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 15689 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2492 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1008 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 460 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 351 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 292 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 82 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1594026 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 510577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 50448 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 25290 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 18597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 16379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 14128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 12156 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 9819 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 296 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 233 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -188,181 +188,170 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 54841 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 74169 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 96317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 106970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 112981 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 116642 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 107891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 106380 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 105711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 108843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 109894 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 108607 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 105867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 106408 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 98436 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 96529 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 94372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 91211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 4176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 3101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 1802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 725 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 589 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 554 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 302 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 273 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 268 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1000117 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 175.617981 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 106.594305 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 248.236984 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 645970 64.59% 64.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 191036 19.10% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 45051 4.50% 88.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 21747 2.17% 90.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15328 1.53% 91.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 10644 1.06% 92.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8285 0.83% 93.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 7295 0.73% 94.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 54761 5.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1000117 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 87721 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.505238 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 108.849756 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 87718 100.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 50983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 63815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 77905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 83850 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 82535 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 80562 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 80737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 81986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 81840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 82529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 87953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 83182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 82789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 95240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 86941 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 82400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 79288 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 6110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 6766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 5946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 6638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 4938 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 3930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3705 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3619 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 2936 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1351 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 1091 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 719 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 631 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 743 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 541 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 504 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 526 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 1324 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 813055 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 12096 1.49% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6222 0.77% 93.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 87721 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 87721 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.779745 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.605058 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.125024 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 56948 64.92% 64.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 16031 18.27% 83.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 6972 7.95% 91.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 3738 4.26% 95.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 1084 1.24% 96.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 357 0.41% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 239 0.27% 97.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 271 0.31% 97.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 649 0.74% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 108 0.12% 98.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 85 0.10% 98.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 76 0.09% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 135 0.15% 98.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 76 0.09% 98.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 51 0.06% 98.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 73 0.08% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 134 0.15% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 41 0.05% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 31 0.04% 99.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 49 0.06% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 179 0.20% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 16 0.02% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 31 0.04% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 14 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 43 0.05% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 12 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 20 0.02% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 30 0.03% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 97 0.11% 99.85% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 18 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 14 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 10 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 13 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 11 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 6 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 6 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 14 0.02% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 3 0.00% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 12 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 4 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 3 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 87721 # Writes before turning the bus around for reads -system.physmem.totQLat 32913462781 # Total ticks spent queuing -system.physmem.totMemAccLat 50192281531 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4607685000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35715.83 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 73772 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 73772 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.369218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 71961 97.55% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 712 0.97% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 29 0.04% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 36 0.05% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 132 0.18% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 174 0.24% 99.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 342 0.46% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 135 0.18% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 19 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 64 0.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.04% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 12 0.02% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.01% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 4 0.01% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 7 0.01% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 10 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 9 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 6 0.01% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 15 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 2 0.00% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 1 0.00% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 6 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 7 0.01% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 3 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::576-591 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::720-735 2 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 73772 # Writes before turning the bus around for reads +system.physmem.totQLat 20326500723 # Total ticks spent queuing +system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers +system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54465.83 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.24 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.46 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.19 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.47 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.03 # Data bus utilization in percentage +system.physmem.busUtil 0.02 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.25 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.28 # Average write queue length when enqueuing -system.physmem.readRowHits 687654 # Number of row buffer hits during reads -system.physmem.writeRowHits 1056585 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.96 # Row buffer hit rate for writes -system.physmem.avgGap 17230665.31 # Average gap between requests -system.physmem.pageHitRate 63.56 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 3832851960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 2091337875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3491865000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 5991881040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1200455054145 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27393437346750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 31705942010610 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.749637 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 45570820980751 # Time in different power states -system.physmem_0.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing +system.physmem.readRowHits 509481 # Number of row buffer hits during reads +system.physmem.writeRowHits 909439 # Number of row buffer hits during writes +system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes +system.physmem.avgGap 20763390.98 # Average gap between requests +system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.635370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states +system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 256810103749 # Time in different power states +system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 3728032560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 2034144750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3696084600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 5819992560 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3096641673840 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1191404828700 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 27401376141000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 31704700898010 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.723459 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 45584059811251 # Time in different power states -system.physmem_1.memoryStateTime::REF 1583150140000 # Time in different power states +system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.605711 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states +system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 243570222499 # Time in different power states +system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory @@ -393,9 +382,9 @@ system.realview.nvmem.bw_total::total 4 # To system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 1670 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 6842880 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 1673 # Number of DMA write transactions. +system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 1670 # Number of DMA write transactions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -426,66 +415,67 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 107972 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 107972 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9276 # Level at which table walker walks with long descriptors terminate -system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 83163 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walks 95467 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate +system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 107963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 107963 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 107963 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 92448 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 17595.764614 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 15306.328665 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 15454.252367 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-65535 91009 98.44% 98.44% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::65536-131071 1235 1.34% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-196607 66 0.07% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-262143 55 0.06% 99.91% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-327679 65 0.07% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 92448 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples -2398441544 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.163884 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.370170 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -2005375084 83.61% 83.61% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 -393066460 16.39% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total -2398441544 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 83163 89.97% 89.97% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 9276 10.03% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 92439 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 107972 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 107972 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92439 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92439 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 200411 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 83792624 # DTB read hits -system.cpu0.dtb.read_misses 78614 # DTB read misses -system.cpu0.dtb.write_hits 76883618 # DTB write hits -system.cpu0.dtb.write_misses 29358 # DTB write misses +system.cpu0.dtb.read_hits 81219280 # DTB read hits +system.cpu0.dtb.read_misses 71070 # DTB read misses +system.cpu0.dtb.write_hits 73504932 # DTB write hits +system.cpu0.dtb.write_misses 24397 # DTB write misses system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 38297 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4651 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 10679 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 83871238 # DTB read accesses -system.cpu0.dtb.write_accesses 76912976 # DTB write accesses +system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 81290350 # DTB read accesses +system.cpu0.dtb.write_accesses 73529329 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 160676242 # DTB hits -system.cpu0.dtb.misses 107972 # DTB misses -system.cpu0.dtb.accesses 160784214 # DTB accesses +system.cpu0.dtb.hits 154724212 # DTB hits +system.cpu0.dtb.misses 95467 # DTB misses +system.cpu0.dtb.accesses 154819679 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -515,236 +505,239 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 64255 # Table walker walks requested -system.cpu0.itb.walker.walksLong 64255 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walksLongTerminationLevel::Level2 637 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58227 # Level at which table walker walks with long descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 64255 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 64255 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 64255 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 58864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 20635.902164 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 17664.674655 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 19771.927470 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-65535 57276 97.30% 97.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::65536-131071 1371 2.33% 99.63% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::131072-196607 47 0.08% 99.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::196608-262143 91 0.15% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::262144-327679 53 0.09% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::327680-393215 19 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::393216-458751 5 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 58864 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples -673300296 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -673300296 100.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total -673300296 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 58227 98.92% 98.92% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 637 1.08% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 58864 # Table walker page sizes translated +system.cpu0.itb.walker.walks 56383 # Table walker walks requested +system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 64255 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 64255 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 58864 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 58864 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 123119 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 448595101 # ITB inst hits -system.cpu0.itb.inst_misses 64255 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 434853798 # ITB inst hits +system.cpu0.itb.inst_misses 56383 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 26739 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 448659356 # ITB inst accesses -system.cpu0.itb.hits 448595101 # DTB hits -system.cpu0.itb.misses 64255 # DTB misses -system.cpu0.itb.accesses 448659356 # DTB accesses -system.cpu0.numCycles 94821563304 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses +system.cpu0.itb.hits 434853798 # DTB hits +system.cpu0.itb.misses 56383 # DTB misses +system.cpu0.itb.accesses 434910181 # DTB accesses +system.cpu0.numCycles 94735635148 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 448345930 # Number of instructions committed -system.cpu0.committedOps 527651436 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 484594714 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 558267 # Number of float alu accesses -system.cpu0.num_func_calls 26890258 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 68074268 # number of instructions that are conditional controls -system.cpu0.num_int_insts 484594714 # number of integer instructions -system.cpu0.num_fp_insts 558267 # number of float instructions -system.cpu0.num_int_register_reads 706750752 # number of times the integer registers were read -system.cpu0.num_int_register_writes 384547382 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 893879 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 490056 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 117567828 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 117277075 # number of times the CC registers were written -system.cpu0.num_mem_refs 160668093 # number of memory refs -system.cpu0.num_load_insts 83788812 # Number of load instructions -system.cpu0.num_store_insts 76879281 # Number of store instructions -system.cpu0.num_idle_cycles 93729284290.716034 # Number of idle cycles -system.cpu0.num_busy_cycles 1092279013.283977 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011519 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988481 # Percentage of idle cycles -system.cpu0.Branches 100174256 # Number of branches fetched +system.cpu0.committedInsts 434594659 # Number of instructions committed +system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses +system.cpu0.num_func_calls 25685063 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls +system.cpu0.num_int_insts 468245604 # number of integer instructions +system.cpu0.num_fp_insts 368958 # number of float instructions +system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read +system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written +system.cpu0.num_mem_refs 154715442 # number of memory refs +system.cpu0.num_load_insts 81215665 # Number of load instructions +system.cpu0.num_store_insts 73499777 # Number of store instructions +system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles +system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles +system.cpu0.Branches 96525602 # Number of branches fetched system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 365953478 69.32% 69.32% # Class of executed instruction -system.cpu0.op_class::IntMult 1186010 0.22% 69.54% # Class of executed instruction -system.cpu0.op_class::IntDiv 57830 0.01% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 8 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 13 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 21 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.55% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 78277 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::MemRead 83788812 15.87% 85.44% # Class of executed instruction -system.cpu0.op_class::MemWrite 76879281 14.56% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction +system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction +system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction +system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction +system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 527943731 # Class of executed instruction +system.cpu0.op_class::total 510121531 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 5474 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 5753925 # number of replacements -system.cpu0.dcache.tags.tagsinuse 509.684776 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 154679022 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 5754435 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 26.879967 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 3644714000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 509.684776 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.995478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.995478 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 390 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 327127592 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 327127592 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 77833401 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77833401 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72535559 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72535559 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 180949 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 180949 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 117408 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 117408 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1813577 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 1813577 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1784599 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 1784599 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 150368960 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 150368960 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 150549909 # number of overall hits -system.cpu0.dcache.overall_hits::total 150549909 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3079415 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 3079415 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1439122 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1439122 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 698265 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 698265 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 782756 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 782756 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 172905 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 172905 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 200615 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 200615 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4518537 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 4518537 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5216802 # number of overall misses -system.cpu0.dcache.overall_misses::total 5216802 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 45365631768 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 45365631768 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 25986134990 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 25986134990 # number of WriteReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 26026367891 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 26026367891 # number of WriteInvalidateReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2610218258 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 2610218258 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4265500897 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 4265500897 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2243000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2243000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 71351766758 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 71351766758 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 71351766758 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 71351766758 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 80912816 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 80912816 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73974681 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73974681 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 879214 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 879214 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 900164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 900164 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1986482 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 1986482 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1985214 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 1985214 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154887497 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154887497 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 155766711 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 155766711 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.038058 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.038058 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.019454 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.019454 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.794192 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.794192 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.869570 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.869570 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.087041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.087041 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.101055 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.101055 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029173 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.029173 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.033491 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.033491 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14731.899328 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14731.899328 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18056.936792 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18056.936792 # average WriteReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 33249.656203 # average WriteInvalidateReq miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 33249.656203 # average WriteInvalidateReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15096.256661 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15096.256661 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21262.123455 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21262.123455 # average StoreCondReq miss latency +system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed +system.cpu0.dcache.tags.replacements 5284481 # number of replacements +system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits +system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses +system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027731 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15790.900187 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15790.900187 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13677.300146 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13677.300146 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15431.397107 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15431.397107 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13377.518755 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13377.518755 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -753,92 +746,92 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 3895213 # number of writebacks -system.cpu0.dcache.writebacks::total 3895213 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 35120 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 35120 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21470 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 21470 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 46933 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 46933 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 56590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 56590 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 56590 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 56590 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3044295 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 3044295 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1417652 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 1417652 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 692633 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 692633 # number of SoftPFReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 782756 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 782756 # number of WriteInvalidateReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 125972 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 125972 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 200615 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 200615 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 4461947 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 4461947 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 5154580 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 5154580 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37795344499 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37795344499 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 22579422262 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 22579422262 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 14234213672 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 14234213672 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24458156109 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 24458156109 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1564829744 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1564829744 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3853276103 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3853276103 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2137000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2137000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 60374766761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 60374766761 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 74608980433 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 74608980433 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2287793998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2287793998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2244465248 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2244465248 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4532259246 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4532259246 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.037624 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.037624 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019164 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019164 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.787787 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.787787 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.869570 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.869570 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.063415 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.063415 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.101055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.101055 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028808 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028808 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.033092 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.033092 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12415.138644 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12415.138644 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15927.337782 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15927.337782 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 20550.874232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 20550.874232 # average SoftPFReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 31246.207131 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 31246.207131 # average WriteInvalidateReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12422.044137 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12422.044137 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19207.318012 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19207.318012 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 3634622 # number of writebacks +system.cpu0.dcache.writebacks::total 3634622 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28612 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 28612 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21357 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 21357 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 38145 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 38145 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 49969 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 49969 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 49969 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 49969 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2791784 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 2791784 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1299186 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 1299186 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 630147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 630147 # number of SoftPFReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 746024 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 746024 # number of WriteInvalidateReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 117927 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 117927 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 182947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 182947 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 4090970 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 4090970 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 4721117 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 4721117 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34314944268 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34314944268 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 21777665637 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 21777665637 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 12432309289 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 12432309289 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29820271426 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29820271426 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1422971246 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1422971246 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3676791544 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3676791544 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1208000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1208000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 56092609905 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 56092609905 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68524919194 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 68524919194 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4525228998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4525228998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4129291250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4129291250 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 8654520248 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 8654520248 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035537 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035537 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.774878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.774878 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.839055 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.839055 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064853 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064853 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.100684 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.100684 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027396 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.027396 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031445 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.031445 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12291.403729 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12291.403729 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16762.546423 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16762.546423 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 19729.220783 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 19729.220783 # average SoftPFReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39972.268219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39972.268219 # average WriteInvalidateReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12066.543251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12066.543251 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20097.577681 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20097.577681 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13531.036286 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13531.036286 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14474.308369 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14474.308369 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13711.322719 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13711.322719 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14514.556448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14514.556448 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -846,58 +839,58 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 5166576 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.910022 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 443428013 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 5167088 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 85.817778 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 30209622750 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.910022 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999824 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999824 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 4499955 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.899412 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 430353331 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 4500467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 95.624150 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 33435593250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899412 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 324 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 127 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 329 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 902357290 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 902357290 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 443428013 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 443428013 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 443428013 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 443428013 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 443428013 # number of overall hits -system.cpu0.icache.overall_hits::total 443428013 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 5167088 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 5167088 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 5167088 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 5167088 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 5167088 # number of overall misses -system.cpu0.icache.overall_misses::total 5167088 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 53694723563 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 53694723563 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 53694723563 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 53694723563 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 53694723563 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 53694723563 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 448595101 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 448595101 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 448595101 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 448595101 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 448595101 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 448595101 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011518 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.011518 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011518 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.011518 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011518 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.011518 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10391.679717 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10391.679717 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10391.679717 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10391.679717 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10391.679717 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 874208063 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 874208063 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 430353331 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 430353331 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 430353331 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 430353331 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 430353331 # number of overall hits +system.cpu0.icache.overall_hits::total 430353331 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 4500467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 4500467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 4500467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 4500467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 4500467 # number of overall misses +system.cpu0.icache.overall_misses::total 4500467 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47768563979 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 47768563979 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 47768563979 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 47768563979 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 47768563979 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 47768563979 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 434853798 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 434853798 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 434853798 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 434853798 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 434853798 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 434853798 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.010349 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.010349 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.010349 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.010349 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.010349 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.010349 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10614.134928 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10614.134928 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10614.134928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10614.134928 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10614.134928 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -906,241 +899,240 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5167088 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 5167088 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 5167088 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 5167088 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 5167088 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 5167088 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45925261947 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 45925261947 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45925261947 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 45925261947 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45925261947 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 45925261947 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3405609750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 3405609750 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011518 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.011518 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011518 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.011518 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8888.035572 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8888.035572 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8888.035572 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4500467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 4500467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 4500467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 4500467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 4500467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 4500467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 43254050535 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 43254050535 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 43254050535 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 43254050535 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 43254050535 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 43254050535 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 3811870500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.010349 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.010349 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.010349 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.010349 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9611.013820 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9611.013820 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9611.013820 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 7865373 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 7866135 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 648 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 7625512 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 7625539 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 985913 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 2427001 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16243.780061 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 11146490 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 2442996 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 4.562631 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 4729494500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 7283.700781 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 78.630524 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 92.657228 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3931.432813 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3992.358247 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 865.000469 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.444562 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004799 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.005655 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.239956 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.243674 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.052795 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.991442 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1466 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14457 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 31 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 296 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 826 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 313 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 41 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 947 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4330 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6826 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2259 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.089478 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.882385 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 256470983 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 256470983 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 224791 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 150515 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4652887 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 2883530 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 7911723 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 3895212 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 3895212 # number of Writeback hits -system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 236831 # number of WriteInvalidateReq hits -system.cpu0.l2cache.WriteInvalidateReq_hits::total 236831 # number of WriteInvalidateReq hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 106550 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 106550 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 34358 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 34358 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 952634 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 952634 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 224791 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 150515 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 4652887 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 3836164 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 8864357 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 224791 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 150515 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 4652887 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 3836164 # number of overall hits -system.cpu0.l2cache.overall_hits::total 8864357 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10425 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 9020 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 514201 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 979370 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1513016 # number of ReadReq misses +system.cpu0.l2cache.prefetcher.pfSpanPage 975949 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 2276475 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16164.000425 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 9930056 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 2292579 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 4.331391 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 5342662500 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 7643.384526 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 57.376858 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 75.669060 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3718.900652 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3598.062438 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1070.606892 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.466515 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003502 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004618 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.226984 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.219608 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.065345 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.986572 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1394 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14660 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 18 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 592 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 515 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 17 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 21 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 811 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4617 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5283 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3880 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.085083 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.003052 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.894775 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 232158629 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 232158629 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 184213 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 122134 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 3989528 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 2659243 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 6955118 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 3634621 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 3634621 # number of Writeback hits +system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 174040 # number of WriteInvalidateReq hits +system.cpu0.l2cache.WriteInvalidateReq_hits::total 174040 # number of WriteInvalidateReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 97614 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 97614 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30602 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 30602 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 869323 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 869323 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 184213 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 122134 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 3989528 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 3528566 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 7824441 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 184213 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 122134 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 3989528 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 3528566 # number of overall hits +system.cpu0.l2cache.overall_hits::total 7824441 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 8450 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 6821 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 510939 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 880615 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 1406825 # number of ReadReq misses system.cpu0.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses system.cpu0.l2cache.Writeback_misses::total 1 # number of Writeback misses -system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 544650 # number of WriteInvalidateReq misses -system.cpu0.l2cache.WriteInvalidateReq_misses::total 544650 # number of WriteInvalidateReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 122779 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 122779 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 166249 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 166249 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 8 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 253376 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 253376 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10425 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 9020 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 514201 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 1232746 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 1766392 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10425 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 9020 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 514201 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 1232746 # number of overall misses -system.cpu0.l2cache.overall_misses::total 1766392 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 401624493 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 376564494 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15423284566 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 32417465776 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 48618939329 # number of ReadReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 194184961 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 194184961 # number of WriteInvalidateReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2456096364 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 2456096364 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3361972231 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3361972231 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2084000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2084000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 11515878505 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 11515878505 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 401624493 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 376564494 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15423284566 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 43933344281 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 60134817834 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 401624493 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 376564494 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15423284566 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 43933344281 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 60134817834 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 235216 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 159535 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5167088 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3862900 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 9424739 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 3895213 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 3895213 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 781481 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.WriteInvalidateReq_accesses::total 781481 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 229329 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 229329 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 200607 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 200607 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 8 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1206010 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 1206010 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 235216 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 159535 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 5167088 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 5068910 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 10630749 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 235216 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 159535 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 5167088 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 5068910 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 10630749 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.044321 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.056539 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.099515 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.253532 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.160537 # miss rate for ReadReq accesses +system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 570673 # number of WriteInvalidateReq misses +system.cpu0.l2cache.WriteInvalidateReq_misses::total 570673 # number of WriteInvalidateReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 121192 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 121192 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 152342 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 152342 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 228613 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 228613 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 8450 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 6821 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 510939 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 1109228 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 1635438 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 8450 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 6821 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 510939 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 1109228 # number of overall misses +system.cpu0.l2cache.overall_misses::total 1635438 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 233396250 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 201613986 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15055870276 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 27344253636 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 42835134148 # number of ReadReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 214216390 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 214216390 # number of WriteInvalidateReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2669808389 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 2669808389 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3193098671 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3193098671 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 1181000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1181000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 10520875436 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 10520875436 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 233396250 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 201613986 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15055870276 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 37865129072 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 53356009584 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 233396250 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 201613986 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15055870276 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 37865129072 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 53356009584 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 192663 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 128955 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 4500467 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3539858 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 8361943 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 3634622 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 3634622 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 744713 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.WriteInvalidateReq_accesses::total 744713 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 218806 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 218806 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 182944 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 182944 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1097936 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 1097936 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 192663 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 128955 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 4500467 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 4637794 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 9459879 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 192663 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 128955 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 4500467 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 4637794 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 9459879 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.052894 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.113530 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.248771 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.168241 # miss rate for ReadReq accesses system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses system.cpu0.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.696946 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.696946 # miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.535384 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.535384 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.828730 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.828730 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.766299 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.766299 # miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.553879 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.553879 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.832725 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.832725 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.210094 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.210094 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.044321 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.056539 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.099515 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.243197 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.166159 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.044321 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.056539 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.099515 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.243197 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.166159 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 38525.131223 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 41747.726608 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29994.660777 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33100.325491 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32133.790607 # average ReadReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 356.531646 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 356.531646 # average WriteInvalidateReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 20004.205638 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 20004.205638 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20222.510999 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20222.510999 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 260500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 260500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 45449.760455 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 45449.760455 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 38525.131223 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 41747.726608 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29994.660777 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 35638.602178 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 34043.868991 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 38525.131223 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 41747.726608 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29994.660777 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 35638.602178 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 34043.868991 # average overall miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.208221 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.208221 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.052894 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.113530 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.239171 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.172881 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.043859 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.052894 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.113530 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.239171 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.172881 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 29557.834042 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 29467.060209 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 31051.314861 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30448.089953 # average ReadReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 375.375022 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 375.375022 # average WriteInvalidateReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 22029.576119 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 22029.576119 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20960.067946 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20960.067946 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 393666.666667 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 393666.666667 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 46020.460061 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 46020.460061 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 32624.905123 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27620.857988 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 29557.834042 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 29467.060209 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 34136.470655 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 32624.905123 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1149,140 +1141,140 @@ system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 1390929 # number of writebacks -system.cpu0.l2cache.writebacks::total 1390929 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 412 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5653 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 5653 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6065 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6065 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6065 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6065 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10425 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 9020 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 514201 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 978958 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 1512604 # number of ReadReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 1283433 # number of writebacks +system.cpu0.l2cache.writebacks::total 1283433 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 443 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 443 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3351 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 3351 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3794 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 3794 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3794 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 3794 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 8450 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 6821 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 510939 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 880172 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 1406382 # number of ReadReq MSHR misses system.cpu0.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses system.cpu0.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 705771 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 705771 # number of HardPFReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 544650 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 544650 # number of WriteInvalidateReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 122779 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 122779 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 166249 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 166249 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 8 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 247723 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 247723 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10425 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 9020 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 514201 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1226681 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 1760327 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10425 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 9020 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 514201 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1226681 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 705771 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 2466098 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 312733504 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 11805310434 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25478803206 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 37924779653 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 34882867408 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 34882867408 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 18696199399 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 18696199399 # number of WriteInvalidateReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2085589258 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2085589258 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2284466860 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2284466860 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1713000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1713000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9147060396 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9147060396 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 312733504 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11805310434 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 34625863602 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 47071840049 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 327932509 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 312733504 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11805310434 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 34625863602 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 34882867408 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 81954707457 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2174725243 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5236589993 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2129495502 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2129495502 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3061864750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 4304220745 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 7366085495 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.253426 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.160493 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 635942 # number of HardPFReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 570673 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 570673 # number of WriteInvalidateReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 121192 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 121192 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 152342 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 152342 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 225262 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 225262 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 8450 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 6821 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 510939 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1105434 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 1631644 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 8450 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 6821 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 510939 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1105434 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 635942 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 2267586 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 157112514 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 11720586224 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 21558629277 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 33614638265 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 23030840367 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24220184845 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24220184845 # number of WriteInvalidateReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2529730528 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2529730528 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2304861456 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2304861456 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1005500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1005500 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 8691962659 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 8691962659 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 157112514 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 11720586224 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 30250591936 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 42306600924 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 178310250 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 157112514 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 11720586224 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 30250591936 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 23030840367 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 65337441291 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 4307274002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 7775525002 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 3933705500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 3933705500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 8240979502 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 11709230502 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.248646 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.168188 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.696946 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.696946 # mshr miss rate for WriteInvalidateReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.535384 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.535384 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.828730 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.828730 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.766299 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.766299 # mshr miss rate for WriteInvalidateReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.553879 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.553879 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.832725 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.832725 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205407 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205407 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.165588 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.044321 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.056539 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.099515 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.242001 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.205169 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.205169 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.172480 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.043859 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.052894 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.113530 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.238353 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231978 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26026.451805 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25072.510487 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 49425.192319 # average HardPFReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 34326.997887 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 34326.997887 # average WriteInvalidateReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16986.530742 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16986.530742 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13741.236699 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13741.236699 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 214125 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 214125 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 36924.550389 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36924.550389 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26740.395420 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31456.355779 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 34671.120177 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22958.552072 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28227.276368 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 49425.192319 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 33232.542850 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.239706 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 24493.654964 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 23901.499212 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 36215.315810 # average HardPFReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42441.441675 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42441.441675 # average WriteInvalidateReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20873.741897 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20873.741897 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15129.520789 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15129.520789 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 335166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 335166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38586.013882 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38586.013882 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25928.818372 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 21101.804734 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 23033.648145 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22939.306305 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27365.353278 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 36215.315810 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28813.655266 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1292,58 +1284,56 @@ system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 11541292 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 9690709 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 15329 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 15329 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 3895213 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 1069383 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1166255 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 781481 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 444610 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 368177 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 498972 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 1328849 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 1215209 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10420426 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16690518 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 351532 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 549297 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 28011773 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 330866132 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 630631769 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1276280 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1881728 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 964655909 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 4194903 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 19756578 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.197801 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.398341 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 15848715 80.22% 80.22% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 3907863 19.78% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 19756578 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 12645685295 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 194485993 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 7813325558 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 8298663367 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 192341003 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 314436506 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1374,74 +1364,67 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 99527 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 99527 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9603 # Level at which table walker walks with long descriptors terminate -system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 74573 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walks 92509 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate +system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 99518 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 0.271308 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 67.169326 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-2047 99516 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::6144-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::18432-20479 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 99518 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 84185 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 16581.674289 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 15037.130908 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 10932.627488 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 81471 96.78% 96.78% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2185 2.60% 99.37% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 285 0.34% 99.71% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-131071 159 0.19% 99.90% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::131072-163839 19 0.02% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 14 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::196608-229375 18 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::229376-262143 4 0.00% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::262144-294911 15 0.02% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::327680-360447 5 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 84185 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1589468256 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.778279 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.415405 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -352419148 22.17% 22.17% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 -1237049108 77.83% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1589468256 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 74574 88.59% 88.59% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 9603 11.41% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 84177 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 99527 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 99527 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 84177 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 84177 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 183704 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 83767099 # DTB read hits -system.cpu1.dtb.read_misses 74857 # DTB read misses -system.cpu1.dtb.write_hits 75685520 # DTB write hits -system.cpu1.dtb.write_misses 24670 # DTB write misses +system.cpu1.dtb.read_hits 78277454 # DTB read hits +system.cpu1.dtb.read_misses 68245 # DTB read misses +system.cpu1.dtb.write_hits 71517077 # DTB write hits +system.cpu1.dtb.write_misses 24264 # DTB write misses system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 36584 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4104 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 9015 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 83841956 # DTB read accesses -system.cpu1.dtb.write_accesses 75710190 # DTB write accesses +system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 78345699 # DTB read accesses +system.cpu1.dtb.write_accesses 71541341 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 159452619 # DTB hits -system.cpu1.dtb.misses 99527 # DTB misses -system.cpu1.dtb.accesses 159552146 # DTB accesses +system.cpu1.dtb.hits 149794531 # DTB hits +system.cpu1.dtb.misses 92509 # DTB misses +system.cpu1.dtb.accesses 149887040 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1471,239 +1454,242 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 55326 # Table walker walks requested -system.cpu1.itb.walker.walksLong 55326 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walksLongTerminationLevel::Level2 571 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walksLongTerminationLevel::Level3 49211 # Level at which table walker walks with long descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 55326 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 55326 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 55326 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 49782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 18533.691816 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 16693.913266 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 13345.941074 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-32767 47101 94.61% 94.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-65535 2168 4.35% 98.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-98303 178 0.36% 99.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::98304-131071 248 0.50% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-163839 12 0.02% 99.85% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::163840-196607 16 0.03% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::196608-229375 24 0.05% 99.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.01% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::262144-294911 18 0.04% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::294912-327679 3 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 49782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1199136648 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1199136648 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1199136648 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 49211 98.85% 98.85% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 571 1.15% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 49782 # Table walker page sizes translated +system.cpu1.itb.walker.walks 60524 # Table walker walks requested +system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 55326 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 55326 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 49782 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 49782 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 105108 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 441493680 # ITB inst hits -system.cpu1.itb.inst_misses 55326 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 409921957 # ITB inst hits +system.cpu1.itb.inst_misses 60524 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 41330 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 25739 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 441549006 # ITB inst accesses -system.cpu1.itb.hits 441493680 # DTB hits -system.cpu1.itb.misses 55326 # DTB misses -system.cpu1.itb.accesses 441549006 # DTB accesses -system.cpu1.numCycles 94821563303 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses +system.cpu1.itb.hits 409921957 # DTB hits +system.cpu1.itb.misses 60524 # DTB misses +system.cpu1.itb.accesses 409982481 # DTB accesses +system.cpu1.numCycles 94735635148 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 441187041 # Number of instructions committed -system.cpu1.committedOps 519063105 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 477531543 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 364386 # Number of float alu accesses -system.cpu1.num_func_calls 26570520 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 66815511 # number of instructions that are conditional controls -system.cpu1.num_int_insts 477531543 # number of integer instructions -system.cpu1.num_fp_insts 364386 # number of float instructions -system.cpu1.num_int_register_reads 690361032 # number of times the integer registers were read -system.cpu1.num_int_register_writes 378560518 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 602629 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 273816 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 113424708 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 113111436 # number of times the CC registers were written -system.cpu1.num_mem_refs 159443034 # number of memory refs -system.cpu1.num_load_insts 83763663 # Number of load instructions -system.cpu1.num_store_insts 75679371 # Number of store instructions -system.cpu1.num_idle_cycles 93795188251.508850 # Number of idle cycles -system.cpu1.num_busy_cycles 1026375051.491154 # Number of busy cycles -system.cpu1.not_idle_fraction 0.010824 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.989176 # Percentage of idle cycles -system.cpu1.Branches 98214896 # Number of branches fetched +system.cpu1.committedInsts 409652284 # Number of instructions committed +system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses +system.cpu1.num_func_calls 25682090 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls +system.cpu1.num_int_insts 446181756 # number of integer instructions +system.cpu1.num_fp_insts 565626 # number of float instructions +system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read +system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written +system.cpu1.num_mem_refs 149782083 # number of memory refs +system.cpu1.num_load_insts 78271508 # Number of load instructions +system.cpu1.num_store_insts 71510575 # Number of store instructions +system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles +system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles +system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles +system.cpu1.Branches 91673037 # Number of branches fetched system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 358777055 69.08% 69.08% # Class of executed instruction -system.cpu1.op_class::IntMult 1052972 0.20% 69.28% # Class of executed instruction -system.cpu1.op_class::IntDiv 61499 0.01% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.29% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 35293 0.01% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.30% # Class of executed instruction -system.cpu1.op_class::MemRead 83763663 16.13% 85.43% # Class of executed instruction -system.cpu1.op_class::MemWrite 75679371 14.57% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction +system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction +system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction +system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction +system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 519369853 # Class of executed instruction +system.cpu1.op_class::total 484255317 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 13999 # number of quiesce instructions executed -system.cpu1.dcache.tags.replacements 4977655 # number of replacements -system.cpu1.dcache.tags.tagsinuse 421.597899 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 154271186 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 4978165 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 30.989569 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 8379002972500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 421.597899 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.823433 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.823433 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::1 442 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 323862009 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 323862009 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 78232018 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 78232018 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 71864508 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 71864508 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191698 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 191698 # number of SoftPFReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 211446 # number of WriteInvalidateReq hits -system.cpu1.dcache.WriteInvalidateReq_hits::total 211446 # number of WriteInvalidateReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1712714 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 1712714 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1673213 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 1673213 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 150096526 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 150096526 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 150288224 # number of overall hits -system.cpu1.dcache.overall_hits::total 150288224 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 2870044 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 2870044 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1235849 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1235849 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 574884 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 574884 # number of SoftPFReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 468795 # number of WriteInvalidateReq misses -system.cpu1.dcache.WriteInvalidateReq_misses::total 468795 # number of WriteInvalidateReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 161452 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 161452 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 199386 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 199386 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 4105893 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 4105893 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 4680777 # number of overall misses -system.cpu1.dcache.overall_misses::total 4680777 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 39400522531 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 39400522531 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 20561069776 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 20561069776 # number of WriteReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 12119187041 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 12119187041 # number of WriteInvalidateReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2308132257 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 2308132257 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4261474455 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 4261474455 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1966000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1966000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 59961592307 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 59961592307 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 59961592307 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 59961592307 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 81102062 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 81102062 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 73100357 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 73100357 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 766582 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 766582 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 680241 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.WriteInvalidateReq_accesses::total 680241 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1874166 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 1874166 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1872599 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 1872599 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 154202419 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 154202419 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 154969001 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 154969001 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035388 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.035388 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016906 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.016906 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.749932 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.749932 # miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.689160 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.689160 # miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.086146 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.086146 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106476 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106476 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026627 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026627 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030205 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.030205 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13728.194596 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13728.194596 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16637.202260 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 16637.202260 # average WriteReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 25851.783916 # average WriteInvalidateReq miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 25851.783916 # average WriteInvalidateReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14296.089593 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14296.089593 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21372.987346 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21372.987346 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed +system.cpu1.dcache.tags.replacements 4752540 # number of replacements +system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits +system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits +system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses +system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses +system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 57180589082 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 75812564 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 144853988 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 144853988 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 145536809 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.730474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027078 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14603.788337 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14603.788337 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12810.179230 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 12810.179230 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1712,92 +1698,92 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 3230902 # number of writebacks -system.cpu1.dcache.writebacks::total 3230902 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11797 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 11797 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 280 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 280 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 42800 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 42800 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 12077 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 12077 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 12077 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 12077 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2858247 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 2858247 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1235569 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 1235569 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 574884 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 574884 # number of SoftPFReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 468795 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 468795 # number of WriteInvalidateReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 118652 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 118652 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 199386 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 199386 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 4093816 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 4093816 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 4668700 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 4668700 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 33045194740 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 33045194740 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 18021373474 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 18021373474 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 10397149259 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 10397149259 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11178014959 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11178014959 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1426804491 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1426804491 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3852246545 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3852246545 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1872000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1872000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 51066568214 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 51066568214 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 61463717473 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 61463717473 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4074474250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4074474250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3958410750 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3958410750 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8032885000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8032885000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035243 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035243 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016902 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016902 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.749932 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.749932 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.689160 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.689160 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063309 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063309 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106476 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106476 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026548 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026548 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030127 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030127 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11561.350275 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11561.350275 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14585.485290 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14585.485290 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18085.647294 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18085.647294 # average SoftPFReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 23844.142875 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 23844.142875 # average WriteInvalidateReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12025.119602 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12025.119602 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19320.546804 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19320.546804 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks +system.cpu1.dcache.writebacks::total 3063492 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46682 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 11897 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2756082 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1154410 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 1154410 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 498783 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 498783 # number of SoftPFReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 496292 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 496292 # number of WriteInvalidateReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 111639 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 111639 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 3910492 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 4409275 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 32859790378 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 17743172214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 17743172214 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 9770846491 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 11134079098 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 11134079098 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3498646925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 60373809083 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 60373809083 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1936116751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2164016499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2164016499 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4100133250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.016721 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.730474 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.724271 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15369.905158 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15369.905158 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19589.373517 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12474.075096 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12474.075096 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13165.060396 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13165.060396 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13692.457169 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1805,59 +1791,59 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 4937125 # number of replacements -system.cpu1.icache.tags.tagsinuse 496.391317 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 436556038 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 4937637 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 88.413960 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 8378975635000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.391317 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969514 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.969514 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 5523110 # number of replacements +system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969418 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 262 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 239 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 887925002 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 887925002 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 436556038 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 436556038 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 436556038 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 436556038 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 436556038 # number of overall hits -system.cpu1.icache.overall_hits::total 436556038 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 4937642 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 4937642 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 4937642 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 4937642 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 4937642 # number of overall misses -system.cpu1.icache.overall_misses::total 4937642 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 50835870381 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 50835870381 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 50835870381 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 50835870381 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 50835870381 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 50835870381 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 441493680 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 441493680 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 441493680 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 441493680 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 441493680 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 441493680 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.011184 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.011184 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.011184 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.011184 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.011184 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.011184 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10295.576387 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 10295.576387 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 10295.576387 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10295.576387 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 10295.576387 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 825367541 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 404398330 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 404398330 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 404398330 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 404398330 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 404398330 # number of overall hits +system.cpu1.icache.overall_hits::total 404398330 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 5523627 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 5523627 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 5523627 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 5523627 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 5523627 # number of overall misses +system.cpu1.icache.overall_misses::total 5523627 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 54612807078 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 54612807078 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 54612807078 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 54612807078 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 409921957 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 409921957 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 409921957 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 409921957 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 409921957 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013475 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013475 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013475 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013475 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1866,239 +1852,236 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4937642 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 4937642 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 4937642 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 4937642 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 4937642 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 4937642 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 43414323627 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 43414323627 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 43414323627 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 43414323627 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 43414323627 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 43414323627 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8951000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8951000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8951000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8951000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.011184 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.011184 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.011184 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.011184 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8792.521537 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8792.521537 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8792.521537 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5523627 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 5523627 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 5523627 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 5523627 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 5523627 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 5523627 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 49075741422 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 49075741422 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 49075741422 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 49075741422 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 49075741422 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 49075741422 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9805750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9805750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9805750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9805750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013475 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013475 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013475 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013475 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8884.695042 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8884.695042 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8884.695042 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 6896094 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 6896721 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 539 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 5870481 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 5870524 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 29 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 853759 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 1907013 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 13040.746764 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 10338978 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 1923015 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 5.376442 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 9789299685500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 5807.381964 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.245810 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 78.947620 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2946.895146 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3156.020749 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 990.255474 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.354454 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003738 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.004819 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.179864 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.192628 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.060440 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.795944 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1412 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 94 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14496 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 26 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1121 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 188 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1044 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1799 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 10295 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1321 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.086182 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005737 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.884766 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 227501804 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 227501804 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 207163 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 127057 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4446186 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 2697591 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 7477997 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 3230902 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 3230902 # number of Writeback hits -system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 181429 # number of WriteInvalidateReq hits -system.cpu1.l2cache.WriteInvalidateReq_hits::total 181429 # number of WriteInvalidateReq hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 59189 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 59189 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 31769 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 31769 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 842543 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 842543 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 207163 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 127057 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 4446186 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 3540134 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 8320540 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 207163 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 127057 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 4446186 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 3540134 # number of overall hits -system.cpu1.l2cache.overall_hits::total 8320540 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 8925 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 6995 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 491456 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 854192 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 1361568 # number of ReadReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 285701 # number of WriteInvalidateReq misses -system.cpu1.l2cache.WriteInvalidateReq_misses::total 285701 # number of WriteInvalidateReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 127179 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 127179 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167611 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 167611 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 208488 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 208488 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 8925 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 6995 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 491456 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 1062680 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 1570056 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 8925 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 6995 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 491456 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 1062680 # number of overall misses -system.cpu1.l2cache.overall_misses::total 1570056 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 266500250 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 219567495 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 14267491069 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 25122385610 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 39875944424 # number of ReadReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 189007871 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 189007871 # number of WriteInvalidateReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2544221753 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 2544221753 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3390574541 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3390574541 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1824999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1824999 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8358339864 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 8358339864 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 266500250 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 219567495 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 14267491069 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 33480725474 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 48234284288 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 266500250 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 219567495 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 14267491069 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 33480725474 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 48234284288 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 216088 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 134052 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4937642 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3551783 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 8839565 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 3230902 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 3230902 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 467130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.WriteInvalidateReq_accesses::total 467130 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 186368 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 186368 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 199380 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 199380 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1051031 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 1051031 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 216088 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 134052 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 4937642 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 4602814 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 9890596 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 216088 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 134052 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 4937642 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 4602814 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 9890596 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052181 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.099533 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.240497 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.154031 # miss rate for ReadReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.611609 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.611609 # miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.682408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.682408 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.840661 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.840661 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.prefetcher.pfSpanPage 773012 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 1638473 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 13410.207774 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 10772955 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 1654198 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.512494 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 10040948806000 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 5186.730932 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 70.626422 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 88.861590 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3789.090493 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3453.027216 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 821.871120 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.316573 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004311 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005424 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.231268 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.210756 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.050163 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.818494 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1616 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 82 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14027 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 271 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 744 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 601 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 43 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 21 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2440 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6290 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 5121 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.098633 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005005 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.856140 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 229858181 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 229858181 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 196843 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 146711 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 5082589 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 2590406 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 8016549 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 3063492 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 3063492 # number of Writeback hits +system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 265137 # number of WriteInvalidateReq hits +system.cpu1.l2cache.WriteInvalidateReq_hits::total 265137 # number of WriteInvalidateReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 50742 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 50742 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 28295 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 28295 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 777406 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 777406 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 196843 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 146711 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 5082589 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 3367812 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 8793955 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 196843 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 146711 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 5082589 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 3367812 # number of overall hits +system.cpu1.l2cache.overall_hits::total 8793955 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9130 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7601 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 441038 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 776098 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 1233867 # number of ReadReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 229595 # number of WriteInvalidateReq misses +system.cpu1.l2cache.WriteInvalidateReq_misses::total 229595 # number of WriteInvalidateReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120541 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 120541 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 147968 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 147968 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 207551 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 207551 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9130 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7601 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 441038 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 983649 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 1441418 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9130 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7601 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 441038 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 983649 # number of overall misses +system.cpu1.l2cache.overall_misses::total 1441418 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 287537248 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 274641499 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 13255864672 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 23821498253 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 37639541672 # number of ReadReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 209637116 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 209637116 # number of WriteInvalidateReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2569493734 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 2569493734 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3076594441 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3076594441 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1773498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1773498 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 8057830380 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 8057830380 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 287537248 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 274641499 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 13255864672 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 31879328633 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 45697372052 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 287537248 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 274641499 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 13255864672 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 31879328633 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 45697372052 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 205973 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 154312 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 5523627 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3366504 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 9250416 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 3063492 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 3063492 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 494732 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.WriteInvalidateReq_accesses::total 494732 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 171283 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 171283 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 176263 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 176263 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 984957 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 984957 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 205973 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 154312 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 5523627 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 4351461 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 10235373 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 205973 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 154312 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 5523627 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 4351461 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 10235373 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.049257 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.079846 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.230535 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.133385 # miss rate for ReadReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.464080 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.464080 # miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.703753 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.703753 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.839473 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.839473 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.198365 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.198365 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052181 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.099533 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.230876 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.158742 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.041303 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052181 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.099533 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.230876 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.158742 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 29859.971989 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 31389.205861 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 29031.064976 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 29410.701119 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 29286.781434 # average ReadReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 661.558311 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 661.558311 # average WriteInvalidateReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 20005.046061 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 20005.046061 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20228.830691 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20228.830691 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 304166.500000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 304166.500000 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40090.268332 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40090.268332 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 29859.971989 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 31389.205861 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 29031.064976 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 31505.933559 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 30721.378274 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 29859.971989 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 31389.205861 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 29031.064976 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 31505.933559 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 30721.378274 # average overall miss latency +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210721 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210721 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.049257 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.079846 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.226050 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.140827 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.044326 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.049257 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.079846 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.226050 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.140827 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 36132.285094 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30056.060185 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 30693.930732 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 30505.347555 # average ReadReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 913.073525 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 913.073525 # average WriteInvalidateReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21316.346587 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21316.346587 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20792.295909 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20792.295909 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 354699.600000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 354699.600000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 38823.375363 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 38823.375363 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31703.067432 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 31493.674480 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 36132.285094 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30056.060185 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 32409.252318 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31703.067432 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2107,136 +2090,136 @@ system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 911309 # number of writebacks -system.cpu1.l2cache.writebacks::total 911309 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 380 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 380 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 5401 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 5401 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 5781 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 5781 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 5781 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 5781 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 8925 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 6995 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 491456 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 853812 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 1361188 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 639196 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 639196 # number of HardPFReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 285701 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 285701 # number of WriteInvalidateReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 127179 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 127179 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167611 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167611 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 203087 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 203087 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 8925 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 6995 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 491456 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1056899 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 1564275 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 8925 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 6995 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 491456 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1056899 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 639196 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 2203471 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 170362507 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 10812394931 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 19078738641 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 30265237329 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 29755594933 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 29755594933 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7736539648 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7736539648 # number of WriteInvalidateReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2151571523 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2151571523 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2290441908 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2290441908 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1495999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1495999 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6293487581 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6293487581 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 170362507 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10812394931 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25372226222 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 36558724910 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 203741250 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 170362507 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10812394931 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25372226222 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 29755594933 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 66314319843 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8087000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3880010250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3888097250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3784845500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3784845500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8087000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7664855750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7672942750 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.240390 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.153988 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 764216 # number of writebacks +system.cpu1.l2cache.writebacks::total 764216 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 323 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 323 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 2534 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 2534 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 2857 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 2857 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 2857 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 2857 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9130 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7601 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 441038 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 775775 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 1233544 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 524912 # number of HardPFReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 229595 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 229595 # number of WriteInvalidateReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120541 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120541 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 147968 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 147968 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 205017 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 205017 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9130 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7601 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 441038 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 980792 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 1438561 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9130 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7601 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 441038 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 980792 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 524912 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 1963473 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 224849501 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 10375497328 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 18713747169 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 29541935250 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 17727784992 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 7402905507 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 7402905507 # number of WriteInvalidateReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2380480811 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2380480811 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2176947075 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2176947075 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1480998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1480998 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 6436785468 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 6436785468 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 224849501 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 10375497328 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 25150532637 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 35978720718 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 227841252 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 224849501 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 10375497328 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 25150532637 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 17727784992 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 53706505710 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8938250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 1841380999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 1850319249 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2067303001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2067303001 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 8938250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3908684000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3917622250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.230439 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.133350 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.611609 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.611609 # mshr miss rate for WriteInvalidateReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.682408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.682408 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.840661 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.840661 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.464080 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.464080 # mshr miss rate for WriteInvalidateReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.703753 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.703753 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.839473 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.839473 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193226 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193226 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.158158 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.041303 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.052181 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.099533 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.229620 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.208148 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.208148 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140548 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.222784 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 22345.362493 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 22234.428550 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 46551.597527 # average HardPFReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 27079.147948 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 27079.147948 # average WriteInvalidateReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16917.663474 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16917.663474 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13665.224287 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13665.224287 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 249333.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 249333.166667 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30989.120825 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30989.120825 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23371.034447 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22828.151261 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 24354.897355 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22000.738481 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24006.292202 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46551.597527 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 30095.390338 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -2246,66 +2229,63 @@ system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 11132088 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 9059631 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 23142 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 23142 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 3230902 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 957658 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1110389 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 467130 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 407372 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 365584 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 452132 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 59 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 1208854 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 1057926 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9875504 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14402767 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 299311 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 504421 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 25082003 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 316009528 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 537745480 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1072416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1728704 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 856556128 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 4579678 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 18388489 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.234421 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.423637 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 14077834 76.56% 76.56% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 4310655 23.44% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 18388489 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 10772824519 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 181931492 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 7414134377 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 7417250282 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 165377004 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 288475000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40416 # Transaction distribution -system.iobus.trans_dist::ReadResp 40416 # Transaction distribution -system.iobus.trans_dist::WriteReq 136984 # Transaction distribution -system.iobus.trans_dist::WriteResp 30064 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 106920 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48038 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 40336 # Transaction distribution +system.iobus.trans_dist::ReadResp 40336 # Transaction distribution +system.iobus.trans_dist::WriteReq 136623 # Transaction distribution +system.iobus.trans_dist::WriteResp 29895 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -2315,18 +2295,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123076 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231644 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231644 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354800 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48058 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2336,18 +2316,18 @@ system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17645 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156137 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7351344 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7351344 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155735 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7338856 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7509567 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36527000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7496677 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36212000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2367,7 +2347,7 @@ system.iobus.reqLayer16.occupancy 12000 # La system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 22064000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) @@ -2375,71 +2355,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1044902599 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 607542087 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93015000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179432954 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148516061 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115804 # number of replacements -system.iocache.tags.tagsinuse 11.285754 # Cycle average of tags in use +system.iocache.tags.replacements 115606 # number of replacements +system.iocache.tags.tagsinuse 11.280528 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115820 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115622 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 9175904776000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.836841 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 7.448912 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.239803 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.465557 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.705360 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 9179145722000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 7.421794 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 3.858734 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.463862 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.241171 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.705033 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1042755 # Number of tag accesses -system.iocache.tags.data_accesses 1042755 # Number of data accesses +system.iocache.tags.tag_accesses 1040802 # Number of tag accesses +system.iocache.tags.data_accesses 1040802 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8902 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8939 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8877 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8914 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 106920 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 106920 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8902 # number of demand (read+write) misses -system.iocache.demand_misses::total 8942 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8877 # number of demand (read+write) misses +system.iocache.demand_misses::total 8917 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8902 # number of overall misses -system.iocache.overall_misses::total 8942 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5707000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1942659591 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1948366591 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 357000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 357000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28987663054 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28987663054 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 6064000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1942659591 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1948723591 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 6064000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1942659591 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1948723591 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8877 # number of overall misses +system.iocache.overall_misses::total 8917 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1629440754 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1634636254 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19888935272 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19888935272 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1629440754 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1635005254 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1629440754 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1635005254 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8902 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8939 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8877 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8914 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 106920 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 106920 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8902 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8942 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8917 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8902 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8942 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8917 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -2453,55 +2433,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 154243.243243 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 218227.318692 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 217962.478018 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 119000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 119000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 271115.441957 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 271115.441957 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 217929.276560 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 151600 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 218227.318692 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 217929.276560 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 228501 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 183557.593106 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 183378.534216 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186351.615996 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 186351.615996 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183358.220702 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 183557.593106 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183358.220702 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 110662 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27689 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16220 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.252411 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.822565 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 106887 # number of writebacks -system.iocache.writebacks::total 106887 # number of writebacks +system.iocache.writebacks::writebacks 106699 # number of writebacks +system.iocache.writebacks::total 106699 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8902 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8939 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8877 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8914 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106920 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 106920 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8902 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8942 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8877 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8917 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8902 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8942 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3783000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1479616613 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1483399613 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 201000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23427435940 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23427435940 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3984000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1479616613 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1483600613 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3984000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1479616613 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1483600613 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8877 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8917 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166654804 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1169925304 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14339007344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14339007344 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1166654804 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1170138304 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1166654804 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1170138304 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -2515,560 +2495,561 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 102243.243243 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 166211.706695 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 165946.930641 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 67000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 67000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 219111.821362 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 219111.821362 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 99600 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 166211.706695 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 165913.734399 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131424.445646 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 131245.827238 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134350.942058 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134350.942058 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 131424.445646 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131225.558372 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1354462 # number of replacements -system.l2c.tags.tagsinuse 64231.297434 # Cycle average of tags in use -system.l2c.tags.total_refs 4107458 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1415378 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.902022 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9445810500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 19768.926665 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 228.224478 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 327.605712 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4403.400979 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 13076.363837 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14280.609802 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 81.212634 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 119.963342 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2392.943065 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3574.441825 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 5977.605096 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.301650 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.003482 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.004999 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.067191 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.199529 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217905 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001239 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.001830 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.036513 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.054542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.091211 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.980092 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 11341 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 263 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 49312 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 100 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 2022 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 9219 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 259 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 991 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 9958 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 38095 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.173050 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.004013 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.752441 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 56299103 # Number of tag accesses -system.l2c.tags.data_accesses 56299103 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 5350 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4570 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 461305 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 560254 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 286198 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 4527 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 3561 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 447471 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 478954 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 267354 # number of ReadReq hits -system.l2c.ReadReq_hits::total 2519544 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 2302237 # number of Writeback hits -system.l2c.Writeback_hits::total 2302237 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 120106 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 132921 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 253027 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 30097 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 26085 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 56182 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 6492 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 6040 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 12532 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 53617 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 43662 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 97279 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 5350 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4570 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 461305 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 613871 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 286198 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 4527 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 3561 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 447471 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 522616 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 267354 # number of demand (read+write) hits -system.l2c.demand_hits::total 2616823 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 5350 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4570 # number of overall hits -system.l2c.overall_hits::cpu0.inst 461305 # number of overall hits -system.l2c.overall_hits::cpu0.data 613871 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 286198 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 4527 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 3561 # number of overall hits -system.l2c.overall_hits::cpu1.inst 447471 # number of overall hits -system.l2c.overall_hits::cpu1.data 522616 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 267354 # number of overall hits -system.l2c.overall_hits::total 2616823 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 2413 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2450 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 52896 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 145508 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 228001 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 1040 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 936 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 43985 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 87538 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 186786 # number of ReadReq misses -system.l2c.ReadReq_misses::total 751553 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 416232 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 144931 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 561163 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 42338 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 43944 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 86282 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 11190 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 10651 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 21841 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 76863 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 48194 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 125057 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 2413 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2450 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 52896 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 222371 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 228001 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 1040 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 936 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 43985 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 135732 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 186786 # number of demand (read+write) misses -system.l2c.demand_misses::total 876610 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 2413 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2450 # number of overall misses -system.l2c.overall_misses::cpu0.inst 52896 # number of overall misses -system.l2c.overall_misses::cpu0.data 222371 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 228001 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 1040 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 936 # number of overall misses -system.l2c.overall_misses::cpu1.inst 43985 # number of overall misses -system.l2c.overall_misses::cpu1.data 135732 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 186786 # number of overall misses -system.l2c.overall_misses::total 876610 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 195380250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 200494999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 4090074480 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 12129961164 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 29105524558 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 84415498 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 77437999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3371676973 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 7239872891 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 24292116803 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 80786955615 # number of ReadReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 28586777 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 37049410 # number of WriteInvalidateReq miss cycles -system.l2c.WriteInvalidateReq_miss_latency::total 65636187 # number of WriteInvalidateReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 168593848 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 188274034 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 356867882 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 43019164 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 45414580 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 88433744 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6101127950 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 3658485827 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9759613777 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 195380250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 200494999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 4090074480 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 18231089114 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 29105524558 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 84415498 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 77437999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3371676973 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 10898358718 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 24292116803 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 90546569392 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 195380250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 200494999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 4090074480 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 18231089114 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 29105524558 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 84415498 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 77437999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3371676973 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 10898358718 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 24292116803 # number of overall miss cycles -system.l2c.overall_miss_latency::total 90546569392 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 7763 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 7020 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 514201 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 705762 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 514199 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 5567 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 4497 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 491456 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 566492 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 454140 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3271097 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 2302237 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 2302237 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 536338 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 277852 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 814190 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 72435 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 70029 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 142464 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 17682 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 16691 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 34373 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 130480 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 91856 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 222336 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 7763 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 7020 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 514201 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 836242 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 514199 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 5567 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 4497 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 491456 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 658348 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 454140 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3493433 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 7763 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 7020 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 514201 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 836242 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 514199 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 5567 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 4497 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 491456 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 658348 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 454140 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3493433 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.310833 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.349003 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.102870 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.206171 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.443410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.186815 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.208139 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.089499 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.154526 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.411296 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.229756 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.776063 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.521612 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.689229 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.584496 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.627511 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.605641 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.632847 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.638128 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.635412 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.589079 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.524669 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.562469 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.310833 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.349003 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.102870 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.265917 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.443410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.186815 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.208139 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.089499 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.206171 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.411296 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.250931 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.310833 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.349003 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.102870 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.265917 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.443410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.186815 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.208139 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.089499 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.206171 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.411296 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.250931 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80969.850808 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 81834.693469 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 77322.944646 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 83362.847156 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 127655.249573 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81168.748077 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 82732.904915 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 76655.154553 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 82705.486657 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 130053.198864 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 107493.357907 # average ReadReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 68.679912 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 255.634819 # average WriteInvalidateReq miss latency -system.l2c.WriteInvalidateReq_avg_miss_latency::total 116.964566 # average WriteInvalidateReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3982.092872 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4284.408201 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4136.064092 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 3844.429312 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 4263.879448 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 4048.978710 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 79376.656519 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75911.645163 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 78041.323373 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80969.850808 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 81834.693469 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 77322.944646 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 81985.012047 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 127655.249573 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81168.748077 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82732.904915 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76655.154553 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 80293.215439 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 130053.198864 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 103291.736795 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80969.850808 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 81834.693469 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 77322.944646 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 81985.012047 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 127655.249573 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81168.748077 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82732.904915 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76655.154553 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 80293.215439 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 130053.198864 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 103291.736795 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 198 # number of cycles access was blocked +system.l2c.tags.replacements 1063912 # number of replacements +system.l2c.tags.tagsinuse 64178.177670 # Cycle average of tags in use +system.l2c.tags.total_refs 3766892 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1123413 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.353079 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 11093199000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 24092.358885 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 75.949373 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 107.097830 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4212.805606 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 7550.293396 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 7226.795277 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 149.211397 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 222.509709 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4405.039325 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 7865.744621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8270.372252 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.367620 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001159 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.001634 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.064282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.115208 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.110272 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002277 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003395 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.067216 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.120022 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.126196 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.979281 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 9644 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 191 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 49666 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 226 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 9286 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 191 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 1430 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4883 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 43236 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.147156 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.002914 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.757843 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 50574940 # Number of tag accesses +system.l2c.tags.data_accesses 50574940 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 5180 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4259 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 469863 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 537542 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 313027 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 4490 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 3587 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 401752 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 405704 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 231220 # number of ReadReq hits +system.l2c.ReadReq_hits::total 2376624 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 2047649 # number of Writeback hits +system.l2c.Writeback_hits::total 2047649 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 135493 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 115685 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 251178 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 31239 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 22507 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 53746 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 6431 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 5062 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 11493 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 47681 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 46115 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 93796 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 5180 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4259 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 469863 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 585223 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 313027 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 4490 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 3587 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 401752 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 451819 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 231220 # number of demand (read+write) hits +system.l2c.demand_hits::total 2470420 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 5180 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4259 # number of overall hits +system.l2c.overall_hits::cpu0.inst 469863 # number of overall hits +system.l2c.overall_hits::cpu0.data 585223 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 313027 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 4490 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 3587 # number of overall hits +system.l2c.overall_hits::cpu1.inst 401752 # number of overall hits +system.l2c.overall_hits::cpu1.data 451819 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 231220 # number of overall hits +system.l2c.overall_hits::total 2470420 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 577 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 634 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 41076 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 94183 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 149529 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1129 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1344 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 39286 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 84710 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq misses +system.l2c.ReadReq_misses::total 531147 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 427179 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 105657 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 532836 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 47914 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 38699 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 86613 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 10572 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 7951 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 18523 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 64089 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 43672 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 107761 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 577 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 634 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 41076 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 158272 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 149529 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1129 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 1344 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 39286 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 128382 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) misses +system.l2c.demand_misses::total 638908 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 577 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 634 # number of overall misses +system.l2c.overall_misses::cpu0.inst 41076 # number of overall misses +system.l2c.overall_misses::cpu0.data 158272 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 149529 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1129 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 1344 # number of overall misses +system.l2c.overall_misses::cpu1.inst 39286 # number of overall misses +system.l2c.overall_misses::cpu1.data 128382 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 118679 # number of overall misses +system.l2c.overall_misses::total 638908 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 51297750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 55466264 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 3464868273 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 8461586857 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 98269250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.itb.walker 120308250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3289147097 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 7432991468 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 55049336677 # number of ReadReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 56781694 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 44775578 # number of WriteInvalidateReq miss cycles +system.l2c.WriteInvalidateReq_miss_latency::total 101557272 # number of WriteInvalidateReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 267824472 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 195648800 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 463473272 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 46262535 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 41400197 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 87662732 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5583608052 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 3566659435 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 9150267487 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 51297750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 55466264 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 3464868273 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 14045194909 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 98269250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 120308250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3289147097 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 10999650903 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 64199604164 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 51297750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 55466264 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 3464868273 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 14045194909 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18227791613 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 98269250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 120308250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3289147097 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 10999650903 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 13847609855 # number of overall miss cycles +system.l2c.overall_miss_latency::total 64199604164 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 5757 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4893 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 510939 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 631725 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 462556 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5619 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 4931 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 441038 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 490414 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 349899 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2907771 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 2047649 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 2047649 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 562672 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 221342 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 784014 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 79153 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 61206 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 140359 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 17003 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 13013 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 30016 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111770 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 89787 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 201557 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 5757 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4893 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 510939 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 743495 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 462556 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5619 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 4931 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 441038 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 580201 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 349899 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3109328 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 5757 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4893 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 510939 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 743495 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 462556 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5619 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 4931 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 441038 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 580201 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 349899 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3109328 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.129573 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.080393 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.149089 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.272561 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.089076 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.172732 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.182665 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.759197 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.477347 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.679626 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.605334 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.632275 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.617082 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.621773 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.611004 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.617104 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.573401 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.486396 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.534643 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.129573 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.080393 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.212876 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.272561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.089076 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.221272 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.205481 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.100226 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.129573 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.080393 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.212876 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.323267 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.200925 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.272561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.089076 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.221272 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.339181 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.205481 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 87486.220820 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84352.621312 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 89841.976333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89515.066964 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 83723.135392 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 87746.328273 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 103642.375231 # average ReadReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 132.922484 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 423.782409 # average WriteInvalidateReq miss latency +system.l2c.WriteInvalidateReq_avg_miss_latency::total 190.597617 # average WriteInvalidateReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5589.691364 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 5055.655185 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5351.082078 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 4375.949205 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5206.916992 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 4732.642229 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87122.720779 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 81669.248832 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 84912.607409 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 100483.331190 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88904.246101 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 87486.220820 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 84352.621312 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 88740.869573 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 121901.381090 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 87040.965456 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89515.066964 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 83723.135392 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 85679.074193 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 116681.214495 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 100483.331190 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 154 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 154 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1054885 # number of writebacks -system.l2c.writebacks::total 1054885 # number of writebacks +system.l2c.writebacks::writebacks 850996 # number of writebacks +system.l2c.writebacks::total 850996 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 92 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 68 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 78 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 18 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 256 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 20 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.l2cache.prefetcher 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.inst 88 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 223 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 92 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 68 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 78 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 256 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 88 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 21 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 223 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 92 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 68 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 78 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 256 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 2413 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2450 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 52804 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 145440 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 228001 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1040 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 936 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 43907 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 87520 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 186786 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 751297 # number of ReadReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 416232 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 144931 # number of WriteInvalidateReq MSHR misses -system.l2c.WriteInvalidateReq_mshr_misses::total 561163 # number of WriteInvalidateReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 42338 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 43944 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 86282 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 11190 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 10651 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 21841 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 76863 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 48194 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 125057 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 2413 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 2450 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 52804 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 222303 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 228001 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 1040 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 936 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 43907 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 135714 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 186786 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 876354 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 2413 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 2450 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 52804 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 222303 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 228001 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 1040 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 936 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 43907 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 135714 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 186786 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 876354 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 165146250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 169847499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3419732984 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10297367216 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 26304444558 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 71400998 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 65754499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2814972981 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 6141826747 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21997660303 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 71448154035 # number of ReadReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 9351321200 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 2933979052 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.WriteInvalidateReq_mshr_miss_latency::total 12285300252 # number of WriteInvalidateReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 426814585 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 447026638 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 873841223 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 112957622 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 108321571 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 221279193 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5133347486 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3050003137 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8183350623 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 165146250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 169847499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 3419732984 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 15430714702 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 26304444558 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 71400998 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 65754499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2814972981 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 9191829884 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21997660303 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 79631504658 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 165146250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 169847499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 3419732984 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 15430714702 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 26304444558 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 71400998 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 65754499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2814972981 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 9191829884 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21997660303 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 79631504658 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 1919142750 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6014500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3441525748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 7612880248 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1867778498 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 3390717000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 5258495498 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2246197250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 3786921248 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6014500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6832242748 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 12871375746 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.206075 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.154495 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.229677 # mshr miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.776063 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.521612 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.689229 # mshr miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.584496 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.627511 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.605641 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.632847 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.638128 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.635412 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.589079 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.524669 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.562469 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.250858 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.310833 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.349003 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.102691 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.265836 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.443410 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.186815 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.208139 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089341 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.206143 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.411296 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.250858 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 70801.479758 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 70176.265391 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 95099.746219 # average ReadReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 22466.608046 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 20243.971628 # average WriteInvalidateReq mshr miss latency -system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 21892.569988 # average WriteInvalidateReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10081.122986 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10172.643319 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10127.734904 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10094.514924 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10170.084593 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10131.367291 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66785.676932 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 63285.951301 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 65436.965728 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 68440.219644 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 69325.509796 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64762.763882 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69412.984539 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 115369.864860 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68654.805769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70250.533120 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64112.168470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67729.415418 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117769.320522 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 90866.823975 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu0.data 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 88 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 21 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 223 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 577 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 634 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 40984 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 94163 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1129 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1344 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 39198 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 84689 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 530924 # number of ReadReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 427179 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 105657 # number of WriteInvalidateReq MSHR misses +system.l2c.WriteInvalidateReq_mshr_misses::total 532836 # number of WriteInvalidateReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 47914 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 38699 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 86613 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 10572 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 7951 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 18523 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 64089 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 43672 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 107761 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 577 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 634 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 40984 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 158252 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1129 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 1344 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 39198 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 128361 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 638685 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 577 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 634 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 40984 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 158252 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 149527 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1129 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 1344 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 39198 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 128361 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 118679 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 638685 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 47468736 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2944278477 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 7281223143 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 103357750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2790521653 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 6370080782 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 48441561155 # number of ReadReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 13848705306 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 3323050924 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.WriteInvalidateReq_mshr_miss_latency::total 17171756230 # number of WriteInvalidateReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 851924300 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 688614575 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1540538875 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 188348548 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 142101429 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 330449977 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4782492948 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3019981565 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 7802474513 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 47468736 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 2944278477 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12063716091 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 103357750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 2790521653 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 9390062347 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 56244035668 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 44023250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 47468736 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 2944278477 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12063716091 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16390258603 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 84050250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 103357750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 2790521653 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 9390062347 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 12386298511 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 56244035668 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3774730500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6744750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1609448501 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 7996683251 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3450397000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1827911500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 5278308500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 7225127500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6744750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3437360001 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 13274991751 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.149057 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.182588 # mshr miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759197 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.477347 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.679626 # mshr miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.605334 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.632275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.617082 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.621773 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.611004 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.617104 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.573401 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.486396 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.534643 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.205409 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.100226 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.129573 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.080213 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.212849 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.323262 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200925 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.272561 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.088877 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.221235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.339181 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.205409 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 77325.734556 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 75217.333798 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 91240.104337 # average ReadReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32418.974964 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31451.308706 # average WriteInvalidateReq mshr miss latency +system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32227.094697 # average WriteInvalidateReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17780.279250 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17794.118065 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.462483 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17815.791525 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17872.145516 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.981482 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74622.680148 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69151.437191 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72405.364770 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 76296.793761 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 74871.823344 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71839.705178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 76231.049788 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109614.040294 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74446.634190 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76903.087798 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71190.409026 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73153.546225 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104368.072793 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -3083,58 +3064,58 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 841910 # Transaction distribution -system.membus.trans_dist::ReadResp 841910 # Transaction distribution -system.membus.trans_dist::WriteReq 38471 # Transaction distribution -system.membus.trans_dist::WriteResp 38471 # Transaction distribution -system.membus.trans_dist::Writeback 1161772 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 665270 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 665270 # Transaction distribution -system.membus.trans_dist::UpgradeReq 386597 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 321242 # Transaction distribution -system.membus.trans_dist::UpgradeResp 114625 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 138806 # Transaction distribution -system.membus.trans_dist::ReadExResp 121371 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123076 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 622157 # Transaction distribution +system.membus.trans_dist::ReadResp 622157 # Transaction distribution +system.membus.trans_dist::WriteReq 38973 # Transaction distribution +system.membus.trans_dist::WriteResp 38973 # Transaction distribution +system.membus.trans_dist::Writeback 957695 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution +system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution +system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution +system.membus.trans_dist::ReadExReq 123220 # Transaction distribution +system.membus.trans_dist::ReadExResp 104410 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122628 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25442 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4847759 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4996369 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336372 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 336372 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5332741 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156137 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 159245812 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 159453037 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14112640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14112640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 173565677 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 613627 # Total snoops (count) -system.membus.snoop_fanout::samples 3433927 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 581158 # Total snoops (count) +system.membus.snoop_fanout::samples 2928688 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3433927 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3433927 # Request fanout histogram -system.membus.reqLayer0.occupancy 100976496 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2928688 # Request fanout histogram +system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 55500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 22065500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 18062213474 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9212060141 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 187637046 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted @@ -3178,45 +3159,45 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 13 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 4185645 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 4178412 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 38471 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 38471 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 2302237 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 921111 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 814190 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 436280 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 333774 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 770054 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 100 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 100 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 280654 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 280654 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7279651 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5709072 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 12988723 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 243910125 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 179631296 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 423541421 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1593139 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 8378399 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.013829 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.116780 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1518303 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 8262536 98.62% 98.62% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 115863 1.38% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 8378399 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 16938572035 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 7678500 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 11018810399 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 9692180196 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt index 11eb5dd0c..d577712e0 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-simple-timing/stats.txt @@ -1,138 +1,138 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.821157 # Number of seconds simulated -sim_ticks 51821157171000 # Number of ticks simulated -final_tick 51821157171000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.824462 # Number of seconds simulated +sim_ticks 51824462100500 # Number of ticks simulated +final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 734878 # Simulator instruction rate (inst/s) -host_op_rate 863519 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 42416153440 # Simulator tick rate (ticks/s) -host_mem_usage 712380 # Number of bytes of host memory used -host_seconds 1221.73 # Real time elapsed on the host -sim_insts 897823750 # Number of instructions simulated -sim_ops 1054987960 # Number of ops (including micro ops) simulated +host_inst_rate 723017 # Simulator instruction rate (inst/s) +host_op_rate 849578 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 41937024652 # Simulator tick rate (ticks/s) +host_mem_usage 712044 # Number of bytes of host memory used +host_seconds 1235.77 # Real time elapsed on the host +sim_insts 893481288 # Number of instructions simulated +sim_ops 1049881338 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 267456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 270528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 5250612 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 52674824 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 383808 # Number of bytes read from this memory -system.physmem.bytes_read::total 58847228 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 5250612 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5250612 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 79637568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 266048 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 259456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 5261620 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 50351624 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 398272 # Number of bytes read from this memory +system.physmem.bytes_read::total 56537020 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 5261620 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5261620 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 77705792 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 79658148 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 4179 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 4227 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 122448 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 823057 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 5997 # Number of read requests responded to by this memory -system.physmem.num_reads::total 959908 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1244337 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 77726372 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 4157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 4054 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 122620 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 786757 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6223 # Number of read requests responded to by this memory +system.physmem.num_reads::total 923811 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1214153 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1246910 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 5161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 5220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 101322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1016473 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 7406 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1135583 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 101322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 101322 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1536777 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1216726 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 5134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 5006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 101528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 971580 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 7685 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1090933 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 101528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 101528 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499404 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1537174 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1536777 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 5161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 5220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 101322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1016870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 7406 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2672757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 959908 # Number of read requests accepted -system.physmem.writeReqs 1865455 # Number of write requests accepted -system.physmem.readBursts 959908 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 1865455 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 61382336 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 51776 # Total number of bytes read from write queue -system.physmem.bytesWritten 118954432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 58847228 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 119245028 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 809 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6774 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 36275 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 56974 # Per bank write bursts -system.physmem.perBankRdBursts::1 60608 # Per bank write bursts -system.physmem.perBankRdBursts::2 56247 # Per bank write bursts -system.physmem.perBankRdBursts::3 58787 # Per bank write bursts -system.physmem.perBankRdBursts::4 55621 # Per bank write bursts -system.physmem.perBankRdBursts::5 61105 # Per bank write bursts -system.physmem.perBankRdBursts::6 53454 # Per bank write bursts -system.physmem.perBankRdBursts::7 55202 # Per bank write bursts -system.physmem.perBankRdBursts::8 54549 # Per bank write bursts -system.physmem.perBankRdBursts::9 101006 # Per bank write bursts -system.physmem.perBankRdBursts::10 57136 # Per bank write bursts -system.physmem.perBankRdBursts::11 59250 # Per bank write bursts -system.physmem.perBankRdBursts::12 54470 # Per bank write bursts -system.physmem.perBankRdBursts::13 61564 # Per bank write bursts -system.physmem.perBankRdBursts::14 57688 # Per bank write bursts -system.physmem.perBankRdBursts::15 55438 # Per bank write bursts -system.physmem.perBankWrBursts::0 113578 # Per bank write bursts -system.physmem.perBankWrBursts::1 118177 # Per bank write bursts -system.physmem.perBankWrBursts::2 119014 # Per bank write bursts -system.physmem.perBankWrBursts::3 122732 # Per bank write bursts -system.physmem.perBankWrBursts::4 115108 # Per bank write bursts -system.physmem.perBankWrBursts::5 118421 # Per bank write bursts -system.physmem.perBankWrBursts::6 110433 # Per bank write bursts -system.physmem.perBankWrBursts::7 110649 # Per bank write bursts -system.physmem.perBankWrBursts::8 111009 # Per bank write bursts -system.physmem.perBankWrBursts::9 115530 # Per bank write bursts -system.physmem.perBankWrBursts::10 116272 # Per bank write bursts -system.physmem.perBankWrBursts::11 116171 # Per bank write bursts -system.physmem.perBankWrBursts::12 116950 # Per bank write bursts -system.physmem.perBankWrBursts::13 121923 # Per bank write bursts -system.physmem.perBankWrBursts::14 117171 # Per bank write bursts -system.physmem.perBankWrBursts::15 115525 # Per bank write bursts +system.physmem.bw_write::total 1499801 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 5134 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 5006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 101528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 971977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 7685 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2590734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 923811 # Number of read requests accepted +system.physmem.writeReqs 1833124 # Number of write requests accepted +system.physmem.readBursts 923811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 1833124 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 59092736 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 31168 # Total number of bytes read from write queue +system.physmem.bytesWritten 114062016 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 56537020 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 117175844 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 487 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 50880 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 36215 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 57129 # Per bank write bursts +system.physmem.perBankRdBursts::1 60965 # Per bank write bursts +system.physmem.perBankRdBursts::2 52485 # Per bank write bursts +system.physmem.perBankRdBursts::3 50413 # Per bank write bursts +system.physmem.perBankRdBursts::4 54002 # Per bank write bursts +system.physmem.perBankRdBursts::5 59718 # Per bank write bursts +system.physmem.perBankRdBursts::6 51713 # Per bank write bursts +system.physmem.perBankRdBursts::7 51669 # Per bank write bursts +system.physmem.perBankRdBursts::8 50247 # Per bank write bursts +system.physmem.perBankRdBursts::9 101235 # Per bank write bursts +system.physmem.perBankRdBursts::10 59848 # Per bank write bursts +system.physmem.perBankRdBursts::11 58323 # Per bank write bursts +system.physmem.perBankRdBursts::12 55369 # Per bank write bursts +system.physmem.perBankRdBursts::13 55988 # Per bank write bursts +system.physmem.perBankRdBursts::14 51743 # Per bank write bursts +system.physmem.perBankRdBursts::15 52477 # Per bank write bursts +system.physmem.perBankWrBursts::0 110630 # Per bank write bursts +system.physmem.perBankWrBursts::1 112240 # Per bank write bursts +system.physmem.perBankWrBursts::2 108805 # Per bank write bursts +system.physmem.perBankWrBursts::3 108103 # Per bank write bursts +system.physmem.perBankWrBursts::4 111102 # Per bank write bursts +system.physmem.perBankWrBursts::5 113339 # Per bank write bursts +system.physmem.perBankWrBursts::6 105567 # Per bank write bursts +system.physmem.perBankWrBursts::7 107723 # Per bank write bursts +system.physmem.perBankWrBursts::8 108849 # Per bank write bursts +system.physmem.perBankWrBursts::9 115780 # Per bank write bursts +system.physmem.perBankWrBursts::10 115663 # Per bank write bursts +system.physmem.perBankWrBursts::11 113049 # Per bank write bursts +system.physmem.perBankWrBursts::12 112494 # Per bank write bursts +system.physmem.perBankWrBursts::13 116984 # Per bank write bursts +system.physmem.perBankWrBursts::14 111502 # Per bank write bursts +system.physmem.perBankWrBursts::15 110389 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 1 # Number of times write queue was full causing retry -system.physmem.totGap 51821154615000 # Total gap between requests +system.physmem.numWrRetry 145 # Number of times write queue was full causing retry +system.physmem.totGap 51824459475500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 43101 # Read request sizes (log2) system.physmem.readPktSize::3 13 # Read request sizes (log2) system.physmem.readPktSize::4 2 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 916792 # Read request sizes (log2) +system.physmem.readPktSize::6 880695 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 1 # Write request sizes (log2) system.physmem.writePktSize::3 2572 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 1862882 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 923488 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 30071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 548 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 197 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 102 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 100 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 96 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 84 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 78 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 56 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 45 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 1830551 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 889155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 28186 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 257 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 462 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 455 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 746 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 480 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1765 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 102 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 92 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -159,181 +159,165 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 58678 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 72148 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 102041 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 104846 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 108153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 122813 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 127000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 113028 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 114051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 111714 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 109570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 106267 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 103051 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 101586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 96822 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 95736 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 95578 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 94283 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 3053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 2654 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 2224 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 1788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1599 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 637 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 502 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 347 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 269 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 242 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 150 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 51 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 18 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 1 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 618930 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 291.368084 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 166.608476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 330.498173 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 256436 41.43% 41.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 152224 24.59% 66.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 51996 8.40% 74.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 28892 4.67% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 20098 3.25% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 13547 2.19% 84.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 10018 1.62% 86.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 9306 1.50% 87.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 76413 12.35% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 618930 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 92468 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 10.372118 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 105.903641 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-1023 92466 100.00% 100.00% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 57524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 60978 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 91825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 117209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 106855 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 97040 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 98714 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 93369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 94185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 92986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 93402 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 98737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 96397 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 94916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 105152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 97025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 94048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 92817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 5441 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 5084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 5738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 7709 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 7730 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 6924 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 6738 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 7452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 5737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 5138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 4676 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 5004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 4547 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 3838 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 3903 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 3022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 2209 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 1452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 1128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 643 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 524 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 509 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 510 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 478 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 329 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 603787 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 286.780656 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 164.845955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 326.273004 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 251324 41.62% 41.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 149673 24.79% 66.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 51779 8.58% 74.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 28017 4.64% 79.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 19714 3.27% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 13055 2.16% 85.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 9885 1.64% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 8959 1.48% 88.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 71381 11.82% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 603787 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 89136 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 10.358104 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 107.922360 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-1023 89134 100.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 92468 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 92468 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.100608 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.118632 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.444453 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 55053 59.54% 59.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 30512 33.00% 92.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 2134 2.31% 94.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 1149 1.24% 96.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 862 0.93% 97.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 455 0.49% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 271 0.29% 97.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 154 0.17% 97.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 523 0.57% 98.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 85 0.09% 98.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 63 0.07% 98.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 90 0.10% 98.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 138 0.15% 98.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 53 0.06% 99.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 45 0.05% 99.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 77 0.08% 99.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 126 0.14% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 47 0.05% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 24 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 42 0.05% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 157 0.17% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 6 0.01% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 21 0.02% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 16 0.02% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 59 0.06% 99.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 9 0.01% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 28 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 35 0.04% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 128 0.14% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 15 0.02% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.00% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 6 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 16 0.02% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 15 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 3 0.00% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 7 0.01% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 10 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 3 0.00% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 5 0.01% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 2 0.00% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 4 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 2 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 3 0.00% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::248-251 1 0.00% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 92468 # Writes before turning the bus around for reads -system.physmem.totQLat 12424177254 # Total ticks spent queuing -system.physmem.totMemAccLat 30407283504 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4795495000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12954.01 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 89136 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 89136 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.994379 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.728374 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 17.051434 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 87330 97.97% 97.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 694 0.78% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 23 0.03% 98.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 47 0.05% 98.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 149 0.17% 99.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 187 0.21% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 322 0.36% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 118 0.13% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 42 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 62 0.07% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 32 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 11 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 9 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 3 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.00% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.00% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 10 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 26 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.00% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::432-447 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 5 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 2 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 4 0.00% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::640-655 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 89136 # Writes before turning the bus around for reads +system.physmem.totQLat 12043609520 # Total ticks spent queuing +system.physmem.totMemAccLat 29355934520 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4616620000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13043.75 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31704.01 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.18 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.30 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.14 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.30 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 31793.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.14 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 2.20 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.26 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.29 # Average write queue length when enqueuing -system.physmem.readRowHits 722238 # Number of row buffer hits during reads -system.physmem.writeRowHits 1476593 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.44 # Row buffer hit rate for writes -system.physmem.avgGap 18341414.75 # Average gap between requests -system.physmem.pageHitRate 78.03 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 2336584320 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 1274922000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 3572345400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 6014165760 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 1308692927565 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 29944715868000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 34651312636245 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.671195 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 49815023694250 # Time in different power states -system.physmem_0.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem.avgWrQLen 25.36 # Average write queue length when enqueuing +system.physmem.readRowHits 694872 # Number of row buffer hits during reads +system.physmem.writeRowHits 1406883 # Number of row buffer hits during writes +system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 78.94 # Row buffer hit rate for writes +system.physmem.avgGap 18797853.22 # Average gap between requests +system.physmem.pageHitRate 77.68 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 2251693080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 1228602375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 3417133200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 5686258320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 1307306510865 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 29947912845000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 34652724495480 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.655841 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 49820369752426 # Time in different power states +system.physmem_0.memoryStateTime::REF 1730532440000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 275710901250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 273552725074 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 2342526480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 1278164250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3908587800 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 6029970480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 3384705823200 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 1310912306640 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 29942769044250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 34651946423100 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.683425 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 49811721549250 # Time in different power states -system.physmem_1.memoryStateTime::REF 1730422200000 # Time in different power states +system.physmem_1.actEnergy 2312936640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 1262019000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 3784755000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 5862520800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 3384921452640 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 1309001038785 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 29946426417000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 34653571139865 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.672178 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 49817859630672 # Time in different power states +system.physmem_1.memoryStateTime::REF 1730532440000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 279009798250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 276069619328 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu.data 36 # Number of bytes read from this memory @@ -387,73 +371,68 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 215397 # Table walker walks requested -system.cpu.dtb.walker.walksLong 215397 # Table walker walks initiated with long descriptors -system.cpu.dtb.walker.walksLongTerminationLevel::Level2 16603 # Level at which table walker walks with long descriptors terminate -system.cpu.dtb.walker.walksLongTerminationLevel::Level3 166513 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walks 211321 # Table walker walks requested +system.cpu.dtb.walker.walksLong 211321 # Table walker walks initiated with long descriptors +system.cpu.dtb.walker.walksLongTerminationLevel::Level2 15784 # Level at which table walker walks with long descriptors terminate +system.cpu.dtb.walker.walksLongTerminationLevel::Level3 163511 # Level at which table walker walks with long descriptors terminate system.cpu.dtb.walker.walksSquashedBefore 14 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 215383 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 0.157858 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 54.935133 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-2047 215381 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::samples 211307 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 0.170368 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 58.877055 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-2047 211305 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::10240-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::22528-24575 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 215383 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 183130 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 21825.061432 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 17519.574906 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 14463.524428 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 181175 98.93% 98.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 4 0.00% 98.93% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1496 0.82% 99.75% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 183 0.10% 99.85% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 74 0.04% 99.89% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::163840-196607 58 0.03% 99.92% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::196608-229375 49 0.03% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::229376-262143 36 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::262144-294911 18 0.01% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 14 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::327680-360447 8 0.00% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::360448-393215 11 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 183130 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 800972760 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 2.488036 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 -1191876296 -148.80% -148.80% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::1 1992849056 248.80% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 800972760 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 166514 90.93% 90.93% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::2M 16603 9.07% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 183117 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 215397 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::total 211307 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 179309 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 23338.389317 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 19372.996771 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 15325.519359 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-65535 177365 98.92% 98.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-131071 1663 0.93% 99.84% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-196607 114 0.06% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::196608-262143 88 0.05% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-327679 58 0.03% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::327680-393215 14 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 179309 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples -200578036 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean -2.729096 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 -747974796 372.91% 372.91% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::1 547396760 -272.91% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total -200578036 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 163512 91.20% 91.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::2M 15784 8.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 179296 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 211321 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 215397 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 183117 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 211321 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 179296 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 183117 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 398514 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 179296 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 390617 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 168647599 # DTB read hits -system.cpu.dtb.read_misses 158984 # DTB read misses -system.cpu.dtb.write_hits 153347297 # DTB write hits -system.cpu.dtb.write_misses 56413 # DTB write misses +system.cpu.dtb.read_hits 167775531 # DTB read hits +system.cpu.dtb.read_misses 155743 # DTB read misses +system.cpu.dtb.write_hits 152648275 # DTB write hits +system.cpu.dtb.write_misses 55578 # DTB write misses system.cpu.dtb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.dtb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID -system.cpu.dtb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 74349 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 75520 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 8039 # Number of TLB faults due to prefetch +system.cpu.dtb.prefetch_faults 8371 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 19949 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 168806583 # DTB read accesses -system.cpu.dtb.write_accesses 153403710 # DTB write accesses +system.cpu.dtb.perms_faults 19881 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 167931274 # DTB read accesses +system.cpu.dtb.write_accesses 152703853 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 321994896 # DTB hits -system.cpu.dtb.misses 215397 # DTB misses -system.cpu.dtb.accesses 322210293 # DTB accesses +system.cpu.dtb.hits 320423806 # DTB hits +system.cpu.dtb.misses 211321 # DTB misses +system.cpu.dtb.accesses 320635127 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,91 +462,97 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 123370 # Table walker walks requested -system.cpu.itb.walker.walksLong 123370 # Table walker walks initiated with long descriptors -system.cpu.itb.walker.walksLongTerminationLevel::Level2 1120 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walksLongTerminationLevel::Level3 111048 # Level at which table walker walks with long descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 123370 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 123370 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 123370 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 112168 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 24898.509379 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 20785.013360 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 17155.421945 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-65535 109848 97.93% 97.93% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::65536-131071 2031 1.81% 99.74% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::131072-196607 132 0.12% 99.86% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::196608-262143 101 0.09% 99.95% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::262144-327679 23 0.02% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::327680-393215 19 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 112168 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples -1257598296 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 -1257598296 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total -1257598296 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 111048 99.00% 99.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::2M 1120 1.00% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 112168 # Table walker page sizes translated +system.cpu.itb.walker.walks 122916 # Table walker walks requested +system.cpu.itb.walker.walksLong 122916 # Table walker walks initiated with long descriptors +system.cpu.itb.walker.walksLongTerminationLevel::Level2 1122 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walksLongTerminationLevel::Level3 110644 # Level at which table walker walks with long descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 122916 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 122916 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 122916 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 111766 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 26583.507059 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 22687.613632 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 18325.329143 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-32767 56090 50.19% 50.19% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-65535 53429 47.80% 97.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::65536-98303 753 0.67% 98.66% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::98304-131071 1184 1.06% 99.72% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::131072-163839 19 0.02% 99.74% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::163840-196607 105 0.09% 99.83% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::196608-229375 43 0.04% 99.87% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::229376-262143 54 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::262144-294911 30 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::294912-327679 11 0.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::327680-360447 20 0.02% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::360448-393215 11 0.01% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::393216-425983 8 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::425984-458751 2 0.00% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::458752-491519 4 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::491520-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 111766 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples -853761296 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 -853761296 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total -853761296 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 110644 99.00% 99.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::2M 1122 1.00% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 111766 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 123370 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 123370 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 122916 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 122916 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 112168 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 112168 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 235538 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 898375907 # ITB inst hits -system.cpu.itb.inst_misses 123370 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 111766 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 111766 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 234682 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 894030670 # ITB inst hits +system.cpu.itb.inst_misses 122916 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.itb.flush_tlb 10 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu.itb.flush_tlb_mva_asid 43021 # Number of times TLB was flushed by MVA & ASID -system.cpu.itb.flush_tlb_asid 1067 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 52826 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_tlb_mva_asid 42687 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 1063 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 53866 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 898499277 # ITB inst accesses -system.cpu.itb.hits 898375907 # DTB hits -system.cpu.itb.misses 123370 # DTB misses -system.cpu.itb.accesses 898499277 # DTB accesses -system.cpu.numCycles 103642314342 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 894153586 # ITB inst accesses +system.cpu.itb.hits 894030670 # DTB hits +system.cpu.itb.misses 122916 # DTB misses +system.cpu.itb.accesses 894153586 # DTB accesses +system.cpu.numCycles 103648924201 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 897823750 # Number of instructions committed -system.cpu.committedOps 1054987960 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 968534129 # Number of integer alu accesses -system.cpu.num_fp_alu_accesses 900653 # Number of float alu accesses -system.cpu.num_func_calls 53156799 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 137185420 # number of instructions that are conditional controls -system.cpu.num_int_insts 968534129 # number of integer instructions -system.cpu.num_fp_insts 900653 # number of float instructions -system.cpu.num_int_register_reads 1413400107 # number of times the integer registers were read -system.cpu.num_int_register_writes 768429309 # number of times the integer registers were written -system.cpu.num_fp_register_reads 1451290 # number of times the floating registers were read -system.cpu.num_fp_register_writes 764324 # number of times the floating registers were written -system.cpu.num_cc_register_reads 236274909 # number of times the CC registers were read -system.cpu.num_cc_register_writes 235673566 # number of times the CC registers were written -system.cpu.num_mem_refs 321978685 # number of memory refs -system.cpu.num_load_insts 168640749 # Number of load instructions -system.cpu.num_store_insts 153337936 # Number of store instructions -system.cpu.num_idle_cycles 100474351324.032059 # Number of idle cycles -system.cpu.num_busy_cycles 3167963017.967939 # Number of busy cycles -system.cpu.not_idle_fraction 0.030566 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.969434 # Percentage of idle cycles -system.cpu.Branches 200551202 # Number of branches fetched +system.cpu.committedInsts 893481288 # Number of instructions committed +system.cpu.committedOps 1049881338 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 963989017 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 895873 # Number of float alu accesses +system.cpu.num_func_calls 52999943 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 136446519 # number of instructions that are conditional controls +system.cpu.num_int_insts 963989017 # number of integer instructions +system.cpu.num_fp_insts 895873 # number of float instructions +system.cpu.num_int_register_reads 1405913792 # number of times the integer registers were read +system.cpu.num_int_register_writes 764688301 # number of times the integer registers were written +system.cpu.num_fp_register_reads 1443674 # number of times the floating registers were read +system.cpu.num_fp_register_writes 760516 # number of times the floating registers were written +system.cpu.num_cc_register_reads 234750393 # number of times the CC registers were read +system.cpu.num_cc_register_writes 234155899 # number of times the CC registers were written +system.cpu.num_mem_refs 320407593 # number of memory refs +system.cpu.num_load_insts 167768846 # Number of load instructions +system.cpu.num_store_insts 152638747 # Number of store instructions +system.cpu.num_idle_cycles 100474792122.552063 # Number of idle cycles +system.cpu.num_busy_cycles 3174132078.447939 # Number of busy cycles +system.cpu.not_idle_fraction 0.030624 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.969376 # Percentage of idle cycles +system.cpu.Branches 199584978 # Number of branches fetched system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 731167173 69.27% 69.27% # Class of executed instruction -system.cpu.op_class::IntMult 2227672 0.21% 69.48% # Class of executed instruction -system.cpu.op_class::IntDiv 99245 0.01% 69.49% # Class of executed instruction +system.cpu.op_class::IntAlu 727639004 69.27% 69.27% # Class of executed instruction +system.cpu.op_class::IntMult 2217476 0.21% 69.48% # Class of executed instruction +system.cpu.op_class::IntDiv 99175 0.01% 69.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction system.cpu.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction @@ -590,126 +575,126 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 69.49% # Cl system.cpu.op_class::SimdFloatCmp 13 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 21 0.00% 69.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 110423 0.01% 69.50% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 110553 0.01% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction -system.cpu.op_class::MemRead 168640749 15.98% 85.47% # Class of executed instruction -system.cpu.op_class::MemWrite 153337936 14.53% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 167768846 15.97% 85.47% # Class of executed instruction +system.cpu.op_class::MemWrite 152638747 14.53% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 1055583241 # Class of executed instruction +system.cpu.op_class::total 1050473844 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 16365 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 10281150 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.969700 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 311526777 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 10281662 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 30.299263 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 3093156250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.969700 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999941 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999941 # Average percentage of cache occupancy +system.cpu.kern.inst.quiesce 16327 # number of quiesce instructions executed +system.cpu.dcache.tags.replacements 10213653 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.965664 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 310015199 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 10214165 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 30.351497 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 3500615250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.965664 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999933 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999933 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 401 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 64 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1297920552 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1297920552 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 157560037 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 157560037 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 145486469 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 145486469 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 397138 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 397138 # number of SoftPFReq hits -system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 335387 # number of WriteInvalidateReq hits -system.cpu.dcache.WriteInvalidateReq_hits::total 335387 # number of WriteInvalidateReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 3699332 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 3699332 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 4002690 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 4002690 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 303046506 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 303046506 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 303443644 # number of overall hits -system.cpu.dcache.overall_hits::total 303443644 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 5342305 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 5342305 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2238545 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2238545 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 1309963 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 1309963 # number of SoftPFReq misses -system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232790 # number of WriteInvalidateReq misses -system.cpu.dcache.WriteInvalidateReq_misses::total 1232790 # number of WriteInvalidateReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 305057 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 305057 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 1291569953 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1291569953 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 156758765 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 156758765 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 144836105 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 144836105 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 393576 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 393576 # number of SoftPFReq hits +system.cpu.dcache.WriteInvalidateReq_hits::cpu.data 334400 # number of WriteInvalidateReq hits +system.cpu.dcache.WriteInvalidateReq_hits::total 334400 # number of WriteInvalidateReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 3672090 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 3672090 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 3974747 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 3974747 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 301594870 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 301594870 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 301988446 # number of overall hits +system.cpu.dcache.overall_hits::total 301988446 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 5315823 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 5315823 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2219045 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2219045 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 1297249 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 1297249 # number of SoftPFReq misses +system.cpu.dcache.WriteInvalidateReq_misses::cpu.data 1232796 # number of WriteInvalidateReq misses +system.cpu.dcache.WriteInvalidateReq_misses::total 1232796 # number of WriteInvalidateReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 304342 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 304342 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 7580850 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 7580850 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 8890813 # number of overall misses -system.cpu.dcache.overall_misses::total 8890813 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 83595802503 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 83595802503 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 64185055523 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 64185055523 # number of WriteReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 27578524507 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.WriteInvalidateReq_miss_latency::total 27578524507 # number of WriteInvalidateReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4441396750 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 4441396750 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 150000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 147780858026 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 147780858026 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 147780858026 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 147780858026 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 162902342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 162902342 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 147725014 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 147725014 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 1707101 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 1707101 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1568177 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.WriteInvalidateReq_accesses::total 1568177 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 4004389 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 4004389 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 4002692 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 4002692 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 310627356 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 310627356 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 312334457 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 312334457 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032795 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.032795 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015153 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.015153 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767361 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.767361 # miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786129 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786129 # miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076181 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.024405 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.024405 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.028466 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.028466 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15647.890284 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15647.890284 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28672.667077 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 28672.667077 # average WriteReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 22370.821070 # average WriteInvalidateReq miss latency -system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 22370.821070 # average WriteInvalidateReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14559.235651 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14559.235651 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19493.969413 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19493.969413 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 16621.748543 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 16621.748543 # average overall miss latency +system.cpu.dcache.demand_misses::cpu.data 7534868 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 7534868 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 8832117 # number of overall misses +system.cpu.dcache.overall_misses::total 8832117 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 84066704475 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 84066704475 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66382286210 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66382286210 # number of WriteReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::cpu.data 32849513005 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.WriteInvalidateReq_miss_latency::total 32849513005 # number of WriteInvalidateReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 4463810234 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 4463810234 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 164000 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 150448990685 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 150448990685 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 150448990685 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 150448990685 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 162074588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 162074588 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 147055150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 147055150 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 1690825 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 1690825 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::cpu.data 1567196 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.WriteInvalidateReq_accesses::total 1567196 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3976432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 3976432 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 3974749 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 3974749 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 309129738 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 309129738 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 310820563 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 310820563 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.032799 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.032799 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015090 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.015090 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.767228 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.767228 # miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::cpu.data 0.786625 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_miss_rate::total 0.786625 # miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.076536 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.076536 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.024374 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.024374 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.028415 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.028415 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15814.428824 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15814.428824 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29914.799479 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 29914.799479 # average WriteReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::cpu.data 26646.349441 # average WriteInvalidateReq miss latency +system.cpu.dcache.WriteInvalidateReq_avg_miss_latency::total 26646.349441 # average WriteInvalidateReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14667.085825 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14667.085825 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 82000 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 82000 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 19967.037337 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 19967.037337 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 17034.306802 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 17034.306802 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -718,88 +703,88 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 7913457 # number of writebacks -system.cpu.dcache.writebacks::total 7913457 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7211 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7211 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21165 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 21165 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 71123 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 71123 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 28376 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 28376 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 28376 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 28376 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5335094 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 5335094 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2217380 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 2217380 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1308216 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 1308216 # number of SoftPFReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232790 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232790 # number of WriteInvalidateReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233934 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 233934 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 7878976 # number of writebacks +system.cpu.dcache.writebacks::total 7878976 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 16016 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 16016 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 21118 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 21118 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 70685 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 70685 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 37134 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 37134 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 37134 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 37134 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 5299807 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 5299807 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2197927 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 2197927 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1295520 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 1295520 # number of SoftPFReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::cpu.data 1232796 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.WriteInvalidateReq_mshr_misses::total 1232796 # number of WriteInvalidateReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 233657 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 233657 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 7552474 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 7552474 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 8860690 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 8860690 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 72364530247 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 72364530247 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58930269477 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 58930269477 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 19541293498 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 19541293498 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 25112944493 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 25112944493 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2872283000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2872283000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 131294799724 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 131294799724 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 150836093222 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 150836093222 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5727964499 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5727964499 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5573385250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5573385250 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11301349749 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 11301349749 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015010 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015010 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766338 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766338 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786129 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786129 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058419 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058419 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000000 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024314 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.024314 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028369 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.028369 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13563.871648 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13563.871648 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 26576.531527 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 26576.531527 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14937.360113 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14937.360113 # average SoftPFReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 20370.821059 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 20370.821059 # average WriteInvalidateReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12278.176751 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12278.176751 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17384.343160 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17384.343160 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17023.064030 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 17023.064030 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_misses::cpu.data 7497734 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 62224351540 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 20153084274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 20153084274 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::cpu.data 31000318995 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.WriteInvalidateReq_mshr_miss_latency::total 31000318995 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 2998156750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 2998156750 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 161000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137713909065 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 137713909065 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 157866993339 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 157866993339 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5751194250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5751194250 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 5618584250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 5618584250 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 11369778500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 11369778500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032700 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032700 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.014946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.014946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.766206 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.766206 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.786625 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.786625 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.058760 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.058760 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.024254 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.024254 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.028290 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.028290 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14243.831431 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14243.831431 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28310.472341 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28310.472341 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 15555.980822 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 15555.980822 # average SoftPFReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 25146.349433 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25146.349433 # average WriteInvalidateReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12831.444168 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12831.444168 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 80500 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18367.403947 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -807,59 +792,59 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13791662 # number of replacements -system.cpu.icache.tags.tagsinuse 511.892960 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 884583728 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 13792174 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 64.136642 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 31822438250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.892960 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.999791 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.999791 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 13753173 # number of replacements +system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 880276980 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 13753685 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 64.002991 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 35133104250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.880059 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.999766 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.999766 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 193 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 912168086 # Number of tag accesses -system.cpu.icache.tags.data_accesses 912168086 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 884583728 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 884583728 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 884583728 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 884583728 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 884583728 # number of overall hits -system.cpu.icache.overall_hits::total 884583728 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 13792179 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 13792179 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 13792179 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 13792179 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 13792179 # number of overall misses -system.cpu.icache.overall_misses::total 13792179 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 184446403226 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 184446403226 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 184446403226 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 184446403226 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 184446403226 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 184446403226 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 898375907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 898375907 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 898375907 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 898375907 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 898375907 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 898375907 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015352 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.015352 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.015352 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.015352 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.015352 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.015352 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13373.260543 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13373.260543 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13373.260543 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13373.260543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13373.260543 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13373.260543 # average overall miss latency +system.cpu.icache.tags.tag_accesses 907784360 # Number of tag accesses +system.cpu.icache.tags.data_accesses 907784360 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 880276980 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 880276980 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 880276980 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 880276980 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 880276980 # number of overall hits +system.cpu.icache.overall_hits::total 880276980 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 13753690 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 13753690 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 13753690 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 13753690 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 13753690 # number of overall misses +system.cpu.icache.overall_misses::total 13753690 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 184520052183 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 184520052183 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 184520052183 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 184520052183 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 184520052183 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 184520052183 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 894030670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 894030670 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 894030670 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 894030670 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 894030670 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 894030670 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015384 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.015384 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.015384 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.015384 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.015384 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.015384 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13416.039782 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13416.039782 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13416.039782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13416.039782 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13416.039782 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -868,208 +853,209 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13792179 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 13792179 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 13792179 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 13792179 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 13792179 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 13792179 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 156833610274 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 156833610274 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 156833610274 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 156833610274 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 156833610274 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 156833610274 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 2831639000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 2831639000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 2831639000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 2831639000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015352 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.015352 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015352 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.015352 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11371.198871 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11371.198871 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11371.198871 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11371.198871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11371.198871 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11371.198871 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 13753690 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 13753690 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 13753690 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 163860958817 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 163860958817 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 163860958817 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 3211087000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 3211087000 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 3211087000 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 3211087000 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.015384 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.015384 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.015384 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.015384 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11913.963367 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11913.963367 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 1330655 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65236.148872 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 27755474 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 1393687 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 19.915142 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 6373825000 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 38814.158351 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 314.572055 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 427.557921 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 6384.961919 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 19294.898626 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.592257 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004800 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006524 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.097427 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.294417 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.995425 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 245 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 62787 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 245 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 411 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2448 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5435 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54454 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.003738 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.958054 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 265729281 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 265729281 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 380608 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 251172 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 13712819 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 6587464 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 20932063 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 7913457 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 7913457 # number of Writeback hits -system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 720904 # number of WriteInvalidateReq hits -system.cpu.l2cache.WriteInvalidateReq_hits::total 720904 # number of WriteInvalidateReq hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 10014 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 10014 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 1637190 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 1637190 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 380608 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 251172 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 13712819 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 8224654 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 22569253 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 380608 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 251172 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 13712819 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 8224654 # number of overall hits -system.cpu.l2cache.overall_hits::total 22569253 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4179 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4227 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 79360 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 289780 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 377546 # number of ReadReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 511886 # number of WriteInvalidateReq misses -system.cpu.l2cache.WriteInvalidateReq_misses::total 511886 # number of WriteInvalidateReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 35708 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 35708 # number of UpgradeReq misses +system.cpu.l2cache.tags.replacements 1292250 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 27666738 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 1355280 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 20.414038 # Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 7588597000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 38342.781923 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 308.197317 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 420.773838 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 6468.758735 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 19751.242576 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.585064 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.004703 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.006420 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.098705 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.301380 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.996273 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 297 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 62733 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 391 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2458 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5452 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54401 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.004532 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.957230 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 264471216 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 264471216 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 371629 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 250715 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 13674158 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 6553954 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 20850456 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 7878976 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 7878976 # number of Writeback hits +system.cpu.l2cache.WriteInvalidateReq_hits::cpu.data 723057 # number of WriteInvalidateReq hits +system.cpu.l2cache.WriteInvalidateReq_hits::total 723057 # number of WriteInvalidateReq hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 9863 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 9863 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 1639498 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 1639498 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 371629 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 250715 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 13674158 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 8193452 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 22489954 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 371629 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 250715 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 13674158 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 8193452 # number of overall hits +system.cpu.l2cache.overall_hits::total 22489954 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 4157 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 4054 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 79532 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 275030 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 362773 # number of ReadReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::cpu.data 509738 # number of WriteInvalidateReq misses +system.cpu.l2cache.WriteInvalidateReq_misses::total 509738 # number of WriteInvalidateReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 35651 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 35651 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 534468 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 534468 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 4179 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 4227 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 79360 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 824248 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 912014 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 4179 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 4227 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 79360 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 824248 # number of overall misses -system.cpu.l2cache.overall_misses::total 912014 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 326739750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 334789750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 5912719487 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22025051995 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28599300982 # number of ReadReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 117495 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 117495 # number of WriteInvalidateReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 415763234 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 415763234 # number of UpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 144000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.SCUpgradeReq_miss_latency::total 144000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 39424784684 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 39424784684 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 326739750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 334789750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 5912719487 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 61449836679 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 68024085666 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 326739750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 334789750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 5912719487 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 61449836679 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 68024085666 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 384787 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 255399 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 13792179 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 6877244 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 21309609 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 7913457 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 7913457 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1232790 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.WriteInvalidateReq_accesses::total 1232790 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45722 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 45722 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_misses::cpu.data 512916 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 512916 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 4157 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 4054 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 79532 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 787946 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 875689 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 4157 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 4054 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 79532 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 787946 # number of overall misses +system.cpu.l2cache.overall_misses::total 875689 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 357827500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 356872250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6528298780 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 22994549799 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30237548329 # number of ReadReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::cpu.data 123996 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.WriteInvalidateReq_miss_latency::total 123996 # number of WriteInvalidateReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 554901623 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 554901623 # number of UpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.SCUpgradeReq_miss_latency::total 159000 # number of SCUpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 41601774937 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 41601774937 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 357827500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 356872250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6528298780 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 64596324736 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 71839323266 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 357827500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 356872250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6528298780 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 64596324736 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 71839323266 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 375786 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 254769 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 13753690 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 6828984 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 21213229 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 7878976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 7878976 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::cpu.data 1232795 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.WriteInvalidateReq_accesses::total 1232795 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 45514 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 45514 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 2 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 2171658 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 2171658 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 384787 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 255399 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 13792179 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 9048902 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 23481267 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 384787 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 255399 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 13792179 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 9048902 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 23481267 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.010861 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.016551 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005754 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.042136 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.017717 # miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.415226 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.415226 # miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.780981 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.780981 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 2152414 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 2152414 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 375786 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 254769 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 13753690 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 8981398 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 23365643 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 375786 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 254769 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 13753690 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 8981398 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 23365643 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.011062 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.015912 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.005783 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.040274 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.017101 # miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::cpu.data 0.413482 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_miss_rate::total 0.413482 # miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.783297 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.783297 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 1 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.246111 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.246111 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.010861 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.016551 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005754 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.091088 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.038840 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.010861 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.016551 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005754 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.091088 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.038840 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 78186.109117 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 79202.685119 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74505.033858 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76006.114967 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75750.507175 # average ReadReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.229534 # average WriteInvalidateReq miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.229534 # average WriteInvalidateReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11643.419794 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11643.419794 # average UpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 72000 # average SCUpgradeReq miss latency -system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 72000 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73764.537230 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73764.537230 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 78186.109117 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 79202.685119 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74505.033858 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74552.606350 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74586.668259 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 78186.109117 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 79202.685119 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74505.033858 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74552.606350 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74586.668259 # average overall miss latency +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238298 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.238298 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.011062 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.015912 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.005783 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087731 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.037478 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.011062 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.015912 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.005783 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087731 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.037478 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 86078.301660 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 88029.662062 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 82083.925715 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83607.423914 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 83351.154383 # average ReadReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::cpu.data 0.243254 # average WriteInvalidateReq miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_miss_latency::total 0.243254 # average WriteInvalidateReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15564.826316 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15564.826316 # average UpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 79500 # average SCUpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81108.358751 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81108.358751 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82037.485073 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86078.301660 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 88029.662062 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82083.925715 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81980.649354 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82037.485073 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1078,108 +1064,108 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 1137707 # number of writebacks -system.cpu.l2cache.writebacks::total 1137707 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4179 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4227 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 79360 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 289780 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 377546 # number of ReadReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 511886 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 511886 # number of WriteInvalidateReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35708 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 35708 # number of UpgradeReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 1107523 # number of writebacks +system.cpu.l2cache.writebacks::total 1107523 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 4157 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 4054 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 79532 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 275030 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 362773 # number of ReadReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::cpu.data 509738 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.WriteInvalidateReq_mshr_misses::total 509738 # number of WriteInvalidateReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35651 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 35651 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 534468 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 534468 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4179 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4227 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 79360 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 824248 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 912014 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4179 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4227 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 79360 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 824248 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 912014 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 274533250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 281888250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 4919274513 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 18395024005 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23870720018 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 11039301007 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 11039301007 # number of WriteInvalidateReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 357176707 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 357176707 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 120000 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 32752998316 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 32752998316 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 274533250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 281888250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 4919274513 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 51148022321 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 56623718334 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 274533250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 281888250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 4919274513 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 51148022321 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 56623718334 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2248902500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5288010501 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7536913001 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5166015500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5166015500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2248902500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10454026001 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 12702928501 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.042136 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017717 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.415226 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.415226 # mshr miss rate for WriteInvalidateReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.780981 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.780981 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 512916 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 512916 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 4157 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 4054 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 79532 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 787946 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 875689 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 4157 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 4054 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19548409701 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25690889671 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu.data 16058529504 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_latency::total 16058529504 # number of WriteInvalidateReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 625079648 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 625079648 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 135000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 135000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35188398563 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35188398563 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 305614500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 305848750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5531016720 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54736808264 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 60879288234 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 305614500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 305848750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5531016720 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54736808264 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 60879288234 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 2585776000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5279091500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 7864867500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 5180093000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 5180093000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 2585776000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10459184500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 13044960500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.040274 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.017101 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu.data 0.413482 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.413482 # mshr miss rate for WriteInvalidateReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.783297 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.783297 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.246111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.246111 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.038840 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.010861 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.016551 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005754 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.091088 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.038840 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61986.826021 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63479.273949 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63225.991053 # average ReadReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 21565.936570 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 21565.936570 # average WriteInvalidateReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10002.708273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10002.708273 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61281.495461 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61281.495461 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65693.527160 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 66687.544358 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61986.826021 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62054.166126 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62086.457372 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.238298 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.037478 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.011062 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.015912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.005783 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087731 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.037478 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69544.544586 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71077.372290 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70818.086437 # average ReadReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu.data 31503.496902 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 31503.496902 # average WriteInvalidateReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17533.299150 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17533.299150 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 67500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68604.603021 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68604.603021 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 73518.041857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 75443.697583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1189,62 +1175,60 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 21752331 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 21744344 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 33872 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 7913457 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339455 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232790 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 45725 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 33710 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 7878976 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 1339565 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateResp 1232795 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 45517 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 45727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 2171658 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 2171658 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27670608 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28704497 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 624113 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 1013195 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 58012413 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 882871956 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1164737260 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2043192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3078296 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 2052730704 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 473368 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 33145716 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.003486 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.058938 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 45519 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 2152414 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 2152414 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 27593630 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 28534080 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 622119 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 992785 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 57742614 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 880408660 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1158207750 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 2038152 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 470306 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 33030174 99.65% 99.65% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 115542 0.35% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 33145716 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 25733748000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 1332000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 20755677476 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 20698021683 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 14427270036 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 14320653166 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 369197500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 367823750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 628893000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 617486750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 40403 # Transaction distribution -system.iobus.trans_dist::ReadResp 40403 # Transaction distribution -system.iobus.trans_dist::WriteReq 136733 # Transaction distribution -system.iobus.trans_dist::WriteResp 30069 # Transaction distribution +system.iobus.trans_dist::ReadReq 40333 # Transaction distribution +system.iobus.trans_dist::ReadResp 40333 # Transaction distribution +system.iobus.trans_dist::WriteReq 136571 # Transaction distribution +system.iobus.trans_dist::WriteResp 29907 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48308 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47822 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -1259,13 +1243,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 123190 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231002 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 231002 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122704 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231024 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 231024 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 354272 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48328 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353808 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47842 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1280,13 +1264,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 156320 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334440 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334440 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155834 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334528 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334528 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492846 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 36706000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 7492448 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 36301000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1314,71 +1298,71 @@ system.iobus.reqLayer25.occupancy 32658000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 1042395169 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 606968921 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 93124000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 92800000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 179037771 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 148463571 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks) +system.iobus.respLayer4.occupancy 174500 # Layer occupancy (ticks) system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 115482 # number of replacements -system.iocache.tags.tagsinuse 10.457347 # Cycle average of tags in use +system.iocache.tags.replacements 115493 # number of replacements +system.iocache.tags.tagsinuse 10.456626 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115498 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115509 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 13153920852000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.510781 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.946566 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.219424 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::realview.ide 0.434160 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.653584 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 13157260299000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ethernet 3.510556 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.946069 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.219410 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::realview.ide 0.434129 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.653539 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039866 # Number of tag accesses -system.iocache.tags.data_accesses 1039866 # Number of data accesses +system.iocache.tags.tag_accesses 1039965 # Number of tag accesses +system.iocache.tags.data_accesses 1039965 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8837 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8874 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8848 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8885 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8837 # number of demand (read+write) misses -system.iocache.demand_misses::total 8877 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8848 # number of demand (read+write) misses +system.iocache.demand_misses::total 8888 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8837 # number of overall misses -system.iocache.overall_misses::total 8877 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ethernet 5479000 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::realview.ide 1901914612 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 1907393612 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::realview.ethernet 339000 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 339000 # number of WriteReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 28843036786 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 28843036786 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ethernet 5818000 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::realview.ide 1901914612 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 1907732612 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ethernet 5818000 # number of overall miss cycles -system.iocache.overall_miss_latency::realview.ide 1901914612 # number of overall miss cycles -system.iocache.overall_miss_latency::total 1907732612 # number of overall miss cycles +system.iocache.overall_misses::realview.ide 8848 # number of overall misses +system.iocache.overall_misses::total 8888 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ethernet 5072000 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 1591055254 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 1596127254 # number of ReadReq miss cycles +system.iocache.WriteReq_miss_latency::realview.ethernet 352500 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 352500 # number of WriteReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19834612096 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 19834612096 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ethernet 5424500 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::realview.ide 1591055254 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 1596479754 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ethernet 5424500 # number of overall miss cycles +system.iocache.overall_miss_latency::realview.ide 1591055254 # number of overall miss cycles +system.iocache.overall_miss_latency::total 1596479754 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8837 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8874 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8848 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8885 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8837 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8877 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8848 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8888 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8837 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8877 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8848 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8888 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -1392,55 +1376,55 @@ system.iocache.demand_miss_rate::total 1 # mi system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ethernet 148081.081081 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::realview.ide 215221.750820 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 214941.808880 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::realview.ethernet 113000 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 113000 # average WriteReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 270410.230125 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 270410.230125 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.demand_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 214907.357441 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ethernet 145450 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 215221.750820 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 214907.357441 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 223600 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ethernet 137081.081081 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 179820.892179 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 179642.909848 # average ReadReq miss latency +system.iocache.WriteReq_avg_miss_latency::realview.ethernet 117500 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 117500 # average WriteReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 185954.137253 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 185954.137253 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.demand_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 179621.934518 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ethernet 135612.500000 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 179820.892179 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 179621.934518 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 109316 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 27526 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 16121 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.123229 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.780969 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 106630 # number of writebacks system.iocache.writebacks::total 106630 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::realview.ide 8837 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 8848 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 8885 # number of ReadReq MSHR misses system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106664 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 106664 # number of WriteInvalidateReq MSHR misses system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::realview.ide 8837 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 8877 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::realview.ide 8848 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 8888 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses -system.iocache.overall_mshr_misses::realview.ide 8837 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 8877 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3555000 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::realview.ide 1442304112 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 1445859112 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 183000 # number of WriteReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 23296466828 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 23296466828 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ethernet 3738000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 1442304112 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 1446042112 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ethernet 3738000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 1442304112 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 1446042112 # number of overall MSHR miss cycles +system.iocache.overall_mshr_misses::realview.ide 8848 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 8888 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3142000 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 1129796362 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 1132938362 # number of ReadReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 193500 # number of WriteReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14288050130 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14288050130 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ethernet 3335500 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 1129796362 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 1133131862 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ethernet 3335500 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 1129796362 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 1133131862 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -1454,71 +1438,71 @@ system.iocache.demand_mshr_miss_rate::total 1 # system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 96081.081081 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 163211.962431 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 162932.061303 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 61000 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 218409.836758 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 218409.836758 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 93450 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 163211.962431 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 162897.613158 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 84918.918919 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 127689.462251 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 127511.351941 # average ReadReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 64500 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 64500 # average WriteReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 133953.818814 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 133953.818814 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 83387.500000 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 127689.462251 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 127490.083483 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 463332 # Transaction distribution -system.membus.trans_dist::ReadResp 463332 # Transaction distribution -system.membus.trans_dist::WriteReq 33872 # Transaction distribution -system.membus.trans_dist::WriteResp 33872 # Transaction distribution -system.membus.trans_dist::Writeback 1244337 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 618545 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 618545 # Transaction distribution -system.membus.trans_dist::UpgradeReq 36281 # Transaction distribution +system.membus.trans_dist::ReadReq 448489 # Transaction distribution +system.membus.trans_dist::ReadResp 448489 # Transaction distribution +system.membus.trans_dist::WriteReq 33710 # Transaction distribution +system.membus.trans_dist::WriteResp 33710 # Transaction distribution +system.membus.trans_dist::Writeback 1214153 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 616398 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 616398 # Transaction distribution +system.membus.trans_dist::UpgradeReq 36221 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 36283 # Transaction distribution -system.membus.trans_dist::ReadExReq 533903 # Transaction distribution -system.membus.trans_dist::ReadExResp 533903 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 123190 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 36223 # Transaction distribution +system.membus.trans_dist::ReadExReq 512353 # Transaction distribution +system.membus.trans_dist::ReadExResp 512353 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 122704 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 6942 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4147646 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4277836 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 334832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 334832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 4612668 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 156320 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4040402 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4170106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 335069 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 4505175 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 155834 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 13884 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 164057632 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 164227968 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14034624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14034624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 178262592 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 3539 # Total snoops (count) -system.membus.snoop_fanout::samples 2819489 # Request fanout histogram +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 159663776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 159833626 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14049088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 3324 # Total snoops (count) +system.membus.snoop_fanout::samples 2750930 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 2819489 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 2819489 # Request fanout histogram -system.membus.reqLayer0.occupancy 106085000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 2750930 # Request fanout histogram +system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 31000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 5679999 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 5171500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 17900056737 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 10418059043 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 9260714451 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 5433894864 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 186597229 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 151694929 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt index 5213927ce..f36b7859c 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview64-switcheroo-atomic/stats.txt @@ -1,74 +1,74 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 51.111151 # Number of seconds simulated -sim_ticks 51111150553500 # Number of ticks simulated -final_tick 51111150553500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 51.111153 # Number of seconds simulated +sim_ticks 51111152682000 # Number of ticks simulated +final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1151312 # Simulator instruction rate (inst/s) -host_op_rate 1352981 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59753764865 # Simulator tick rate (ticks/s) -host_mem_usage 728116 # Number of bytes of host memory used -host_seconds 855.36 # Real time elapsed on the host -sim_insts 984789519 # Number of instructions simulated -sim_ops 1157289961 # Number of ops (including micro ops) simulated +host_inst_rate 1095499 # Simulator instruction rate (inst/s) +host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 56869697369 # Simulator tick rate (ticks/s) +host_mem_usage 728040 # Number of bytes of host memory used +host_seconds 898.74 # Real time elapsed on the host +sim_insts 984570519 # Number of instructions simulated +sim_ops 1157031967 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 200576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 185152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3380276 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 37995016 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 209984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 187968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 2175808 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 37325312 # Number of bytes read from this memory -system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory -system.physmem.bytes_read::total 82097788 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 3380276 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 2175808 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 5556084 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 103277696 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 203392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 187968 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 3328564 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 37865864 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 208384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 188288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 2234176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 36967936 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 441792 # Number of bytes read from this memory +system.physmem.bytes_read::total 81626364 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 3328564 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 2234176 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 5562740 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 103043072 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory -system.physmem.bytes_written::total 103298276 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 3134 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2893 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 93224 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 593685 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 3281 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2937 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 33997 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 583208 # Number of read requests responded to by this memory -system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory -system.physmem.num_reads::total 1323198 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 1613714 # Number of write requests responded to by this memory +system.physmem.bytes_written::total 103063652 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 3178 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2937 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 92416 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 591667 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3256 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2942 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 34909 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 577624 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 6903 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1315832 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 1610048 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory -system.physmem.num_writes::total 1616287 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 3623 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 66136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 743380 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 4108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 730277 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 8564 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1606260 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 66136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42570 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 108706 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2020649 # Write bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 1612621 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3979 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 3678 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 65124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 740853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 4077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 3684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 723285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 8644 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1597036 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 65124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 108836 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2016058 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 403 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2021052 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2020649 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 3623 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 66136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 743783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 4108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 730277 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 8564 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3627311 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2016461 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2016058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 3678 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 65124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 741256 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 4077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 3684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 723285 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 8644 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3613497 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 132 # Number of bytes read from this memory @@ -121,45 +121,45 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 144982 # Table walker walks requested -system.cpu0.dtb.walker.walksLong 144982 # Table walker walks initiated with long descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 144982 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 144982 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 144982 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 144734 # Table walker walks requested +system.cpu0.dtb.walker.walksLong 144734 # Table walker walks initiated with long descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 144734 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 144734 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 144734 # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walksPending::samples 22846000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 22846000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 22846000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 108340 85.69% 85.69% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::2M 18088 14.31% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 126428 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144982 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 107995 85.62% 85.62% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::2M 18140 14.38% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 126135 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 144734 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144982 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126428 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 144734 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 126135 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126428 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 271410 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 126135 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 270869 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 91965302 # DTB read hits -system.cpu0.dtb.read_misses 107321 # DTB read misses -system.cpu0.dtb.write_hits 84365950 # DTB write hits -system.cpu0.dtb.write_misses 37661 # DTB write misses +system.cpu0.dtb.read_hits 91873100 # DTB read hits +system.cpu0.dtb.read_misses 107254 # DTB read misses +system.cpu0.dtb.write_hits 84300346 # DTB write hits +system.cpu0.dtb.write_misses 37480 # DTB write misses system.cpu0.dtb.flush_tlb 51121 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 56687 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 56998 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 4951 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 5021 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 11060 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 92072623 # DTB read accesses -system.cpu0.dtb.write_accesses 84403611 # DTB write accesses +system.cpu0.dtb.perms_faults 11101 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 91980354 # DTB read accesses +system.cpu0.dtb.write_accesses 84337826 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 176331252 # DTB hits -system.cpu0.dtb.misses 144982 # DTB misses -system.cpu0.dtb.accesses 176476234 # DTB accesses +system.cpu0.dtb.hits 176173446 # DTB hits +system.cpu0.dtb.misses 144734 # DTB misses +system.cpu0.dtb.accesses 176318180 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -189,219 +189,219 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 70785 # Table walker walks requested -system.cpu0.itb.walker.walksLong 70785 # Table walker walks initiated with long descriptors -system.cpu0.itb.walker.walkWaitTime::samples 70785 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 70785 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 70785 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walks 70623 # Table walker walks requested +system.cpu0.itb.walker.walksLong 70623 # Table walker walks initiated with long descriptors +system.cpu0.itb.walker.walkWaitTime::samples 70623 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 70623 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 70623 # Table walker wait (enqueue to first request) latency system.cpu0.itb.walker.walksPending::samples 22844500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 22844500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 22844500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 62159 96.07% 96.07% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::2M 2545 3.93% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 64704 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 62003 96.05% 96.05% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::2M 2552 3.95% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 64555 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70785 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70785 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 70623 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 70623 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64704 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64704 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 135489 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 493804573 # ITB inst hits -system.cpu0.itb.inst_misses 70785 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 64555 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 64555 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 135178 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 493558289 # ITB inst hits +system.cpu0.itb.inst_misses 70623 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 51121 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 25055 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 566 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 40296 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb_mva_asid 25137 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 567 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 40618 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 493875358 # ITB inst accesses -system.cpu0.itb.hits 493804573 # DTB hits -system.cpu0.itb.misses 70785 # DTB misses -system.cpu0.itb.accesses 493875358 # DTB accesses -system.cpu0.numCycles 98036815347 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 493628912 # ITB inst accesses +system.cpu0.itb.hits 493558289 # DTB hits +system.cpu0.itb.misses 70623 # DTB misses +system.cpu0.itb.accesses 493628912 # DTB accesses +system.cpu0.numCycles 98036732821 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 493589418 # Number of instructions committed -system.cpu0.committedOps 579610206 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 531010156 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 454321 # Number of float alu accesses -system.cpu0.num_func_calls 28538505 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 76169999 # number of instructions that are conditional controls -system.cpu0.num_int_insts 531010156 # number of integer instructions -system.cpu0.num_fp_insts 454321 # number of float instructions -system.cpu0.num_int_register_reads 784912346 # number of times the integer registers were read -system.cpu0.num_int_register_writes 421695474 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 742936 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 362460 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 132983142 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 132661017 # number of times the CC registers were written -system.cpu0.num_mem_refs 176454648 # number of memory refs -system.cpu0.num_load_insts 92059270 # Number of load instructions -system.cpu0.num_store_insts 84395378 # Number of store instructions -system.cpu0.num_idle_cycles 96925999292.039536 # Number of idle cycles -system.cpu0.num_busy_cycles 1110816054.960464 # Number of busy cycles -system.cpu0.not_idle_fraction 0.011331 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.988669 # Percentage of idle cycles -system.cpu0.Branches 110347037 # Number of branches fetched +system.cpu0.committedInsts 493343054 # Number of instructions committed +system.cpu0.committedOps 579320783 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 530703417 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 453665 # Number of float alu accesses +system.cpu0.num_func_calls 28504103 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 76145406 # number of instructions that are conditional controls +system.cpu0.num_int_insts 530703417 # number of integer instructions +system.cpu0.num_fp_insts 453665 # number of float instructions +system.cpu0.num_int_register_reads 784985742 # number of times the integer registers were read +system.cpu0.num_int_register_writes 421507499 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 741739 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 362084 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 133043946 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 132723498 # number of times the CC registers were written +system.cpu0.num_mem_refs 176296730 # number of memory refs +system.cpu0.num_load_insts 91967123 # Number of load instructions +system.cpu0.num_store_insts 84329607 # Number of store instructions +system.cpu0.num_idle_cycles 96926191341.047134 # Number of idle cycles +system.cpu0.num_busy_cycles 1110541479.952863 # Number of busy cycles +system.cpu0.not_idle_fraction 0.011328 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.988672 # Percentage of idle cycles +system.cpu0.Branches 110281342 # Number of branches fetched system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 402205176 69.35% 69.35% # Class of executed instruction -system.cpu0.op_class::IntMult 1169973 0.20% 69.56% # Class of executed instruction -system.cpu0.op_class::IntDiv 50634 0.01% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.56% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 52759 0.01% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.57% # Class of executed instruction -system.cpu0.op_class::MemRead 92059270 15.87% 85.45% # Class of executed instruction -system.cpu0.op_class::MemWrite 84395378 14.55% 100.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 402074699 69.37% 69.37% # Class of executed instruction +system.cpu0.op_class::IntMult 1168928 0.20% 69.57% # Class of executed instruction +system.cpu0.op_class::IntDiv 50558 0.01% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 52783 0.01% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction +system.cpu0.op_class::MemRead 91967123 15.87% 85.45% # Class of executed instruction +system.cpu0.op_class::MemWrite 84329607 14.55% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 579933190 # Class of executed instruction +system.cpu0.op_class::total 579643698 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 16775 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 11615783 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.999718 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 340859093 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 11616295 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 29.343185 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 11612141 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.999719 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 340775537 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 11612653 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 29.345192 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 265.932740 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 246.066978 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.519400 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.480600 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 264.268132 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 247.731587 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.516149 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.483851 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 206 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 290 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 1421517922 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 1421517922 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 85766676 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 85839710 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 171606386 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 79896763 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 79669373 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 159566136 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208546 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215430 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 423976 # number of SoftPFReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146337 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191461 # number of WriteInvalidateReq hits -system.cpu0.dcache.WriteInvalidateReq_hits::total 337798 # number of WriteInvalidateReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2132895 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2177393 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 4310288 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2256573 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2306673 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 4563246 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 165663439 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 165509083 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 331172522 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 165871985 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 165724513 # number of overall hits -system.cpu0.dcache.overall_hits::total 331596498 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 3019403 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 2994182 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 6013585 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1302154 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 1267314 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 2569468 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789306 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 795194 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 1584500 # number of SoftPFReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 766302 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 478957 # number of WriteInvalidateReq misses -system.cpu0.dcache.WriteInvalidateReq_misses::total 1245259 # number of WriteInvalidateReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 124586 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 130174 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 254760 # number of LoadLockedReq misses +system.cpu0.dcache.tags.tag_accesses 1421165468 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 1421165468 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 85681160 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 85885886 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 171567046 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 79835128 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 79687740 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 159522868 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 208530 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu1.data 215328 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 423858 # number of SoftPFReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 146037 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::cpu1.data 191672 # number of WriteInvalidateReq hits +system.cpu0.dcache.WriteInvalidateReq_hits::total 337709 # number of WriteInvalidateReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2127418 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 2183031 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 4310449 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2250403 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 2312061 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 4562464 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 165516288 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 165573626 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 331089914 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 165724818 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 165788954 # number of overall hits +system.cpu0.dcache.overall_hits::total 331513772 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 3015225 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 2995068 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 6010293 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1305618 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 1264641 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 2570259 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 792908 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu1.data 791180 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 1584088 # number of SoftPFReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 765143 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::cpu1.data 480206 # number of WriteInvalidateReq misses +system.cpu0.dcache.WriteInvalidateReq_misses::total 1245349 # number of WriteInvalidateReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 123898 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 129919 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 253817 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu1.data 1 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 1 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 4321557 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 4261496 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 8583053 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 5110863 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 5056690 # number of overall misses -system.cpu0.dcache.overall_misses::total 10167553 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 88786079 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 88833892 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 177619971 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81198917 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 80936687 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 162135604 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 997852 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1010624 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 2008476 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 912639 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 670418 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583057 # number of WriteInvalidateReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2257481 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2307567 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 4565048 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2256573 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2306674 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 4563247 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 169984996 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 169770579 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 339755575 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 170982848 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 170781203 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 341764051 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.034008 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033705 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.033856 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016037 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015658 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.015848 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791005 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786835 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788907 # miss rate for SoftPFReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839655 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714415 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786617 # miss rate for WriteInvalidateReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055188 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056412 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055807 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.demand_misses::cpu0.data 4320843 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 4259709 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 8580552 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 5113751 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 5050889 # number of overall misses +system.cpu0.dcache.overall_misses::total 10164640 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 88696385 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 88880954 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 177577339 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81140746 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 80952381 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 162093127 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1001438 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 1006508 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 2007946 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 911180 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::cpu1.data 671878 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.WriteInvalidateReq_accesses::total 1583058 # number of WriteInvalidateReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2251316 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 2312950 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 4564266 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2250403 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 2312062 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 4562465 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 169837131 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 169833335 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 339670466 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 170838569 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 170839843 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 341678412 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033995 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033698 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033846 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016091 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.015622 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.015857 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.791769 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.786064 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.788910 # miss rate for SoftPFReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839728 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.714722 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.786673 # miss rate for WriteInvalidateReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055034 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.056170 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055610 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu1.data 0.000000 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000000 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025423 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025101 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025262 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029891 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029609 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029750 # miss rate for overall accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025441 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.025082 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.025261 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029933 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.029565 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029749 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -410,63 +410,63 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 8923646 # number of writebacks -system.cpu0.dcache.writebacks::total 8923646 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 8921315 # number of writebacks +system.cpu0.dcache.writebacks::total 8921315 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 14287218 # number of replacements +system.cpu0.icache.tags.replacements 14295641 # number of replacements system.cpu0.icache.tags.tagsinuse 511.984599 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 971093500 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 14287730 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 67.966955 # Average number of references to valid blocks. +system.cpu0.icache.tags.total_refs 970865862 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 14296153 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 67.910987 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6061930000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 267.813987 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 244.170612 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523074 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476896 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 268.250565 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 243.734034 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.523927 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.476043 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999970 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 999668970 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 999668970 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 486710504 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 484382996 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 971093500 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 486710504 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 484382996 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 971093500 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 486710504 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 484382996 # number of overall hits -system.cpu0.icache.overall_hits::total 971093500 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 7158773 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 7128962 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 14287735 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 7158773 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 7128962 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 14287735 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 7158773 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 7128962 # number of overall misses -system.cpu0.icache.overall_misses::total 14287735 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 493869277 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 491511958 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 985381235 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 493869277 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 491511958 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 985381235 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 493869277 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 491511958 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 985381235 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014495 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014504 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014500 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014495 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014504 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014500 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014495 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014504 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014500 # miss rate for overall accesses +system.cpu0.icache.tags.tag_accesses 999458178 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 999458178 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 486466334 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 484399528 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 970865862 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 486466334 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 484399528 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 970865862 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 486466334 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 484399528 # number of overall hits +system.cpu0.icache.overall_hits::total 970865862 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 7156510 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 7139648 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 14296158 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 7156510 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 7139648 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 14296158 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 7156510 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 7139648 # number of overall misses +system.cpu0.icache.overall_misses::total 14296158 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 493622844 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 491539176 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 985162020 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 493622844 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 491539176 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 985162020 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 493622844 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 491539176 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 985162020 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014498 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014525 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014511 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014498 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014525 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014511 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014498 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014525 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014511 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -505,45 +505,45 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 143312 # Table walker walks requested -system.cpu1.dtb.walker.walksLong 143312 # Table walker walks initiated with long descriptors -system.cpu1.dtb.walker.walkWaitTime::samples 143312 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 143312 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 143312 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 143589 # Table walker walks requested +system.cpu1.dtb.walker.walksLong 143589 # Table walker walks initiated with long descriptors +system.cpu1.dtb.walker.walkWaitTime::samples 143589 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 143589 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 143589 # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walksPending::samples 1000001000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000001000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000001000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 106567 85.62% 85.62% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::2M 17903 14.38% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 124470 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143312 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 106707 85.51% 85.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::2M 18085 14.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 124792 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 143589 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143312 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124470 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 143589 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 124792 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124470 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 267782 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 124792 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 268381 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 92072581 # DTB read hits -system.cpu1.dtb.read_misses 106555 # DTB read misses -system.cpu1.dtb.write_hits 83907281 # DTB write hits -system.cpu1.dtb.write_misses 36757 # DTB write misses +system.cpu1.dtb.read_hits 92120843 # DTB read hits +system.cpu1.dtb.read_misses 106565 # DTB read misses +system.cpu1.dtb.write_hits 83929435 # DTB write hits +system.cpu1.dtb.write_misses 37024 # DTB write misses system.cpu1.dtb.flush_tlb 51112 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 56101 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 56458 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 4637 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 4753 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 10591 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 92179136 # DTB read accesses -system.cpu1.dtb.write_accesses 83944038 # DTB write accesses +system.cpu1.dtb.perms_faults 10550 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 92227408 # DTB read accesses +system.cpu1.dtb.write_accesses 83966459 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 175979862 # DTB hits -system.cpu1.dtb.misses 143312 # DTB misses -system.cpu1.dtb.accesses 176123174 # DTB accesses +system.cpu1.dtb.hits 176050278 # DTB hits +system.cpu1.dtb.misses 143589 # DTB misses +system.cpu1.dtb.accesses 176193867 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -573,113 +573,113 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 69790 # Table walker walks requested -system.cpu1.itb.walker.walksLong 69790 # Table walker walks initiated with long descriptors -system.cpu1.itb.walker.walkWaitTime::samples 69790 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 69790 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 69790 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walks 69863 # Table walker walks requested +system.cpu1.itb.walker.walksLong 69863 # Table walker walks initiated with long descriptors +system.cpu1.itb.walker.walkWaitTime::samples 69863 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 69863 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 69863 # Table walker wait (enqueue to first request) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 61179 95.99% 95.99% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::2M 2554 4.01% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 63733 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 61226 95.98% 95.98% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::2M 2567 4.02% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 63793 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69790 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69790 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 69863 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 69863 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63733 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63733 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 133523 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 491448225 # ITB inst hits -system.cpu1.itb.inst_misses 69790 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63793 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63793 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 133656 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 491475383 # ITB inst hits +system.cpu1.itb.inst_misses 69863 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 51112 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 24716 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 573 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 40454 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 24634 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 572 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 40934 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 491518015 # ITB inst accesses -system.cpu1.itb.hits 491448225 # DTB hits -system.cpu1.itb.misses 69790 # DTB misses -system.cpu1.itb.accesses 491518015 # DTB accesses -system.cpu1.numCycles 97463256917 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 491545246 # ITB inst accesses +system.cpu1.itb.hits 491475383 # DTB hits +system.cpu1.itb.misses 69863 # DTB misses +system.cpu1.itb.accesses 491545246 # DTB accesses +system.cpu1.numCycles 97463064529 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 491200101 # Number of instructions committed -system.cpu1.committedOps 577679755 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 529688376 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 426452 # Number of float alu accesses -system.cpu1.num_func_calls 28536988 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 75796446 # number of instructions that are conditional controls -system.cpu1.num_int_insts 529688376 # number of integer instructions -system.cpu1.num_fp_insts 426452 # number of float instructions -system.cpu1.num_int_register_reads 779402047 # number of times the integer registers were read -system.cpu1.num_int_register_writes 420937852 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 676063 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 385332 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 131460069 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 131204494 # number of times the CC registers were written -system.cpu1.num_mem_refs 176098133 # number of memory refs -system.cpu1.num_load_insts 92164972 # Number of load instructions -system.cpu1.num_store_insts 83933161 # Number of store instructions -system.cpu1.num_idle_cycles 96357264034.410416 # Number of idle cycles -system.cpu1.num_busy_cycles 1105992882.589586 # Number of busy cycles +system.cpu1.committedInsts 491227465 # Number of instructions committed +system.cpu1.committedOps 577711184 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 529752049 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 427140 # Number of float alu accesses +system.cpu1.num_func_calls 28552264 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 75795428 # number of instructions that are conditional controls +system.cpu1.num_int_insts 529752049 # number of integer instructions +system.cpu1.num_fp_insts 427140 # number of float instructions +system.cpu1.num_int_register_reads 779016428 # number of times the integer registers were read +system.cpu1.num_int_register_writes 420937292 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 677260 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 385836 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 131363112 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 131105905 # number of times the CC registers were written +system.cpu1.num_mem_refs 176168876 # number of memory refs +system.cpu1.num_load_insts 92213308 # Number of load instructions +system.cpu1.num_store_insts 83955568 # Number of store instructions +system.cpu1.num_idle_cycles 96357044010.669601 # Number of idle cycles +system.cpu1.num_busy_cycles 1106020518.330400 # Number of busy cycles system.cpu1.not_idle_fraction 0.011348 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.988652 # Percentage of idle cycles -system.cpu1.Branches 109788123 # Number of branches fetched +system.cpu1.Branches 109807220 # Number of branches fetched system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 400601727 69.31% 69.31% # Class of executed instruction -system.cpu1.op_class::IntMult 1185429 0.21% 69.51% # Class of executed instruction -system.cpu1.op_class::IntDiv 51217 0.01% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.52% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 55063 0.01% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.53% # Class of executed instruction -system.cpu1.op_class::MemRead 92164972 15.95% 85.48% # Class of executed instruction -system.cpu1.op_class::MemWrite 83933161 14.52% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 400561917 69.30% 69.30% # Class of executed instruction +system.cpu1.op_class::IntMult 1185819 0.21% 69.50% # Class of executed instruction +system.cpu1.op_class::IntDiv 51201 0.01% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 55039 0.01% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction +system.cpu1.op_class::MemRead 92213308 15.95% 85.48% # Class of executed instruction +system.cpu1.op_class::MemWrite 83955568 14.52% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 577991612 # Class of executed instruction +system.cpu1.op_class::total 578022895 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.iobus.trans_dist::ReadReq 40296 # Transaction distribution -system.iobus.trans_dist::ReadResp 40296 # Transaction distribution -system.iobus.trans_dist::WriteReq 136621 # Transaction distribution -system.iobus.trans_dist::WriteResp 29957 # Transaction distribution +system.iobus.trans_dist::ReadReq 40246 # Transaction distribution +system.iobus.trans_dist::ReadResp 40246 # Transaction distribution +system.iobus.trans_dist::WriteReq 136515 # Transaction distribution +system.iobus.trans_dist::WriteResp 29851 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 106664 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47598 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) @@ -694,13 +694,13 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 122798 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230956 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 230956 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 122480 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230962 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 230962 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 353834 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47936 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 353522 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47618 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -715,54 +715,54 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 155928 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 7334256 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 155610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 7334280 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 7492270 # Cumulative packet size per connected master and slave (bytes) -system.iocache.tags.replacements 115460 # number of replacements +system.iobus.pkt_size::total 7491976 # Cumulative packet size per connected master and slave (bytes) +system.iocache.tags.replacements 115463 # number of replacements system.iocache.tags.tagsinuse 10.407109 # Cycle average of tags in use system.iocache.tags.total_refs 3 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 115476 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 115479 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 13082113302009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ethernet 3.554601 # Average occupied blocks per requestor -system.iocache.tags.occ_blocks::realview.ide 6.852508 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ethernet 0.222163 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ethernet 3.554599 # Average occupied blocks per requestor +system.iocache.tags.occ_blocks::realview.ide 6.852510 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ethernet 0.222162 # Average percentage of cache occupancy system.iocache.tags.occ_percent::realview.ide 0.428282 # Average percentage of cache occupancy system.iocache.tags.occ_percent::total 0.650444 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 1039659 # Number of tag accesses -system.iocache.tags.data_accesses 1039659 # Number of data accesses +system.iocache.tags.tag_accesses 1039686 # Number of tag accesses +system.iocache.tags.data_accesses 1039686 # Number of data accesses system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses -system.iocache.ReadReq_misses::realview.ide 8814 # number of ReadReq misses -system.iocache.ReadReq_misses::total 8851 # number of ReadReq misses +system.iocache.ReadReq_misses::realview.ide 8817 # number of ReadReq misses +system.iocache.ReadReq_misses::total 8854 # number of ReadReq misses system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses system.iocache.WriteReq_misses::total 3 # number of WriteReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 106664 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 106664 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses -system.iocache.demand_misses::realview.ide 8814 # number of demand (read+write) misses -system.iocache.demand_misses::total 8854 # number of demand (read+write) misses +system.iocache.demand_misses::realview.ide 8817 # number of demand (read+write) misses +system.iocache.demand_misses::total 8857 # number of demand (read+write) misses system.iocache.overall_misses::realview.ethernet 40 # number of overall misses -system.iocache.overall_misses::realview.ide 8814 # number of overall misses -system.iocache.overall_misses::total 8854 # number of overall misses +system.iocache.overall_misses::realview.ide 8817 # number of overall misses +system.iocache.overall_misses::total 8857 # number of overall misses system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::realview.ide 8814 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 8851 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::realview.ide 8817 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 8854 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 106664 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses -system.iocache.demand_accesses::realview.ide 8814 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 8854 # number of demand (read+write) accesses +system.iocache.demand_accesses::realview.ide 8817 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 8857 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses -system.iocache.overall_accesses::realview.ide 8814 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 8854 # number of overall (read+write) accesses +system.iocache.overall_accesses::realview.ide 8817 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 8857 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -787,198 +787,197 @@ system.iocache.cache_copies 0 # nu system.iocache.writebacks::writebacks 106631 # number of writebacks system.iocache.writebacks::total 106631 # number of writebacks system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 1726938 # number of replacements -system.l2c.tags.tagsinuse 65261.456077 # Cycle average of tags in use -system.l2c.tags.total_refs 30061688 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 1789677 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 16.797270 # Average number of references to valid blocks. +system.l2c.tags.replacements 1722682 # number of replacements +system.l2c.tags.tagsinuse 65341.862498 # Cycle average of tags in use +system.l2c.tags.total_refs 30065488 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 1785979 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 16.834178 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 37843.446470 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 133.851039 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 182.256334 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3658.181664 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 9398.442867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 138.187628 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 187.456005 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2615.769048 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 11103.865022 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.577445 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.002781 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.055819 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.143409 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002109 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.002860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.039913 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.169432 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.995811 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 246 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 62493 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 239 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 597 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2750 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4968 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54021 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.003754 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.953568 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 291022560 # Number of tag accesses -system.l2c.tags.data_accesses 291022560 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 283104 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 147368 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 7108650 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 3755195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 278245 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 144464 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 7094952 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3753176 # number of ReadReq hits -system.l2c.ReadReq_hits::total 22565154 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 8923646 # number of Writeback hits -system.l2c.Writeback_hits::total 8923646 # number of Writeback hits -system.l2c.WriteInvalidateReq_hits::cpu0.data 347701 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::cpu1.data 349614 # number of WriteInvalidateReq hits -system.l2c.WriteInvalidateReq_hits::total 697315 # number of WriteInvalidateReq hits -system.l2c.UpgradeReq_hits::cpu0.data 5665 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5567 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 11232 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 860452 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 824150 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 1684602 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 283104 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 147368 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 7108650 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 4615647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 278245 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 144464 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7094952 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 4577326 # number of demand (read+write) hits -system.l2c.demand_hits::total 24249756 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 283104 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 147368 # number of overall hits -system.l2c.overall_hits::cpu0.inst 7108650 # number of overall hits -system.l2c.overall_hits::cpu0.data 4615647 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 278245 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 144464 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7094952 # number of overall hits -system.l2c.overall_hits::cpu1.data 4577326 # number of overall hits -system.l2c.overall_hits::total 24249756 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 3134 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2893 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 50123 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 178100 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 3281 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 2937 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 34010 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 166374 # number of ReadReq misses -system.l2c.ReadReq_misses::total 440852 # number of ReadReq misses -system.l2c.WriteInvalidateReq_misses::cpu0.data 418601 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::cpu1.data 129343 # number of WriteInvalidateReq misses -system.l2c.WriteInvalidateReq_misses::total 547944 # number of WriteInvalidateReq misses -system.l2c.UpgradeReq_misses::cpu0.data 19998 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 20032 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 40030 # number of UpgradeReq misses +system.l2c.tags.occ_blocks::writebacks 37141.097811 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 156.460660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 243.495240 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3601.604762 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 9619.799415 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.654107 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 201.240500 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2659.657984 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 11566.852019 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.566728 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002387 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.003715 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.054956 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.146786 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002314 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.003071 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.040583 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.176496 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.997038 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 276 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 63021 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 276 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 588 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2715 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4911 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54671 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.004211 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.961624 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 290964090 # Number of tag accesses +system.l2c.tags.data_accesses 290964090 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 279435 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 145257 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 7107195 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 3754972 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 276854 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 142760 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 7104726 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3749259 # number of ReadReq hits +system.l2c.ReadReq_hits::total 22560458 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 8921315 # number of Writeback hits +system.l2c.Writeback_hits::total 8921315 # number of Writeback hits +system.l2c.WriteInvalidateReq_hits::cpu0.data 345123 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::cpu1.data 349209 # number of WriteInvalidateReq hits +system.l2c.WriteInvalidateReq_hits::total 694332 # number of WriteInvalidateReq hits +system.l2c.UpgradeReq_hits::cpu0.data 5687 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 5536 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 11223 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 864873 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 827736 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 1692609 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 279435 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 145257 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 7107195 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 4619845 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 276854 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 142760 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 7104726 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 4576995 # number of demand (read+write) hits +system.l2c.demand_hits::total 24253067 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 279435 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 145257 # number of overall hits +system.l2c.overall_hits::cpu0.inst 7107195 # number of overall hits +system.l2c.overall_hits::cpu0.data 4619845 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 276854 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 142760 # number of overall hits +system.l2c.overall_hits::cpu1.inst 7104726 # number of overall hits +system.l2c.overall_hits::cpu1.data 4576995 # number of overall hits +system.l2c.overall_hits::total 24253067 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 3178 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2937 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 49315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 177059 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 3256 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 2942 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 34922 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 166908 # number of ReadReq misses +system.l2c.ReadReq_misses::total 440517 # number of ReadReq misses +system.l2c.WriteInvalidateReq_misses::cpu0.data 420020 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::cpu1.data 130997 # number of WriteInvalidateReq misses +system.l2c.WriteInvalidateReq_misses::total 551017 # number of WriteInvalidateReq misses +system.l2c.UpgradeReq_misses::cpu0.data 19994 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 19925 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 39919 # number of UpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 1 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 416039 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 417565 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 833604 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 3134 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2893 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 50123 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 594139 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 3281 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 2937 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 34010 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 583939 # number of demand (read+write) misses -system.l2c.demand_misses::total 1274456 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 3134 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2893 # number of overall misses -system.l2c.overall_misses::cpu0.inst 50123 # number of overall misses -system.l2c.overall_misses::cpu0.data 594139 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 3281 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 2937 # number of overall misses -system.l2c.overall_misses::cpu1.inst 34010 # number of overall misses -system.l2c.overall_misses::cpu1.data 583939 # number of overall misses -system.l2c.overall_misses::total 1274456 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.dtb.walker 286238 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 150261 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 7158773 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 3933295 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 281526 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 147401 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 7128962 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 3919550 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 23006006 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 8923646 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 8923646 # number of Writeback accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu0.data 766302 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::cpu1.data 478957 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.WriteInvalidateReq_accesses::total 1245259 # number of WriteInvalidateReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 25663 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 25599 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 51262 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_misses::cpu0.data 415064 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 411444 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 826508 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 3178 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2937 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 49315 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 592123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 3256 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2942 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 34922 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 578352 # number of demand (read+write) misses +system.l2c.demand_misses::total 1267025 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 3178 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2937 # number of overall misses +system.l2c.overall_misses::cpu0.inst 49315 # number of overall misses +system.l2c.overall_misses::cpu0.data 592123 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 3256 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2942 # number of overall misses +system.l2c.overall_misses::cpu1.inst 34922 # number of overall misses +system.l2c.overall_misses::cpu1.data 578352 # number of overall misses +system.l2c.overall_misses::total 1267025 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 282613 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 148194 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 7156510 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 3932031 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 280110 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 145702 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 7139648 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 3916167 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 23000975 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 8921315 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 8921315 # number of Writeback accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu0.data 765143 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::cpu1.data 480206 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.WriteInvalidateReq_accesses::total 1245349 # number of WriteInvalidateReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 25681 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 25461 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 51142 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 1 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 1 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 1276491 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 1241715 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 2518206 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 286238 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 150261 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 7158773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 5209786 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 281526 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 147401 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 7128962 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 5161265 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 25524212 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 286238 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 150261 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 7158773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 5209786 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 281526 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 147401 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 7128962 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 5161265 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 25524212 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019253 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.007002 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.045280 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.019925 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.004771 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.042447 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.019162 # miss rate for ReadReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.546261 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.270051 # miss rate for WriteInvalidateReq accesses -system.l2c.WriteInvalidateReq_miss_rate::total 0.440024 # miss rate for WriteInvalidateReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.779254 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782531 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.780890 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_accesses::cpu0.data 1279937 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 1239180 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 2519117 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 282613 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 148194 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 7156510 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 5211968 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 280110 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 145702 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 7139648 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 5155347 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 25520092 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 282613 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 148194 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 7156510 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 5211968 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 280110 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 145702 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 7139648 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 5155347 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 25520092 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.019819 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.006891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.045030 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.020192 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.004891 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.042620 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.548943 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.272793 # miss rate for WriteInvalidateReq accesses +system.l2c.WriteInvalidateReq_miss_rate::total 0.442460 # miss rate for WriteInvalidateReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.778552 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.782569 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.780552 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.325924 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.336281 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.331031 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.019253 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.007002 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.114043 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.019925 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.004771 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.113139 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.049931 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.010949 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.019253 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.007002 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.114043 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011654 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.019925 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.004771 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.113139 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.049931 # miss rate for overall accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.324285 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.332029 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.328094 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.019819 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.006891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.113608 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.020192 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.004891 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.112185 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.049648 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.011245 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.019819 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.006891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.113608 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.011624 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.020192 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.004891 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.112185 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.049648 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -987,49 +986,49 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 1507083 # number of writebacks -system.l2c.writebacks::total 1507083 # number of writebacks +system.l2c.writebacks::writebacks 1503417 # number of writebacks +system.l2c.writebacks::total 1503417 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 526435 # Transaction distribution -system.membus.trans_dist::ReadResp 526435 # Transaction distribution -system.membus.trans_dist::WriteReq 33712 # Transaction distribution -system.membus.trans_dist::WriteResp 33712 # Transaction distribution -system.membus.trans_dist::Writeback 1613714 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 654603 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 654603 # Transaction distribution -system.membus.trans_dist::UpgradeReq 40598 # Transaction distribution +system.membus.trans_dist::ReadReq 526050 # Transaction distribution +system.membus.trans_dist::ReadResp 526050 # Transaction distribution +system.membus.trans_dist::WriteReq 33606 # Transaction distribution +system.membus.trans_dist::WriteResp 33606 # Transaction distribution +system.membus.trans_dist::Writeback 1610048 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 657676 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 657676 # Transaction distribution +system.membus.trans_dist::UpgradeReq 40486 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.membus.trans_dist::UpgradeResp 40599 # Transaction distribution -system.membus.trans_dist::ReadExReq 833044 # Transaction distribution -system.membus.trans_dist::ReadExResp 833044 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122798 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 40487 # Transaction distribution +system.membus.trans_dist::ReadExReq 825949 # Transaction distribution +system.membus.trans_dist::ReadExResp 825949 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122480 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 58 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6654 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5323323 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 5452833 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 337667 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 5790500 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155928 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5310719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 5439911 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 337673 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 5777584 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155610 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 132 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13308 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 213243872 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 213413240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 14217344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 227630584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 212730400 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 212899450 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 3591663 # Request fanout histogram +system.membus.snoop_fanout::samples 3583531 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 3591663 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 3591663 # Request fanout histogram +system.membus.snoop_fanout::total 3583531 # Request fanout histogram system.realview.ethernet.txBytes 966 # Bytes Transmitted system.realview.ethernet.txPackets 3 # Number of Packets Transmitted system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device @@ -1072,43 +1071,41 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 18 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 23461417 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 23461417 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 33712 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 33712 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 8923646 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 1245259 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateResp 1245259 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 51262 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 23464706 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 23464706 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 33606 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 33606 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 8921315 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 1245349 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateResp 1245349 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 51142 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51263 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 2518206 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 2518206 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28661720 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32393430 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655510 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 63543360 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 914587540 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314747172 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3330800 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6622040 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 2239287552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 116335 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 36238577 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 5.003188 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.056370 # Request fanout histogram +system.toL2Bus.trans_dist::UpgradeResp 51143 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 2519117 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 2519117 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 28678566 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 32383249 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 832126 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1655216 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 63549157 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 915126612 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1314364326 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 3328504 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 116338 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 36123059 99.68% 99.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 115518 0.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 36238577 # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index b290fab5a..3b1b184c8 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -1,129 +1,125 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 5.188464 # Number of seconds simulated -sim_ticks 5188464227000 # Number of ticks simulated -final_tick 5188464227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 5.184750 # Number of seconds simulated +sim_ticks 5184749789500 # Number of ticks simulated +final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 671592 # Simulator instruction rate (inst/s) -host_op_rate 1294539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27056983658 # Simulator tick rate (ticks/s) -host_mem_usage 641928 # Number of bytes of host memory used -host_seconds 191.76 # Real time elapsed on the host -sim_insts 128784844 # Number of instructions simulated -sim_ops 248241672 # Number of ops (including micro ops) simulated +host_inst_rate 858252 # Simulator instruction rate (inst/s) +host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34581252938 # Simulator tick rate (ticks/s) +host_mem_usage 653812 # Number of bytes of host memory used +host_seconds 149.93 # Real time elapsed on the host +sim_insts 128677191 # Number of instructions simulated +sim_ops 248045844 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 828672 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9042304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 827904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9015040 # Number of bytes read from this memory system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory -system.physmem.bytes_read::total 9899712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 828672 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 828672 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8125568 # Number of bytes written to this memory -system.physmem.bytes_written::total 8125568 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 9871616 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 827904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 827904 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8126080 # Number of bytes written to this memory +system.physmem.bytes_written::total 8126080 # Number of bytes written to this memory system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141286 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 140860 # Number of read requests responded to by this memory system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 154683 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126962 # Number of write requests responded to by this memory -system.physmem.num_writes::total 126962 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::total 154244 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 126970 # Number of write requests responded to by this memory +system.physmem.num_writes::total 126970 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 159714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1742771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::pc.south_bridge.ide 5464 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1908024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 159714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 159714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1566083 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1566083 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1566083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 159681 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1738761 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::pc.south_bridge.ide 5468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1903972 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 159681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 159681 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1567304 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1567304 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1567304 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 159714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1742771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::pc.south_bridge.ide 5464 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3474107 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 154683 # Number of read requests accepted -system.physmem.writeReqs 173682 # Number of write requests accepted -system.physmem.readBursts 154683 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 173682 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 9893504 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue -system.physmem.bytesWritten 10954816 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 9899712 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11115648 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 2485 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 1609 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10173 # Per bank write bursts -system.physmem.perBankRdBursts::1 9740 # Per bank write bursts -system.physmem.perBankRdBursts::2 9593 # Per bank write bursts -system.physmem.perBankRdBursts::3 9430 # Per bank write bursts -system.physmem.perBankRdBursts::4 10001 # Per bank write bursts -system.physmem.perBankRdBursts::5 9691 # Per bank write bursts -system.physmem.perBankRdBursts::6 9399 # Per bank write bursts -system.physmem.perBankRdBursts::7 9276 # Per bank write bursts -system.physmem.perBankRdBursts::8 9154 # Per bank write bursts -system.physmem.perBankRdBursts::9 9223 # Per bank write bursts -system.physmem.perBankRdBursts::10 9471 # Per bank write bursts -system.physmem.perBankRdBursts::11 9338 # Per bank write bursts -system.physmem.perBankRdBursts::12 9899 # Per bank write bursts -system.physmem.perBankRdBursts::13 10266 # Per bank write bursts -system.physmem.perBankRdBursts::14 9992 # Per bank write bursts -system.physmem.perBankRdBursts::15 9940 # Per bank write bursts -system.physmem.perBankWrBursts::0 11451 # Per bank write bursts -system.physmem.perBankWrBursts::1 10885 # Per bank write bursts -system.physmem.perBankWrBursts::2 11361 # Per bank write bursts -system.physmem.perBankWrBursts::3 10717 # Per bank write bursts -system.physmem.perBankWrBursts::4 11001 # Per bank write bursts -system.physmem.perBankWrBursts::5 10578 # Per bank write bursts -system.physmem.perBankWrBursts::6 10603 # Per bank write bursts -system.physmem.perBankWrBursts::7 9872 # Per bank write bursts -system.physmem.perBankWrBursts::8 10400 # Per bank write bursts -system.physmem.perBankWrBursts::9 10659 # Per bank write bursts -system.physmem.perBankWrBursts::10 10851 # Per bank write bursts -system.physmem.perBankWrBursts::11 10912 # Per bank write bursts -system.physmem.perBankWrBursts::12 10837 # Per bank write bursts -system.physmem.perBankWrBursts::13 10879 # Per bank write bursts -system.physmem.perBankWrBursts::14 9964 # Per bank write bursts -system.physmem.perBankWrBursts::15 10199 # Per bank write bursts +system.physmem.bw_total::cpu.inst 159681 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1738761 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::pc.south_bridge.ide 5468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3471276 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 154244 # Number of read requests accepted +system.physmem.writeReqs 173690 # Number of write requests accepted +system.physmem.readBursts 154244 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 173690 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 9865536 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6080 # Total number of bytes read from write queue +system.physmem.bytesWritten 9446080 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 9871616 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 9927 # Per bank write bursts +system.physmem.perBankRdBursts::1 9220 # Per bank write bursts +system.physmem.perBankRdBursts::2 9906 # Per bank write bursts +system.physmem.perBankRdBursts::3 9744 # Per bank write bursts +system.physmem.perBankRdBursts::4 9716 # Per bank write bursts +system.physmem.perBankRdBursts::5 9338 # Per bank write bursts +system.physmem.perBankRdBursts::6 9475 # Per bank write bursts +system.physmem.perBankRdBursts::7 9515 # Per bank write bursts +system.physmem.perBankRdBursts::8 8926 # Per bank write bursts +system.physmem.perBankRdBursts::9 9405 # Per bank write bursts +system.physmem.perBankRdBursts::10 9702 # Per bank write bursts +system.physmem.perBankRdBursts::11 9402 # Per bank write bursts +system.physmem.perBankRdBursts::12 9788 # Per bank write bursts +system.physmem.perBankRdBursts::13 10193 # Per bank write bursts +system.physmem.perBankRdBursts::14 9798 # Per bank write bursts +system.physmem.perBankRdBursts::15 10094 # Per bank write bursts +system.physmem.perBankWrBursts::0 9407 # Per bank write bursts +system.physmem.perBankWrBursts::1 8748 # Per bank write bursts +system.physmem.perBankWrBursts::2 9677 # Per bank write bursts +system.physmem.perBankWrBursts::3 9718 # Per bank write bursts +system.physmem.perBankWrBursts::4 9428 # Per bank write bursts +system.physmem.perBankWrBursts::5 9072 # Per bank write bursts +system.physmem.perBankWrBursts::6 8868 # Per bank write bursts +system.physmem.perBankWrBursts::7 9192 # Per bank write bursts +system.physmem.perBankWrBursts::8 8615 # Per bank write bursts +system.physmem.perBankWrBursts::9 8711 # Per bank write bursts +system.physmem.perBankWrBursts::10 9601 # Per bank write bursts +system.physmem.perBankWrBursts::11 9113 # Per bank write bursts +system.physmem.perBankWrBursts::12 9702 # Per bank write bursts +system.physmem.perBankWrBursts::13 9421 # Per bank write bursts +system.physmem.perBankWrBursts::14 9363 # Per bank write bursts +system.physmem.perBankWrBursts::15 8959 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 5188464163500 # Total gap between requests +system.physmem.numWrRetry 68 # Number of times write queue was full causing retry +system.physmem.totGap 5184749726000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 154683 # Read request sizes (log2) +system.physmem.readPktSize::6 154244 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 173682 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151354 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 2788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 35 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 27 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 173690 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 150873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 2864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 42 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 31 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 32 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 24 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see @@ -156,209 +152,194 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 8699 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 9820 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 10213 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 11279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 11696 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 12708 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 12272 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 12858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 11610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 11043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 6960 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 6830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 422 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 379 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 288 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 262 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 237 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 225 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 193 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 69 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 58562 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 356.003142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 207.252442 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 358.966719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 19491 33.28% 33.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 13719 23.43% 56.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5713 9.76% 66.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3485 5.95% 72.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2346 4.01% 76.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1652 2.82% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1138 1.94% 81.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1007 1.72% 82.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10011 17.09% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 58562 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6360 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 24.303774 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 600.449814 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6359 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5607 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5544 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5616 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6039 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7751 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8321 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6074 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6495 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1383 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 3046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 3049 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2409 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 2529 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 3647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 2146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 2360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 2108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 853 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 368 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 460 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 226 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 238 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 120 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 127 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 57050 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 338.502226 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 199.067588 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 346.604467 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19329 33.88% 33.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 13844 24.27% 58.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5928 10.39% 68.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3298 5.78% 74.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2346 4.11% 78.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1576 2.76% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1245 2.18% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 971 1.70% 85.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8513 14.92% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57050 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.117303 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 658.027323 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5293 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::47104-49151 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6360 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6360 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 26.913365 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 21.548238 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 26.273775 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 4929 77.50% 77.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 43 0.68% 78.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 22 0.35% 78.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 287 4.51% 83.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 171 2.69% 85.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 0.85% 86.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 36 0.57% 87.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 31 0.49% 87.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 174 2.74% 90.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.30% 90.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 20 0.31% 90.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 9 0.14% 91.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 42 0.66% 91.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.30% 92.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.13% 92.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 53 0.83% 93.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 89 1.40% 94.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 11 0.17% 94.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 4 0.06% 94.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.22% 94.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 158 2.48% 97.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 9 0.14% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 4 0.06% 97.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 23 0.36% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 5 0.08% 98.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 8 0.13% 98.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 4 0.06% 98.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 28 0.44% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 11 0.17% 98.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 98.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 9 0.14% 99.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 14 0.22% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 8 0.13% 99.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.06% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 7 0.11% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 2 0.03% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 6 0.09% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 3 0.05% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.06% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-211 1 0.02% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::212-215 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 2 0.03% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::228-231 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6360 # Writes before turning the bus around for reads -system.physmem.totQLat 1439298500 # Total ticks spent queuing -system.physmem.totMemAccLat 4337786000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 772930000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9310.67 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.879675 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.284410 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 52.982511 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 4909 92.73% 92.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 99 1.87% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 16 0.30% 94.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 5 0.09% 94.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 10 0.19% 95.18% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 12 0.23% 95.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 21 0.40% 95.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 16 0.30% 96.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 28 0.53% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.11% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 43 0.81% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 33 0.62% 98.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 9 0.17% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 4 0.08% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 98.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.06% 98.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 2 0.04% 98.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 9 0.17% 98.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 7 0.13% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.06% 98.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 17 0.32% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 15 0.28% 99.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.04% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.06% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.04% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 4 0.08% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 3 0.06% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 5 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 2 0.04% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads +system.physmem.totQLat 1425327951 # Total ticks spent queuing +system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28060.67 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1.91 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.11 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1.91 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 2.14 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing -system.physmem.readRowHits 127137 # Number of row buffer hits during reads -system.physmem.writeRowHits 140055 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.24 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 81.81 # Row buffer hit rate for writes -system.physmem.avgGap 15800904.98 # Average gap between requests -system.physmem.pageHitRate 82.02 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 219436560 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 119732250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 602963400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 560312640 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 133861007610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 2995654884750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 3469903395930 # Total energy per rank (pJ) -system.physmem_0.averagePower 668.773100 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 4983444491000 # Time in different power states -system.physmem_0.memoryStateTime::REF 173254120000 # Time in different power states +system.physmem.avgWrQLen 22.98 # Average write queue length when enqueuing +system.physmem.readRowHits 126892 # Number of row buffer hits during reads +system.physmem.writeRowHits 117801 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.81 # Row buffer hit rate for writes +system.physmem.avgGap 15810345.15 # Average gap between requests +system.physmem.pageHitRate 81.09 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 212315040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 115846500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ) +system.physmem_0.averagePower 668.758961 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states +system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31762771500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 223292160 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121836000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 602799600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 548862480 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 338885058720 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 134523004185 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2995074186000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 3469979039145 # Total energy per rank (pJ) -system.physmem_1.averagePower 668.787680 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4982479156750 # Time in different power states -system.physmem_1.memoryStateTime::REF 173254120000 # Time in different power states +system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 603002400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 476182800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 134835847830 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2992571337000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 3467467313340 # Total energy per rank (pJ) +system.physmem_1.averagePower 668.782314 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 4978313509331 # Time in different power states +system.physmem_1.memoryStateTime::REF 173130100000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32730835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 33303731919 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks -system.cpu.numCycles 10376928454 # number of cpu cycles simulated +system.cpu.numCycles 10369499579 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 128784844 # Number of instructions committed -system.cpu.committedOps 248241672 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 232811079 # Number of integer alu accesses +system.cpu.committedInsts 128677191 # Number of instructions committed +system.cpu.committedOps 248045844 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 232619140 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses -system.cpu.num_func_calls 2318021 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 23218427 # number of instructions that are conditional controls -system.cpu.num_int_insts 232811079 # number of integer instructions +system.cpu.num_func_calls 2317433 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 23196735 # number of instructions that are conditional controls +system.cpu.num_int_insts 232619140 # number of integer instructions system.cpu.num_fp_insts 48 # number of float instructions -system.cpu.num_int_register_reads 436120957 # number of times the integer registers were read -system.cpu.num_int_register_writes 198544312 # number of times the integer registers were written +system.cpu.num_int_register_reads 435790308 # number of times the integer registers were read +system.cpu.num_int_register_writes 198379629 # number of times the integer registers were written system.cpu.num_fp_register_reads 48 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 133281322 # number of times the CC registers were read -system.cpu.num_cc_register_writes 95783918 # number of times the CC registers were written -system.cpu.num_mem_refs 22376754 # number of memory refs -system.cpu.num_load_insts 13962110 # Number of load instructions -system.cpu.num_store_insts 8414644 # Number of store instructions -system.cpu.num_idle_cycles 9778737102.998116 # Number of idle cycles -system.cpu.num_busy_cycles 598191351.001885 # Number of busy cycles -system.cpu.not_idle_fraction 0.057646 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.942354 # Percentage of idle cycles -system.cpu.Branches 26395735 # Number of branches fetched -system.cpu.op_class::No_OpClass 172520 0.07% 0.07% # Class of executed instruction -system.cpu.op_class::IntAlu 225434965 90.81% 90.88% # Class of executed instruction -system.cpu.op_class::IntMult 140546 0.06% 90.94% # Class of executed instruction -system.cpu.op_class::IntDiv 123415 0.05% 90.99% # Class of executed instruction +system.cpu.num_cc_register_reads 133146964 # number of times the CC registers were read +system.cpu.num_cc_register_writes 95675934 # number of times the CC registers were written +system.cpu.num_mem_refs 22361713 # number of memory refs +system.cpu.num_load_insts 13951833 # Number of load instructions +system.cpu.num_store_insts 8409880 # Number of store instructions +system.cpu.num_idle_cycles 9769324889.998116 # Number of idle cycles +system.cpu.num_busy_cycles 600174689.001884 # Number of busy cycles +system.cpu.not_idle_fraction 0.057879 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.942121 # Percentage of idle cycles +system.cpu.Branches 26373024 # Number of branches fetched +system.cpu.op_class::No_OpClass 172503 0.07% 0.07% # Class of executed instruction +system.cpu.op_class::IntAlu 225254349 90.81% 90.88% # Class of executed instruction +system.cpu.op_class::IntMult 140413 0.06% 90.94% # Class of executed instruction +system.cpu.op_class::IntDiv 123366 0.05% 90.99% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCmp 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::FloatCvt 16 0.00% 90.99% # Class of executed instruction @@ -385,150 +366,149 @@ system.cpu.op_class::SimdFloatMisc 0 0.00% 90.99% # Cl system.cpu.op_class::SimdFloatMult 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 90.99% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 90.99% # Class of executed instruction -system.cpu.op_class::MemRead 13957123 5.62% 96.61% # Class of executed instruction -system.cpu.op_class::MemWrite 8414644 3.39% 100.00% # Class of executed instruction +system.cpu.op_class::MemRead 13946864 5.62% 96.61% # Class of executed instruction +system.cpu.op_class::MemWrite 8409880 3.39% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 248243229 # Class of executed instruction +system.cpu.op_class::total 248047391 # Class of executed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu.dcache.tags.replacements 1624253 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.996840 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 20159481 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 1624765 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 12.407629 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 51171250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.996840 # Average occupied blocks per requestor +system.cpu.dcache.tags.replacements 1622522 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.996992 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 20153045 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1623034 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 12.416896 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 54942250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.996992 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 78 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 88800329 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 88800329 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 12017170 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 12017170 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 8080876 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 8080876 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 59251 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 59251 # number of SoftPFReq hits -system.cpu.dcache.demand_hits::cpu.data 20098046 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 20098046 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 20157297 # number of overall hits -system.cpu.dcache.overall_hits::total 20157297 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 908286 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 908286 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 325792 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 325792 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 402501 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 402501 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 1234078 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1234078 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1636579 # number of overall misses -system.cpu.dcache.overall_misses::total 1636579 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12749281750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12749281750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11335230829 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11335230829 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24084512579 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24084512579 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24084512579 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24084512579 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 12925456 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 12925456 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 8406668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 8406668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 461752 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 461752 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 21332124 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 21332124 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 21793876 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 21793876 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070271 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.070271 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038754 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.038754 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.871682 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.871682 # miss rate for SoftPFReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.057851 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.057851 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.075094 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.075094 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14036.637964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14036.637964 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34792.845831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34792.845831 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 19516.199607 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 19516.199607 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 14716.376404 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 14716.376404 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 9103 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 88765477 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 88765477 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 12014873 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 12014873 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 8077139 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 8077139 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 58853 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 58853 # number of SoftPFReq hits +system.cpu.dcache.demand_hits::cpu.data 20092012 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 20092012 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 20150865 # number of overall hits +system.cpu.dcache.overall_hits::total 20150865 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 906821 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 906821 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 324755 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 324755 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 403161 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 403161 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 1231576 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1231576 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1634737 # number of overall misses +system.cpu.dcache.overall_misses::total 1634737 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 12921694 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 8401894 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 8401894 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 462014 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 462014 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 21323588 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 21323588 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 21785602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 21785602 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.070178 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.070178 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038653 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.038653 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.872616 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.872616 # miss rate for SoftPFReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.057757 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.057757 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.075037 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.075037 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14154.917253 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14154.917253 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37412.674465 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 37412.674465 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 20287.768935 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 20287.768935 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 15284.372541 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 15284.372541 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5424 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 96 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 73 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 94.822917 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 74.301370 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 1540563 # number of writebacks -system.cpu.dcache.writebacks::total 1540563 # number of writebacks +system.cpu.dcache.writebacks::writebacks 1539491 # number of writebacks +system.cpu.dcache.writebacks::total 1539491 # number of writebacks system.cpu.dcache.ReadReq_mshr_hits::cpu.data 290 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 290 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9246 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 9246 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 9536 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 9536 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 9536 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 9536 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 907996 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 907996 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 316546 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 316546 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 402467 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 402467 # number of SoftPFReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1224542 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1224542 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1627009 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1627009 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10925755250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10925755250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10200095361 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 10200095361 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5340766250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5340766250 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 21125850611 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 21125850611 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26466616861 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 26466616861 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94247525000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94247525000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2568413500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2568413500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96815938500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 96815938500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070249 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070249 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037654 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037654 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.871609 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.871609 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074654 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.074654 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12032.823107 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12032.823107 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32223.106155 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32223.106155 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13270.072453 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13270.072453 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 17252.042487 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 17252.042487 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16267.037774 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 16267.037774 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 9162 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 9162 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 9452 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 9452 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 9452 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 9452 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 906531 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 906531 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315593 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 315593 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 403125 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 403125 # number of SoftPFReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 1222124 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1222124 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1625249 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1625249 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 11468758782 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 11468758782 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11117308860 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11117308860 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 5627297500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 5627297500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 22586067642 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 22586067642 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28213365142 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 28213365142 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94364463500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94364463500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2593293500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2593293500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96957757000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 96957757000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.070156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.070156 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037562 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037562 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.872538 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.872538 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057313 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057313 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074602 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.074602 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12651.259341 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12651.259341 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35226.728286 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35226.728286 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13959.187597 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13959.187597 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 18480.995089 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 18480.995089 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17359.410861 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 17359.410861 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -536,58 +516,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dtb_walker_cache.tags.replacements 7518 # number of replacements -system.cpu.dtb_walker_cache.tags.tagsinuse 5.053105 # Cycle average of tags in use -system.cpu.dtb_walker_cache.tags.total_refs 13360 # Total number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.sampled_refs 7533 # Sample count of references to valid blocks. -system.cpu.dtb_walker_cache.tags.avg_refs 1.773530 # Average number of references to valid blocks. -system.cpu.dtb_walker_cache.tags.warmup_cycle 5157758038000 # Cycle when the warmup percentage was hit. -system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.053105 # Average occupied blocks per requestor -system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315819 # Average percentage of cache occupancy -system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315819 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.replacements 8888 # number of replacements +system.cpu.dtb_walker_cache.tags.tagsinuse 5.045606 # Cycle average of tags in use +system.cpu.dtb_walker_cache.tags.total_refs 12184 # Total number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.sampled_refs 8903 # Sample count of references to valid blocks. +system.cpu.dtb_walker_cache.tags.avg_refs 1.368527 # Average number of references to valid blocks. +system.cpu.dtb_walker_cache.tags.warmup_cycle 5156876909000 # Cycle when the warmup percentage was hit. +system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.045606 # Average occupied blocks per requestor +system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315350 # Average percentage of cache occupancy +system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315350 # Average percentage of cache occupancy system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id -system.cpu.dtb_walker_cache.tags.tag_accesses 52972 # Number of tag accesses -system.cpu.dtb_walker_cache.tags.data_accesses 52972 # Number of data accesses -system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13370 # number of ReadReq hits -system.cpu.dtb_walker_cache.ReadReq_hits::total 13370 # number of ReadReq hits -system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13370 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.demand_hits::total 13370 # number of demand (read+write) hits -system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13370 # number of overall hits -system.cpu.dtb_walker_cache.overall_hits::total 13370 # number of overall hits -system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8744 # number of ReadReq misses -system.cpu.dtb_walker_cache.ReadReq_misses::total 8744 # number of ReadReq misses -system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8744 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.demand_misses::total 8744 # number of demand (read+write) misses -system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8744 # number of overall misses -system.cpu.dtb_walker_cache.overall_misses::total 8744 # number of overall misses -system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 92278000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 92278000 # number of ReadReq miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 92278000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.demand_miss_latency::total 92278000 # number of demand (read+write) miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 92278000 # number of overall miss cycles -system.cpu.dtb_walker_cache.overall_miss_latency::total 92278000 # number of overall miss cycles -system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22114 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.ReadReq_accesses::total 22114 # number of ReadReq accesses(hits+misses) -system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22114 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.demand_accesses::total 22114 # number of demand (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22114 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.overall_accesses::total 22114 # number of overall (read+write) accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.395406 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.395406 # miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.395406 # miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_miss_rate::total 0.395406 # miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.395406 # miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_miss_rate::total 0.395406 # miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10553.293687 # average ReadReq miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10553.293687 # average ReadReq miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency -system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10553.293687 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10553.293687 # average overall miss latency -system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10553.293687 # average overall miss latency +system.cpu.dtb_walker_cache.tags.tag_accesses 54641 # Number of tag accesses +system.cpu.dtb_walker_cache.tags.data_accesses 54641 # Number of data accesses +system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12184 # number of ReadReq hits +system.cpu.dtb_walker_cache.ReadReq_hits::total 12184 # number of ReadReq hits +system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12184 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.demand_hits::total 12184 # number of demand (read+write) hits +system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12184 # number of overall hits +system.cpu.dtb_walker_cache.overall_hits::total 12184 # number of overall hits +system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 10091 # number of ReadReq misses +system.cpu.dtb_walker_cache.ReadReq_misses::total 10091 # number of ReadReq misses +system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 10091 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.demand_misses::total 10091 # number of demand (read+write) misses +system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 10091 # number of overall misses +system.cpu.dtb_walker_cache.overall_misses::total 10091 # number of overall misses +system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 104642000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 104642000 # number of ReadReq miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 104642000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.demand_miss_latency::total 104642000 # number of demand (read+write) miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 104642000 # number of overall miss cycles +system.cpu.dtb_walker_cache.overall_miss_latency::total 104642000 # number of overall miss cycles +system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 22275 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.ReadReq_accesses::total 22275 # number of ReadReq accesses(hits+misses) +system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 22275 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.demand_accesses::total 22275 # number of demand (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 22275 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.overall_accesses::total 22275 # number of overall (read+write) accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.453019 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.453019 # miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.453019 # miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_miss_rate::total 0.453019 # miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.453019 # miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_miss_rate::total 0.453019 # miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10369.834506 # average ReadReq miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10369.834506 # average ReadReq miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10369.834506 # average overall miss latency +system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10369.834506 # average overall miss latency system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -596,86 +576,86 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.dtb_walker_cache.writebacks::writebacks 2885 # number of writebacks -system.cpu.dtb_walker_cache.writebacks::total 2885 # number of writebacks -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8744 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8744 # number of ReadReq MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8744 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.demand_mshr_misses::total 8744 # number of demand (read+write) MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8744 # number of overall MSHR misses -system.cpu.dtb_walker_cache.overall_mshr_misses::total 8744 # number of overall MSHR misses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 74789500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 74789500 # number of ReadReq MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 74789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 74789500 # number of demand (read+write) MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 74789500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 74789500 # number of overall MSHR miss cycles -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.395406 # mshr miss rate for ReadReq accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.395406 # mshr miss rate for demand accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.395406 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.395406 # mshr miss rate for overall accesses -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8553.236505 # average ReadReq mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency -system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8553.236505 # average overall mshr miss latency -system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8553.236505 # average overall mshr miss latency +system.cpu.dtb_walker_cache.writebacks::writebacks 3116 # number of writebacks +system.cpu.dtb_walker_cache.writebacks::total 3116 # number of writebacks +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 10091 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 10091 # number of ReadReq MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 10091 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.demand_mshr_misses::total 10091 # number of demand (read+write) MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 10091 # number of overall MSHR misses +system.cpu.dtb_walker_cache.overall_mshr_misses::total 10091 # number of overall MSHR misses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 89505500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 89505500 # number of ReadReq MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 89505500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 89505500 # number of demand (read+write) MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 89505500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 89505500 # number of overall MSHR miss cycles +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.453019 # mshr miss rate for ReadReq accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.453019 # mshr miss rate for demand accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.453019 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.453019 # mshr miss rate for overall accesses +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8869.834506 # average ReadReq mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8869.834506 # average overall mshr miss latency +system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8869.834506 # average overall mshr miss latency system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 794079 # number of replacements -system.cpu.icache.tags.tagsinuse 510.347189 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 145115978 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 794591 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 182.629778 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 161164789250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.347189 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.996772 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.996772 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 794465 # number of replacements +system.cpu.icache.tags.tagsinuse 510.329327 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 144962865 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 794977 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 182.348502 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 161575846250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 510.329327 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.996737 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.996737 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 307 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 301 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 10 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 146705174 # Number of tag accesses -system.cpu.icache.tags.data_accesses 146705174 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 145115978 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 145115978 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 145115978 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 145115978 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 145115978 # number of overall hits -system.cpu.icache.overall_hits::total 145115978 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 794598 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 794598 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 794598 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 794598 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 794598 # number of overall misses -system.cpu.icache.overall_misses::total 794598 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11149966366 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11149966366 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11149966366 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11149966366 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11149966366 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11149966366 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 145910576 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 145910576 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 145910576 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 145910576 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 145910576 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 145910576 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005446 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.005446 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.005446 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.005446 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.005446 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.005446 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14032.210459 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14032.210459 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14032.210459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14032.210459 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14032.210459 # average overall miss latency +system.cpu.icache.tags.tag_accesses 146552833 # Number of tag accesses +system.cpu.icache.tags.data_accesses 146552833 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 144962865 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 144962865 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 144962865 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 144962865 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 144962865 # number of overall hits +system.cpu.icache.overall_hits::total 144962865 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 794984 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 794984 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 794984 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 794984 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 794984 # number of overall misses +system.cpu.icache.overall_misses::total 794984 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11253089237 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11253089237 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11253089237 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11253089237 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11253089237 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11253089237 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 145757849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 145757849 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 145757849 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 145757849 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 145757849 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 145757849 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005454 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.005454 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.005454 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.005454 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.005454 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.005454 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14155.114112 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14155.114112 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14155.114112 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14155.114112 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14155.114112 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -684,88 +664,88 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794598 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 794598 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 794598 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 794598 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 794598 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 794598 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9555900634 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9555900634 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9555900634 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9555900634 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9555900634 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9555900634 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005446 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.005446 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005446 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.005446 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12026.081911 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12026.081911 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12026.081911 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12026.081911 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 794984 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 794984 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 794984 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 794984 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 794984 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 794984 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10055827763 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 10055827763 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10055827763 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 10055827763 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10055827763 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 10055827763 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005454 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.005454 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005454 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.005454 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12649.094526 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12649.094526 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12649.094526 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12649.094526 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.itb_walker_cache.tags.replacements 3473 # number of replacements -system.cpu.itb_walker_cache.tags.tagsinuse 3.069566 # Cycle average of tags in use -system.cpu.itb_walker_cache.tags.total_refs 7987 # Total number of references to valid blocks. -system.cpu.itb_walker_cache.tags.sampled_refs 3486 # Sample count of references to valid blocks. -system.cpu.itb_walker_cache.tags.avg_refs 2.291165 # Average number of references to valid blocks. -system.cpu.itb_walker_cache.tags.warmup_cycle 5161163241000 # Cycle when the warmup percentage was hit. -system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.069566 # Average occupied blocks per requestor -system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191848 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_percent::total 0.191848 # Average percentage of cache occupancy -system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 13 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.replacements 4440 # number of replacements +system.cpu.itb_walker_cache.tags.tagsinuse 3.061283 # Cycle average of tags in use +system.cpu.itb_walker_cache.tags.total_refs 7028 # Total number of references to valid blocks. +system.cpu.itb_walker_cache.tags.sampled_refs 4451 # Sample count of references to valid blocks. +system.cpu.itb_walker_cache.tags.avg_refs 1.578971 # Average number of references to valid blocks. +system.cpu.itb_walker_cache.tags.warmup_cycle 5161420260000 # Cycle when the warmup percentage was hit. +system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.061283 # Average occupied blocks per requestor +system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191330 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_percent::total 0.191330 # Average percentage of cache occupancy +system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 11 # Occupied blocks per task id system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id -system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.812500 # Percentage of cache occupancy per task id -system.cpu.itb_walker_cache.tags.tag_accesses 28991 # Number of tag accesses -system.cpu.itb_walker_cache.tags.data_accesses 28991 # Number of data accesses -system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7985 # number of ReadReq hits -system.cpu.itb_walker_cache.ReadReq_hits::total 7985 # number of ReadReq hits +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id +system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.687500 # Percentage of cache occupancy per task id +system.cpu.itb_walker_cache.tags.tag_accesses 29974 # Number of tag accesses +system.cpu.itb_walker_cache.tags.data_accesses 29974 # Number of data accesses +system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7029 # number of ReadReq hits +system.cpu.itb_walker_cache.ReadReq_hits::total 7029 # number of ReadReq hits system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits -system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7987 # number of demand (read+write) hits -system.cpu.itb_walker_cache.demand_hits::total 7987 # number of demand (read+write) hits -system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7987 # number of overall hits -system.cpu.itb_walker_cache.overall_hits::total 7987 # number of overall hits -system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4339 # number of ReadReq misses -system.cpu.itb_walker_cache.ReadReq_misses::total 4339 # number of ReadReq misses -system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4339 # number of demand (read+write) misses -system.cpu.itb_walker_cache.demand_misses::total 4339 # number of demand (read+write) misses -system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4339 # number of overall misses -system.cpu.itb_walker_cache.overall_misses::total 4339 # number of overall misses -system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 42562750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.ReadReq_miss_latency::total 42562750 # number of ReadReq miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 42562750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.demand_miss_latency::total 42562750 # number of demand (read+write) miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 42562750 # number of overall miss cycles -system.cpu.itb_walker_cache.overall_miss_latency::total 42562750 # number of overall miss cycles -system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12324 # number of ReadReq accesses(hits+misses) -system.cpu.itb_walker_cache.ReadReq_accesses::total 12324 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7031 # number of demand (read+write) hits +system.cpu.itb_walker_cache.demand_hits::total 7031 # number of demand (read+write) hits +system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7031 # number of overall hits +system.cpu.itb_walker_cache.overall_hits::total 7031 # number of overall hits +system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 5304 # number of ReadReq misses +system.cpu.itb_walker_cache.ReadReq_misses::total 5304 # number of ReadReq misses +system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 5304 # number of demand (read+write) misses +system.cpu.itb_walker_cache.demand_misses::total 5304 # number of demand (read+write) misses +system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 5304 # number of overall misses +system.cpu.itb_walker_cache.overall_misses::total 5304 # number of overall misses +system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 51550250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.ReadReq_miss_latency::total 51550250 # number of ReadReq miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 51550250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.demand_miss_latency::total 51550250 # number of demand (read+write) miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 51550250 # number of overall miss cycles +system.cpu.itb_walker_cache.overall_miss_latency::total 51550250 # number of overall miss cycles +system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12333 # number of ReadReq accesses(hits+misses) +system.cpu.itb_walker_cache.ReadReq_accesses::total 12333 # number of ReadReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses) system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses) -system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12326 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.demand_accesses::total 12326 # number of demand (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12326 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.overall_accesses::total 12326 # number of overall (read+write) accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.352077 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.352077 # miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.352020 # miss rate for demand accesses -system.cpu.itb_walker_cache.demand_miss_rate::total 0.352020 # miss rate for demand accesses -system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.352020 # miss rate for overall accesses -system.cpu.itb_walker_cache.overall_miss_rate::total 0.352020 # miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9809.345471 # average ReadReq miss latency -system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9809.345471 # average ReadReq miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency -system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9809.345471 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9809.345471 # average overall miss latency -system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9809.345471 # average overall miss latency +system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12335 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.demand_accesses::total 12335 # number of demand (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12335 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.overall_accesses::total 12335 # number of overall (read+write) accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.430066 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.430066 # miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.429996 # miss rate for demand accesses +system.cpu.itb_walker_cache.demand_miss_rate::total 0.429996 # miss rate for demand accesses +system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.429996 # miss rate for overall accesses +system.cpu.itb_walker_cache.overall_miss_rate::total 0.429996 # miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 9719.127074 # average ReadReq miss latency +system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 9719.127074 # average ReadReq miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.demand_avg_miss_latency::total 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 9719.127074 # average overall miss latency +system.cpu.itb_walker_cache.overall_avg_miss_latency::total 9719.127074 # average overall miss latency system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,177 +754,163 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed -system.cpu.itb_walker_cache.writebacks::writebacks 618 # number of writebacks -system.cpu.itb_walker_cache.writebacks::total 618 # number of writebacks -system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4339 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4339 # number of ReadReq MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4339 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.demand_mshr_misses::total 4339 # number of demand (read+write) MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4339 # number of overall MSHR misses -system.cpu.itb_walker_cache.overall_mshr_misses::total 4339 # number of overall MSHR misses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 33883250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 33883250 # number of ReadReq MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 33883250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 33883250 # number of demand (read+write) MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 33883250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 33883250 # number of overall MSHR miss cycles -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.352077 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.352077 # mshr miss rate for ReadReq accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.352020 # mshr miss rate for demand accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.352020 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.352020 # mshr miss rate for overall accesses -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 7808.999770 # average ReadReq mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency -system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 7808.999770 # average overall mshr miss latency -system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 7808.999770 # average overall mshr miss latency +system.cpu.itb_walker_cache.writebacks::writebacks 759 # number of writebacks +system.cpu.itb_walker_cache.writebacks::total 759 # number of writebacks +system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 5304 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 5304 # number of ReadReq MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 5304 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.demand_mshr_misses::total 5304 # number of demand (read+write) MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 5304 # number of overall MSHR misses +system.cpu.itb_walker_cache.overall_mshr_misses::total 5304 # number of overall MSHR misses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 43592750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 43592750 # number of ReadReq MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 43592750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 43592750 # number of demand (read+write) MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 43592750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 43592750 # number of overall MSHR miss cycles +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.430066 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.430066 # mshr miss rate for ReadReq accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.429996 # mshr miss rate for demand accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.429996 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.429996 # mshr miss rate for overall accesses +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8218.844268 # average ReadReq mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8218.844268 # average overall mshr miss latency +system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8218.844268 # average overall mshr miss latency system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 87360 # number of replacements -system.cpu.l2cache.tags.tagsinuse 64748.911122 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3495788 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 152066 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 22.988623 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 87146 # number of replacements +system.cpu.l2cache.tags.tagsinuse 64741.188816 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 3494549 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 151845 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 23.013922 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 50325.123938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.006393 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141290 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3224.854795 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 11198.784706 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.767900 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 50454.801369 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141667 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 3260.512095 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 11025.733685 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.769879 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049207 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.170880 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.987990 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 64706 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 83 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2949 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5093 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56562 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987335 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 32257665 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 32257665 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6357 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 2756 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 781636 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1281044 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2071793 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 1544066 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 1544066 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 321 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 321 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 200764 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 200764 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 6357 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 2756 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 781636 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1481808 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2272557 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 6357 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 2756 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 781636 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1481808 # number of overall hits -system.cpu.l2cache.overall_hits::total 2272557 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049751 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.168239 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.987872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 64699 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 65 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2964 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5133 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 56510 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.987228 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 32250710 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 32250710 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 7142 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3328 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 782034 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 1280353 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2072857 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 1543366 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 1543366 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 317 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 317 # number of UpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 200136 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 200136 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 7142 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 3328 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 782034 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 1480489 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2272993 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 7142 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 3328 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 782034 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 1480489 # number of overall hits +system.cpu.l2cache.overall_hits::total 2272993 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12949 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 28624 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 41579 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 1347 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 1347 # number of UpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 113593 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 113593 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12937 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 28518 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 41460 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 1357 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 1357 # number of UpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 113272 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 113272 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12949 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142217 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 155172 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses +system.cpu.l2cache.demand_misses::cpu.inst 12937 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 141790 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 154732 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12949 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 142217 # number of overall misses -system.cpu.l2cache.overall_misses::total 155172 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 405750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 944829500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2144751500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 3090076000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16383859 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 16383859 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7839721470 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 7839721470 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 405750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 944829500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9984472970 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 10929797470 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 405750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 944829500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9984472970 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 10929797470 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6358 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 2761 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 794585 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 1309668 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2113372 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 1544066 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 1544066 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1668 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 1668 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 314357 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 314357 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6358 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 2761 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 794585 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 1624025 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2427729 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6358 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 2761 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 794585 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 1624025 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2427729 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000157 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001811 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016297 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021856 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.019674 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.807554 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.807554 # miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361350 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.361350 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000157 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001811 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016297 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.087571 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.063917 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000157 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001811 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016297 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.087571 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.063917 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 81150 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72965.441347 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74928.434181 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 74318.189471 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 12163.221232 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 12163.221232 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69015.885398 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69015.885398 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70436.660416 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 81150 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72965.441347 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70205.903443 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70436.660416 # average overall miss latency +system.cpu.l2cache.overall_misses::cpu.inst 12937 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 141790 # number of overall misses +system.cpu.l2cache.overall_misses::total 154732 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 387750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1049449751 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2341413282 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 3391250783 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 21334859 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 21334859 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8652486971 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8652486971 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 387750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1049449751 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 10993900253 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12043737754 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 387750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1049449751 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 10993900253 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12043737754 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 7142 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3333 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 794971 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 1308871 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 2114317 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 1543366 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 1543366 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1674 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 1674 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 313408 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 313408 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 7142 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 3333 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 794971 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 1622279 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2427725 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 7142 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 3333 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 794971 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 1622279 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2427725 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001500 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016274 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021788 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.019609 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.810633 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.810633 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361420 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.361420 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001500 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016274 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.087402 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.063735 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001500 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016274 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.087402 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.063735 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 77550 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81120.024040 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82102.997475 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 81795.725591 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 15722.077377 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 15722.077377 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76386.812019 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76386.812019 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77836.115051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 77550 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81120.024040 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77536.499422 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77836.115051 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -953,90 +919,78 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 80295 # number of writebacks -system.cpu.l2cache.writebacks::total 80295 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses +system.cpu.l2cache.writebacks::writebacks 80303 # number of writebacks +system.cpu.l2cache.writebacks::total 80303 # number of writebacks system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12949 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28624 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 41579 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1347 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 1347 # number of UpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113593 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 113593 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12937 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1357 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12949 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 142217 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 155172 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12937 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 141790 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 154732 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12949 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 142217 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 155172 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 342750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 782620000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1786397500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2569436500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14401829 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14401829 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6419846030 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6419846030 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 342750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 782620000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8206243530 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8989282530 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 342750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 782620000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8206243530 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8989282530 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86686810500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86686810500 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2401284500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2401284500 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89088095000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89088095000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021856 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019674 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.807554 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.807554 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361350 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361350 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.063917 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000157 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001811 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016297 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087571 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.063917 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 68550 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60438.643911 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62409.079793 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61796.495827 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10691.780995 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10691.780995 # average UpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56516.211650 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56516.211650 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 68550 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60438.643911 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57702.268575 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57931.086343 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2872181717 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2411090500 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 88554571000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 88554571000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.063735 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1044,59 +998,59 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2700583 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2700055 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 13918 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 13918 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 1544066 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2197 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 314362 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 314362 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589183 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5984618 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 7718 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 17987 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7599506 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50853440 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204220931 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 216256 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 591552 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 255882179 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 53190 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4026335 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 3.011814 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.108047 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 13916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 13916 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 1543366 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46773 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 20349 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7586177 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50878144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204018925 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 54167 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 3978769 98.82% 98.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 47566 1.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4026335 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3838165000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 477000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1194331866 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 3057201859 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 6509250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 13116250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 15136500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 230298 # Transaction distribution -system.iobus.trans_dist::ReadResp 230298 # Transaction distribution +system.iobus.trans_dist::ReadReq 228399 # Transaction distribution +system.iobus.trans_dist::ReadResp 228399 # Transaction distribution system.iobus.trans_dist::WriteReq 57726 # Transaction distribution system.iobus.trans_dist::WriteResp 11006 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.iobus.trans_dist::MessageReq 1653 # Transaction distribution -system.iobus.trans_dist::MessageResp 1653 # Transaction distribution +system.iobus.trans_dist::MessageReq 1652 # Transaction distribution +system.iobus.trans_dist::MessageResp 1652 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes) @@ -1105,7 +1059,7 @@ system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 432904 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist1.pio 170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes) @@ -1115,12 +1069,12 @@ system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 480916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95132 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3306 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3306 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 579354 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 477136 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95114 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95114 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3304 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 575554 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes) @@ -1129,7 +1083,7 @@ system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 216452 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist1.pio 85 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes) @@ -1139,13 +1093,13 @@ system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 246738 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6612 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 3280662 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 3941856 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 244848 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 3278696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 3940536 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1163,7 +1117,7 @@ system.iobus.reqLayer7.occupancy 50000 # La system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks) +system.iobus.reqLayer9.occupancy 216453000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -1181,54 +1135,54 @@ system.iobus.reqLayer17.occupancy 9000 # La system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 448396611 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 257203754 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 1064000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 469910000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 466130000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 52232002 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 50194752 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer2.occupancy 1653000 # Layer occupancy (ticks) +system.iobus.respLayer2.occupancy 1652000 # Layer occupancy (ticks) system.iobus.respLayer2.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 47511 # number of replacements -system.iocache.tags.tagsinuse 0.108263 # Cycle average of tags in use +system.iocache.tags.replacements 47502 # number of replacements +system.iocache.tags.tagsinuse 0.095966 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 47527 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 47518 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 5045849712000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.108263 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006766 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.006766 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 5046161981000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.095966 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005998 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.005998 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 428094 # Number of tag accesses -system.iocache.tags.data_accesses 428094 # Number of data accesses -system.iocache.ReadReq_misses::pc.south_bridge.ide 846 # number of ReadReq misses -system.iocache.ReadReq_misses::total 846 # number of ReadReq misses +system.iocache.tags.tag_accesses 428013 # Number of tag accesses +system.iocache.tags.data_accesses 428013 # Number of data accesses +system.iocache.ReadReq_misses::pc.south_bridge.ide 837 # number of ReadReq misses +system.iocache.ReadReq_misses::total 837 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 46720 # number of WriteInvalidateReq misses -system.iocache.demand_misses::pc.south_bridge.ide 846 # number of demand (read+write) misses -system.iocache.demand_misses::total 846 # number of demand (read+write) misses -system.iocache.overall_misses::pc.south_bridge.ide 846 # number of overall misses -system.iocache.overall_misses::total 846 # number of overall misses -system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 144419686 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 144419686 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 12361743923 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 12361743923 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::pc.south_bridge.ide 144419686 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 144419686 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::pc.south_bridge.ide 144419686 # number of overall miss cycles -system.iocache.overall_miss_latency::total 144419686 # number of overall miss cycles -system.iocache.ReadReq_accesses::pc.south_bridge.ide 846 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 846 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::pc.south_bridge.ide 837 # number of demand (read+write) misses +system.iocache.demand_misses::total 837 # number of demand (read+write) misses +system.iocache.overall_misses::pc.south_bridge.ide 837 # number of overall misses +system.iocache.overall_misses::total 837 # number of overall misses +system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 132288440 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 132288440 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::pc.south_bridge.ide 8590965562 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 8590965562 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::pc.south_bridge.ide 132288440 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 132288440 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::pc.south_bridge.ide 132288440 # number of overall miss cycles +system.iocache.overall_miss_latency::total 132288440 # number of overall miss cycles +system.iocache.ReadReq_accesses::pc.south_bridge.ide 837 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::pc.south_bridge.ide 846 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 846 # number of demand (read+write) accesses -system.iocache.overall_accesses::pc.south_bridge.ide 846 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 846 # number of overall (read+write) accesses +system.iocache.demand_accesses::pc.south_bridge.ide 837 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 837 # number of demand (read+write) accesses +system.iocache.overall_accesses::pc.south_bridge.ide 837 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 837 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1237,40 +1191,40 @@ system.iocache.demand_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 170708.848700 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 264592.121640 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264592.121640 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 170708.848700 # average overall miss latency -system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 170708.848700 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 170708.848700 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 70486 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 158050.704898 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::pc.south_bridge.ide 183881.968365 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183881.968365 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 158050.704898 # average overall miss latency +system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 158050.704898 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 158050.704898 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 29647 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 9156 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 4442 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.698340 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.674246 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 46667 # number of writebacks system.iocache.writebacks::total 46667 # number of writebacks -system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 846 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 846 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 837 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 837 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 46720 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::pc.south_bridge.ide 846 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 846 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::pc.south_bridge.ide 846 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 846 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 100401686 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 9932299927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 9932299927 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 100401686 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 100401686 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 100401686 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::pc.south_bridge.ide 837 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 837 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::pc.south_bridge.ide 837 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 837 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 88419930 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 6161511576 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6161511576 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 88419930 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 88419930 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 88419930 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1279,71 +1233,71 @@ system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 118678.115839 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 212592.036109 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212592.036109 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 118678.115839 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 118678.115839 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 105639.103943 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide 131881.669007 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131881.669007 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 105639.103943 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 105639.103943 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 624018 # Transaction distribution -system.membus.trans_dist::ReadResp 624018 # Transaction distribution -system.membus.trans_dist::WriteReq 13918 # Transaction distribution -system.membus.trans_dist::WriteResp 13918 # Transaction distribution -system.membus.trans_dist::Writeback 126962 # Transaction distribution +system.membus.trans_dist::ReadReq 617109 # Transaction distribution +system.membus.trans_dist::ReadResp 617109 # Transaction distribution +system.membus.trans_dist::WriteReq 13916 # Transaction distribution +system.membus.trans_dist::WriteResp 13916 # Transaction distribution +system.membus.trans_dist::Writeback 126970 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution -system.membus.trans_dist::UpgradeResp 1627 # Transaction distribution -system.membus.trans_dist::ReadExReq 113313 # Transaction distribution -system.membus.trans_dist::ReadExResp 113313 # Transaction distribution -system.membus.trans_dist::MessageReq 1653 # Transaction distribution -system.membus.trans_dist::MessageResp 1653 # Transaction distribution -system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3306 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.apicbridge.master::total 3306 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480916 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710106 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 393192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1584214 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 141396 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1728916 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6612 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.apicbridge.master::total 6612 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246738 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420209 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15010240 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16677187 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution +system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution +system.membus.trans_dist::ReadExReq 112993 # Transaction distribution +system.membus.trans_dist::ReadExResp 112993 # Transaction distribution +system.membus.trans_dist::MessageReq 1652 # Transaction distribution +system.membus.trans_dist::MessageResp 1652 # Transaction distribution +system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1400637 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14982656 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16628141 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 6005120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22688919 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 1602 # Total snoops (count) -system.membus.snoop_fanout::samples 331576 # Request fanout histogram +system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 1583 # Total snoops (count) +system.membus.snoop_fanout::samples 331203 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 331576 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 331576 # Request fanout histogram -system.membus.reqLayer0.occupancy 257309000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 331203 # Request fanout histogram +system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 358083500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3306000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer3.occupancy 1729903000 # Layer occupancy (ticks) +system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks) system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.respLayer0.occupancy 1653000 # Layer occupancy (ticks) +system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 2619799141 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer4.occupancy 54348998 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks) system.membus.respLayer4.utilization 0.0 # Layer utilization (%) system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD). diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index eedb7e6a0..f228f639d 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000035 # Number of seconds simulated -sim_ticks 34993500 # Number of ticks simulated -final_tick 34993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000038 # Number of seconds simulated +sim_ticks 37928000 # Number of ticks simulated +final_tick 37928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25302 # Simulator instruction rate (inst/s) -host_op_rate 25300 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138325772 # Simulator tick rate (ticks/s) -host_mem_usage 279800 # Number of bytes of host memory used -host_seconds 0.25 # Real time elapsed on the host +host_inst_rate 174102 # Simulator instruction rate (inst/s) +host_op_rate 174036 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1031016392 # Simulator tick rate (ticks/s) +host_mem_usage 293404 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 665723634 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309085973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 974809607 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 665723634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 665723634 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 665723634 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309085973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 974809607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 614216410 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 285171905 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899388315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 614216410 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 614216410 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 614216410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 285171905 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899388315 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 34895000 # Total gap between requests +system.physmem.totGap 37822500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,8 +90,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 439 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 89 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 442 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -186,77 +186,77 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 90 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 365.511111 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 232.220198 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 333.209697 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22 24.44% 24.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 24 26.67% 51.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 11.11% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 8.89% 71.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.44% 75.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 7 7.78% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.11% 84.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.44% 88.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 11.11% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 90 # Bytes accessed per row activation -system.physmem.totQLat 3849750 # Total ticks spent queuing -system.physmem.totMemAccLat 13843500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 84 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 381.714286 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 247.680361 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 333.730884 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 19 22.62% 22.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 20 23.81% 46.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 10 11.90% 58.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 11 13.10% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 4.76% 76.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.57% 79.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.38% 82.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 7.14% 89.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 10.71% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84 # Bytes accessed per row activation +system.physmem.totQLat 3251500 # Total ticks spent queuing +system.physmem.totMemAccLat 13245250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2665000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7222.80 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25972.80 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 974.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 899.39 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 974.81 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.39 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.62 # Data bus utilization in percentage -system.physmem.busUtilRead 7.62 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.03 # Data bus utilization in percentage +system.physmem.busUtilRead 7.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.21 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 435 # Number of row buffer hits during reads +system.physmem.readRowHits 437 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.61 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 65469.04 # Average gap between requests -system.physmem.pageHitRate 81.61 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 257040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 140250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2082600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 70961.54 # Average gap between requests +system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 21404070 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 25985700 # Total energy per rank (pJ) -system.physmem_0.averagePower 827.438306 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 15500 # Time in different power states +system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) +system.physmem_0.averagePower 825.080242 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 371750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 30363250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1677000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 340200 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 185625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1521000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 2034240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 20164320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1173750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 25645245 # Total energy per rank (pJ) -system.physmem_1.averagePower 815.785757 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2149750 # Time in different power states +system.physmem_1.actBackEnergy 20293425 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1041750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 25416240 # Total energy per rank (pJ) +system.physmem_1.averagePower 809.305525 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1595750 # Time in different power states system.physmem_1.memoryStateTime::REF 1040000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 28549750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1972 # Number of BP lookups -system.cpu.branchPred.condPredicted 1208 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1968 # Number of BP lookups +system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1563 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1559 # Number of BTB lookups system.cpu.branchPred.BTBHits 385 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.632118 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 24.695318 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 2254 # DT system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_accesses 2268 # DTB accesses -system.cpu.itb.fetch_hits 2642 # ITB hits +system.cpu.itb.fetch_hits 2639 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2659 # ITB accesses +system.cpu.itb.fetch_accesses 2656 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,80 +293,80 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 69987 # number of cpu cycles simulated +system.cpu.numCycles 75856 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1109 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1110 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 10.935469 # CPI: cycles per instruction -system.cpu.ipc 0.091446 # IPC: instructions per cycle -system.cpu.tickCycles 12616 # Number of cycles that the object actually ticked -system.cpu.idleCycles 57371 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.852500 # CPI: cycles per instruction +system.cpu.ipc 0.084370 # IPC: instructions per cycle +system.cpu.tickCycles 12576 # Number of cycles that the object actually ticked +system.cpu.idleCycles 63280 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 104.036694 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1973 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.896503 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.674556 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 104.036694 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025400 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025400 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.896503 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025365 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025365 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 25 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4569 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4569 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1233 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1233 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 740 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 740 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1973 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1973 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1973 # number of overall hits -system.cpu.dcache.overall_hits::total 1973 # number of overall hits +system.cpu.dcache.tags.tag_accesses 4571 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4571 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits +system.cpu.dcache.overall_hits::total 1975 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 125 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 125 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 227 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 227 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 227 # number of overall misses -system.cpu.dcache.overall_misses::total 227 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7703250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7703250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8670250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8670250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16373500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16373500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16373500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16373500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1335 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1335 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 124 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 226 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses +system.cpu.dcache.overall_misses::total 226 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8143750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8143750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9234250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9234250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17378000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17378000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17378000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17378000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1336 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2200 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2200 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2200 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2200 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076404 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076404 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.144509 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.103182 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.103182 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.103182 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.103182 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75522.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75522.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69362 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 69362 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72129.955947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72129.955947 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72129.955947 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 2201 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2201 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2201 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2201 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076347 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076347 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.102681 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.102681 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102681 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102681 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79840.686275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79840.686275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74469.758065 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74469.758065 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76893.805310 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76893.805310 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -377,12 +377,12 @@ system.cpu.dcache.fast_writes 0 # nu system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 58 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 58 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 58 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 51 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 57 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 57 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 57 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 96 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 96 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7131000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5119000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5119000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12250000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12250000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12250000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071910 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071910 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7563250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7563250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12927500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12927500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12927500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071856 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071856 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076818 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076818 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74281.250000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70123.287671 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70123.287671 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 72485.207101 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 72485.207101 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076783 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076783 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78783.854167 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78783.854167 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 176.047314 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2277 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.733533 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.238356 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 176.047314 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085961 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085961 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.733533 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085807 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 118 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 247 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5649 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5649 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2277 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2277 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2277 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2277 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2277 # number of overall hits -system.cpu.icache.overall_hits::total 2277 # number of overall hits +system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5643 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits +system.cpu.icache.overall_hits::total 2274 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25886500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25886500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25886500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25886500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25886500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25886500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2642 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2642 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2642 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2642 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2642 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2642 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138153 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138153 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138153 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138153 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138153 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70921.917808 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70921.917808 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70921.917808 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70921.917808 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70921.917808 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28333250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28333250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28333250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28333250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28333250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77625.342466 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77625.342466 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77625.342466 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77625.342466 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24998500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24998500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24998500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24998500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24998500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24998500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138153 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138153 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138153 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68489.041096 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68489.041096 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68489.041096 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68489.041096 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27622250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27622250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27622250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75677.397260 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75677.397260 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.762820 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.387081 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 176.091079 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.671740 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005374 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007134 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.765541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.621541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005364 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001758 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007122 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 325 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014038 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4805 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4805 # Number of data accesses @@ -534,17 +534,17 @@ system.cpu.l2cache.demand_misses::total 533 # nu system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24623500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7033500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 31657000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5044000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5044000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 24623500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12077500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 36701000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 24623500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12077500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 36701000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 34712000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5290250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5290250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27246250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12756000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40002250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27246250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12756000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40002250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 365 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 96 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) @@ -567,17 +567,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67646.978022 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73265.625000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 68819.565217 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69095.890411 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69095.890411 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68857.410882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67646.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71464.497041 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68857.410882 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74852.335165 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77768.229167 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75460.869565 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75051.125704 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75051.125704 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,17 +597,17 @@ system.cpu.l2cache.demand_mshr_misses::total 533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20056500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5835000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25891500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4138000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20056500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9973000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30029500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20056500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9973000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30029500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6259250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28945500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4378250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4378250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10637500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33323750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10637500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33323750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses @@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55100.274725 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60781.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56285.869565 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 56684.931507 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55100.274725 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59011.834320 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56340.525328 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62324.862637 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65200.520833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution @@ -654,10 +654,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 534 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 267000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 626500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 279000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 629250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.7 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 286000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 460 # Transaction distribution system.membus.trans_dist::ReadResp 460 # Transaction distribution @@ -678,9 +678,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 606000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4968000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.2 # Layer utilization (%) +system.membus.reqLayer0.occupancy 604000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 7064bc28f..edf4ba710 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,42 +1,42 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20537500 # Number of ticks simulated -final_tick 20537500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22074000 # Number of ticks simulated +final_tick 22074000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92569 # Simulator instruction rate (inst/s) -host_op_rate 92553 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 298254404 # Simulator tick rate (ticks/s) -host_mem_usage 293992 # Number of bytes of host memory used +host_inst_rate 94896 # Simulator instruction rate (inst/s) +host_op_rate 94876 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 328609283 # Simulator tick rate (ticks/s) +host_mem_usage 293652 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory -system.physmem.bytes_read::total 31168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory +system.physmem.bytes_read::total 31104 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory -system.physmem.num_reads::total 487 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 975386488 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 542227632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1517614121 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 975386488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 975386488 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 975386488 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 542227632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1517614121 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 487 # Number of read requests accepted +system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory +system.physmem.num_reads::total 486 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 907492978 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 501585576 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1409078554 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 907492978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 907492978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 907492978 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 501585576 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1409078554 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 486 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 487 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 486 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 31168 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 31104 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 31168 # Total read bytes from the system interface side +system.physmem.bytesReadSys 31104 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -51,7 +51,7 @@ system.physmem.perBankRdBursts::6 1 # Pe system.physmem.perBankRdBursts::7 3 # Per bank write bursts system.physmem.perBankRdBursts::8 0 # Per bank write bursts system.physmem.perBankRdBursts::9 1 # Per bank write bursts -system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::10 22 # Per bank write bursts system.physmem.perBankRdBursts::11 25 # Per bank write bursts system.physmem.perBankRdBursts::12 14 # Per bank write bursts system.physmem.perBankRdBursts::13 120 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20412000 # Total gap between requests +system.physmem.totGap 21941500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 487 # Read request sizes (log2) +system.physmem.readPktSize::6 486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 139 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,100 +186,99 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 82 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 341.853659 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 204.819475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 342.253502 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 28 34.15% 34.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 20.73% 54.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 10.98% 65.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 9.76% 75.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 4.88% 80.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 1.22% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.22% 82.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.66% 86.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 13.41% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 82 # Bytes accessed per row activation -system.physmem.totQLat 4742750 # Total ticks spent queuing -system.physmem.totMemAccLat 13874000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9738.71 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 81 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 332.641975 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 207.818416 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 321.662840 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 25 30.86% 30.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 22.22% 53.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 11.11% 64.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 11.11% 75.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 7.41% 82.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.23% 83.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 3.70% 87.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 12.35% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 81 # Bytes accessed per row activation +system.physmem.totQLat 4363750 # Total ticks spent queuing +system.physmem.totMemAccLat 13476250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2430000 # Total ticks spent in databus transfers +system.physmem.avgQLat 8978.91 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28488.71 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1517.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27728.91 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1409.08 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1517.61 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1409.08 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.86 # Data bus utilization in percentage -system.physmem.busUtilRead 11.86 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.01 # Data bus utilization in percentage +system.physmem.busUtilRead 11.01 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.72 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 390 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.08 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.25 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 41913.76 # Average gap between requests -system.physmem.pageHitRate 80.08 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1755000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 45147.12 # Average gap between requests +system.physmem.pageHitRate 80.25 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1653600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10809765 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10785825 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 38250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13982370 # Total energy per rank (pJ) -system.physmem_0.averagePower 881.195525 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 22000 # Time in different power states +system.physmem_0.totalEnergy 13833660 # Total energy per rank (pJ) +system.physmem_0.averagePower 873.750829 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 118250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15339250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15303750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 332640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 181500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1365000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 325080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 177375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1255800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10541295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 252750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13690305 # Total energy per rank (pJ) -system.physmem_1.averagePower 864.696352 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 637250 # Time in different power states +system.physmem_1.actBackEnergy 10123200 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 619500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13518075 # Total energy per rank (pJ) +system.physmem_1.averagePower 853.818096 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 963500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14974750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14362750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2806 # Number of BP lookups -system.cpu.branchPred.condPredicted 1662 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2808 # Number of BP lookups +system.cpu.branchPred.condPredicted 1660 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 479 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 2112 # Number of BTB lookups -system.cpu.branchPred.BTBHits 686 # Number of BTB hits +system.cpu.branchPred.BTBHits 676 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.481061 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 395 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.007576 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 398 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 30 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 2085 # DTB read hits -system.cpu.dtb.read_misses 55 # DTB read misses +system.cpu.dtb.read_hits 2105 # DTB read hits +system.cpu.dtb.read_misses 56 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2140 # DTB read accesses -system.cpu.dtb.write_hits 1069 # DTB write hits +system.cpu.dtb.read_accesses 2161 # DTB read accesses +system.cpu.dtb.write_hits 1074 # DTB write hits system.cpu.dtb.write_misses 30 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1099 # DTB write accesses -system.cpu.dtb.data_hits 3154 # DTB hits -system.cpu.dtb.data_misses 85 # DTB misses +system.cpu.dtb.write_accesses 1104 # DTB write accesses +system.cpu.dtb.data_hits 3179 # DTB hits +system.cpu.dtb.data_misses 86 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3239 # DTB accesses -system.cpu.itb.fetch_hits 2196 # ITB hits -system.cpu.itb.fetch_misses 38 # ITB misses +system.cpu.dtb.data_accesses 3265 # DTB accesses +system.cpu.itb.fetch_hits 2195 # ITB hits +system.cpu.itb.fetch_misses 34 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2234 # ITB accesses +system.cpu.itb.fetch_accesses 2229 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,237 +292,237 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 41076 # number of cpu cycles simulated +system.cpu.numCycles 44149 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8744 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16221 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2806 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1081 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4165 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 8603 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16272 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1074 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4302 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1040 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 25 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 801 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2196 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.137917 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547719 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 735 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2195 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 341 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.147127 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.556854 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11405 80.01% 80.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 289 2.03% 82.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 215 1.51% 83.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 201 1.41% 84.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 243 1.70% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 210 1.47% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 240 1.68% 89.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 179 1.26% 91.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1273 8.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11330 79.87% 79.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 287 2.02% 81.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 214 1.51% 83.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 204 1.44% 84.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 242 1.71% 86.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 209 1.47% 88.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 241 1.70% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 178 1.25% 90.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1280 9.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14255 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.068312 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.394902 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8821 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2387 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2410 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 194 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 14185 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.063603 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.368570 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8626 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2504 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2413 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 199 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 443 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 229 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14785 # Number of instructions handled by decode +system.cpu.decode.BranchResolved 227 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14877 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 224 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 443 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8987 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1032 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 429 # count of cycles rename stalled for serializing inst +system.cpu.rename.IdleCycles 8799 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1077 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 424 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2422 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 942 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14195 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 42 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 850 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 10723 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17814 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17805 # Number of integer rename lookups +system.cpu.rename.UnblockCycles 1020 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14259 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 15 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 32 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 922 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 10782 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17904 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17895 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6153 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6212 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 32 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 504 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2660 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1309 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. +system.cpu.rename.skidInsts 534 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2680 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1315 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 12936 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 28 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10718 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 21 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6142 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3483 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 10742 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6197 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3553 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14255 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.751877 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.485144 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14185 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.757279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.490412 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10249 71.90% 71.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1278 8.97% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 900 6.31% 87.18% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 686 4.81% 91.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 522 3.66% 95.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 330 2.31% 97.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 212 1.49% 99.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.36% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10181 71.77% 71.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1265 8.92% 80.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 910 6.42% 87.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 677 4.77% 91.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 530 3.74% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 330 2.33% 97.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 213 1.50% 99.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 54 0.38% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 25 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14255 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14185 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 30 20.69% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 20.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 73 50.34% 71.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 42 28.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 29 19.86% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 74 50.68% 70.55% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 43 29.45% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7258 67.72% 67.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.75% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2331 21.75% 89.51% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1124 10.49% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7248 67.47% 67.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.50% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2358 21.95% 89.47% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1131 10.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10718 # Type of FU issued -system.cpu.iq.rate 0.260931 # Inst issue rate -system.cpu.iq.fu_busy_cnt 145 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013529 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 35836 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 19060 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9783 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10742 # Type of FU issued +system.cpu.iq.rate 0.243312 # Inst issue rate +system.cpu.iq.fu_busy_cnt 146 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.013592 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35814 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19169 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9787 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10850 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10875 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 70 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1477 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1497 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 444 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 70 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 65 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 443 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1002 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12999 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 102 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1309 # Number of dispatched store instructions +system.cpu.iew.iewBlockCycles 1035 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13050 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 109 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2680 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1315 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 22 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 81 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 391 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 470 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10224 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2143 # Number of load instructions executed +system.cpu.iew.branchMispredicts 472 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10248 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2164 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 494 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 89 # number of nop insts executed -system.cpu.iew.exec_refs 3244 # number of memory reference insts executed -system.cpu.iew.exec_branches 1603 # Number of branches executed -system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.248904 # Inst execution rate -system.cpu.iew.wb_sent 9953 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9793 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5300 # num instructions producing a value -system.cpu.iew.wb_consumers 7279 # num instructions consuming a value +system.cpu.iew.exec_nop 86 # number of nop insts executed +system.cpu.iew.exec_refs 3270 # number of memory reference insts executed +system.cpu.iew.exec_branches 1599 # Number of branches executed +system.cpu.iew.exec_stores 1106 # Number of stores executed +system.cpu.iew.exec_rate 0.232123 # Inst execution rate +system.cpu.iew.wb_sent 9960 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9797 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5308 # num instructions producing a value +system.cpu.iew.wb_consumers 7306 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.238412 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.728122 # average fanout of values written-back +system.cpu.iew.wb_rate 0.221908 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.726526 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6609 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6660 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13051 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489541 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.404135 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12983 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.492105 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.404730 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10600 81.22% 81.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1162 8.90% 90.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 501 3.84% 93.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.62% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 133 1.02% 96.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 75 0.57% 97.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 89 0.68% 97.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 89 0.68% 98.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 191 1.46% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10525 81.07% 81.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1166 8.98% 90.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 505 3.89% 93.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 209 1.61% 95.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 137 1.06% 96.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 75 0.58% 97.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 89 0.69% 97.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 87 0.67% 98.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 190 1.46% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13051 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12983 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -569,187 +568,187 @@ system.cpu.commit.op_class_0::MemWrite 865 13.54% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6389 # Class of committed instruction -system.cpu.commit.bw_lim_events 191 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25507 # The number of ROB reads -system.cpu.rob.rob_writes 27214 # The number of ROB writes -system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 26821 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25491 # The number of ROB reads +system.cpu.rob.rob_writes 27316 # The number of ROB writes +system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 29964 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.446328 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.446328 # CPI: Total CPI of All Threads -system.cpu.ipc 0.155127 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.155127 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12992 # number of integer regfile reads -system.cpu.int_regfile_writes 7455 # number of integer regfile writes +system.cpu.cpi 6.928594 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.928594 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144329 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144329 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13019 # number of integer regfile reads +system.cpu.int_regfile_writes 7461 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 107.148001 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2314 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.298851 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 107.596270 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2347 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.566474 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 107.148001 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.026159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 174 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 119 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.042480 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5846 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5846 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1808 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1808 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2314 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2314 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2314 # number of overall hits -system.cpu.dcache.overall_hits::total 2314 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 163 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 522 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 522 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 522 # number of overall misses -system.cpu.dcache.overall_misses::total 522 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11503750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11503750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22566471 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22566471 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34070221 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34070221 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34070221 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1971 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1971 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 107.596270 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.026269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5893 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5893 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2347 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2347 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2347 # number of overall hits +system.cpu.dcache.overall_hits::total 2347 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 157 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses +system.cpu.dcache.overall_misses::total 513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12056250 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12056250 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24043225 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24043225 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36099475 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36099475 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36099475 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36099475 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2836 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2836 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2836 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2836 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.082699 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184062 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184062 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184062 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184062 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70575.153374 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70575.153374 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62859.250696 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 62859.250696 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65268.622605 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65268.622605 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1879 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2860 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2860 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2860 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2860 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078697 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078697 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.179371 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.179371 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.179371 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.179371 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76791.401274 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 76791.401274 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67537.148876 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67537.148876 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 70369.346979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 70369.346979 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 70369.346979 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2245 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 42 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 38 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.738095 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.078947 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 287 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 287 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 348 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 348 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 348 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 340 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 340 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 340 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 8025750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5483750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 13509500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 13509500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051750 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051750 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8557250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8557250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5645250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5645250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 14202500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14202500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 14202500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.050627 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.050627 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061354 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061354 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78683.823529 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76163.194444 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77640.804598 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 77640.804598 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.060490 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.060490 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.060490 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 84725.247525 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 84725.247525 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78406.250000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78406.250000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82095.375723 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 82095.375723 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 158.374396 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1718 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.400693 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1716 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.471338 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.464968 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.374396 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077331 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077331 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.400693 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077344 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077344 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 139 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4706 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4706 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1718 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1718 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1718 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1718 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1718 # number of overall hits -system.cpu.icache.overall_hits::total 1718 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses -system.cpu.icache.overall_misses::total 478 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31723500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31723500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31723500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31723500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31723500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31723500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2196 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2196 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2196 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2196 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2196 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2196 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217668 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217668 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217668 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217668 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217668 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217668 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 66367.154812 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 66367.154812 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 66367.154812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 66367.154812 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 66367.154812 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4704 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4704 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1716 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1716 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1716 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1716 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1716 # number of overall hits +system.cpu.icache.overall_hits::total 1716 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses +system.cpu.icache.overall_misses::total 479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34067500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34067500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34067500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34067500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34067500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34067500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2195 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2195 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2195 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2195 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2195 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218223 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.218223 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.218223 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.218223 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.218223 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.218223 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71122.129436 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71122.129436 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71122.129436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71122.129436 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71122.129436 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -758,54 +757,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 164 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 164 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 164 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 164 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 164 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 164 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22315500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22315500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22315500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22315500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142987 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142987 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142987 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142987 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71068.471338 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71068.471338 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71068.471338 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 71068.471338 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24276250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24276250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24276250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24276250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24276250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24276250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143052 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143052 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143052 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143052 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77312.898089 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77312.898089 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77312.898089 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77312.898089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77312.898089 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77312.898089 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.773509 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 219.195035 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 415 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 414 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.460945 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 60.312564 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.471795 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 60.723240 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004836 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006676 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 415 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 224 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012665 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4391 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4391 # Number of data accesses +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001853 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006689 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012634 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 4382 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 4382 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -813,60 +812,60 @@ system.cpu.l2cache.demand_hits::total 1 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 102 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 415 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses -system.cpu.l2cache.overall_misses::total 487 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21990500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7915750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29906250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5408750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5408750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21990500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 13324500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 35315000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21990500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 13324500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 35315000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses +system.cpu.l2cache.overall_misses::total 486 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23950750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 8448250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 32399000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5570250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5570250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 23950750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 14018500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37969250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 23950750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 14018500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37969250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 416 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70257.188498 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77605.392157 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72063.253012 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75121.527778 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75121.527778 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72515.400411 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70257.188498 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76577.586207 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72515.400411 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76519.968051 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 83646.039604 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 78258.454106 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77364.583333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77364.583333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76519.968051 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81031.791908 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78126.028807 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76519.968051 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81031.791908 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78126.028807 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -876,100 +875,100 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 415 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18043000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6661250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24704250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4522750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4522750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18043000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11184000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 29227000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18043000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11184000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 29227000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 20032750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 7188250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 27221000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4674250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 20032750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11862500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31895250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 20032750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11862500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31895250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57645.367412 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65306.372549 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59528.313253 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62815.972222 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62815.972222 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57645.367412 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64275.862069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60014.373717 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64002.396166 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71170.792079 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 65751.207729 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64920.138889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64920.138889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64002.396166 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68569.364162 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65628.086420 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 416 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 416 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 415 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 415 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 628 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 348 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 976 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 974 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 31232 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 488 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 487 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 488 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 487 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 488 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 244000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 528500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 487 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 243500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 535750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 285500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 415 # Transaction distribution -system.membus.trans_dist::ReadResp 415 # Transaction distribution +system.membus.trans_dist::ReadReq 414 # Transaction distribution +system.membus.trans_dist::ReadResp 414 # Transaction distribution system.membus.trans_dist::ReadExReq 72 # Transaction distribution system.membus.trans_dist::ReadExResp 72 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 974 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31168 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 972 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 972 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 31104 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 487 # Request fanout histogram +system.membus.snoop_fanout::samples 486 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 487 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 486 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 487 # Request fanout histogram -system.membus.reqLayer0.occupancy 610000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4554500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.2 # Layer utilization (%) +system.membus.snoop_fanout::total 486 # Request fanout histogram +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 2581250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.7 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt index dcfebc3a2..95d6f5391 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000033 # Number of seconds simulated -sim_ticks 32544000 # Number of ticks simulated -final_tick 32544000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 32544500 # Number of ticks simulated +final_tick 32544500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 485157 # Simulator instruction rate (inst/s) -host_op_rate 484642 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2465828156 # Simulator tick rate (ticks/s) -host_mem_usage 286540 # Number of bytes of host memory used +host_inst_rate 643051 # Simulator instruction rate (inst/s) +host_op_rate 642147 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3266208350 # Simulator tick rate (ticks/s) +host_mem_usage 291356 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 446 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546705998 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 330383481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 877089479 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546705998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546705998 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546705998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 330383481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 877089479 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 373 # Transaction distribution -system.membus.trans_dist::ReadResp 373 # Transaction distribution -system.membus.trans_dist::ReadExReq 73 # Transaction distribution -system.membus.trans_dist::ReadExResp 73 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 446 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 446 # Request fanout histogram -system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4014000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.3 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 546697599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 330378405 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 877076004 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546697599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546697599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546697599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 330378405 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 877076004 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 65088 # number of cpu cycles simulated +system.cpu.numCycles 65089 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6390 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 2058 # nu system.cpu.num_load_insts 1190 # Number of load instructions system.cpu.num_store_insts 868 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 65088 # Number of busy cycles +system.cpu.num_busy_cycles 65089 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 1050 # Number of branches fetched @@ -144,15 +121,119 @@ system.cpu.op_class::MemWrite 868 13.56% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 6400 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 103.757933 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 103.757933 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits +system.cpu.dcache.overall_hits::total 1880 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.dcache.overall_misses::total 168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5082500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3905500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8988000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8988000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 127.998991 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 127.992738 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6122 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 279 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 21.942652 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 127.998991 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.062500 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.062500 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 127.992738 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.062496 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.062496 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 279 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id @@ -171,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 279 # n system.cpu.icache.demand_misses::total 279 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 279 # number of overall misses system.cpu.icache.overall_misses::total 279 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15303000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15303000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15303000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15303000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15303000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15303500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15303500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15303500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15303500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15303500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15303500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6401 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6401 # number of demand (read+write) accesses @@ -189,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.043587 system.cpu.icache.demand_miss_rate::total 0.043587 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.043587 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.043587 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54849.462366 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54849.462366 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54849.462366 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54849.462366 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54851.254480 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54851.254480 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54851.254480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54851.254480 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54851.254480 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -209,33 +290,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 279 system.cpu.icache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14745000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14745000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14745000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14745000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14885000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14885000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14885000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14885000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14885000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14885000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043587 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.043587 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043587 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.043587 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52849.462366 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52849.462366 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53351.254480 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53351.254480 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53351.254480 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53351.254480 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.497210 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.488660 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.017765 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 56.479444 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 128.011543 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 56.477117 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003907 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001724 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005630 # Average percentage of cache occupancy @@ -262,17 +343,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4940000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19396000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3796000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8736000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23192000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8736000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23192000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4987500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19583000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3832500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8820000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23415500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8820000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23415500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 279 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 374 # number of ReadReq accesses(hits+misses) @@ -295,17 +376,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.340483 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.121076 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.121076 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -325,17 +406,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3847500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15106500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2956500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2956500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6804000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18063000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6804000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18063000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997326 # mshr miss rate for ReadReq accesses @@ -347,122 +428,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.762109 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1880 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.190476 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.762109 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025333 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 141 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1088 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1088 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1880 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1880 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1880 # number of overall hits -system.cpu.dcache.overall_hits::total 1880 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses -system.cpu.dcache.overall_misses::total 168 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5225000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5225000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4015000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4015000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9240000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9240000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9240000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080304 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080304 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.082031 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.082031 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.082031 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.082031 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5035000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3869000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8904000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8904000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 374 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution @@ -491,5 +468,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 418500 # La system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 252000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.membus.trans_dist::ReadReq 373 # Transaction distribution +system.membus.trans_dist::ReadResp 373 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 446 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 446 # Request fanout histogram +system.membus.reqLayer0.occupancy 446500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2230500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index 6a0f7583b..a634edee1 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18733500 # Number of ticks simulated -final_tick 18733500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20287000 # Number of ticks simulated +final_tick 20287000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33056 # Simulator instruction rate (inst/s) -host_op_rate 33048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 239448729 # Simulator tick rate (ticks/s) -host_mem_usage 278492 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 136939 # Simulator instruction rate (inst/s) +host_op_rate 136838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1073215892 # Simulator tick rate (ticks/s) +host_mem_usage 292092 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14272 # Nu system.physmem.num_reads::cpu.inst 223 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 308 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 761843756 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 290388876 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1052232631 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 761843756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 761843756 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 761843756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 290388876 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1052232631 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 703504707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 268152019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 971656726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 703504707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 703504707 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 703504707 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 268152019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 971656726 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 308 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 308 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18651500 # Total gap between requests +system.physmem.totGap 20198000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 43 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 421.209302 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 281.192017 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 321.893842 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 23.26% 23.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8 18.60% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 6.98% 48.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 6.98% 55.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 13.95% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 9.30% 79.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 9.30% 88.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 4.65% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 6.98% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 43 # Bytes accessed per row activation -system.physmem.totQLat 1952250 # Total ticks spent queuing -system.physmem.totMemAccLat 7727250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 41 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 427.707317 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 281.056415 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 329.596590 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 10 24.39% 24.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 6 14.63% 39.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 4 9.76% 48.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2 4.88% 53.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 17.07% 70.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 4.88% 75.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 9.76% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 7.32% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 7.32% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 41 # Bytes accessed per row activation +system.physmem.totQLat 1763250 # Total ticks spent queuing +system.physmem.totMemAccLat 7538250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1540000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6338.47 # Average queueing delay per DRAM burst +system.physmem.avgQLat 5724.84 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25088.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1052.23 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24474.84 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 971.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1052.23 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 971.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 8.22 # Data bus utilization in percentage -system.physmem.busUtilRead 8.22 # Data bus utilization in percentage for reads +system.physmem.busUtil 7.59 # Data bus utilization in percentage +system.physmem.busUtilRead 7.59 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.26 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 257 # Number of row buffer hits during reads +system.physmem.readRowHits 258 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.44 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.77 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 60556.82 # Average gap between requests -system.physmem.pageHitRate 83.44 # Row buffer hit rate, read and write combined +system.physmem.avgGap 65577.92 # Average gap between requests +system.physmem.pageHitRate 83.77 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 83160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 45375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 780000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10790100 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12765855 # Total energy per rank (pJ) -system.physmem_0.averagePower 806.306964 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 894750 # Time in different power states +system.physmem_0.actBackEnergy 10555830 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 240000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12721485 # Total energy per rank (pJ) +system.physmem_0.averagePower 803.504500 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 765250 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15310750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 14968250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1294800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 189000 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1185600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10507095 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 282750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13440630 # Total energy per rank (pJ) -system.physmem_1.averagePower 848.926575 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 429000 # Time in different power states +system.physmem_1.actBackEnergy 10492560 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 300000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 13287405 # Total energy per rank (pJ) +system.physmem_1.averagePower 838.851326 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 458000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14897250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14875250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 793 # Number of BP lookups +system.cpu.branchPred.lookups 791 # Number of BP lookups system.cpu.branchPred.condPredicted 397 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 168 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 562 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 563 # Number of BTB lookups system.cpu.branchPred.BTBHits 58 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 10.320285 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 139 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 10.301954 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 136 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 2 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits @@ -276,10 +276,10 @@ system.cpu.dtb.data_hits 816 # DT system.cpu.dtb.data_misses 13 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations system.cpu.dtb.data_accesses 829 # DTB accesses -system.cpu.itb.fetch_hits 974 # ITB hits +system.cpu.itb.fetch_hits 969 # ITB hits system.cpu.itb.fetch_misses 13 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 987 # ITB accesses +system.cpu.itb.fetch_accesses 982 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,29 +293,29 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 37467 # number of cpu cycles simulated +system.cpu.numCycles 40574 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 596 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 595 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 14.494004 # CPI: cycles per instruction -system.cpu.ipc 0.068994 # IPC: instructions per cycle -system.cpu.tickCycles 5412 # Number of cycles that the object actually ticked -system.cpu.idleCycles 32055 # Total number of cycles that the object has spent stopped +system.cpu.cpi 15.695938 # CPI: cycles per instruction +system.cpu.ipc 0.063711 # IPC: instructions per cycle +system.cpu.tickCycles 5396 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35178 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 48.478730 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 48.342007 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 8.141176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 48.478730 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011836 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011836 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 48.342007 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011802 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011802 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 1677 # Number of tag accesses system.cpu.dcache.tags.data_accesses 1677 # Number of data accesses @@ -335,14 +335,14 @@ system.cpu.dcache.demand_misses::cpu.data 104 # n system.cpu.dcache.demand_misses::total 104 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 104 # number of overall misses system.cpu.dcache.overall_misses::total 104 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4644500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4644500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3502000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3502000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8146500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8146500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8146500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8146500 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4962000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4962000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 3282500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 3282500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 8244500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 8244500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 8244500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 8244500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 502 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) @@ -359,14 +359,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.130653 system.cpu.dcache.demand_miss_rate::total 0.130653 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.130653 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.130653 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76139.344262 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 76139.344262 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81441.860465 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 81441.860465 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 78331.730769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 78331.730769 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 78331.730769 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81344.262295 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 81344.262295 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76337.209302 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 76337.209302 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 79274.038462 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 79274.038462 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 79274.038462 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,14 +391,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4310500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4310500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2079250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2079250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6389750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6389750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6389750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6389750 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4628250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4628250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2009000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2009000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6637250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6637250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6637250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6637250 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.115538 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses @@ -407,66 +407,66 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.106784 system.cpu.dcache.demand_mshr_miss_rate::total 0.106784 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.106784 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.106784 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 74318.965517 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 74318.965517 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 77009.259259 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 77009.259259 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75173.529412 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75173.529412 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79797.413793 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79797.413793 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74407.407407 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74407.407407 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78085.294118 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78085.294118 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 118.465909 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 751 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 117.949271 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 746 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 223 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.367713 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.345291 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 118.465909 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057845 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057845 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.949271 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057592 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057592 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 223 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 114 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2171 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2171 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 751 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 751 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 751 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 751 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 751 # number of overall hits -system.cpu.icache.overall_hits::total 751 # number of overall hits +system.cpu.icache.tags.tag_accesses 2161 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2161 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 746 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 746 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 746 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 746 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 746 # number of overall hits +system.cpu.icache.overall_hits::total 746 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 223 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 223 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 223 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 223 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.icache.overall_misses::total 223 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15423500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15423500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15423500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15423500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15423500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15423500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 974 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 974 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 974 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 974 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 974 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69163.677130 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69163.677130 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69163.677130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69163.677130 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69163.677130 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17117250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17117250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17117250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17117250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17117250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17117250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 969 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 969 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 969 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 969 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 969 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 969 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230134 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.230134 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.230134 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.230134 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.230134 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.230134 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76758.968610 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76758.968610 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76758.968610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76758.968610 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76758.968610 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,39 +481,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 223 system.cpu.icache.demand_mshr_misses::total 223 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 223 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14884500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14884500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14884500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14884500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14884500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14884500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.228953 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.228953 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.228953 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66746.636771 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66746.636771 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66746.636771 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66746.636771 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16684250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16684250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16684250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16684250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16684250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16684250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.230134 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.230134 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.230134 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.230134 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74817.264574 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74817.264574 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74817.264574 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74817.264574 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 146.534478 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 145.900805 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 281 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.615214 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.919264 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003620 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004472 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 118.086871 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 27.813934 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003604 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000849 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004453 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 281 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 142 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 151 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.008575 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2772 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2772 # Number of data accesses @@ -528,17 +528,17 @@ system.cpu.l2cache.demand_misses::total 308 # nu system.cpu.l2cache.overall_misses::cpu.inst 223 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 308 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14661500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4251500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18913000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2052250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2052250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14661500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6303750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20965250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14661500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6303750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20965250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16461250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4569250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21030500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1982000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1982000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16461250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6551250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23012500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16461250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6551250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23012500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 223 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 58 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 281 # number of ReadReq accesses(hits+misses) @@ -561,17 +561,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65746.636771 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 73301.724138 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67306.049822 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76009.259259 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76009.259259 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68068.993506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65746.636771 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74161.764706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68068.993506 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73817.264574 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78780.172414 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 74841.637011 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73407.407407 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73407.407407 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74715.909091 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73817.264574 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77073.529412 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74715.909091 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -591,17 +591,17 @@ system.cpu.l2cache.demand_mshr_misses::total 308 system.cpu.l2cache.overall_mshr_misses::cpu.inst 223 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 308 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11864500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3534000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15398500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1718250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1718250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11864500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5252250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17116750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11864500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5252250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17116750 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13669750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3841250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17511000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1642000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1642000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13669750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5483250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19153000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13669750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5483250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19153000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -613,17 +613,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53204.035874 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60931.034483 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54798.932384 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63638.888889 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63638.888889 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53204.035874 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61791.176471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55573.863636 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61299.327354 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66228.448276 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62316.725979 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60814.814815 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60814.814815 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61299.327354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64508.823529 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62185.064935 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 281 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 281 # Transaction distribution @@ -649,9 +649,9 @@ system.cpu.toL2Bus.snoop_fanout::max_value 1 # system.cpu.toL2Bus.snoop_fanout::total 308 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 154000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 381000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 136750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 383750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 143250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) system.membus.trans_dist::ReadReq 281 # Transaction distribution system.membus.trans_dist::ReadResp 281 # Transaction distribution @@ -672,9 +672,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 308 # Request fanout histogram -system.membus.reqLayer0.occupancy 363000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2868750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 15.3 # Layer utilization (%) +system.membus.reqLayer0.occupancy 360000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 1638500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 8.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 49b58755c..165a7d5f5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11765500 # Number of ticks simulated -final_tick 11765500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 12774000 # Number of ticks simulated +final_tick 12774000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73154 # Simulator instruction rate (inst/s) -host_op_rate 73124 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 360297045 # Simulator tick rate (ticks/s) -host_mem_usage 293708 # Number of bytes of host memory used +host_inst_rate 77109 # Simulator instruction rate (inst/s) +host_op_rate 77075 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 412290611 # Simulator tick rate (ticks/s) +host_mem_usage 293132 # Number of bytes of host memory used host_seconds 0.03 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 11968 # Nu system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory system.physmem.num_reads::total 272 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1017211338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 462368790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1479580128 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1017211338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1017211338 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1017211338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 462368790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1479580128 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 936903084 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 425865038 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1362768123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 936903084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 936903084 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 936903084 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 425865038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1362768123 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 272 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 272 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 11676000 # Total gap between requests +system.physmem.totGap 12677500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,9 +91,9 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 156 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 83 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 82 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 379.076923 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 220.895953 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 363.044972 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 33.33% 33.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 7 17.95% 51.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3 7.69% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 7.69% 66.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 5.13% 71.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 7.69% 79.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 2.56% 82.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 2.56% 84.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 6 15.38% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39 # Bytes accessed per row activation -system.physmem.totQLat 1802000 # Total ticks spent queuing -system.physmem.totMemAccLat 6902000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 36 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 394.666667 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 235.952583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 357.320824 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 12 33.33% 33.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 5 13.89% 47.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3 8.33% 55.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 8.33% 63.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 8.33% 72.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 5.56% 77.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 5.56% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 2.78% 86.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 5 13.89% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 36 # Bytes accessed per row activation +system.physmem.totQLat 1960500 # Total ticks spent queuing +system.physmem.totMemAccLat 7060500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1360000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6625.00 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7207.72 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 25375.00 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1479.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 25957.72 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1362.77 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1479.58 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1362.77 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.56 # Data bus utilization in percentage -system.physmem.busUtilRead 11.56 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.65 # Data bus utilization in percentage +system.physmem.busUtilRead 10.65 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.71 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 223 # Number of row buffer hits during reads +system.physmem.readRowHits 226 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.09 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42926.47 # Average gap between requests -system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined +system.physmem.avgGap 46608.46 # Average gap between requests +system.physmem.pageHitRate 83.09 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 37125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 631800 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 585000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 5478840 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 21750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 6746115 # Total energy per rank (pJ) -system.physmem_0.averagePower 838.417275 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 206000 # Time in different power states +system.physmem_0.totalEnergy 6699315 # Total energy per rank (pJ) +system.physmem_0.averagePower 832.600901 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 22500 # Time in different power states system.physmem_0.memoryStateTime::REF 260000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 7778000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 7777500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 158760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 86625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 850200 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 787800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5222340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 7073235 # Total energy per rank (pJ) -system.physmem_1.averagePower 879.072239 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 397500 # Time in different power states +system.physmem_1.actBackEnergy 5200965 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 265500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 6961470 # Total energy per rank (pJ) +system.physmem_1.averagePower 865.181917 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 428500 # Time in different power states system.physmem_1.memoryStateTime::REF 260000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 7402500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 7371500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1090 # Number of BP lookups -system.cpu.branchPred.condPredicted 548 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 734 # Number of BTB lookups -system.cpu.branchPred.BTBHits 202 # Number of BTB hits +system.cpu.branchPred.lookups 1106 # Number of BP lookups +system.cpu.branchPred.condPredicted 562 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 228 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 735 # Number of BTB lookups +system.cpu.branchPred.BTBHits 214 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 27.520436 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 199 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 29.115646 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 201 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 9 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 689 # DTB read hits -system.cpu.dtb.read_misses 23 # DTB read misses +system.cpu.dtb.read_hits 705 # DTB read hits +system.cpu.dtb.read_misses 25 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 712 # DTB read accesses -system.cpu.dtb.write_hits 352 # DTB write hits -system.cpu.dtb.write_misses 18 # DTB write misses +system.cpu.dtb.read_accesses 730 # DTB read accesses +system.cpu.dtb.write_hits 367 # DTB write hits +system.cpu.dtb.write_misses 19 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 370 # DTB write accesses -system.cpu.dtb.data_hits 1041 # DTB hits -system.cpu.dtb.data_misses 41 # DTB misses +system.cpu.dtb.write_accesses 386 # DTB write accesses +system.cpu.dtb.data_hits 1072 # DTB hits +system.cpu.dtb.data_misses 44 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1082 # DTB accesses -system.cpu.itb.fetch_hits 938 # ITB hits +system.cpu.dtb.data_accesses 1116 # DTB accesses +system.cpu.itb.fetch_hits 947 # ITB hits system.cpu.itb.fetch_misses 26 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 964 # ITB accesses +system.cpu.itb.fetch_accesses 973 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,236 +293,236 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 23532 # number of cpu cycles simulated +system.cpu.numCycles 25549 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4442 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 6549 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1090 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 401 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1376 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 508 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 4412 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6683 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1106 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 415 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1538 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 502 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1107 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 938 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 155 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.330561 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 947 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 152 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.910863 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.331734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6093 84.50% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 49 0.68% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 123 1.71% 86.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 84 1.16% 88.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 131 1.82% 89.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 58 0.80% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 67 0.93% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 62 0.86% 92.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 544 7.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6194 84.42% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 50 0.68% 85.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 126 1.72% 86.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 86 1.17% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 137 1.87% 89.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 59 0.80% 90.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 69 0.94% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 62 0.85% 92.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 554 7.55% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7211 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.046320 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.278302 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5244 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 757 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 975 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 55 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 180 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 156 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 7337 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.043289 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.261576 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5200 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 911 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 995 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 54 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 177 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 159 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 76 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 5674 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 276 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 180 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5327 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 452 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 280 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 942 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 30 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 5438 # Number of instructions processed by rename +system.cpu.decode.DecodedInsts 5779 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 271 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 177 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5279 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 611 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 290 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 960 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 20 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5531 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu.rename.RenamedOperands 3913 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6138 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6131 # Number of integer rename lookups +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.RenamedOperands 3966 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6277 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6270 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 6 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2145 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2198 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 115 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 883 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 455 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 2 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 4685 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.skidInsts 117 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 895 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4768 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 3891 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2057 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 3966 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2151 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1238 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7211 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.539592 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.280898 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7337 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.540548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.288327 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5712 79.21% 79.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 492 6.82% 86.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 353 4.90% 90.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 253 3.51% 94.44% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 197 2.73% 97.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 121 1.68% 98.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 52 0.72% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 19 0.26% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5813 79.23% 79.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 503 6.86% 86.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 359 4.89% 90.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 255 3.48% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 198 2.70% 97.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 113 1.54% 98.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 62 0.85% 99.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 21 0.29% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7211 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7337 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 11.76% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.76% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 43.14% 54.90% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 45.10% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 18.97% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.97% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 37.93% 56.90% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 25 43.10% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2776 71.34% 71.34% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.37% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 739 18.99% 90.36% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 375 9.64% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2817 71.03% 71.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.03% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.05% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 757 19.09% 90.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 391 9.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 3891 # Type of FU issued -system.cpu.iq.rate 0.165349 # Inst issue rate -system.cpu.iq.fu_busy_cnt 51 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.013107 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15045 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 6745 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3580 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 3966 # Type of FU issued +system.cpu.iq.rate 0.155231 # Inst issue rate +system.cpu.iq.fu_busy_cnt 58 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.014624 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 15337 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 6922 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3670 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 3935 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4017 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 32 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 468 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 480 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 4 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 161 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 24 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 180 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 393 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5027 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 177 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 538 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5114 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 28 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 883 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 455 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 895 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 4 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 22 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 169 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 191 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 3755 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 713 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 136 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 21 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 167 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 188 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3845 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 731 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 121 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 336 # number of nop insts executed -system.cpu.iew.exec_refs 1083 # number of memory reference insts executed -system.cpu.iew.exec_branches 638 # Number of branches executed -system.cpu.iew.exec_stores 370 # Number of stores executed -system.cpu.iew.exec_rate 0.159570 # Inst execution rate -system.cpu.iew.wb_sent 3650 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3586 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1711 # num instructions producing a value -system.cpu.iew.wb_consumers 2190 # num instructions consuming a value +system.cpu.iew.exec_nop 340 # number of nop insts executed +system.cpu.iew.exec_refs 1117 # number of memory reference insts executed +system.cpu.iew.exec_branches 655 # Number of branches executed +system.cpu.iew.exec_stores 386 # Number of stores executed +system.cpu.iew.exec_rate 0.150495 # Inst execution rate +system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3676 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1745 # num instructions producing a value +system.cpu.iew.wb_consumers 2262 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.152388 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.781279 # average fanout of values written-back +system.cpu.iew.wb_rate 0.143880 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.771441 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2437 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2526 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 157 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6757 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.381234 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.252230 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 154 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6873 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.374800 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238011 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5909 87.45% 87.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 193 2.86% 90.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 297 4.40% 94.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 108 1.60% 96.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 72 1.07% 97.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.78% 98.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.49% 98.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22 0.33% 98.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 70 1.04% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6022 87.62% 87.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 192 2.79% 90.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 299 4.35% 94.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 111 1.62% 96.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 72 1.05% 97.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 55 0.80% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.48% 98.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 20 0.29% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 69 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6757 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6873 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -568,102 +568,102 @@ system.cpu.commit.op_class_0::MemWrite 294 11.41% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2576 # Class of committed instruction -system.cpu.commit.bw_lim_events 70 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11453 # The number of ROB reads -system.cpu.rob.rob_writes 10498 # The number of ROB writes -system.cpu.timesIdled 160 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 16321 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 11659 # The number of ROB reads +system.cpu.rob.rob_writes 10686 # The number of ROB writes +system.cpu.timesIdled 151 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18212 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 9.858400 # CPI: Cycles Per Instruction -system.cpu.cpi_total 9.858400 # CPI: Total CPI of All Threads -system.cpu.ipc 0.101436 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.101436 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4543 # number of integer regfile reads -system.cpu.int_regfile_writes 2774 # number of integer regfile writes +system.cpu.cpi 10.703393 # CPI: Cycles Per Instruction +system.cpu.cpi_total 10.703393 # CPI: Total CPI of All Threads +system.cpu.ipc 0.093428 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.093428 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4655 # number of integer regfile reads +system.cpu.int_regfile_writes 2832 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 46.118209 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 729 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 46.039302 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 743 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 8.576471 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 8.741176 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 46.118209 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011259 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011259 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 46.039302 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011240 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011240 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 85 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 69 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.020752 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1939 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1939 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 516 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 516 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 729 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 729 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 729 # number of overall hits -system.cpu.dcache.overall_hits::total 729 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 117 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 117 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 198 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 198 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 198 # number of overall misses -system.cpu.dcache.overall_misses::total 198 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7447000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7447000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5312000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5312000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12759000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12759000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12759000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 633 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 633 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 1969 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1969 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 525 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 525 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 218 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 218 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 743 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 743 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 743 # number of overall hits +system.cpu.dcache.overall_hits::total 743 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 199 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 199 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 199 # number of overall misses +system.cpu.dcache.overall_misses::total 199 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8172750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8172750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5678000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5678000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13850750 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13850750 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13850750 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13850750 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 648 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 648 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 927 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 927 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 927 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 927 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.184834 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.213592 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.213592 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.213592 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.213592 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63649.572650 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63649.572650 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65580.246914 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65580.246914 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 64439.393939 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 64439.393939 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 131 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 942 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 942 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 942 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 942 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.189815 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.189815 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.258503 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.258503 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.211253 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.211253 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.211253 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.211253 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 66445.121951 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 66445.121951 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74710.526316 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74710.526316 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 69601.758794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 69601.758794 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 69601.758794 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 145 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 65.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 113 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 113 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 52 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 114 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 114 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -672,87 +672,87 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4512500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1719750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6232250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6232250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.096367 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.096367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4793500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4793500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1841500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1841500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6635000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6635000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6635000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094136 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094136 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.091694 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.091694 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 73975.409836 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71656.250000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73320.588235 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 73320.588235 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.090234 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090234 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.090234 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78581.967213 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78581.967213 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76729.166667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78058.823529 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 78058.823529 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 92.065177 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 685 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 91.893913 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 694 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.663102 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.711230 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 92.065177 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.044954 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.044954 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 91.893913 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.044870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.044870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 187 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 163 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 35 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.091309 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2063 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2063 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 685 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 685 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 685 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 685 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 685 # number of overall hits -system.cpu.icache.overall_hits::total 685 # number of overall hits +system.cpu.icache.tags.tag_accesses 2081 # Number of tag accesses +system.cpu.icache.tags.data_accesses 2081 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 694 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 694 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 694 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 694 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 694 # number of overall hits +system.cpu.icache.overall_hits::total 694 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 253 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 253 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 253 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 253 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 253 # number of overall misses system.cpu.icache.overall_misses::total 253 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17329249 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17329249 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17329249 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17329249 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17329249 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17329249 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 938 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 938 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 938 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 938 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 938 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.269723 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.269723 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.269723 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.269723 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.269723 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.269723 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68495.055336 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68495.055336 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68495.055336 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68495.055336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68495.055336 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68495.055336 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 110 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18914999 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18914999 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18914999 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18914999 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18914999 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18914999 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 947 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 947 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 947 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 947 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 947 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.267159 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.267159 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.267159 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.267159 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.267159 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.267159 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74762.841897 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74762.841897 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74762.841897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74762.841897 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74762.841897 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -768,39 +768,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187 system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12893999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12893999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12893999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12893999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12893999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12893999 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.199360 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.199360 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.199360 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.199360 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68951.866310 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68951.866310 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68951.866310 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68951.866310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68951.866310 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68951.866310 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14404999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14404999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14404999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14404999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14404999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14404999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.197466 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.197466 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.197466 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.197466 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77032.080214 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77032.080214 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77032.080214 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77032.080214 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 121.503793 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 121.236486 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 92.265551 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 29.238242 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002816 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000892 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.003708 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 92.076745 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 29.159741 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.003700 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 248 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 214 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 34 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007568 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 2448 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 2448 # Number of data accesses @@ -815,17 +815,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12706250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4451500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17157750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1694250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1694250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12706250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6145750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18852000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12706250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6145750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18852000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14216750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4732500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18949250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1816000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1816000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14216750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6548500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20765250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14216750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6548500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20765250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -848,17 +848,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67947.860963 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72975.409836 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69184.475806 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70593.750000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70593.750000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 69308.823529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67947.860963 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72302.941176 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 69308.823529 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76025.401070 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77581.967213 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76408.266129 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75666.666667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75666.666667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76342.830882 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76025.401070 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77041.176471 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76342.830882 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -878,17 +878,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10348750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3702000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14050750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1400750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1400750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10348750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5102750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15451500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10348750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5102750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15451500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11881250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15850750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1520000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11881250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5489500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17370750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11881250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5489500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17370750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -900,17 +900,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55340.909091 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60688.524590 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56656.250000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58364.583333 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58364.583333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55340.909091 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60032.352941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56806.985294 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63536.096257 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65073.770492 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63914.314516 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63333.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63536.096257 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64582.352941 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63863.051471 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 248 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 248 # Transaction distribution @@ -935,10 +935,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 272 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 136000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 314250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 133250 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 318750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 139500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.trans_dist::ReadReq 248 # Transaction distribution system.membus.trans_dist::ReadResp 248 # Transaction distribution @@ -959,9 +959,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 272 # Request fanout histogram -system.membus.reqLayer0.occupancy 339500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2545000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 21.6 # Layer utilization (%) +system.membus.reqLayer0.occupancy 341000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 1440250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt index 6695f502c..364bc6f05 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16524000 # Number of ticks simulated -final_tick 16524000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16524500 # Number of ticks simulated +final_tick 16524500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 428144 # Simulator instruction rate (inst/s) -host_op_rate 427151 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2733498759 # Simulator tick rate (ticks/s) -host_mem_usage 286260 # Number of bytes of host memory used +host_inst_rate 396950 # Simulator instruction rate (inst/s) +host_op_rate 396157 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2535599202 # Simulator tick rate (ticks/s) +host_mem_usage 290048 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 10432 # Nu system.physmem.num_reads::cpu.inst 163 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 82 # Number of read requests responded to by this memory system.physmem.num_reads::total 245 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 631324135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 317598644 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 948922779 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 631324135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 631324135 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 631324135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 317598644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 948922779 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 218 # Transaction distribution -system.membus.trans_dist::ReadResp 218 # Transaction distribution -system.membus.trans_dist::ReadExReq 27 # Transaction distribution -system.membus.trans_dist::ReadExResp 27 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 245 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245 # Request fanout histogram -system.membus.reqLayer0.occupancy 245000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) -system.membus.respLayer1.occupancy 2205000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 13.3 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 631305032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 317589034 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 948894066 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 631305032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 631305032 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 631305032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 317589034 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 948894066 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -86,7 +63,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 33048 # number of cpu cycles simulated +system.cpu.numCycles 33049 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2577 # Number of instructions committed @@ -105,7 +82,7 @@ system.cpu.num_mem_refs 717 # nu system.cpu.num_load_insts 419 # Number of load instructions system.cpu.num_store_insts 298 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 33048 # Number of busy cycles +system.cpu.num_busy_cycles 33049 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 396 # Number of branches fetched @@ -144,15 +121,119 @@ system.cpu.op_class::MemWrite 298 11.53% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 2585 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 47.433873 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 47.433873 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits +system.cpu.dcache.overall_hits::total 627 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses +system.cpu.dcache.overall_misses::total 82 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1444500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4387000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4387000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4387000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 80.050296 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 80.042941 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2423 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 163 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 14.865031 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 80.050296 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.039087 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.039087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 80.042941 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.039083 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.039083 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 163 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 61 # Occupied blocks per task id @@ -171,12 +252,12 @@ system.cpu.icache.demand_misses::cpu.inst 163 # n system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.icache.overall_misses::total 163 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8965000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8965000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8965000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8965000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8965000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8965500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8965500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8965500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8965500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8965500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8965500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses @@ -189,12 +270,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 system.cpu.icache.demand_miss_rate::total 0.063032 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.063032 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 55000 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55003.067485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 55003.067485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 55003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 55003.067485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 55003.067485 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -209,34 +290,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 163 system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8721000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 8721000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8721000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 8721000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8721000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 8721000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063032 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.063032 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.063032 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53503.067485 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53503.067485 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53503.067485 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53503.067485 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 107.162861 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 107.153052 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 218 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.168669 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 26.994192 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002447 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 80.161341 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 26.991711 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002446 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000824 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.003270 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 218 # Occupied blocks per task id @@ -256,17 +337,17 @@ system.cpu.l2cache.demand_misses::total 245 # nu system.cpu.l2cache.overall_misses::cpu.inst 163 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 82 # number of overall misses system.cpu.l2cache.overall_misses::total 245 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8476000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1404000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8476000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4264000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 12740000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8476000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4264000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 12740000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8558000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 11445500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1417500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8558000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4305000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 12863000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8558000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4305000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 12863000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 163 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 218 # number of ReadReq accesses(hits+misses) @@ -289,17 +370,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52503.067485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52502.293578 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52502.040816 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52503.067485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52502.040816 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -319,17 +400,17 @@ system.cpu.l2cache.demand_mshr_misses::total 245 system.cpu.l2cache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 245 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6520000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 9800000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6601500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8829000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1093500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6601500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3321000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 9922500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6601500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3321000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9922500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -341,122 +422,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 47.437790 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 627 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 82 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 7.646341 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 47.437790 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.011581 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 82 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 43 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.020020 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 1500 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 1500 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 360 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 360 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 267 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 267 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 627 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 627 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 627 # number of overall hits -system.cpu.dcache.overall_hits::total 627 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 27 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 27 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 82 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 82 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 82 # number of overall misses -system.cpu.dcache.overall_misses::total 82 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 1485000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 1485000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 4510000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 4510000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 4510000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 709 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 709 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 709 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 709 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.132530 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.091837 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.115656 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.115656 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.115656 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.115656 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 27 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 27 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 82 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 82 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 82 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1431000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4346000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4346000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.132530 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.091837 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.115656 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.115656 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 218 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 27 # Transaction distribution @@ -485,5 +462,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 244500 # La system.cpu.toL2Bus.respLayer0.utilization 1.5 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 123000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 218 # Transaction distribution +system.membus.trans_dist::ReadResp 218 # Transaction distribution +system.membus.trans_dist::ReadExReq 27 # Transaction distribution +system.membus.trans_dist::ReadExResp 27 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 490 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 15680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 245 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 245 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 245 # Request fanout histogram +system.membus.reqLayer0.occupancy 245500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 1225500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 452f74fef..a4c548b0e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27981000 # Number of ticks simulated -final_tick 27981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000030 # Number of seconds simulated +sim_ticks 30427500 # Number of ticks simulated +final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 40383 # Simulator instruction rate (inst/s) -host_op_rate 47269 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 245344554 # Simulator tick rate (ticks/s) -host_mem_usage 297404 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 90683 # Simulator instruction rate (inst/s) +host_op_rate 106136 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 599001910 # Simulator tick rate (ticks/s) +host_mem_usage 308040 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 4604 # Number of instructions simulated sim_ops 5390 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 697616240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 265322898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 962939137 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 697616240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 697616240 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 697616240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 265322898 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 962939137 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27895500 # Total gap between requests +system.physmem.totGap 30336000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,75 +187,76 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 403.301587 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 282.308639 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 327.677686 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 9 14.29% 14.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 39.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 20.63% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2478000 # Total ticks spent queuing -system.physmem.totMemAccLat 10371750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2605000 # Total ticks spent queuing +system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5885.99 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24635.99 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 962.94 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 962.94 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.52 # Data bus utilization in percentage -system.physmem.busUtilRead 7.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.92 # Data bus utilization in percentage +system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 350 # Number of row buffer hits during reads +system.physmem.readRowHits 348 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.14 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 66260.10 # Average gap between requests -system.physmem.pageHitRate 83.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2090400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 72057.01 # Average gap between requests +system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20220195 # Total energy per rank (pJ) -system.physmem_0.averagePower 856.107753 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 12000 # Time in different power states +system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ) +system.physmem_0.averagePower 848.018629 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22840500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22840000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 136080 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 74250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 702000 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 694200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15972255 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 160500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 18570765 # Total energy per rank (pJ) -system.physmem_1.averagePower 786.272135 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1588250 # Time in different power states +system.physmem_1.actBackEnergy 15437025 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ) +system.physmem_1.averagePower 782.664197 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22654750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1926 # Number of BP lookups +system.cpu.branchPred.lookups 1927 # Number of BP lookups system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1596 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups system.cpu.branchPred.BTBHits 326 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 20.426065 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -376,44 +377,44 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 55962 # number of cpu cycles simulated +system.cpu.numCycles 60855 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4604 # Number of instructions committed system.cpu.committedOps 5390 # Number of ops (including micro ops) committed system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 12.155083 # CPI: cycles per instruction -system.cpu.ipc 0.082270 # IPC: instructions per cycle -system.cpu.tickCycles 10640 # Number of cycles that the object actually ticked -system.cpu.idleCycles 45322 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.217854 # CPI: cycles per instruction +system.cpu.ipc 0.075655 # IPC: instructions per cycle +system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked +system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.669090 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1922 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.164384 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.669090 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021159 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021159 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4354 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4354 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1054 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1054 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1900 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1900 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1900 # number of overall hits -system.cpu.dcache.overall_hits::total 1900 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits +system.cpu.dcache.overall_hits::total 1899 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses @@ -422,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6708741 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6708741 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4576500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4576500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 11285241 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 11285241 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 11285241 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 11285241 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1169 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1169 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2082 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2082 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2082 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2082 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098375 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098375 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087416 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087416 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087416 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087416 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58336.878261 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58336.878261 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 68305.970149 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 68305.970149 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62006.818681 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62006.818681 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62006.818681 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -482,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6015258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6015258 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2857500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8872758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8872758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8872758 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8872758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088109 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088109 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070125 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070125 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070125 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58400.563107 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58400.563107 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 66453.488372 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 66453.488372 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60772.315068 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60772.315068 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 162.236148 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1919 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.959627 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 162.236148 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.079217 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.079217 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4804 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4804 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1919 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1919 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1919 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1919 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1919 # number of overall hits -system.cpu.icache.overall_hits::total 1919 # number of overall hits +system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4806 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits +system.cpu.icache.overall_hits::total 1920 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21729250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21729250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21729250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21729250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21729250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21729250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2241 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2241 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2241 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2241 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2241 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143686 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143686 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143686 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143686 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143686 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143686 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67482.142857 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67482.142857 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67482.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67482.142857 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67482.142857 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23941750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23941750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23941750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23941750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23941750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23941750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74353.260870 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74353.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74353.260870 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -572,39 +573,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20954750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20954750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20954750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20954750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20954750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20954750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143686 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143686 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143686 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143686 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 65076.863354 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 65076.863354 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 65076.863354 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 65076.863354 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23324250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23324250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23324250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23324250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23324250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23324250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72435.559006 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72435.559006 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.981905 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.764479 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.217425 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004723 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001258 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.221063 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004706 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005962 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses @@ -628,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20459750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5689250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 26149000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2814500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2814500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20459750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8503750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28963500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20459750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8503750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28963500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22823750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6224500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 29048250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22823750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9360750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32184500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22823750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9360750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32184500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) @@ -661,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67081.147541 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70237.654321 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67743.523316 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65453.488372 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65453.488372 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 67513.986014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67081.147541 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 68578.629032 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 67513.986014 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74831.967213 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76845.679012 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75254.533679 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75022.144522 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75022.144522 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -697,17 +698,17 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16622750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4317750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20940500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2273500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16622750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6591250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23214000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16622750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6591250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23214000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19001750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4779000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23780750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7377750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26379500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19001750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7377750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26379500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses @@ -719,17 +720,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54500.819672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59147.260274 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55398.148148 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52872.093023 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54500.819672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56821.120690 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55140.142518 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62300.819672 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution @@ -743,25 +744,23 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 468 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 548250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 378 # Transaction distribution system.membus.trans_dist::ReadResp 378 # Transaction distribution @@ -782,9 +781,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 3936000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index bac015830..eb7b98cb0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16223000 # Number of ticks simulated -final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000017 # Number of seconds simulated +sim_ticks 17307500 # Number of ticks simulated +final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54860 # Simulator instruction rate (inst/s) -host_op_rate 64243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 193800024 # Simulator tick rate (ticks/s) -host_mem_usage 308908 # Number of bytes of host memory used +host_inst_rate 56147 # Simulator instruction rate (inst/s) +host_op_rate 65749 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 211593476 # Simulator tick rate (ticks/s) +host_mem_usage 308560 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory system.physmem.bytes_read::total 25408 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1020598007 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 447436083 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1468034089 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1020598007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1020598007 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1020598007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 447436083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1468034089 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 397 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16156000 # Total gap between requests +system.physmem.totGap 17240500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,76 +187,77 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 388.063492 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 254.022879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 340.382701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 25.40% 46.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 14.29% 60.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.59% 84.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3126000 # Total ticks spent queuing -system.physmem.totMemAccLat 10569750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 3336500 # Total ticks spent queuing +system.physmem.totMemAccLat 10780250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7874.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8404.28 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26624.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27154.28 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1468.03 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1468.03 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.24 # Data bus utilization in percentage -system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.47 # Data bus utilization in percentage +system.physmem.busUtilRead 11.47 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 331 # Number of row buffer hits during reads +system.physmem.readRowHits 330 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40695.21 # Average gap between requests -system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2238600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43426.95 # Average gap between requests +system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2074800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14571510 # Total energy per rank (pJ) -system.physmem_0.averagePower 920.354334 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14395920 # Total energy per rank (pJ) +system.physmem_0.averagePower 909.263856 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) +system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10477170 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 309000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12832590 # Total energy per rank (pJ) -system.physmem_1.averagePower 810.522027 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 784250 # Time in different power states +system.physmem_1.actBackEnergy 10358325 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 414750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12772695 # Total energy per rank (pJ) +system.physmem_1.averagePower 806.611620 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 897000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14853250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14679500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2638 # Number of BP lookups -system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2634 # Number of BP lookups +system.cpu.branchPred.condPredicted 1633 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups -system.cpu.branchPred.BTBHits 783 # Number of BTB hits +system.cpu.branchPred.BTBLookups 2098 # Number of BTB lookups +system.cpu.branchPred.BTBHits 781 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 37.225929 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 353 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -495,95 +496,95 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 32447 # number of cpu cycles simulated +system.cpu.numCycles 34616 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1011 # Number of cycles fetch has spent squashing +system.cpu.fetch.icacheStallCycles 7775 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12462 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2634 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1134 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4935 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1009 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 273 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2063 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 315 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.090163 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.470015 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10832 80.12% 80.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 265 1.96% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 242 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 236 1.75% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 238 1.76% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.14% 89.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 142 1.05% 90.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 172 1.27% 91.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1103 8.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2145 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 13520 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.076092 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.360007 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6427 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4469 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2141 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 348 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12076 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2064 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups +system.cpu.rename.SquashCycles 348 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6634 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 859 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2379 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2057 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1243 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 177 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 1054 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11789 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 52593 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12687 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6295 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 43 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 434 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2310 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1632 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10336 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued +system.cpu.iq.iqInstsIssued 8345 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 4743 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12819 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.617234 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373407 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10276 76.01% 76.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1181 8.74% 84.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 737 5.45% 90.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 452 3.34% 93.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 368 2.72% 96.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 283 2.09% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 137 1.01% 99.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 63 0.47% 99.83% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13520 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available @@ -619,113 +620,113 @@ system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5033 60.31% 60.31% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.38% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2011 24.10% 84.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1292 15.48% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8358 # Type of FU issued -system.cpu.iq.rate 0.257589 # Inst issue rate +system.cpu.iq.FU_type_0::total 8345 # Type of FU issued +system.cpu.iq.rate 0.241073 # Inst issue rate system.cpu.iq.fu_busy_cnt 169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.020252 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30336 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15016 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7551 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses +system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 8471 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 694 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 348 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 819 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2310 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1632 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations +system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 251 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 363 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8047 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1910 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 11 # number of nop insts executed -system.cpu.iew.exec_refs 3148 # number of memory reference insts executed -system.cpu.iew.exec_branches 1457 # Number of branches executed -system.cpu.iew.exec_stores 1240 # Number of stores executed -system.cpu.iew.exec_rate 0.248498 # Inst execution rate -system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7601 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3572 # num instructions producing a value -system.cpu.iew.wb_consumers 6998 # num instructions consuming a value +system.cpu.iew.exec_refs 3142 # number of memory reference insts executed +system.cpu.iew.exec_branches 1452 # Number of branches executed +system.cpu.iew.exec_stores 1232 # Number of stores executed +system.cpu.iew.exec_rate 0.232465 # Inst execution rate +system.cpu.iew.wb_sent 7714 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7583 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3567 # num instructions producing a value +system.cpu.iew.wb_consumers 6985 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back +system.cpu.iew.wb_rate 0.219061 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.510666 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5019 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 12644 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.425261 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.266647 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10588 83.74% 83.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 887 7.02% 90.75% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 425 3.36% 94.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 213 1.68% 95.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 117 0.93% 96.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 214 1.69% 98.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 50 0.40% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.29% 99.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 113 0.89% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12644 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -771,122 +772,122 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22692 # The number of ROB reads -system.cpu.rob.rob_writes 21720 # The number of ROB writes -system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22770 # The number of ROB reads +system.cpu.rob.rob_writes 21679 # The number of ROB writes +system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21096 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads -system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7945 # number of integer regfile reads -system.cpu.int_regfile_writes 4420 # number of integer regfile writes -system.cpu.fp_regfile_reads 31 # number of floating regfile reads -system.cpu.cc_regfile_reads 28734 # number of cc regfile reads -system.cpu.cc_regfile_writes 3302 # number of cc regfile writes -system.cpu.misc_regfile_reads 3189 # number of misc regfile reads +system.cpu.cpi 7.539970 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.539970 # CPI: Total CPI of All Threads +system.cpu.ipc 0.132627 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.132627 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7923 # number of integer regfile reads +system.cpu.int_regfile_writes 4408 # number of integer regfile writes +system.cpu.fp_regfile_reads 32 # number of floating regfile reads +system.cpu.cc_regfile_reads 28677 # number of cc regfile reads +system.cpu.cc_regfile_writes 3298 # number of cc regfile writes +system.cpu.misc_regfile_reads 3185 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.114563 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.291293 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2178 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.917808 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.114563 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021268 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021268 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 87.291293 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021311 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021311 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits +system.cpu.dcache.tags.tag_accesses 5532 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5532 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1558 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1558 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits -system.cpu.dcache.overall_hits::total 2146 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits +system.cpu.dcache.overall_hits::total 2156 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 198 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 198 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses -system.cpu.dcache.overall_misses::total 521 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353493 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11353493 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 32098993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 32098993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 32098993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses +system.cpu.dcache.overall_misses::total 513 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12309993 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12309993 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22746000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22746000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35055993 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35055993 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35055993 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35055993 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1756 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2669 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2669 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2669 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2669 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55928.536946 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55928.536946 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 61610.351248 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 61610.351248 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.192207 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.192207 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.192207 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.192207 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62171.681818 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62171.681818 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72209.523810 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72209.523810 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 68335.269006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 68335.269006 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 93 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,169 +896,169 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6247255 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9392005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9392005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10297005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10297005 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10297005 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10297005 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059795 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59497.666667 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63891.190476 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 63891.190476 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055077 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055077 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 150.722255 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.998434 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1659 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.642857 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 150.722255 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073595 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073595 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 149.998434 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.073241 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.073241 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4430 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits -system.cpu.icache.overall_hits::total 1666 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses -system.cpu.icache.overall_misses::total 402 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25584000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25584000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25584000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25584000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25584000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25584000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63641.791045 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 63641.791045 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 63641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 63641.791045 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 63641.791045 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4420 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4420 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1659 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1659 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1659 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1659 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1659 # number of overall hits +system.cpu.icache.overall_hits::total 1659 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 404 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 404 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 404 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 404 # number of overall misses +system.cpu.icache.overall_misses::total 404 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28289500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28289500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28289500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28289500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28289500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28289500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2063 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2063 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2063 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2063 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195831 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.195831 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.195831 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.195831 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.195831 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.195831 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70023.514851 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 70023.514851 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 70023.514851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 70023.514851 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 361 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 72.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 110 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 110 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 110 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 110 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19740750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 19740750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19740750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 19740750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19740750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 19740750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67145.408163 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67145.408163 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67145.408163 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67145.408163 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21612000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21612000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21612000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21612000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21612000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21612000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142511 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.142511 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.142511 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73510.204082 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73510.204082 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 188.125989 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.994376 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.336521 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.789468 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004313 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005741 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.852442 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 46.141935 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001408 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005707 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits system.cpu.l2cache.overall_hits::total 39 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 84 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 360 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses system.cpu.l2cache.overall_misses::total 402 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19249250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6012750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19249250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9114500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19249250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9114500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21127500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6646750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27774250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3346500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3346500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21127500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9993250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 31120750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21127500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9993250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31120750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) @@ -1069,28 +1070,28 @@ system.cpu.l2cache.demand_accesses::total 441 # n system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935374 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.800000 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 69997.272727 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70738.235294 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69997.272727 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71767.716535 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76548.913043 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79127.976190 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 77150.694444 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77414.800995 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77414.800995 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1105,50 +1106,50 @@ system.cpu.l2cache.demand_mshr_hits::cpu.data 5 system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 79 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15795750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4738000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15795750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7327250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15795750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7327250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17683000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5328000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17683000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8152000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 25835000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17683000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8152000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 25835000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57439.090909 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59225 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57439.090909 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60059.426230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64068.840580 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67443.037975 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64819.718310 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67238.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67238.095238 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution @@ -1162,7 +1163,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram @@ -1170,21 +1171,17 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 441 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 9 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 495000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 238495 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) system.membus.trans_dist::ReadReq 355 # Transaction distribution system.membus.trans_dist::ReadResp 355 # Transaction distribution @@ -1205,9 +1202,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 499500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.1 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 9157ec7b3..9add0d45b 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,46 +1,46 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16487000 # Number of ticks simulated -final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000018 # Number of seconds simulated +sim_ticks 17911000 # Number of ticks simulated +final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 33036 # Simulator instruction rate (inst/s) -host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 118603969 # Simulator tick rate (ticks/s) -host_mem_usage 248576 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 61363 # Simulator instruction rate (inst/s) +host_op_rate 71855 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 239307903 # Simulator tick rate (ticks/s) +host_mem_usage 305224 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory -system.physmem.bytes_read::total 26048 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25984 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory -system.physmem.num_reads::total 407 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 408 # Number of read requests accepted +system.physmem.num_reads::total 406 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 968343476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 385908101 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 96477025 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1450728603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 968343476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 968343476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 968343476 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 385908101 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 96477025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1450728603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 26048 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side +system.physmem.bytesReadSys 26048 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one @@ -48,7 +48,7 @@ system.physmem.neitherReadNorWriteReqs 0 # Nu system.physmem.perBankRdBursts::0 88 # Per bank write bursts system.physmem.perBankRdBursts::1 45 # Per bank write bursts system.physmem.perBankRdBursts::2 19 # Per bank write bursts -system.physmem.perBankRdBursts::3 45 # Per bank write bursts +system.physmem.perBankRdBursts::3 44 # Per bank write bursts system.physmem.perBankRdBursts::4 18 # Per bank write bursts system.physmem.perBankRdBursts::5 32 # Per bank write bursts system.physmem.perBankRdBursts::6 37 # Per bank write bursts @@ -79,14 +79,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 16473500 # Total gap between requests +system.physmem.totGap 17897500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 408 # Read request sizes (log2) +system.physmem.readPktSize::6 407 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -94,13 +94,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see @@ -190,79 +190,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3192729 # Total ticks spent queuing -system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 57 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 433.403509 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 294.791776 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.955773 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 6 10.53% 10.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 33.33% 43.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 15.79% 59.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 5.26% 64.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.51% 68.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.51% 71.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 7.02% 78.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 3 5.26% 84.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 15.79% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 57 # Bytes accessed per row activation +system.physmem.totQLat 3190492 # Total ticks spent queuing +system.physmem.totMemAccLat 10821742 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers +system.physmem.avgQLat 7839.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26589.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1454.30 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1454.30 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 12.37 # Data bus utilization in percentage -system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.36 # Data bus utilization in percentage +system.physmem.busUtilRead 11.36 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 342 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads +system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40376.23 # Average gap between requests -system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43974.20 # Average gap between requests +system.physmem.pageHitRate 84.03 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 279720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 152625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2035800 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) -system.physmem_0.averagePower 918.403600 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states +system.physmem_0.totalEnergy 14310600 # Total energy per rank (pJ) +system.physmem_0.averagePower 903.874941 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) -system.physmem_1.averagePower 817.101847 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states +system.physmem_1.actBackEnergy 10067625 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 668250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12747240 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.131217 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1195750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14254250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu.branchPred.lookups 2361 # Number of BP lookups -system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted +system.cpu.branchPred.condPredicted 1410 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups -system.cpu.branchPred.BTBHits 473 # Number of BTB hits +system.cpu.branchPred.BTBHits 476 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 54.649828 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 288 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 55 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 32975 # number of cpu cycles simulated +system.cpu.numCycles 35823 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed +system.cpu.fetch.icacheStallCycles 6115 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11289 # Number of instructions fetch has processed system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.predictedBranches 764 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 8098 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched +system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 3842 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 15493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.850771 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.201734 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9287 59.94% 59.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2459 15.87% 75.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 519 3.35% 79.16% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3228 20.84% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5035 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst +system.cpu.fetch.rateDist::total 15493 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065907 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.315133 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5846 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4125 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5024 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 366 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 330 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 9854 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1610 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 366 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6916 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1543 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1980 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 4080 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full +system.cpu.rename.UnblockCycles 608 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8873 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 401 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups +system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 531 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9263 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40182 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9732 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 3769 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 309 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1783 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8340 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued +system.cpu.iq.iqInstsIssued 7136 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 2794 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7753 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 15493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.460595 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.852056 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11312 73.01% 73.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1923 12.41% 85.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1608 10.38% 95.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 603 3.89% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 47 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,149 +466,149 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 15493 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 427 29.53% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 469 32.43% 61.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 550 38.04% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4484 62.84% 62.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.91% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1571 22.02% 84.96% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1073 15.04% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7157 # Type of FU issued -system.cpu.iq.rate 0.217043 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7136 # Type of FU issued +system.cpu.iq.rate 0.199202 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1446 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.202635 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31353 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11164 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8554 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 9 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 756 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 315 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 366 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 898 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8393 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1783 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1253 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 291 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 6736 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1394 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 400 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2417 # number of memory reference insts executed -system.cpu.iew.exec_branches 1277 # Number of branches executed -system.cpu.iew.exec_stores 1017 # Number of stores executed -system.cpu.iew.exec_rate 0.205034 # Inst execution rate -system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6587 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2990 # num instructions producing a value -system.cpu.iew.wb_consumers 5391 # num instructions consuming a value +system.cpu.iew.exec_refs 2409 # number of memory reference insts executed +system.cpu.iew.exec_branches 1271 # Number of branches executed +system.cpu.iew.exec_stores 1015 # Number of stores executed +system.cpu.iew.exec_rate 0.188036 # Inst execution rate +system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6566 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2981 # num instructions producing a value +system.cpu.iew.wb_consumers 5387 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back +system.cpu.iew.wb_rate 0.183290 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.553369 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2567 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14953 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.359593 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.005851 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 12307 82.30% 82.30% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1380 9.23% 91.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 605 4.05% 95.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 296 1.98% 97.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 166 1.11% 98.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 78 0.52% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.31% 99.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 31 0.21% 99.71% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 14953 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -654,122 +654,122 @@ system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22003 # The number of ROB reads -system.cpu.rob.rob_writes 16441 # The number of ROB writes -system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22696 # The number of ROB reads +system.cpu.rob.rob_writes 16433 # The number of ROB writes +system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20330 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads -system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 6737 # number of integer regfile reads -system.cpu.int_regfile_writes 3765 # number of integer regfile writes +system.cpu.cpi 7.802875 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.802875 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128158 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128158 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 6713 # number of integer regfile reads +system.cpu.int_regfile_writes 3756 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 24010 # number of cc regfile reads -system.cpu.cc_regfile_writes 2910 # number of cc regfile writes -system.cpu.misc_regfile_reads 2599 # number of misc regfile reads +system.cpu.cc_regfile_reads 23929 # number of cc regfile reads +system.cpu.cc_regfile_writes 2892 # number of cc regfile writes +system.cpu.misc_regfile_reads 2595 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.129086 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1902 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.394366 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.129086 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164315 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164315 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4674 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4674 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1160 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1160 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits -system.cpu.dcache.overall_hits::total 1876 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits +system.cpu.dcache.overall_hits::total 1882 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses -system.cpu.dcache.overall_misses::total 369 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 362 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 362 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 362 # number of overall misses +system.cpu.dcache.overall_misses::total 362 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9785742 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9785742 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7277250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7277250 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17062992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17062992 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17062992 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17062992 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1331 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133634 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.133634 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2244 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2244 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.128475 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.128475 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164365 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164365 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164365 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164365 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.161319 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.161319 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.161319 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.161319 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57226.561404 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 57226.561404 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47135.337017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47135.337017 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 646 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 717 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 35.888889 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 39.833333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 226 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 226 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -778,120 +778,120 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5294755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5294755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2189500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7484255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7484255 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7484255 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7484255 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076577 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076577 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2367750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2367750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8376505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8376505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8376505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8376505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076634 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063697 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063697 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53402.439024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53402.439024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063725 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063725 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57750 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57750 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 138.060100 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3485 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.773649 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.043653 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3477 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.786441 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 138.060100 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.269649 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.269649 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 254 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.496094 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7990 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7990 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3485 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3485 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3485 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3485 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3485 # number of overall hits -system.cpu.icache.overall_hits::total 3485 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses -system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19725741 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19725741 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19725741 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19725741 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19725741 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19725741 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3847 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3847 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3847 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3847 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3847 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094099 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094099 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094099 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094099 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094099 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094099 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54490.997238 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54490.997238 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54490.997238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54490.997238 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 7642 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 18 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 94 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 136.043653 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.265710 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.265710 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 7977 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7977 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3477 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3477 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3477 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3477 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3477 # number of overall hits +system.cpu.icache.overall_hits::total 3477 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22425741 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22425741 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22425741 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22425741 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22425741 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22425741 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3841 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3841 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3841 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3841 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3841 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094767 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094767 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094767 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094767 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094767 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094767 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61609.178571 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 61609.178571 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 61609.178571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 61609.178571 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8359 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 92 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 81.297872 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 90.858696 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16894743 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16894743 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16894743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16894743 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16894743 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16894743 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077203 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077203 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077203 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56884.656566 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56884.656566 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18519493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18519493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18519493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18519493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18519493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18519493 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077063 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.077063 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.077063 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62565.854730 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62565.854730 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -900,28 +900,28 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.136661 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 192.519523 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.115068 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.115385 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.591914 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 45.333856 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.210892 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008581 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002767 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011910 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.367812 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 44.986812 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.164899 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008445 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002746 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000559 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011750 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021301 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 7446 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 7446 # Number of data accesses +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 7429 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 7429 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits @@ -933,61 +933,61 @@ system.cpu.l2cache.demand_hits::total 53 # nu system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits system.cpu.l2cache.overall_hits::cpu.data 30 # number of overall hits system.cpu.l2cache.overall_hits::total 53 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 387 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses +system.cpu.l2cache.demand_misses::total 386 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses -system.cpu.l2cache.overall_misses::total 387 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16599750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5077250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21677000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2079500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16599750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7156750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23756500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16599750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7156750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23756500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 386 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18219750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5781750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 24001500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2253750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2253750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18219750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8035500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26255250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18219750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8035500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26255250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922559 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922297 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813725 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.894737 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.894472 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922559 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.879545 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922559 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.879545 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60583.029197 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61171.686747 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 60719.887955 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69316.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69316.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 61386.304910 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 61386.304910 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66739.010989 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69659.638554 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67419.943820 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75125 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75125 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 68018.782383 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 68018.782383 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1005,118 +1005,116 @@ system.cpu.l2cache.demand_mshr_hits::total 6 # system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 381 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14211250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4185750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18397000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1810701 # number of HardPFReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1833500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14211250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6019250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20230500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14211250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6019250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 22041201 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15861750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4830750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20692500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1641917 # number of HardPFReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2002750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2002750 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15861750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6833500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22695250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15861750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6833500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24337167 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879397 # mshr miss rate for ReadReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency -system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58315.257353 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61932.692308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59121.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average HardPFReq mshr miss latency +system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167 # average HardPFReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59724.342105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56862.539720 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution -system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution +system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 591 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 67 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram +system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 64 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 378 # Transaction distribution -system.membus.trans_dist::ReadResp 376 # Transaction distribution +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 496749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 228995 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) +system.membus.trans_dist::ReadReq 377 # Transaction distribution +system.membus.trans_dist::ReadResp 375 # Transaction distribution system.membus.trans_dist::ReadExReq 30 # Transaction distribution system.membus.trans_dist::ReadExResp 30 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 812 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 812 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25920 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25920 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 408 # Request fanout histogram +system.membus.snoop_fanout::samples 407 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 407 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 408 # Request fanout histogram -system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 23.0 # Layer utilization (%) +system.membus.snoop_fanout::total 407 # Request fanout histogram +system.membus.reqLayer0.occupancy 509443 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2140258 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.9 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index 72322cbec..cdd01be72 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 396323 # Simulator instruction rate (inst/s) -host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 232084410 # Simulator tick rate (ticks/s) -host_mem_usage 298640 # Number of bytes of host memory used +host_inst_rate 771856 # Simulator instruction rate (inst/s) +host_op_rate 901727 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 450886881 # Simulator tick rate (ticks/s) +host_mem_usage 297796 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -347,18 +347,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index b8c713e42..bd1ca933f 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000003 # Nu sim_ticks 2694500 # Number of ticks simulated final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 370272 # Simulator instruction rate (inst/s) -host_op_rate 433210 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216878622 # Simulator tick rate (ticks/s) -host_mem_usage 297624 # Number of bytes of host memory used +host_inst_rate 801222 # Simulator instruction rate (inst/s) +host_op_rate 936270 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 468120222 # Simulator tick rate (ticks/s) +host_mem_usage 297024 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5377 # Number of ops (including micro ops) simulated @@ -228,18 +228,16 @@ system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram +system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 4 # Request fanout histogram -system.membus.snoop_fanout::max_value 5 # Request fanout histogram +system.membus.snoop_fanout::min_value 2 # Request fanout histogram +system.membus.snoop_fanout::max_value 3 # Request fanout histogram system.membus.snoop_fanout::total 6531 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 872a056d2..8573f117d 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25815000 # Number of ticks simulated -final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25815500 # Number of ticks simulated +final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 376930 # Simulator instruction rate (inst/s) -host_op_rate 439541 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2127142386 # Simulator tick rate (ticks/s) -host_mem_usage 307352 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host +host_inst_rate 263675 # Simulator instruction rate (inst/s) +host_op_rate 307555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1488783160 # Simulator tick rate (ticks/s) +host_mem_usage 306760 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host sim_insts 4565 # Number of instructions simulated sim_ops 5329 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,7 +147,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51630 # number of cpu cycles simulated +system.cpu.numCycles 51631 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4565 # Number of instructions committed @@ -168,7 +168,7 @@ system.cpu.num_mem_refs 1965 # nu system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1007 # Number of branches fetched @@ -208,14 +208,14 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5390 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id @@ -294,14 +294,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses @@ -310,24 +310,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id @@ -346,12 +346,12 @@ system.cpu.icache.demand_misses::cpu.inst 241 # n system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses system.cpu.icache.overall_misses::total 241 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses @@ -364,12 +364,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -384,33 +384,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 241 system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy @@ -440,17 +440,17 @@ system.cpu.l2cache.demand_misses::total 350 # nu system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses system.cpu.l2cache.overall_misses::total 350 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) @@ -473,17 +473,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916230 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,17 +503,17 @@ system.cpu.l2cache.demand_mshr_misses::total 350 system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses @@ -525,17 +525,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution @@ -549,19 +549,17 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) @@ -588,9 +586,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 350 # Request fanout histogram -system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index ca0260a61..f65d4ed09 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 21163500 # Number of ticks simulated -final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 22762000 # Number of ticks simulated +final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 81533 # Simulator instruction rate (inst/s) -host_op_rate 81515 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 345921870 # Simulator tick rate (ticks/s) -host_mem_usage 292088 # Number of bytes of host memory used +host_inst_rate 85129 # Simulator instruction rate (inst/s) +host_op_rate 85110 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 388456550 # Simulator tick rate (ticks/s) +host_mem_usage 291584 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 4986 # Number of instructions simulated sim_ops 4986 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21120 # Nu system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 471 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 997944574 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 426394500 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1424339074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 997944574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 997944574 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 997944574 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 426394500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1424339074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 927862227 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 396450224 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1324312451 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 927862227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 927862227 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 927862227 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 396450224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1324312451 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 471 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 21083000 # Total gap between requests +system.physmem.totGap 22674500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -91,10 +91,10 @@ system.physmem.writePktSize::4 0 # Wr system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,78 +186,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 262.095238 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 179.705030 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 253.763121 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 34 32.38% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 17 16.19% 77.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 10 9.52% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1 0.95% 91.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 1.90% 93.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.90% 95.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation -system.physmem.totQLat 5392000 # Total ticks spent queuing -system.physmem.totMemAccLat 14223250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 181.184943 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 253.583818 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 28 26.92% 26.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 35 33.65% 60.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 18 17.31% 77.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 10 9.62% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3 2.88% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation +system.physmem.totQLat 5218000 # Total ticks spent queuing +system.physmem.totMemAccLat 14049250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11447.98 # Average queueing delay per DRAM burst +system.physmem.avgQLat 11078.56 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30197.98 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1424.34 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 29828.56 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1324.31 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1424.34 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1324.31 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.13 # Data bus utilization in percentage -system.physmem.busUtilRead 11.13 # Data bus utilization in percentage for reads +system.physmem.busUtil 10.35 # Data bus utilization in percentage +system.physmem.busUtilRead 10.35 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing system.physmem.readRowHits 356 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 44762.21 # Average gap between requests +system.physmem.avgGap 48141.19 # Average gap between requests system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) +system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 491400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) -system.physmem_0.averagePower 790.660351 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states +system.physmem_0.actBackEnergy 9465705 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1196250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 12369120 # Total energy per rank (pJ) +system.physmem_0.averagePower 781.248697 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 1950500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 13375750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) -system.physmem_1.averagePower 944.255803 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states +system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14812845 # Total energy per rank (pJ) +system.physmem_1.averagePower 935.597347 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 284750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15222250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2146 # Number of BP lookups -system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1636 # Number of BTB lookups -system.cpu.branchPred.BTBHits 528 # Number of BTB hits +system.cpu.branchPred.lookups 2110 # Number of BP lookups +system.cpu.branchPred.condPredicted 1371 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 423 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1629 # Number of BTB lookups +system.cpu.branchPred.BTBHits 525 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 32.228361 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits @@ -279,236 +279,236 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 42328 # number of cpu cycles simulated +system.cpu.numCycles 45525 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8967 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13064 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2146 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 812 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4771 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing -system.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2037 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.908737 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.207470 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 8934 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12895 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2110 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 805 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing +system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.890662 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.186824 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11035 76.76% 76.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1473 10.25% 87.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 126 0.88% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 160 1.11% 89.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 283 1.97% 90.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 90 0.63% 91.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 137 0.95% 92.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 121 0.84% 93.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 951 6.62% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11164 77.11% 77.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1470 10.15% 87.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 124 0.86% 88.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 160 1.11% 89.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 283 1.95% 91.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 94 0.65% 91.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 128 0.88% 92.71% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 113 0.78% 93.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 942 6.51% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14376 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.050699 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.308637 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8549 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2515 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2791 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing +system.cpu.fetch.rateDist::total 14478 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.046348 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.283251 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8487 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2706 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2773 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 391 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12032 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 11880 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8711 # Number of cycles rename is idle +system.cpu.rename.SquashCycles 391 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8645 # Number of cycles rename is idle system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 944 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2743 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1081 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11544 # Number of instructions processed by rename +system.cpu.rename.serializeStallCycles 1002 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2724 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1214 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11398 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 196 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 6963 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13345 # Number of integer rename lookups +system.cpu.rename.LQFullEvents 231 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 967 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13412 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13162 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3681 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3597 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 13 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 298 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 290 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2474 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1168 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9029 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8940 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8280 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3419 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1838 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8204 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3309 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1790 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14376 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.575960 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.325471 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14478 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.566653 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.310295 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11054 76.89% 76.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1314 9.14% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 739 5.14% 91.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 413 2.87% 94.05% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 345 2.40% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 315 2.19% 98.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 104 0.72% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 66 0.46% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 11167 77.13% 77.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1314 9.08% 86.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 734 5.07% 91.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 423 2.92% 94.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 344 2.38% 96.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 310 2.14% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 102 0.70% 99.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 57 0.39% 99.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 27 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14376 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14478 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 8 4.06% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 131 66.50% 70.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 58 29.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 4.59% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 129 65.82% 70.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4865 58.76% 58.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2336 28.21% 87.05% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1072 12.95% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4822 58.78% 58.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.86% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2303 28.07% 86.93% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1072 13.07% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8280 # Type of FU issued -system.cpu.iq.rate 0.195615 # Inst issue rate -system.cpu.iq.fu_busy_cnt 197 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023792 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31160 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12466 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7466 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8204 # Type of FU issued +system.cpu.iq.rate 0.180209 # Inst issue rate +system.cpu.iq.fu_busy_cnt 196 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023891 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31113 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12267 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7408 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8398 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1342 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 267 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 475 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10593 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 391 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 464 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10483 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2474 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1168 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 13 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7957 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2194 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 323 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 348 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 444 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7875 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1553 # number of nop insts executed -system.cpu.iew.exec_refs 3252 # number of memory reference insts executed -system.cpu.iew.exec_branches 1379 # Number of branches executed -system.cpu.iew.exec_stores 1058 # Number of stores executed -system.cpu.iew.exec_rate 0.187984 # Inst execution rate -system.cpu.iew.wb_sent 7571 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7468 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2915 # num instructions producing a value -system.cpu.iew.wb_consumers 4399 # num instructions consuming a value +system.cpu.iew.exec_nop 1532 # number of nop insts executed +system.cpu.iew.exec_refs 3217 # number of memory reference insts executed +system.cpu.iew.exec_branches 1365 # Number of branches executed +system.cpu.iew.exec_stores 1057 # Number of stores executed +system.cpu.iew.exec_rate 0.172982 # Inst execution rate +system.cpu.iew.wb_sent 7509 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7410 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2869 # num instructions producing a value +system.cpu.iew.wb_consumers 4254 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.176432 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.662651 # average fanout of values written-back +system.cpu.iew.wb_rate 0.162768 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.674424 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4969 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4860 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 386 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13506 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.416333 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.231872 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13623 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.412758 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.228786 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11333 83.91% 83.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 875 6.48% 90.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 515 3.81% 94.20% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 250 1.85% 96.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 149 1.10% 97.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 177 1.31% 98.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 64 0.47% 98.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 102 0.76% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11456 84.09% 84.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 871 6.39% 90.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 510 3.74% 94.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 252 1.85% 96.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 148 1.09% 97.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 178 1.31% 98.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 65 0.48% 98.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.29% 99.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 103 0.76% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13506 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13623 # Number of insts commited each cycle system.cpu.commit.committedInsts 5623 # Number of instructions committed system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -554,102 +554,102 @@ system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5623 # Class of committed instruction -system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23983 # The number of ROB reads -system.cpu.rob.rob_writes 22065 # The number of ROB writes -system.cpu.timesIdled 275 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 27952 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23990 # The number of ROB reads +system.cpu.rob.rob_writes 21831 # The number of ROB writes +system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4986 # Number of Instructions Simulated system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 8.489370 # CPI: Cycles Per Instruction -system.cpu.cpi_total 8.489370 # CPI: Total CPI of All Threads -system.cpu.ipc 0.117794 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.117794 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10767 # number of integer regfile reads -system.cpu.int_regfile_writes 5247 # number of integer regfile writes +system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction +system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads +system.cpu.ipc 0.109522 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.109522 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10639 # number of integer regfile reads +system.cpu.int_regfile_writes 5201 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 164 # number of misc regfile reads +system.cpu.misc_regfile_reads 165 # number of misc regfile reads system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 91.212769 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2418 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 17.148936 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 91.212769 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.022269 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.022269 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits -system.cpu.dcache.overall_hits::total 2445 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses -system.cpu.dcache.overall_misses::total 515 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.tag_accesses 5997 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5997 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1862 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1862 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits +system.cpu.dcache.overall_hits::total 2418 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses +system.cpu.dcache.overall_misses::total 510 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 12038750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 12038750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 24387249 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 24387249 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36425999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36425999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36425999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36425999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2027 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2027 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081401 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.174180 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174180 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174180 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174180 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72962.121212 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 72962.121212 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70687.678261 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 70687.678261 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 71423.527451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 71423.527451 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses @@ -658,82 +658,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7833500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7833500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4084749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4084749 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11918249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11918249 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11918249 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11918249 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044894 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044894 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048156 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048156 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81694.980000 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81694.980000 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 17 # number of replacements -system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 158.205778 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4.783784 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4.735736 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 158.344728 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.077317 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.077317 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 158.205778 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.077249 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.077249 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4407 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4407 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1593 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1593 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1593 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1593 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1593 # number of overall hits -system.cpu.icache.overall_hits::total 1593 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 444 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 444 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 444 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 444 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 444 # number of overall misses -system.cpu.icache.overall_misses::total 444 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 30764750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 30764750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 30764750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 30764750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 30764750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 30764750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2037 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2037 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2037 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2037 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2037 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2037 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217968 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217968 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217968 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217968 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217968 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217968 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69289.977477 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69289.977477 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69289.977477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69289.977477 # average overall miss latency +system.cpu.icache.tags.tag_accesses 4385 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4385 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits +system.cpu.icache.overall_hits::total 1577 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 449 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 449 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 449 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 449 # number of overall misses +system.cpu.icache.overall_misses::total 449 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 34003000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 34003000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 34003000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 34003000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 34003000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 34003000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221619 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.221619 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.221619 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.221619 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.221619 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.221619 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75730.512249 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 75730.512249 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 75730.512249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 75730.512249 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -742,51 +742,51 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 111 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 111 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 111 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 111 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 111 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24043500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24043500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24043500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24043500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24043500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24043500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163476 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.163476 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.163476 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72202.702703 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72202.702703 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26389500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26389500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26389500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26389500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164363 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.164363 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.164363 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79247.747748 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79247.747748 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 218.292920 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 218.150435 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.335208 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.957712 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004893 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.168468 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.981967 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004888 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006662 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006657 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses @@ -807,17 +807,17 @@ system.cpu.l2cache.demand_misses::total 471 # nu system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 471 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23680500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 30897000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3981500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3981500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23680500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 11198000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 34878500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23680500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 11198000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 34878500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26025000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7738500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 33763500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4034000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4034000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26025000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11772500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37797500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26025000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11772500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37797500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 333 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) @@ -840,17 +840,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993671 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71759.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79302.197802 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73389.548694 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79630 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79630 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74052.016985 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74052.016985 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78863.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85038.461538 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80198.337292 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80680 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80680 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80249.469214 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80249.469214 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -870,17 +870,17 @@ system.cpu.l2cache.demand_mshr_misses::total 471 system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19517000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6096000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25613000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3359000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3359000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19517000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9455000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 28972000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19517000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9455000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 28972000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21894000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6598000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28492000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3411000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3411000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21894000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10009000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31903000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21894000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10009000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31903000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses @@ -892,17 +892,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59142.424242 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66989.010989 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60838.479810 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67180 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67180 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66345.454545 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72505.494505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67676.959620 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68220 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68220 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution @@ -927,11 +927,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 569000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 233500 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) system.membus.trans_dist::ReadReq 421 # Transaction distribution system.membus.trans_dist::ReadResp 421 # Transaction distribution system.membus.trans_dist::ReadExReq 50 # Transaction distribution @@ -951,9 +951,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 471 # Request fanout histogram -system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 20.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 598000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 2506000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt index 84d2a731d..4f23a8939 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30902000 # Number of ticks simulated -final_tick 30902000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30902500 # Number of ticks simulated +final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 104539 # Simulator instruction rate (inst/s) -host_op_rate 104503 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 574021463 # Simulator tick rate (ticks/s) -host_mem_usage 276192 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host +host_inst_rate 544856 # Simulator instruction rate (inst/s) +host_op_rate 544118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2985748792 # Simulator tick rate (ticks/s) +host_mem_usage 288768 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host sim_insts 5624 # Number of instructions simulated sim_ops 5624 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,37 +21,14 @@ system.physmem.bytes_inst_read::total 18752 # Nu system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory system.physmem.num_reads::total 430 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 606821565 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 283735681 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 890557245 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 606821565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 606821565 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 606821565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 283735681 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 890557245 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 380 # Transaction distribution -system.membus.trans_dist::ReadResp 380 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 430 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 430 # Request fanout histogram -system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3870000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.5 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses @@ -72,7 +49,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 61804 # number of cpu cycles simulated +system.cpu.numCycles 61805 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5624 # Number of instructions committed @@ -91,7 +68,7 @@ system.cpu.num_mem_refs 2034 # nu system.cpu.num_load_insts 1132 # Number of load instructions system.cpu.num_store_insts 902 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 61804 # Number of busy cycles +system.cpu.num_busy_cycles 61805 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 883 # Number of branches fetched @@ -130,15 +107,119 @@ system.cpu.op_class::MemWrite 902 16.04% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5625 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits +system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses +system.cpu.dcache.overall_misses::total 137 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 129.108186 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 129.108186 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.063041 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.063041 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id @@ -157,12 +238,12 @@ system.cpu.icache.demand_misses::cpu.inst 295 # n system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses system.cpu.icache.overall_misses::total 295 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16141000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16141000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16141000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16141000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16141000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses @@ -175,12 +256,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54715.254237 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54715.254237 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54715.254237 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54715.254237 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -195,33 +276,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 295 system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15551000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15551000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15551000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15551000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52715.254237 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52715.254237 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 183.724070 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.264551 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 53.459518 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.005607 # Average percentage of cache occupancy @@ -248,17 +329,17 @@ system.cpu.l2cache.demand_misses::total 430 # nu system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses system.cpu.l2cache.overall_misses::total 430 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15236000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19760000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2600000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2600000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15236000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7124000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22360000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15236000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7124000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22360000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 382 # number of ReadReq accesses(hits+misses) @@ -281,17 +362,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995370 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -311,17 +392,17 @@ system.cpu.l2cache.demand_mshr_misses::total 430 system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2000000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11720000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11720000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17200000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses @@ -333,122 +414,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.158665 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.158665 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021035 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021035 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits -system.cpu.dcache.overall_hits::total 1896 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses -system.cpu.dcache.overall_misses::total 137 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2650000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2650000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7261000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7261000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7261000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7261000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution @@ -477,5 +454,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 442500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 380 # Transaction distribution +system.membus.trans_dist::ReadResp 380 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 430 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 430 # Request fanout histogram +system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index e81ca8aaa..c9ca56107 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 18857500 # Number of ticks simulated -final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20101000 # Number of ticks simulated +final_tick 20101000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 101158 # Simulator instruction rate (inst/s) -host_op_rate 101133 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 329193143 # Simulator tick rate (ticks/s) -host_mem_usage 288984 # Number of bytes of host memory used +host_inst_rate 103196 # Simulator instruction rate (inst/s) +host_op_rate 103171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 357968408 # Simulator tick rate (ticks/s) +host_mem_usage 289136 # Number of bytes of host memory used host_seconds 0.06 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 21952 # Nu system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory system.physmem.num_reads::total 444 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1092084971 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 321576041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1413661012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1092084971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1092084971 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1092084971 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 321576041 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1413661012 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 444 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 18724000 # Total gap between requests +system.physmem.totGap 19960500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,77 +186,77 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation -system.physmem.totQLat 3635500 # Total ticks spent queuing -system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 78 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 332.307692 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.606609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 342.258819 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 29 37.18% 37.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17 21.79% 58.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 7 8.97% 67.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 4 5.13% 73.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 4 5.13% 78.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.85% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1 1.28% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 4 5.13% 88.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 11.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 78 # Bytes accessed per row activation +system.physmem.totQLat 3861750 # Total ticks spent queuing +system.physmem.totMemAccLat 12186750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst +system.physmem.avgQLat 8697.64 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 27447.64 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1413.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1413.66 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.77 # Data bus utilization in percentage -system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.04 # Data bus utilization in percentage +system.physmem.busUtilRead 11.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 356 # Number of row buffer hits during reads +system.physmem.readRowHits 357 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads +system.physmem.readRowHitRate 80.41 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42171.17 # Average gap between requests -system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 476280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 259875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2644200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 44956.08 # Average gap between requests +system.physmem.pageHitRate 80.41 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 461160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 251625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2511600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10793520 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 15222495 # Total energy per rank (pJ) -system.physmem_0.averagePower 961.471341 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10794375 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 15068130 # Total energy per rank (pJ) +system.physmem_0.averagePower 951.571203 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15315250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15316250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 68040 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 37125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 288600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 8055810 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 2433000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 11899695 # Total energy per rank (pJ) -system.physmem_1.averagePower 751.599242 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4725250 # Time in different power states +system.physmem_1.actBackEnergy 7470990 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 2946000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 11827875 # Total energy per rank (pJ) +system.physmem_1.averagePower 747.063003 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 6720750 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 11341250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 10486250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2332 # Number of BP lookups -system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2330 # Number of BP lookups +system.cpu.branchPred.condPredicted 1881 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups -system.cpu.branchPred.BTBHits 661 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1929 # Number of BTB lookups +system.cpu.branchPred.BTBHits 660 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.214619 # BTB Hit Percentage system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -279,237 +279,237 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 37716 # number of cpu cycles simulated +system.cpu.numCycles 40203 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 865 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 7819 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13492 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2330 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 879 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4287 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 863 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 153 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1828 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 299 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.061192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.469867 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10352 81.42% 81.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 189 1.49% 82.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 216 1.70% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 152 1.20% 85.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 247 1.94% 87.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 139 1.09% 88.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 253 1.99% 90.83% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 114 0.90% 91.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1052 8.27% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked +system.cpu.fetch.rateDist::total 12714 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.057956 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.335597 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7212 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3139 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1951 # Number of cycles decode is running system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 282 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst +system.cpu.decode.DecodedInsts 11562 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 472 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 282 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7370 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 627 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1916 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 1569 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11201 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1508 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 9631 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18130 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18104 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 4633 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 27 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 361 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2014 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1832 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 10320 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9105 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 75 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4184 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3348 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12714 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.716140 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.547958 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9591 75.44% 75.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 944 7.42% 82.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 633 4.98% 87.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 463 3.64% 91.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 426 3.35% 94.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 301 2.37% 97.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 240 1.89% 99.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 71 0.56% 99.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 45 0.35% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12714 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 11 4.37% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.37% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 122 48.41% 52.78% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 119 47.22% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5535 60.79% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1910 20.98% 81.79% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1658 18.21% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9108 # Type of FU issued -system.cpu.iq.rate 0.241489 # Inst issue rate -system.cpu.iq.fu_busy_cnt 251 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9105 # Type of FU issued +system.cpu.iq.rate 0.226476 # Inst issue rate +system.cpu.iq.fu_busy_cnt 252 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.027677 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31189 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14543 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8271 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9323 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 80 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1053 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 786 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 282 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 870 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10383 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2014 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1832 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 12 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 62 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 345 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8701 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1776 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3329 # number of memory reference insts executed -system.cpu.iew.exec_branches 1361 # Number of branches executed +system.cpu.iew.exec_refs 3330 # number of memory reference insts executed +system.cpu.iew.exec_branches 1363 # Number of branches executed system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.230724 # Inst execution rate -system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8300 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4483 # num instructions producing a value -system.cpu.iew.wb_consumers 7102 # num instructions consuming a value +system.cpu.iew.exec_rate 0.216427 # Inst execution rate +system.cpu.iew.wb_sent 8428 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8298 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4465 # num instructions producing a value +system.cpu.iew.wb_consumers 7078 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back +system.cpu.iew.wb_rate 0.206403 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.630828 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4593 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11592 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.499655 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.370216 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 276 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12003 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.482546 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.346027 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9439 81.43% 81.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 839 7.24% 88.66% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 524 4.52% 93.18% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9841 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 848 7.06% 89.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 522 4.35% 93.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 225 1.87% 95.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.40% 96.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 120 1.00% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 110 0.92% 98.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 59 0.49% 99.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 110 0.92% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11592 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12003 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -555,61 +555,61 @@ system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 5792 # Class of committed instruction -system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 110 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21860 # The number of ROB reads -system.cpu.rob.rob_writes 21470 # The number of ROB writes -system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22278 # The number of ROB reads +system.cpu.rob.rob_writes 21482 # The number of ROB writes +system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27489 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction -system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads -system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13744 # number of integer regfile reads -system.cpu.int_regfile_writes 7176 # number of integer regfile writes +system.cpu.cpi 6.941126 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.941126 # CPI: Total CPI of All Threads +system.cpu.ipc 0.144069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.144069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13740 # number of integer regfile reads +system.cpu.int_regfile_writes 7173 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 63.843132 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2276 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 22.313725 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 63.843132 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.015587 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.015587 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits -system.cpu.dcache.overall_hits::total 2261 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses -system.cpu.dcache.overall_misses::total 452 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles +system.cpu.dcache.ReadReq_hits::cpu.data 1556 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1556 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 720 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 720 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2276 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2276 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2276 # number of overall hits +system.cpu.dcache.overall_hits::total 2276 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 111 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 111 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 326 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 326 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses +system.cpu.dcache.overall_misses::total 437 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8814500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8814500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 30924496 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 30924496 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 39738996 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 39738996 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 39738996 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 39738996 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -618,38 +618,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2713 # system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.066587 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.066587 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.311663 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.311663 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.161076 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.161076 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.161076 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.161076 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79409.909910 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79409.909910 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 94860.417178 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 94860.417178 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 90935.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 90935.917620 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 90935.917620 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 623 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 103.833333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 56 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 335 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 335 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 335 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 335 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -658,14 +658,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4529750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4529750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4417498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4417498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8947248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8947248 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8947248 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8947248 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -674,119 +674,119 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 82359.090909 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 82359.090909 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 93989.319149 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 93989.319149 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87718.117647 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87718.117647 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 169.362964 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1389 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 3.979943 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 169.362964 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.082697 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.082697 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4007 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits -system.cpu.icache.overall_hits::total 1391 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses -system.cpu.icache.overall_misses::total 438 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 29787250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 29787250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 29787250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 4005 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4005 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1389 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1389 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1389 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1389 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1389 # number of overall hits +system.cpu.icache.overall_hits::total 1389 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 439 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 439 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 439 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 439 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 439 # number of overall misses +system.cpu.icache.overall_misses::total 439 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31975250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31975250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31975250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31975250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31975250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31975250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1828 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1828 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1828 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1828 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1828 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.240153 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.240153 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.240153 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.240153 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.240153 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.240153 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72836.560364 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 72836.560364 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 72836.560364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 72836.560364 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 72836.560364 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 487 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 97.400000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 89 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 89 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 89 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 89 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 89 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24058750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 24058750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24058750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 24058750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24058750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191361 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.191361 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.191361 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26127750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26127750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26127750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26127750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26127750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26127750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191466 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.191466 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191466 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.191466 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74650.714286 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74650.714286 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74650.714286 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 74650.714286 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 201.157905 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 199.954316 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 169.317933 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.839972 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005167 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000972 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006139 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.205981 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.748335 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000969 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006102 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 199 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 198 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses @@ -810,17 +810,17 @@ system.cpu.l2cache.demand_misses::total 445 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 445 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23649250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4137750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27787000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3745250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3745250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 23649250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 31532250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 23649250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 31532250 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25715250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4463750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 30179000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4367500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4367500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 25715250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8831250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 34546500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 25715250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8831250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 34546500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) @@ -843,17 +843,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984513 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68747.819767 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76625 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 69816.582915 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79686.170213 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79686.170213 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 70858.988764 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74753.633721 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 82662.037037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75826.633166 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92925.531915 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92925.531915 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 77632.584270 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74753.633721 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87438.118812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 77632.584270 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -873,17 +873,17 @@ system.cpu.l2cache.demand_mshr_misses::total 445 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19325250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3474750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22800000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19325250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6644000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25969250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19325250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6644000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25969250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21441250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25233500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3785500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3785500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21441250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7577750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 29019000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21441250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7577750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 29019000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses @@ -895,17 +895,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62329.215116 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70226.851852 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63400.753769 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80542.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80542.553191 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62329.215116 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75027.227723 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65211.235955 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution @@ -930,11 +930,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 589250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 165750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 397 # Transaction distribution system.membus.trans_dist::ReadResp 397 # Transaction distribution system.membus.trans_dist::ReadExReq 47 # Transaction distribution @@ -954,9 +954,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 444 # Request fanout histogram -system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 22.1 # Layer utilization (%) +system.membus.reqLayer0.occupancy 555000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2341000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 11.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt index 52edf7aee..f6a7e842c 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27800000 # Number of ticks simulated -final_tick 27800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 27800500 # Number of ticks simulated +final_tick 27800500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 583909 # Simulator instruction rate (inst/s) -host_op_rate 583078 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3038583452 # Simulator tick rate (ticks/s) -host_mem_usage 285748 # Number of bytes of host memory used +host_inst_rate 510787 # Simulator instruction rate (inst/s) +host_op_rate 510102 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2658808340 # Simulator tick rate (ticks/s) +host_mem_usage 289420 # Number of bytes of host memory used host_seconds 0.01 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -21,40 +21,17 @@ system.physmem.bytes_inst_read::total 16320 # Nu system.physmem.num_reads::cpu.inst 255 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 389 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 587050360 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 308489209 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 895539568 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 587050360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 587050360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 587050360 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 308489209 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 895539568 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 308 # Transaction distribution -system.membus.trans_dist::ReadResp 308 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 389 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 389 # Request fanout histogram -system.membus.reqLayer0.occupancy 389000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3501000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.6 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 587039801 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 308483660 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 895523462 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 587039801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 587039801 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 587039801 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 308483660 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 895523462 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 55600 # number of cpu cycles simulated +system.cpu.numCycles 55601 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5327 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 1401 # nu system.cpu.num_load_insts 723 # Number of load instructions system.cpu.num_store_insts 678 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 55599.998000 # Number of busy cycles +system.cpu.num_busy_cycles 55600.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1121 # Number of branches fetched @@ -112,15 +89,119 @@ system.cpu.op_class::MemWrite 678 12.63% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 5370 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 82.114550 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 82.114550 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020047 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits +system.cpu.dcache.overall_hits::total 1253 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses +system.cpu.dcache.overall_misses::total 135 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2847000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4333500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4333500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7180500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7180500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52722.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52722.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53188.888889 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53188.888889 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 117.043638 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 117.036911 # Cycle average of tags in use system.cpu.icache.tags.total_refs 5114 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 257 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 19.898833 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 117.043638 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.057150 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.057150 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 117.036911 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.057147 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.057147 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 148 # Occupied blocks per task id @@ -139,12 +220,12 @@ system.cpu.icache.demand_misses::cpu.inst 257 # n system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses system.cpu.icache.overall_misses::total 257 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14051000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14051000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14051000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14051000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14051000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 14051500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 14051500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 14051500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 14051500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 14051500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14051500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 5371 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 5371 # number of demand (read+write) accesses @@ -157,12 +238,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.047850 system.cpu.icache.demand_miss_rate::total 0.047850 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.047850 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.047850 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54673.151751 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54673.151751 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54673.151751 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54673.151751 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54675.097276 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54675.097276 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54675.097276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54675.097276 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54675.097276 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,33 +258,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 257 system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 13537000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 13537000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13537000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 13537000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 13666000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 13666000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13666000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 13666000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.047850 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.047850 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.047850 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.047850 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52673.151751 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52673.151751 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53175.097276 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53175.097276 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53175.097276 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53175.097276 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 142.183999 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 142.175920 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.009740 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.519250 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 25.664749 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 116.512586 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 25.663334 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003556 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000783 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004339 # Average percentage of cache occupancy @@ -233,17 +314,17 @@ system.cpu.l2cache.demand_misses::total 389 # nu system.cpu.l2cache.overall_misses::cpu.inst 255 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 389 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13260000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 16016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4212000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13260000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20228000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13260000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20228000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13388000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 16170500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4252500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13388000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20423000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13388000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20423000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 257 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 311 # number of ReadReq accesses(hits+misses) @@ -266,17 +347,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992347 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992218 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992347 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.960784 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.623377 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.285347 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.960784 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.285347 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -296,17 +377,17 @@ system.cpu.l2cache.demand_mshr_misses::total 389 system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10327500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12474000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3280500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10327500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15754500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10327500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15754500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.990354 # mshr miss rate for ReadReq accesses @@ -318,122 +399,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992347 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992347 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.118455 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 9.281481 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.118455 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020048 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 661 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 661 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits -system.cpu.dcache.overall_hits::total 1253 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 54 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 54 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses -system.cpu.dcache.overall_misses::total 135 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2928000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2928000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4455000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4455000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7383000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7383000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7383000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.075524 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.120357 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097262 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097262 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097262 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097262 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54222.222222 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54222.222222 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54688.888889 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54688.888889 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2820000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4293000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7113000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52222.222222 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 52688.888889 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 311 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution @@ -462,5 +439,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 385500 # La system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 308 # Transaction distribution +system.membus.trans_dist::ReadResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 81 # Transaction distribution +system.membus.trans_dist::ReadExResp 81 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 778 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24896 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 389 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 389 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 389 # Request fanout histogram +system.membus.reqLayer0.occupancy 389500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 1945500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 7.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 3b4d7b677..8ea066b3b 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19678000 # Number of ticks simulated -final_tick 19678000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000021 # Number of seconds simulated +sim_ticks 21143500 # Number of ticks simulated +final_tick 21143500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46918 # Simulator instruction rate (inst/s) -host_op_rate 84992 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171550123 # Simulator tick rate (ticks/s) -host_mem_usage 309548 # Number of bytes of host memory used +host_inst_rate 49814 # Simulator instruction rate (inst/s) +host_op_rate 90238 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 195722405 # Simulator tick rate (ticks/s) +host_mem_usage 309420 # Number of bytes of host memory used host_seconds 0.11 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 17600 # Nu system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 894399837 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 458583189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1352983027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 894399837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 894399837 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 894399837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 458583189 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1352983027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 832407123 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 426797834 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1259204957 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 832407123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 832407123 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 832407123 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 426797834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1259204957 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 417 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 417 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 19629500 # Total gap between requests +system.physmem.totGap 21095000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 244 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see @@ -186,308 +186,310 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 98 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 242.285714 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 158.475642 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 257.521253 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 36 36.73% 36.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 30 30.61% 67.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 13 13.27% 80.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 6 6.12% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 6.12% 92.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 4 4.08% 96.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 3 3.06% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 98 # Bytes accessed per row activation -system.physmem.totQLat 4347000 # Total ticks spent queuing -system.physmem.totMemAccLat 12165750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 100 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 237.440000 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 159.807528 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 245.488436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 35 35.00% 35.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 31 31.00% 66.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 16 16.00% 82.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 6 6.00% 88.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 2.00% 90.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 3.00% 93.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 2.00% 95.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1 1.00% 96.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4 4.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 100 # Bytes accessed per row activation +system.physmem.totQLat 5105750 # Total ticks spent queuing +system.physmem.totMemAccLat 12924500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2085000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10424.46 # Average queueing delay per DRAM burst +system.physmem.avgQLat 12244.00 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29174.46 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1356.24 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30994.00 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1262.23 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1356.24 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1262.23 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.60 # Data bus utilization in percentage -system.physmem.busUtilRead 10.60 # Data bus utilization in percentage for reads +system.physmem.busUtil 9.86 # Data bus utilization in percentage +system.physmem.busUtilRead 9.86 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.68 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 309 # Number of row buffer hits during reads +system.physmem.readRowHits 307 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 74.10 # Row buffer hit rate for reads +system.physmem.readRowHitRate 73.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47073.14 # Average gap between requests -system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 219240 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 119625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1084200 # Energy for read commands per rank (pJ) +system.physmem.avgGap 50587.53 # Average gap between requests +system.physmem.pageHitRate 73.62 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 936000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 31500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13267770 # Total energy per rank (pJ) -system.physmem_0.averagePower 837.810088 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11000 # Time in different power states +system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 13058475 # Total energy per rank (pJ) +system.physmem_0.averagePower 824.789199 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15318250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 446040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 243375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1567800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 438480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 239250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 1513200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10701180 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 112500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 14088015 # Total energy per rank (pJ) -system.physmem_1.averagePower 889.816201 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 882750 # Time in different power states +system.physmem_1.actBackEnergy 10696905 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 116250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 14021205 # Total energy per rank (pJ) +system.physmem_1.averagePower 885.596400 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 102500 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 15230750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 15223750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 3423 # Number of BP lookups -system.cpu.branchPred.condPredicted 3423 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 535 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2544 # Number of BTB lookups -system.cpu.branchPred.BTBHits 864 # Number of BTB hits +system.cpu.branchPred.lookups 3414 # Number of BP lookups +system.cpu.branchPred.condPredicted 3414 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 534 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2533 # Number of BTB lookups +system.cpu.branchPred.BTBHits 863 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 33.962264 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 34.070272 # BTB Hit Percentage system.cpu.branchPred.usedRAS 247 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 76 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 39357 # number of cpu cycles simulated +system.cpu.numCycles 42288 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 10915 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15528 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3423 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1111 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9222 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1203 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 54 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1088 # Number of stall cycles due to pending traps +system.cpu.fetch.icacheStallCycles 12291 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15496 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3414 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1110 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9718 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1201 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 55 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 1161 # Number of stall cycles due to pending traps system.cpu.fetch.PendingQuiesceStallCycles 13 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.CacheLines 2168 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 278 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.270406 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.764504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2164 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 23838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.164108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.669642 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 17618 80.47% 80.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 236 1.08% 81.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 174 0.79% 82.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 259 1.18% 83.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 208 0.95% 84.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 227 1.04% 85.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 339 1.55% 87.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 205 0.94% 88.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2627 12.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 19573 82.11% 82.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 236 0.99% 83.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 173 0.73% 83.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 257 1.08% 84.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 208 0.87% 85.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 228 0.96% 86.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 337 1.41% 88.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 205 0.86% 89.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2621 11.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 21893 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.086973 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.394542 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 10660 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6840 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3336 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 456 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 601 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 25755 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 601 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 10929 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2194 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 719 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3480 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 3970 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24219 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 23838 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080732 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.366440 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12043 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7408 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3332 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 455 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 600 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25703 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 600 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 12311 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2293 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 795 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3474 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4365 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 24179 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 93 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 3820 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 27591 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 59364 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 33558 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 4214 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 27545 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 59275 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 33508 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 16528 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 16482 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 29 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 1503 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2441 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1612 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 1507 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1611 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21443 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 21419 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17897 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11052 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16525 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 17882 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 79 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11007 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16508 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 21893 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.817476 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.773238 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 23838 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.750147 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.712551 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 16772 76.61% 76.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1137 5.19% 81.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 886 4.05% 85.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 636 2.91% 88.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 833 3.80% 92.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 590 2.69% 95.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 599 2.74% 97.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 316 1.44% 99.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 124 0.57% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18713 78.50% 78.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1142 4.79% 83.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 888 3.73% 87.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 640 2.68% 89.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 832 3.49% 93.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 584 2.45% 95.64% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 601 2.52% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 314 1.32% 99.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 124 0.52% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 21893 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 23838 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 174 77.68% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 31 13.84% 91.52% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 8.48% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 173 77.58% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 77.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 31 13.90% 91.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 19 8.52% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14382 80.36% 80.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.40% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.44% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2122 11.86% 92.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14368 80.35% 80.37% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.02% 80.39% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 7 0.04% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2121 11.86% 92.29% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1379 7.71% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17897 # Type of FU issued -system.cpu.iq.rate 0.454735 # Inst issue rate -system.cpu.iq.fu_busy_cnt 224 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.012516 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 57983 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32531 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16370 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17882 # Type of FU issued +system.cpu.iq.rate 0.422862 # Inst issue rate +system.cpu.iq.fu_busy_cnt 223 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.012471 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 59896 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32462 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16353 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18114 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18098 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 228 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 235 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1388 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1385 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 11 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 677 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 676 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 601 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1862 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21468 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 600 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1925 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 68 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21444 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 32 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2441 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1612 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1611 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 46 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 60 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 16 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 125 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 570 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 695 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16926 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1969 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 971 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 569 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 694 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 16910 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1967 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 972 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3251 # number of memory reference insts executed -system.cpu.iew.exec_branches 1662 # Number of branches executed +system.cpu.iew.exec_refs 3249 # number of memory reference insts executed +system.cpu.iew.exec_branches 1660 # Number of branches executed system.cpu.iew.exec_stores 1282 # Number of stores executed -system.cpu.iew.exec_rate 0.430063 # Inst execution rate -system.cpu.iew.wb_sent 16636 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16374 # cumulative count of insts written-back -system.cpu.iew.wb_producers 11006 # num instructions producing a value -system.cpu.iew.wb_consumers 17135 # num instructions consuming a value +system.cpu.iew.exec_rate 0.399877 # Inst execution rate +system.cpu.iew.wb_sent 16617 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16357 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10994 # num instructions producing a value +system.cpu.iew.wb_consumers 17115 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.416038 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.642311 # average fanout of values written-back +system.cpu.iew.wb_rate 0.386800 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.642361 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 11720 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11696 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 588 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 19924 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.489209 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.394281 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 587 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 21874 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.445598 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.336765 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16684 83.74% 83.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1003 5.03% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 547 2.75% 91.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 737 3.70% 95.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 365 1.83% 97.05% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 142 0.71% 97.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 113 0.57% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.37% 98.70% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 260 1.30% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 18628 85.16% 85.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1010 4.62% 89.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 544 2.49% 92.26% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 738 3.37% 95.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 369 1.69% 97.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 141 0.64% 97.97% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 113 0.52% 98.49% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 72 0.33% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 259 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 19924 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 21874 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -533,102 +535,102 @@ system.cpu.commit.op_class_0::MemWrite 935 9.59% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 9747 # Class of committed instruction -system.cpu.commit.bw_lim_events 260 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 259 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 41131 # The number of ROB reads -system.cpu.rob.rob_writes 44929 # The number of ROB writes -system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17464 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 43058 # The number of ROB reads +system.cpu.rob.rob_writes 44876 # The number of ROB writes +system.cpu.timesIdled 157 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18450 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.315428 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.315428 # CPI: Total CPI of All Threads -system.cpu.ipc 0.136697 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.136697 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 21341 # number of integer regfile reads -system.cpu.int_regfile_writes 13120 # number of integer regfile writes +system.cpu.cpi 7.860223 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.860223 # CPI: Total CPI of All Threads +system.cpu.ipc 0.127223 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.127223 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 21328 # number of integer regfile reads +system.cpu.int_regfile_writes 13105 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.cc_regfile_reads 8069 # number of cc regfile reads +system.cpu.cc_regfile_reads 8064 # number of cc regfile reads system.cpu.cc_regfile_writes 5036 # number of cc regfile writes -system.cpu.misc_regfile_reads 7491 # number of misc regfile reads +system.cpu.misc_regfile_reads 7485 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.331185 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2400 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 82.313704 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 17.021277 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 16.971631 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.331185 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020100 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020100 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 82.313704 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.020096 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.020096 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5369 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5369 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1543 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1543 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 5351 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5351 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1536 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1536 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 857 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 857 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits -system.cpu.dcache.overall_hits::total 2400 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 136 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 136 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits +system.cpu.dcache.overall_hits::total 2393 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 134 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 134 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 78 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 78 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 214 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 214 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 214 # number of overall misses -system.cpu.dcache.overall_misses::total 214 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9815500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9815500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5771000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5771000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15586500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15586500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15586500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1679 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1679 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 212 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 212 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 212 # number of overall misses +system.cpu.dcache.overall_misses::total 212 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11119000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11119000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 6761250 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 6761250 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17880250 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17880250 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17880250 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17880250 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1670 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081001 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.081001 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2605 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2605 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2605 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2605 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080240 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.080240 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083422 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.083422 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.081867 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.081867 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.081867 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.081867 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72172.794118 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 72172.794118 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73987.179487 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 73987.179487 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 72834.112150 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 72834.112150 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 201 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.081382 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081382 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081382 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081382 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 82977.611940 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 82977.611940 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 86682.692308 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 86682.692308 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 84340.801887 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 84340.801887 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 84340.801887 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 40.200000 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 72 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 72 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 70 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 70 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 70 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 70 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 78 # number of WriteReq MSHR misses @@ -637,82 +639,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5009500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5588000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10597500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10597500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038118 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038118 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5695500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5695500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6612750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6612750 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12308250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12308250 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12308250 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12308250 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.038323 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.038323 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083422 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083422 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054323 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054323 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78273.437500 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71641.025641 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74630.281690 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74630.281690 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.054511 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054511 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.054511 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 88992.187500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 88992.187500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84778.846154 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84778.846154 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 86677.816901 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 86677.816901 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 131.539722 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1800 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 131.513084 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1796 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 276 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.521739 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.507246 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 131.539722 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.064228 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.064228 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 131.513084 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.064215 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.064215 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 276 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 121 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4612 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4612 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1800 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1800 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1800 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1800 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1800 # number of overall hits -system.cpu.icache.overall_hits::total 1800 # number of overall hits +system.cpu.icache.tags.tag_accesses 4604 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4604 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1796 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1796 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1796 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1796 # number of overall hits +system.cpu.icache.overall_hits::total 1796 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses system.cpu.icache.overall_misses::total 368 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25557250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25557250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25557250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25557250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25557250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25557250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2168 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2168 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2168 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2168 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2168 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169742 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.169742 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.169742 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.169742 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.169742 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.169742 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69449.048913 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69449.048913 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69449.048913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69449.048913 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69449.048913 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28645750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28645750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28645750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28645750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28645750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28645750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2164 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2164 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2164 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2164 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2164 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.170055 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.170055 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.170055 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.170055 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.170055 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.170055 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77841.711957 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77841.711957 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77841.711957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77841.711957 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77841.711957 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -733,39 +735,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 276 system.cpu.icache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20059000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20059000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20059000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20059000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20059000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20059000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127306 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.127306 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.127306 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72677.536232 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72677.536232 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72677.536232 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72677.536232 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21933250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 21933250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21933250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 21933250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21933250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 21933250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.127542 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.127542 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.127542 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.127542 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79468.297101 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79468.297101 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79468.297101 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 79468.297101 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 163.220102 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 163.168393 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002959 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.613484 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.606618 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004017 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000965 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.004981 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 131.574096 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.594298 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004015 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.000964 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.004980 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010315 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 3760 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 3760 # Number of data accesses @@ -786,17 +788,17 @@ system.cpu.l2cache.demand_misses::total 417 # nu system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 417 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19772500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4946500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24719000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5510000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5510000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 19772500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10456500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30229000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 19772500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10456500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30229000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21646250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5632500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 27278750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6534750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6534750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21646250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12167250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33813500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21646250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12167250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33813500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 276 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 64 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 340 # number of ReadReq accesses(hits+misses) @@ -819,17 +821,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997608 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996377 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997608 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71900 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77289.062500 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 72917.404130 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70641.025641 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70641.025641 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71900 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 72491.606715 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71900 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73637.323944 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 72491.606715 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78713.636364 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88007.812500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 80468.289086 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83778.846154 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83778.846154 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 81087.529976 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78713.636364 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 85684.859155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 81087.529976 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -849,17 +851,17 @@ system.cpu.l2cache.demand_mshr_misses::total 417 system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 417 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16317000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4156000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20473000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4539500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4539500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16317000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8695500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25012500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16317000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8695500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25012500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18201750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4837000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23038750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5555250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18201750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10392250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 28594000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18201750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10392250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 28594000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997059 # mshr miss rate for ReadReq accesses @@ -871,17 +873,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997608 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996377 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997608 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59334.545455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64937.500000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60392.330383 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58198.717949 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58198.717949 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59334.545455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61235.915493 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59982.014388 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66188.181818 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75578.125000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67960.914454 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71221.153846 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71221.153846 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.181818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73184.859155 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68570.743405 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 340 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution @@ -908,11 +910,11 @@ system.cpu.toL2Bus.snoop_fanout::min_value 3 # system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 462500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 234500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) +system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 471250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) system.membus.trans_dist::ReadReq 339 # Transaction distribution system.membus.trans_dist::ReadResp 338 # Transaction distribution system.membus.trans_dist::ReadExReq 78 # Transaction distribution @@ -934,9 +936,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 417 # Request fanout histogram -system.membus.reqLayer0.occupancy 505000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 3897000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 19.8 # Layer utilization (%) +system.membus.reqLayer0.occupancy 504000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer1.occupancy 2222500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 10.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt index b43d6cab2..2ef89d07d 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 28358000 # Number of ticks simulated -final_tick 28358000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 28358500 # Number of ticks simulated +final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 307468 # Simulator instruction rate (inst/s) -host_op_rate 556583 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1618053178 # Simulator tick rate (ticks/s) -host_mem_usage 302528 # Number of bytes of host memory used +host_inst_rate 312703 # Simulator instruction rate (inst/s) +host_op_rate 566020 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1645401799 # Simulator tick rate (ticks/s) +host_mem_usage 307640 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 5381 # Number of instructions simulated sim_ops 9748 # Number of ops (including micro ops) simulated @@ -21,43 +21,18 @@ system.physmem.bytes_inst_read::total 14528 # Nu system.physmem.num_reads::cpu.inst 227 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 361 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 512306933 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 302419070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 814726003 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 512306933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 512306933 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 512306933 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 302419070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 814726003 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 282 # Transaction distribution -system.membus.trans_dist::ReadResp 282 # Transaction distribution -system.membus.trans_dist::ReadExReq 79 # Transaction distribution -system.membus.trans_dist::ReadExResp 79 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 361 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 361 # Request fanout histogram -system.membus.reqLayer0.occupancy 361000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 3249000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.5 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 512297900 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 302413738 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 814711638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 512297900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 512297900 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 512297900 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 302413738 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 814711638 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 56716 # number of cpu cycles simulated +system.cpu.numCycles 56717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 5381 # Number of instructions committed @@ -78,7 +53,7 @@ system.cpu.num_mem_refs 1988 # nu system.cpu.num_load_insts 1053 # Number of load instructions system.cpu.num_store_insts 935 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 56715.998000 # Number of busy cycles +system.cpu.num_busy_cycles 56716.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 1208 # Number of branches fetched @@ -117,15 +92,119 @@ system.cpu.op_class::MemWrite 935 9.59% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 9748 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 80.793450 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 80.793450 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.019725 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits +system.cpu.dcache.overall_hits::total 1854 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses +system.cpu.dcache.overall_misses::total 134 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2942500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4226500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7169000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7169000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 105.550219 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 105.544338 # Cycle average of tags in use system.cpu.icache.tags.total_refs 6636 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 228 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 29.105263 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 105.550219 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.051538 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.051538 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 105.544338 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.051535 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.051535 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id @@ -144,12 +223,12 @@ system.cpu.icache.demand_misses::cpu.inst 228 # n system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses system.cpu.icache.overall_misses::total 228 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12498000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12498000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12498000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12498000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12498000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12498500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12498500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12498500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12498500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12498500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12498500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 6864 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 6864 # number of demand (read+write) accesses @@ -162,12 +241,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.033217 system.cpu.icache.demand_miss_rate::total 0.033217 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.033217 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.033217 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54815.789474 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54815.789474 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54815.789474 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54815.789474 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54817.982456 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54817.982456 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54817.982456 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54817.982456 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54817.982456 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -182,33 +261,33 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 228 system.cpu.icache.demand_mshr_misses::total 228 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 228 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 228 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12042000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12042000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12042000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12042000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12156500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 12156500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12156500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 12156500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12156500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 12156500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.033217 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.033217 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.033217 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.033217 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52815.789474 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52815.789474 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53317.982456 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53317.982456 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53317.982456 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53317.982456 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 134.034140 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 134.026823 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 282 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.003546 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.558330 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 28.475810 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.552484 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 28.474338 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003221 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000869 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004090 # Average percentage of cache occupancy @@ -235,17 +314,17 @@ system.cpu.l2cache.demand_misses::total 361 # nu system.cpu.l2cache.overall_misses::cpu.inst 227 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 361 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11804000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2860000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14664000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4108000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11804000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6968000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 18772000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11804000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6968000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 18772000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11918000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2887500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14805500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4147500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11918000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7035000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 18953000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11918000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7035000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 18953000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 228 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 283 # number of ReadReq accesses(hits+misses) @@ -268,17 +347,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997238 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995614 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997238 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52502.202643 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.773050 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.385042 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52502.202643 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.385042 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -298,17 +377,17 @@ system.cpu.l2cache.demand_mshr_misses::total 361 system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9193500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2227500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11421000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3199500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3199500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9193500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5427000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14620500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9193500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5427000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14620500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996466 # mshr miss rate for ReadReq accesses @@ -320,122 +399,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997238 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997238 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 80.797237 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1854 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 134 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.835821 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 80.797237 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.019726 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 134 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032715 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4110 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4110 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 998 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 998 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 856 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 856 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1854 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1854 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1854 # number of overall hits -system.cpu.dcache.overall_hits::total 1854 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 55 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 134 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.dcache.overall_misses::total 134 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3025000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3025000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4345000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4345000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7370000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7370000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7370000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1053 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1988 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1988 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1988 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1988 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.084492 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.067404 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.067404 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.067404 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.067404 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 134 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 134 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4187000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7102000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7102000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067404 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067404 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 283 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 79 # Transaction distribution @@ -466,5 +441,30 @@ system.cpu.toL2Bus.respLayer0.occupancy 342000 # La system.cpu.toL2Bus.respLayer0.utilization 1.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 201000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.membus.trans_dist::ReadReq 282 # Transaction distribution +system.membus.trans_dist::ReadResp 282 # Transaction distribution +system.membus.trans_dist::ReadExReq 79 # Transaction distribution +system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 722 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23104 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 361 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 361 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 361 # Request fanout histogram +system.membus.reqLayer0.occupancy 361500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 1805500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 6.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 752a25834..3794759d9 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,61 +1,61 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 23754500 # Number of ticks simulated -final_tick 23754500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000025 # Number of seconds simulated +sim_ticks 25499500 # Number of ticks simulated +final_tick 25499500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70868 # Simulator instruction rate (inst/s) -host_op_rate 70863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 132078042 # Simulator tick rate (ticks/s) -host_mem_usage 294344 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host +host_inst_rate 83845 # Simulator instruction rate (inst/s) +host_op_rate 83838 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167736694 # Simulator tick rate (ticks/s) +host_mem_usage 294000 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 12744 # Number of instructions simulated sim_ops 12744 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 40064 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22336 # Number of bytes read from this memory -system.physmem.bytes_read::total 62400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40064 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40064 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 626 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 349 # Number of read requests responded to by this memory -system.physmem.num_reads::total 975 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1686585700 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 940284999 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2626870698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1686585700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1686585700 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1686585700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 940284999 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2626870698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 975 # Number of read requests accepted +system.physmem.bytes_read::cpu.inst 40704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22144 # Number of bytes read from this memory +system.physmem.bytes_read::total 62848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40704 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40704 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 636 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 346 # Number of read requests responded to by this memory +system.physmem.num_reads::total 982 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1596266593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 868409184 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2464675778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1596266593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1596266593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1596266593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 868409184 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2464675778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 982 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 975 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 982 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 62400 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 62848 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 62400 # Total read bytes from the system interface side +system.physmem.bytesReadSys 62848 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 83 # Per bank write bursts -system.physmem.perBankRdBursts::1 151 # Per bank write bursts -system.physmem.perBankRdBursts::2 78 # Per bank write bursts -system.physmem.perBankRdBursts::3 58 # Per bank write bursts +system.physmem.perBankRdBursts::0 86 # Per bank write bursts +system.physmem.perBankRdBursts::1 152 # Per bank write bursts +system.physmem.perBankRdBursts::2 79 # Per bank write bursts +system.physmem.perBankRdBursts::3 59 # Per bank write bursts system.physmem.perBankRdBursts::4 88 # Per bank write bursts system.physmem.perBankRdBursts::5 49 # Per bank write bursts -system.physmem.perBankRdBursts::6 32 # Per bank write bursts -system.physmem.perBankRdBursts::7 49 # Per bank write bursts -system.physmem.perBankRdBursts::8 41 # Per bank write bursts -system.physmem.perBankRdBursts::9 38 # Per bank write bursts +system.physmem.perBankRdBursts::6 33 # Per bank write bursts +system.physmem.perBankRdBursts::7 50 # Per bank write bursts +system.physmem.perBankRdBursts::8 42 # Per bank write bursts +system.physmem.perBankRdBursts::9 39 # Per bank write bursts system.physmem.perBankRdBursts::10 30 # Per bank write bursts system.physmem.perBankRdBursts::11 34 # Per bank write bursts system.physmem.perBankRdBursts::12 15 # Per bank write bursts -system.physmem.perBankRdBursts::13 122 # Per bank write bursts -system.physmem.perBankRdBursts::14 70 # Per bank write bursts +system.physmem.perBankRdBursts::13 120 # Per bank write bursts +system.physmem.perBankRdBursts::14 69 # Per bank write bursts system.physmem.perBankRdBursts::15 37 # Per bank write bursts system.physmem.perBankWrBursts::0 0 # Per bank write bursts system.physmem.perBankWrBursts::1 0 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 23342000 # Total gap between requests +system.physmem.totGap 25359500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 975 # Read request sizes (log2) +system.physmem.readPktSize::6 982 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,13 +90,13 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 342 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 82 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -186,100 +186,100 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 295.431280 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 188.087836 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 290.004628 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 69 32.70% 32.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 56 26.54% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 25 11.85% 71.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 14 6.64% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 15 7.11% 84.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 9 4.27% 89.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 1.90% 91.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 6 2.84% 93.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 13 6.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation -system.physmem.totQLat 12504500 # Total ticks spent queuing -system.physmem.totMemAccLat 30785750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 4875000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12825.13 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 220 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.836364 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 169.810990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 284.156672 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 81 36.82% 36.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 62 28.18% 65.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 22 10.00% 75.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 14 6.36% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 10 4.55% 85.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 7 3.18% 89.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 6 2.73% 91.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 6 2.73% 94.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 12 5.45% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 220 # Bytes accessed per row activation +system.physmem.totQLat 12877000 # Total ticks spent queuing +system.physmem.totMemAccLat 31289500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 4910000 # Total ticks spent in databus transfers +system.physmem.avgQLat 13113.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 31575.13 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2626.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 31863.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2464.68 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2626.87 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 2464.68 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 20.52 # Data bus utilization in percentage -system.physmem.busUtilRead 20.52 # Data bus utilization in percentage for reads +system.physmem.busUtil 19.26 # Data bus utilization in percentage +system.physmem.busUtilRead 19.26 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 2.40 # Average read queue length when enqueuing +system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 763 # Number of row buffer hits during reads +system.physmem.readRowHits 752 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.26 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23940.51 # Average gap between requests -system.physmem.pageHitRate 78.26 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 899640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 490875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 4578600 # Energy for read commands per rank (pJ) +system.physmem.avgGap 25824.34 # Average gap between requests +system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 929880 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 507375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 4547400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16058610 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 84750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 23638155 # Total energy per rank (pJ) -system.physmem_0.averagePower 1000.821593 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 44000 # Time in different power states +system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 23657895 # Total energy per rank (pJ) +system.physmem_0.averagePower 1001.657370 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 688500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22808500 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 695520 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 379500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 3018600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 15908130 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 216750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 21744180 # Total energy per rank (pJ) -system.physmem_1.averagePower 920.632125 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 278750 # Time in different power states +system.physmem_1.actBackEnergy 15503715 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 591000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 21359100 # Total energy per rank (pJ) +system.physmem_1.averagePower 903.085461 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 888000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22573750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 21996000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 7608 # Number of BP lookups -system.cpu.branchPred.condPredicted 4258 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1618 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 5646 # Number of BTB lookups -system.cpu.branchPred.BTBHits 865 # Number of BTB hits +system.cpu.branchPred.lookups 7477 # Number of BP lookups +system.cpu.branchPred.condPredicted 4177 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1616 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5400 # Number of BTB lookups +system.cpu.branchPred.BTBHits 850 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 15.320581 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1051 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 77 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 15.740741 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1012 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 79 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 5192 # DTB read hits -system.cpu.dtb.read_misses 102 # DTB read misses +system.cpu.dtb.read_hits 4911 # DTB read hits +system.cpu.dtb.read_misses 100 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 5294 # DTB read accesses -system.cpu.dtb.write_hits 2108 # DTB write hits -system.cpu.dtb.write_misses 66 # DTB write misses +system.cpu.dtb.read_accesses 5011 # DTB read accesses +system.cpu.dtb.write_hits 2106 # DTB write hits +system.cpu.dtb.write_misses 69 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2174 # DTB write accesses -system.cpu.dtb.data_hits 7300 # DTB hits -system.cpu.dtb.data_misses 168 # DTB misses +system.cpu.dtb.write_accesses 2175 # DTB write accesses +system.cpu.dtb.data_hits 7017 # DTB hits +system.cpu.dtb.data_misses 169 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 7468 # DTB accesses -system.cpu.itb.fetch_hits 5663 # ITB hits -system.cpu.itb.fetch_misses 57 # ITB misses +system.cpu.dtb.data_accesses 7186 # DTB accesses +system.cpu.itb.fetch_hits 5467 # ITB hits +system.cpu.itb.fetch_misses 60 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5720 # ITB accesses +system.cpu.itb.fetch_accesses 5527 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -294,318 +294,318 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 47510 # number of cpu cycles simulated +system.cpu.numCycles 51000 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1451 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 41889 # Number of instructions fetch has processed -system.cpu.fetch.Branches 7608 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1916 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 11137 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 1416 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 41297 # Number of instructions fetch has processed +system.cpu.fetch.Branches 7477 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1862 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 10878 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1697 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 556 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5663 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 846 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28570 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.466188 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.843743 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.MiscStallCycles 471 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5467 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 803 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.490920 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.868697 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21551 75.43% 75.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 541 1.89% 77.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 402 1.41% 78.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 607 2.12% 80.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 545 1.91% 82.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 439 1.54% 84.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 542 1.90% 86.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 448 1.57% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 3495 12.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20832 75.21% 75.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 522 1.88% 77.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 376 1.36% 78.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 569 2.05% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 524 1.89% 82.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 456 1.65% 84.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 499 1.80% 85.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 422 1.52% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3499 12.63% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28570 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.160135 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.881688 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 37575 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12018 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5449 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 625 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1245 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 719 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 495 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 33794 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 947 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1245 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 38261 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 5449 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1170 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 5378 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 5409 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 31549 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 73 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 407 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 458 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 4425 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 23766 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 39316 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 39298 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 27699 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.146608 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.809745 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 36892 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 11130 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5276 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 643 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1210 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 704 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 509 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 33151 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 887 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1210 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 37566 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 5376 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1365 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5257 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 4377 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 30969 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 146 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 361 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 477 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 3380 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 23374 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 38597 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 38579 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 14626 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 56 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2199 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3120 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1520 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 14234 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 57 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2267 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2994 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1466 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 45 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 25 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2933 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1394 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 11 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.memDep1.insertedLoads 2948 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1410 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 28021 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 23357 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 131 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 14239 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 8472 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28570 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.817536 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.542788 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 27629 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 22900 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 102 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13893 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8231 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 27699 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.826745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.538980 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 19963 69.87% 69.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 2657 9.30% 79.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1959 6.86% 86.03% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1384 4.84% 90.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1325 4.64% 95.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 682 2.39% 97.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 348 1.22% 99.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 184 0.64% 99.76% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 68 0.24% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 19213 69.36% 69.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 2603 9.40% 78.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1960 7.08% 85.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1418 5.12% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1237 4.47% 95.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 696 2.51% 97.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 372 1.34% 99.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 137 0.49% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 63 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28570 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27699 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 22 6.04% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.04% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 263 72.25% 78.30% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 79 21.70% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 27 8.23% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 211 64.33% 72.56% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 90 27.44% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7749 65.04% 65.05% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.06% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.06% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.08% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2973 24.95% 90.03% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1188 9.97% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7493 65.81% 65.83% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.84% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.84% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.85% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2715 23.85% 89.70% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1173 10.30% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 11915 # Type of FU issued +system.cpu.iq.FU_type_0::total 11386 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7559 66.06% 66.08% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.09% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.09% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.11% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2735 23.90% 90.01% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1143 9.99% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7630 66.27% 66.28% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.29% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.29% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.31% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2714 23.57% 89.88% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1165 10.12% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 11442 # Type of FU issued -system.cpu.iq.FU_type::total 23357 0.00% 0.00% # Type of FU issued -system.cpu.iq.rate 0.491623 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 183 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 181 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 364 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.007835 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.007749 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.015584 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75737 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 42325 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_1::total 11514 # Type of FU issued +system.cpu.iq.FU_type::total 22900 0.00% 0.00% # Type of FU issued +system.cpu.iq.rate 0.449020 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 160 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 168 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 328 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.006987 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.007336 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.014323 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 73887 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 41585 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20089 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 23695 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 23202 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 87 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1937 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 655 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1811 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 601 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 426 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 65 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 281 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 75 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1750 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 529 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1765 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 20 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 545 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 346 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1245 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2860 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 601 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 28216 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 318 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 6053 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2914 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 32 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 571 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1210 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 3002 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 780 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 27815 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 312 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5942 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2876 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 747 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 36 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 148 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1270 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1418 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 21922 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2766 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2537 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 5303 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1435 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1217 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1361 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 21491 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2518 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2502 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 5020 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1409 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 71 # number of nop insts executed -system.cpu.iew.exec_nop::1 73 # number of nop insts executed -system.cpu.iew.exec_nop::total 144 # number of nop insts executed -system.cpu.iew.exec_refs::0 3883 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3616 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 7499 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1763 # Number of branches executed -system.cpu.iew.exec_branches::1 1733 # Number of branches executed -system.cpu.iew.exec_branches::total 3496 # Number of branches executed -system.cpu.iew.exec_stores::0 1117 # Number of stores executed -system.cpu.iew.exec_stores::1 1079 # Number of stores executed -system.cpu.iew.exec_stores::total 2196 # Number of stores executed -system.cpu.iew.exec_rate 0.461419 # Inst execution rate -system.cpu.iew.wb_sent::0 10477 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 10192 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 20669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 10260 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 10004 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 20264 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5390 # num instructions producing a value -system.cpu.iew.wb_producers::1 5243 # num instructions producing a value -system.cpu.iew.wb_producers::total 10633 # num instructions producing a value -system.cpu.iew.wb_consumers::0 7128 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6992 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 14120 # num instructions consuming a value +system.cpu.iew.exec_nop::0 69 # number of nop insts executed +system.cpu.iew.exec_nop::1 67 # number of nop insts executed +system.cpu.iew.exec_nop::total 136 # number of nop insts executed +system.cpu.iew.exec_refs::0 3616 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3607 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 7223 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1734 # Number of branches executed +system.cpu.iew.exec_branches::1 1745 # Number of branches executed +system.cpu.iew.exec_branches::total 3479 # Number of branches executed +system.cpu.iew.exec_stores::0 1098 # Number of stores executed +system.cpu.iew.exec_stores::1 1105 # Number of stores executed +system.cpu.iew.exec_stores::total 2203 # Number of stores executed +system.cpu.iew.exec_rate 0.421392 # Inst execution rate +system.cpu.iew.wb_sent::0 10180 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 10330 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 20510 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9974 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 10135 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 20109 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5251 # num instructions producing a value +system.cpu.iew.wb_producers::1 5302 # num instructions producing a value +system.cpu.iew.wb_producers::total 10553 # num instructions producing a value +system.cpu.iew.wb_consumers::0 7044 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 7008 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 14052 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.215955 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.210566 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.426521 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.756173 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.749857 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.753045 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.195569 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.198725 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.394294 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.745457 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.756564 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.750996 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 15441 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 15019 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1167 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28457 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.449028 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.318063 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1130 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 27612 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.462770 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.343029 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23389 82.19% 82.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2450 8.61% 90.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1057 3.71% 94.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 365 1.28% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 316 1.11% 96.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 193 0.68% 97.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 226 0.79% 98.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 154 0.54% 98.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 307 1.08% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22639 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2318 8.39% 90.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1067 3.86% 94.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 382 1.38% 95.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 325 1.18% 96.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 202 0.73% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 208 0.75% 98.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 146 0.53% 98.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 325 1.18% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28457 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 27612 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6389 # Number of instructions committed system.cpu.commit.committedInsts::total 12778 # Number of instructions committed @@ -707,28 +707,28 @@ system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Cl system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_1::total 6389 # Class of committed instruction system.cpu.commit.op_class::total 12778 0.00% 0.00% # Class of committed instruction -system.cpu.commit.bw_lim_events 307 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 325 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 133653 # The number of ROB reads -system.cpu.rob.rob_writes 59305 # The number of ROB writes -system.cpu.timesIdled 412 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 18940 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 130940 # The number of ROB reads +system.cpu.rob.rob_writes 58397 # The number of ROB writes +system.cpu.timesIdled 389 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 23301 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6372 # Number of Instructions Simulated system.cpu.committedInsts::total 12744 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::total 12744 # Number of Ops (including micro ops) Simulated -system.cpu.cpi::0 7.456058 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.456058 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.728029 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.134119 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.134119 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.268238 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 27427 # number of integer regfile reads -system.cpu.int_regfile_writes 15512 # number of integer regfile writes +system.cpu.cpi::0 8.003766 # CPI: Cycles Per Instruction +system.cpu.cpi::1 8.003766 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.001883 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.124941 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.124941 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.249882 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 26966 # number of integer regfile reads +system.cpu.int_regfile_writes 15368 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -736,289 +736,289 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.dcache.tags.replacements::0 0 # number of replacements system.cpu.dcache.tags.replacements::1 0 # number of replacements system.cpu.dcache.tags.replacements::total 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 215.485703 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 5082 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 349 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.561605 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 213.719872 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 5036 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 346 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.554913 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 215.485703 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.052609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.052609 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.085205 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 12575 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 12575 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 4060 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 4060 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 5082 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 5082 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 5082 # number of overall hits -system.cpu.dcache.overall_hits::total 5082 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses -system.cpu.dcache.overall_misses::total 1031 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 22902750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 22902750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 50997162 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 50997162 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 73899912 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 73899912 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 73899912 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 73899912 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 4383 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 4383 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.tags.occ_blocks::cpu.data 213.719872 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.052178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.052178 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 81 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 265 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.084473 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 12454 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 12454 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 4006 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 4006 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1030 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1030 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 5036 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 5036 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 5036 # number of overall hits +system.cpu.dcache.overall_hits::total 5036 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 318 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 318 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 700 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 700 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 1018 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1018 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1018 # number of overall misses +system.cpu.dcache.overall_misses::total 1018 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26557000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26557000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 48843926 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 48843926 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 75400926 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 75400926 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 75400926 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 75400926 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 4324 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 4324 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 6113 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 6113 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 6113 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 6113 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073694 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.073694 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.168657 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.168657 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.168657 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.168657 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70906.346749 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 70906.346749 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72029.889831 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72029.889831 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 71677.897187 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 71677.897187 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 71677.897187 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 5816 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 6054 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 6054 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 6054 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 6054 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073543 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.073543 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.168153 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.168153 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.168153 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.168153 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 83512.578616 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 83512.578616 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69777.037143 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 69777.037143 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 74067.707269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 74067.707269 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 74067.707269 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 5713 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 146 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.835616 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 43.946154 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 119 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 119 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 563 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 563 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 682 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 682 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 682 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 682 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 349 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 349 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16652250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 16652250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883990 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28536240 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 28536240 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28536240 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 28536240 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046543 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046543 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.057091 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057091 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.057091 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81628.676471 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81628.676471 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81958.551724 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81958.551724 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 81765.730659 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 81765.730659 # average overall mshr miss latency +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 116 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 556 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 556 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 672 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 672 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 672 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 672 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 346 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18304750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18304750 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11840493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11840493 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30145243 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30145243 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30145243 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30145243 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.046716 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.046716 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.057152 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.057152 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.057152 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90617.574257 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90617.574257 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82225.645833 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82225.645833 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87124.979769 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87124.979769 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements::0 7 # number of replacements +system.cpu.icache.tags.replacements::0 8 # number of replacements system.cpu.icache.tags.replacements::1 0 # number of replacements -system.cpu.icache.tags.replacements::total 7 # number of replacements -system.cpu.icache.tags.tagsinuse 320.653868 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4726 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 7.525478 # Average number of references to valid blocks. +system.cpu.icache.tags.replacements::total 8 # number of replacements +system.cpu.icache.tags.tagsinuse 322.759154 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4537 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 7.111285 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 320.653868 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.156569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.156569 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 11936 # Number of tag accesses -system.cpu.icache.tags.data_accesses 11936 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4726 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4726 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4726 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4726 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4726 # number of overall hits -system.cpu.icache.overall_hits::total 4726 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 928 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 928 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 928 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 928 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 928 # number of overall misses -system.cpu.icache.overall_misses::total 928 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 64563245 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 64563245 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 64563245 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 64563245 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 64563245 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 64563245 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5654 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5654 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5654 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5654 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5654 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5654 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.164132 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.164132 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.164132 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.164132 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.164132 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.164132 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69572.462284 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69572.462284 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69572.462284 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69572.462284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69572.462284 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69572.462284 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 4138 # number of cycles access was blocked +system.cpu.icache.tags.occ_blocks::cpu.inst 322.759154 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.157597 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.157597 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 630 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 243 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 387 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.307617 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11558 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11558 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4537 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4537 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4537 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4537 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4537 # number of overall hits +system.cpu.icache.overall_hits::total 4537 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 923 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 923 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 923 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 923 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 923 # number of overall misses +system.cpu.icache.overall_misses::total 923 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 70921745 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 70921745 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 70921745 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 70921745 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 70921745 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 70921745 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5460 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5460 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5460 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5460 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5460 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169048 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.169048 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.169048 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.169048 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.169048 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.169048 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76838.293608 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 76838.293608 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 76838.293608 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 76838.293608 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 76838.293608 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 76838.293608 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3978 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 83 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 87 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 49.855422 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 45.724138 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 300 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 300 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 300 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 300 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46837996 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 46837996 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46837996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 46837996 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46837996 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 46837996 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.111072 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.111072 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111072 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.111072 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74582.796178 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74582.796178 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74582.796178 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 74582.796178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74582.796178 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 74582.796178 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 285 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 285 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 285 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 285 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 285 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 51664496 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 51664496 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 51664496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 51664496 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 51664496 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 51664496 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116850 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116850 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116850 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.116850 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.116850 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.116850 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80978.833856 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80978.833856 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80978.833856 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 80978.833856 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80978.833856 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 80978.833856 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements::0 0 # number of replacements system.cpu.l2cache.tags.replacements::1 0 # number of replacements system.cpu.l2cache.tags.replacements::total 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 443.003584 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 444.038251 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 830 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.002410 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 838 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.002387 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 321.314753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 121.688831 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009806 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.003714 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.013519 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 830 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 495 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025330 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses +system.cpu.l2cache.tags.occ_blocks::cpu.inst 323.497640 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 120.540612 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009872 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.003679 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.013551 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 838 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 301 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 537 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.025574 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 8854 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 8854 # Number of data accesses system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 626 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 830 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 626 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 349 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 626 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 349 # number of overall misses -system.cpu.l2cache.overall_misses::total 975 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 46183500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 16439250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 62622750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11732750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11732750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 46183500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 28172000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 74355500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 46183500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 28172000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 74355500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 628 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 832 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 628 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 349 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 977 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 628 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 349 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses::cpu.inst 636 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 202 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 838 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 144 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 144 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 636 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 346 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 982 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 636 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 346 # number of overall misses +system.cpu.l2cache.overall_misses::total 982 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 51000750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 18093750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 69094500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11692500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11692500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 51000750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 29786250 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 80787000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 51000750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 29786250 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 80787000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 202 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 840 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 144 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 144 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 346 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 984 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 346 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996865 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997596 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997619 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996865 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997967 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996865 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73775.559105 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80584.558824 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75449.096386 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80915.517241 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80915.517241 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73775.559105 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80722.063037 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 76262.051282 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73775.559105 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80722.063037 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 76262.051282 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997967 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 80189.858491 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89573.019802 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 82451.670644 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81197.916667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81197.916667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80189.858491 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86087.427746 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 82267.820774 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80189.858491 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86087.427746 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 82267.820774 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1027,101 +1027,101 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 830 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 349 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 349 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 38371500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13925750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 52297250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9959250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 38371500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23885000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 62256500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 38371500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23885000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 62256500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 636 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 838 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 144 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 636 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 346 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 982 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 636 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 346 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 982 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 43045250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15573250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 58618500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9895500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9895500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43045250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25468750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 68514000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43045250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25468750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 68514000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997596 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997619 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997967 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996865 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61296.325879 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68263.480392 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63008.734940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68684.482759 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68684.482759 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61296.325879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68438.395415 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63852.820513 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61296.325879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68438.395415 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63852.820513 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997967 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67681.210692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77095.297030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69950.477327 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68718.750000 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68718.750000 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67681.210692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73609.104046 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69769.857434 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67681.210692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73609.104046 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69769.857434 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 832 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1256 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 698 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 1954 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40192 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadReq 840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 840 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 144 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 144 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 692 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1968 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22144 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 62976 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 977 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 984 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 977 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 984 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 977 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 488500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 1032000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 4.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 556000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 984 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 492000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 1076750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 4.2 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 574250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 2.3 # Layer utilization (%) -system.membus.trans_dist::ReadReq 830 # Transaction distribution -system.membus.trans_dist::ReadResp 830 # Transaction distribution -system.membus.trans_dist::ReadExReq 145 # Transaction distribution -system.membus.trans_dist::ReadExResp 145 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1950 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62400 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadReq 838 # Transaction distribution +system.membus.trans_dist::ReadResp 838 # Transaction distribution +system.membus.trans_dist::ReadExReq 144 # Transaction distribution +system.membus.trans_dist::ReadExResp 144 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1964 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 62848 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 62848 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 975 # Request fanout histogram +system.membus.snoop_fanout::samples 982 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 975 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 982 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 975 # Request fanout histogram -system.membus.reqLayer0.occupancy 1213500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 5.1 # Layer utilization (%) -system.membus.respLayer1.occupancy 9051500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 38.1 # Layer utilization (%) +system.membus.snoop_fanout::total 982 # Request fanout histogram +system.membus.reqLayer0.occupancy 1219500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 4.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 5224000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 20.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index b851aeb29..fe03e9faf 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25944000 # Number of ticks simulated -final_tick 25944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000027 # Number of seconds simulated +sim_ticks 27482500 # Number of ticks simulated +final_tick 27482500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95549 # Simulator instruction rate (inst/s) -host_op_rate 95539 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 171686089 # Simulator tick rate (ticks/s) -host_mem_usage 292480 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 86365 # Simulator instruction rate (inst/s) +host_op_rate 86358 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 164391633 # Simulator tick rate (ticks/s) +host_mem_usage 291648 # Number of bytes of host memory used +host_seconds 0.17 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 22016 # Nu system.physmem.num_reads::cpu.inst 344 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 148 # Number of read requests responded to by this memory system.physmem.num_reads::total 492 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 848596978 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 365094049 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1213691027 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 848596978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 848596978 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 848596978 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 365094049 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1213691027 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 801091604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 344655690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1145747294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 801091604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 801091604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 801091604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 344655690 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1145747294 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 492 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 25892500 # Total gap between requests +system.physmem.totGap 27431000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -90,9 +90,9 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 53 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 10 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -186,307 +186,307 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 72 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 404.444444 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 264.526762 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 350.678412 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 16.67% 16.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 24 33.33% 50.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 7 9.72% 59.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 5.56% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 5.56% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.17% 75.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 8.33% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.39% 84.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 15.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 72 # Bytes accessed per row activation -system.physmem.totQLat 2786000 # Total ticks spent queuing -system.physmem.totMemAccLat 12011000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 71 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 404.732394 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 270.110571 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.824701 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 13 18.31% 18.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18 25.35% 43.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 12.68% 56.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 7 9.86% 66.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 7 9.86% 76.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1 1.41% 77.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 4 5.63% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 2.82% 85.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 14.08% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 71 # Bytes accessed per row activation +system.physmem.totQLat 3613750 # Total ticks spent queuing +system.physmem.totMemAccLat 12838750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers -system.physmem.avgQLat 5662.60 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7345.02 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24412.60 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1213.69 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26095.02 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1145.75 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1213.69 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1145.75 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.48 # Data bus utilization in percentage -system.physmem.busUtilRead 9.48 # Data bus utilization in percentage for reads +system.physmem.busUtil 8.95 # Data bus utilization in percentage +system.physmem.busUtilRead 8.95 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.53 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 411 # Number of row buffer hits during reads +system.physmem.readRowHits 412 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 52627.03 # Average gap between requests -system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2106000 # Energy for read commands per rank (pJ) +system.physmem.avgGap 55754.07 # Average gap between requests +system.physmem.pageHitRate 83.74 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 302400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2059200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 16044930 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 96750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20252445 # Total energy per rank (pJ) -system.physmem_0.averagePower 857.473194 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 279250 # Time in different power states +system.physmem_0.actBackEnergy 15743115 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 361500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 20156895 # Total energy per rank (pJ) +system.physmem_0.averagePower 853.427679 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 520250 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 22761250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 22332250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 226800 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 123750 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 1318200 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 14873580 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1124250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19192260 # Total energy per rank (pJ) -system.physmem_1.averagePower 812.585763 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2246250 # Time in different power states +system.physmem_1.actBackEnergy 15564420 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 518250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 19277100 # Total energy per rank (pJ) +system.physmem_1.averagePower 816.177825 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2637000 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 21062250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 22058500 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 8578 # Number of BP lookups -system.cpu.branchPred.condPredicted 5479 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1058 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 6011 # Number of BTB lookups -system.cpu.branchPred.BTBHits 3046 # Number of BTB hits +system.cpu.branchPred.lookups 8538 # Number of BP lookups +system.cpu.branchPred.condPredicted 5461 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1059 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 5976 # Number of BTB lookups +system.cpu.branchPred.BTBHits 3053 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 50.673765 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 607 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 51.087684 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 609 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 51889 # number of cpu cycles simulated +system.cpu.numCycles 54966 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 14152 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 40300 # Number of instructions fetch has processed -system.cpu.fetch.Branches 8578 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3653 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 16187 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.icacheStallCycles 14246 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 40057 # Number of instructions fetch has processed +system.cpu.fetch.Branches 8538 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3662 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 15957 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2311 # Number of cycles fetch has spent squashing system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 1000 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 6453 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 567 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.239619 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.385650 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 6438 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 569 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.235488 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.378208 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 20972 64.51% 64.51% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 5490 16.89% 81.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 661 2.03% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 508 1.56% 84.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 826 2.54% 87.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 909 2.80% 90.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 334 1.03% 91.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 369 1.14% 92.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2441 7.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20898 64.46% 64.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 5494 16.95% 81.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 685 2.11% 83.51% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 505 1.56% 85.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 819 2.53% 87.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 909 2.80% 90.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 334 1.03% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 371 1.14% 92.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2407 7.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32510 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.165314 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.776658 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 11331 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 12526 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 6844 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 654 # Number of cycles decode is unblocking +system.cpu.fetch.rateDist::total 32422 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.155332 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.728760 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 11347 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 12433 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 6847 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 640 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1155 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30561 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 30502 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1155 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 11931 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1436 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 10087 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 6918 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 983 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27740 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full -system.cpu.rename.SQFullEvents 585 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 25096 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51799 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 42923 # Number of integer rename lookups +system.cpu.rename.IdleCycles 11955 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 1146 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 9859 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 6898 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1409 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27684 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.SQFullEvents 1012 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 25054 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51692 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 42838 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 11277 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 768 # count of serializing insts renamed +system.cpu.rename.UndoneMaps 11235 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 767 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 786 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 3783 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3676 # Number of loads inserted to the mem dependence unit. +system.cpu.rename.skidInsts 3842 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3673 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 2348 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23657 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 23655 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 726 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21921 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9156 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6522 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21924 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9151 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6501 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 251 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32510 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.674285 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.426342 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32422 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.676208 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.425800 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 24124 74.20% 74.20% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3065 9.43% 83.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1561 4.80% 88.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1482 4.56% 92.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 945 2.91% 95.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 726 2.23% 98.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 412 1.27% 99.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 154 0.47% 99.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 41 0.13% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 24009 74.05% 74.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3087 9.52% 83.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1572 4.85% 88.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1483 4.57% 93.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 954 2.94% 95.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 709 2.19% 98.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 413 1.27% 99.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 155 0.48% 99.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 40 0.12% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32510 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32422 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 112 49.56% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 49 21.68% 71.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 65 28.76% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 111 49.33% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 49.33% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 49 21.78% 71.11% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 65 28.89% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16292 74.32% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.32% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3506 15.99% 90.32% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16300 74.35% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.35% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3501 15.97% 90.32% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 2123 9.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21921 # Type of FU issued -system.cpu.iq.rate 0.422459 # Inst issue rate -system.cpu.iq.fu_busy_cnt 226 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010310 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 76635 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 33566 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 20237 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21924 # Type of FU issued +system.cpu.iq.rate 0.398865 # Inst issue rate +system.cpu.iq.fu_busy_cnt 225 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010263 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76549 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 33558 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 20244 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 22147 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22149 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1451 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1448 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 900 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewSquashCycles 1155 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 1122 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 322 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25510 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 207 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3676 # Number of dispatched load instructions +system.cpu.iew.iewBlockCycles 1147 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 7 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25507 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 203 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3673 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 2348 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 726 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 318 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 934 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1193 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20909 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3349 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1194 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20914 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3347 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1010 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1127 # number of nop insts executed -system.cpu.iew.exec_refs 5373 # number of memory reference insts executed -system.cpu.iew.exec_branches 4425 # Number of branches executed +system.cpu.iew.exec_nop 1126 # number of nop insts executed +system.cpu.iew.exec_refs 5371 # number of memory reference insts executed +system.cpu.iew.exec_branches 4427 # Number of branches executed system.cpu.iew.exec_stores 2024 # Number of stores executed -system.cpu.iew.exec_rate 0.402956 # Inst execution rate -system.cpu.iew.wb_sent 20494 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 20237 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9846 # num instructions producing a value -system.cpu.iew.wb_consumers 12767 # num instructions consuming a value +system.cpu.iew.exec_rate 0.380490 # Inst execution rate +system.cpu.iew.wb_sent 20501 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 20244 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9848 # num instructions producing a value +system.cpu.iew.wb_consumers 12670 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.390006 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.771207 # average fanout of values written-back +system.cpu.iew.wb_rate 0.368300 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.777269 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10297 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10287 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1058 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30446 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.497996 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.310786 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1059 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 30361 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.499391 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.308685 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23926 78.59% 78.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3430 11.27% 89.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1163 3.82% 93.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 612 2.01% 95.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 344 1.13% 96.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 240 0.79% 97.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 396 1.30% 98.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23816 78.44% 78.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3429 11.29% 89.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1193 3.93% 93.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 637 2.10% 95.76% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 331 1.09% 96.85% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 224 0.74% 97.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 397 1.31% 98.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 62 0.20% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 273 0.90% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 272 0.90% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30446 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30361 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -532,105 +532,105 @@ system.cpu.commit.op_class_0::MemWrite 1448 9.55% 100.00% # Cl system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 15162 # Class of committed instruction -system.cpu.commit.bw_lim_events 273 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 272 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54809 # The number of ROB reads -system.cpu.rob.rob_writes 52997 # The number of ROB writes -system.cpu.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19379 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 54715 # The number of ROB reads +system.cpu.rob.rob_writes 52974 # The number of ROB writes +system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 22544 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 3.594417 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.594417 # CPI: Total CPI of All Threads -system.cpu.ipc 0.278209 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.278209 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 33401 # number of integer regfile reads -system.cpu.int_regfile_writes 18599 # number of integer regfile writes -system.cpu.misc_regfile_reads 7136 # number of misc regfile reads +system.cpu.cpi 3.807564 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.807564 # CPI: Total CPI of All Threads +system.cpu.ipc 0.262635 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.262635 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 33408 # number of integer regfile reads +system.cpu.int_regfile_writes 18606 # number of integer regfile writes +system.cpu.misc_regfile_reads 7133 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.823294 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 4124 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 98.556611 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 4125 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 28.054422 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 28.061224 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.823294 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024127 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024127 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 98.556611 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.024062 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.024062 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 9491 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 9491 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 3085 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3085 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 9489 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 9489 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 3086 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3086 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4118 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4118 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4118 # number of overall hits -system.cpu.dcache.overall_hits::total 4118 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 139 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 139 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4119 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4119 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4119 # number of overall hits +system.cpu.dcache.overall_hits::total 4119 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 137 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 137 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 548 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 548 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 548 # number of overall misses -system.cpu.dcache.overall_misses::total 548 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8670750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8670750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 26093224 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 26093224 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 34763974 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 34763974 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 34763974 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3224 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3224 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 546 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 546 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 546 # number of overall misses +system.cpu.dcache.overall_misses::total 546 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9397000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9397000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 27538481 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 27538481 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 36935481 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 36935481 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 36935481 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 36935481 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3223 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3223 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4666 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4666 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4666 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4666 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.043114 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.043114 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4665 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4665 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4665 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4665 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.042507 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.042507 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.117445 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.117445 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.117445 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.117445 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62379.496403 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62379.496403 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63797.613692 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 63797.613692 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63437.908759 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63437.908759 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 955 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.117042 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117042 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117042 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117042 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68591.240876 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 68591.240876 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 67331.249389 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 67331.249389 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67647.401099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67647.401099 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67647.401099 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 1052 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 22 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 31.833333 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.818182 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 72 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 400 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 400 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 400 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 398 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 398 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 398 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 398 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 65 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 65 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -639,135 +639,135 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 148 system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6235500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10976500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10976500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020161 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020161 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5143250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5143250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6389250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 6389250 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11532500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11532500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11532500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11532500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020168 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020168 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031719 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031719 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 72938.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75126.506024 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74165.540541 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 74165.540541 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031726 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031726 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031726 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 79126.923077 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 79126.923077 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76978.915663 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76978.915663 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77922.297297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 77922.297297 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 192.510962 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 5925 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 190.975563 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5904 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 346 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 17.124277 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.063584 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 192.510962 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.093999 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.093999 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 190.975563 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.093250 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.093250 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 346 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 253 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 90 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.168945 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 13252 # Number of tag accesses -system.cpu.icache.tags.data_accesses 13252 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 5925 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5925 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5925 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5925 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5925 # number of overall hits -system.cpu.icache.overall_hits::total 5925 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 528 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 528 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 528 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 528 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 528 # number of overall misses -system.cpu.icache.overall_misses::total 528 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32445000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32445000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32445000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32445000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32445000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32445000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 6453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 6453 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 6453 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 6453 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 6453 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 6453 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.081822 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.081822 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.081822 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.081822 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.081822 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.081822 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61448.863636 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61448.863636 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61448.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61448.863636 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61448.863636 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 13222 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13222 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5904 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5904 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5904 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5904 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5904 # number of overall hits +system.cpu.icache.overall_hits::total 5904 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 534 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 534 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 534 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 534 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 534 # number of overall misses +system.cpu.icache.overall_misses::total 534 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 37367000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 37367000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 37367000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 37367000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 37367000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 37367000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6438 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6438 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6438 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6438 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6438 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.082945 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.082945 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.082945 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.082945 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.082945 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.082945 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69975.655431 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 69975.655431 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 69975.655431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 69975.655431 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 69975.655431 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 57 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 42 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 182 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 182 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 182 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 182 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 188 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 188 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 188 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 188 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 188 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 188 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 346 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 346 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 346 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 346 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 346 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 346 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23039750 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23039750 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23039750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23039750 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23039750 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23039750 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053618 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.053618 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053618 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.053618 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66588.872832 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66588.872832 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66588.872832 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 66588.872832 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26526250 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 26526250 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26526250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 26526250 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26526250 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 26526250 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.053743 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.053743 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.053743 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.053743 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 76665.462428 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 76665.462428 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 76665.462428 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 76665.462428 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 226.536653 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 224.896195 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 408 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.004902 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 191.902825 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 34.633828 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005856 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001057 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006913 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 190.368376 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 34.527819 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005810 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001054 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.006863 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 297 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012451 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4443 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4443 # Number of data accesses @@ -788,17 +788,17 @@ system.cpu.l2cache.demand_misses::total 492 # nu system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses system.cpu.l2cache.overall_misses::total 492 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22673250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 27349750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6151000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6151000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22673250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10827500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33500750 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22673250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10827500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33500750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26158750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5078750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 31237500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6304750 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6304750 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 26158750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 11383500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 37542250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 26158750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 11383500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 37542250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 346 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 65 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) @@ -821,17 +821,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995951 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994220 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 65910.610465 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71946.153846 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 66869.804401 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74108.433735 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74108.433735 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68090.955285 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 65910.610465 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73158.783784 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68090.955285 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76042.877907 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78134.615385 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 76375.305623 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75960.843373 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75960.843373 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 76305.386179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76042.877907 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76915.540541 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 76305.386179 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -851,17 +851,17 @@ system.cpu.l2cache.demand_mshr_misses::total 492 system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18347250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3889500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22236750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5131500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5131500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18347250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9021000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27368250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18347250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9021000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27368250 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21861250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4272750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26134000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5278250 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21861250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9551000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 31412250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21861250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9551000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 31412250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995134 # mshr miss rate for ReadReq accesses @@ -873,17 +873,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995951 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994220 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53335.029070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59838.461538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 54368.581907 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61825.301205 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61825.301205 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53335.029070 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60952.702703 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55626.524390 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63550.145349 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65734.615385 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63897.310513 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63593.373494 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63550.145349 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64533.783784 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 63846.036585 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 411 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 410 # Transaction distribution @@ -908,10 +908,10 @@ system.cpu.toL2Bus.snoop_fanout::min_value 1 # system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::total 494 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 247000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 579250 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 233000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 587750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.1 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 245000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) system.membus.trans_dist::ReadReq 409 # Transaction distribution system.membus.trans_dist::ReadResp 408 # Transaction distribution @@ -932,9 +932,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 492 # Request fanout histogram -system.membus.reqLayer0.occupancy 611000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 4586750 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.7 # Layer utilization (%) +system.membus.reqLayer0.occupancy 608000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) +system.membus.respLayer1.occupancy 2599750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 9.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt index 5faa1ad2c..56b893c5d 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000041 # Number of seconds simulated -sim_ticks 41368000 # Number of ticks simulated -final_tick 41368000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 41368500 # Number of ticks simulated +final_tick 41368500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 245276 # Simulator instruction rate (inst/s) -host_op_rate 245221 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 668919684 # Simulator tick rate (ticks/s) -host_mem_usage 285672 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 311873 # Simulator instruction rate (inst/s) +host_op_rate 311783 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 850451247 # Simulator tick rate (ticks/s) +host_mem_usage 289340 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,40 +21,17 @@ system.physmem.bytes_inst_read::total 17792 # Nu system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 416 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 430090892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 213498356 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 643589248 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 430090892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 430090892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 430090892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 213498356 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 643589248 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 331 # Transaction distribution -system.membus.trans_dist::ReadResp 331 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 416 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 416 # Request fanout histogram -system.membus.reqLayer0.occupancy 416000 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 3744000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 9.1 # Layer utilization (%) +system.physmem.bw_read::cpu.inst 430085693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 213495776 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 643581469 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 430085693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 430085693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 430085693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 213495776 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 643581469 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 82736 # number of cpu cycles simulated +system.cpu.numCycles 82737 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 15162 # Number of instructions committed @@ -73,7 +50,7 @@ system.cpu.num_mem_refs 3683 # nu system.cpu.num_load_insts 2231 # Number of load instructions system.cpu.num_store_insts 1452 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 82735.998000 # Number of busy cycles +system.cpu.num_busy_cycles 82736.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 3363 # Number of branches fetched @@ -112,15 +89,123 @@ system.cpu.op_class::MemWrite 1452 9.55% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 15207 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 97.991492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 97.991492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits +system.cpu.dcache.overall_hits::total 3529 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.dcache.overall_misses::total 138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2835500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4547500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4547500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7383000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7383000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 153.782734 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 153.777491 # Cycle average of tags in use system.cpu.icache.tags.total_refs 14928 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 280 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 53.314286 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 153.782734 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.075089 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.075089 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 153.777491 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.075087 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.075087 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 280 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 234 # Occupied blocks per task id @@ -139,12 +224,12 @@ system.cpu.icache.demand_misses::cpu.inst 280 # n system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses system.cpu.icache.overall_misses::total 280 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15316000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15316000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15316000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15316000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15316000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15316500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15316500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15316500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15316500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15316500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15316500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 15208 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 15208 # number of demand (read+write) accesses @@ -157,12 +242,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 system.cpu.icache.demand_miss_rate::total 0.018411 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.018411 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54700 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 54700 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 54700 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 54700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 54700 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 54700 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54701.785714 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54701.785714 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54701.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54701.785714 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54701.785714 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -177,36 +262,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 280 system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 280 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14896500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14896500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14896500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14896500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14896500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14896500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.018411 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.018411 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52700 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52700 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53201.785714 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53201.785714 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53201.785714 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53201.785714 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 184.632038 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 184.625818 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 331 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.006042 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.110886 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.521152 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004673 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.105687 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 31.520131 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004672 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.000962 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005635 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005634 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 331 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 275 # Occupied blocks per task id @@ -230,17 +315,17 @@ system.cpu.l2cache.demand_misses::total 416 # nu system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 416 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14595500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2782500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17378000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4462500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4462500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14595500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7245000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21840500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14595500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7245000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21840500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses) @@ -263,17 +348,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995215 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995215 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.798561 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.510574 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52501.201923 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.798561 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52501.201923 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -293,17 +378,17 @@ system.cpu.l2cache.demand_mshr_misses::total 416 system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2146500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13405500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3442500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5589000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16848000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5589000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16848000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993994 # mshr miss rate for ReadReq accesses @@ -315,126 +400,18 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 97.994344 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3535 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 25.615942 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 97.994344 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.023924 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 2172 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2172 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3529 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3529 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3529 # number of overall hits -system.cpu.dcache.overall_hits::total 3529 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.dcache.overall_misses::total 138 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2915000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2915000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 4675000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 4675000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7590000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7590000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7590000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.023820 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.058946 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.037633 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.037633 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 333 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution @@ -463,5 +440,28 @@ system.cpu.toL2Bus.respLayer0.occupancy 420000 # La system.cpu.toL2Bus.respLayer0.utilization 1.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.membus.trans_dist::ReadReq 331 # Transaction distribution +system.membus.trans_dist::ReadResp 331 # Transaction distribution +system.membus.trans_dist::ReadExReq 85 # Transaction distribution +system.membus.trans_dist::ReadExResp 85 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 832 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26624 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 416 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 416 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 416 # Request fanout histogram +system.membus.reqLayer0.occupancy 416500 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 2080500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 5.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index ffbae61d5..948908ba0 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,88 +1,88 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105542000 # Number of ticks simulated -final_tick 105542000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000108 # Number of seconds simulated +sim_ticks 107944000 # Number of ticks simulated +final_tick 107944000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 163449 # Simulator instruction rate (inst/s) -host_op_rate 163449 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17392605 # Simulator tick rate (ticks/s) -host_mem_usage 309188 # Number of bytes of host memory used -host_seconds 6.07 # Real time elapsed on the host -sim_insts 991839 # Number of instructions simulated -sim_ops 991839 # Number of ops (including micro ops) simulated +host_inst_rate 162812 # Simulator instruction rate (inst/s) +host_op_rate 162812 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17679745 # Simulator tick rate (ticks/s) +host_mem_usage 308116 # Number of bytes of host memory used +host_seconds 6.11 # Real time elapsed on the host +sim_insts 994048 # Number of instructions simulated +sim_ops 994048 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.inst 22976 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 4864 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 23168 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 42496 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 22976 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 4864 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 359 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 76 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42816 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23168 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29056 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 362 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 664 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 217695325 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101874135 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 7276724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7883118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 46085918 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 12127873 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1819181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7883118 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 402645392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 217695325 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 7276724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 46085918 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1819181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 272877148 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 217695325 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101874135 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 7276724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7883118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 46085918 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 12127873 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1819181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7883118 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 402645392 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 665 # Number of read requests accepted +system.physmem.num_reads::total 669 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 214629808 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100200104 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47432002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11858000 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 4150300 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7707700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2964500 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7707700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 396650115 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 214629808 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47432002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 4150300 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2964500 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269176610 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 214629808 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100200104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47432002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11858000 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 4150300 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7707700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2964500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7707700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 396650115 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 670 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 665 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 670 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 42560 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 42880 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 42560 # Total read bytes from the system interface side +system.physmem.bytesReadSys 42880 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 78 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 114 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 76 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 115 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 27 # Per bank write bursts system.physmem.perBankRdBursts::3 60 # Per bank write bursts -system.physmem.perBankRdBursts::4 65 # Per bank write bursts +system.physmem.perBankRdBursts::4 66 # Per bank write bursts system.physmem.perBankRdBursts::5 28 # Per bank write bursts system.physmem.perBankRdBursts::6 18 # Per bank write bursts system.physmem.perBankRdBursts::7 24 # Per bank write bursts system.physmem.perBankRdBursts::8 7 # Per bank write bursts -system.physmem.perBankRdBursts::9 28 # Per bank write bursts -system.physmem.perBankRdBursts::10 22 # Per bank write bursts -system.physmem.perBankRdBursts::11 13 # Per bank write bursts +system.physmem.perBankRdBursts::9 29 # Per bank write bursts +system.physmem.perBankRdBursts::10 23 # Per bank write bursts +system.physmem.perBankRdBursts::11 14 # Per bank write bursts system.physmem.perBankRdBursts::12 65 # Per bank write bursts system.physmem.perBankRdBursts::13 38 # Per bank write bursts system.physmem.perBankRdBursts::14 17 # Per bank write bursts @@ -105,14 +105,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 105514000 # Total gap between requests +system.physmem.totGap 107916000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 665 # Read request sizes (log2) +system.physmem.readPktSize::6 670 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -120,10 +120,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 394 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 61 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 190 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 60 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -216,556 +216,556 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 142 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 280.338028 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.767584 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.989000 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 41 28.87% 28.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 38 26.76% 55.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 26 18.31% 73.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 12 8.45% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 6 4.23% 86.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 6 4.23% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 6 4.23% 95.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 2 1.41% 96.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 3.52% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 142 # Bytes accessed per row activation -system.physmem.totQLat 6421750 # Total ticks spent queuing -system.physmem.totMemAccLat 18890500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 3325000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9656.77 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 148 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 270.702703 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.430987 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 234.776821 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 43 29.05% 29.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 39 26.35% 55.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 25 16.89% 72.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 19 12.84% 85.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 6 4.05% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 6 4.05% 93.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 5 3.38% 96.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 1.35% 97.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 3 2.03% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 148 # Bytes accessed per row activation +system.physmem.totQLat 6539750 # Total ticks spent queuing +system.physmem.totMemAccLat 19102250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 3350000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9760.82 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28406.77 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 403.25 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28510.82 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 397.24 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 403.25 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 397.24 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 3.15 # Data bus utilization in percentage -system.physmem.busUtilRead 3.15 # Data bus utilization in percentage for reads +system.physmem.busUtil 3.10 # Data bus utilization in percentage +system.physmem.busUtilRead 3.10 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.39 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 512 # Number of row buffer hits during reads +system.physmem.readRowHits 511 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.99 # Row buffer hit rate for reads +system.physmem.readRowHitRate 76.27 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 158667.67 # Average gap between requests -system.physmem.pageHitRate 76.99 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 687960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 375375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2753400 # Energy for read commands per rank (pJ) +system.physmem.avgGap 161068.66 # Average gap between requests +system.physmem.pageHitRate 76.27 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2761200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 29877120 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 34680750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 74985885 # Total energy per rank (pJ) -system.physmem_0.averagePower 738.913691 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 57973250 # Time in different power states +system.physmem_0.actBackEnergy 39247065 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 26461500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76167750 # Total energy per rank (pJ) +system.physmem_0.averagePower 750.559832 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 46478250 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 40577250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 54316750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2043600 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 385560 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 2067000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 27463455 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 36789750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 73457280 # Total energy per rank (pJ) -system.physmem_1.averagePower 723.948851 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 62480000 # Time in different power states +system.physmem_1.actBackEnergy 30855240 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 33814500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 73943955 # Total energy per rank (pJ) +system.physmem_1.averagePower 728.745214 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 59727000 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 37046000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 42022000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81296 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78365 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1199 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 77900 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 75117 # Number of BTB hits +system.cpu0.branchPred.lookups 81450 # Number of BP lookups +system.cpu0.branchPred.condPredicted 78581 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1205 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 78182 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 75500 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.427471 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 763 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.BTBHitPct 96.569543 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 747 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211085 # number of cpu cycles simulated +system.cpu0.numCycles 215889 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20068 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 480268 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81296 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 75880 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 163785 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing +system.cpu0.fetch.icacheStallCycles 20419 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 481443 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81450 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76247 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165590 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2709 # Number of cycles fetch has spent squashing system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1916 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 7139 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 648 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 187121 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.566617 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.228608 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 2214 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 7225 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 649 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 189580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.539524 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.227640 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30271 16.18% 16.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 77424 41.38% 57.55% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 764 0.41% 57.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1076 0.58% 58.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 624 0.33% 58.87% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 72740 38.87% 97.74% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 718 0.38% 98.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 448 0.24% 98.37% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3056 1.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 32064 16.91% 16.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 77818 41.05% 57.96% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818 0.43% 58.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1146 0.60% 59.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 623 0.33% 59.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 72992 38.50% 97.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 703 0.37% 98.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 447 0.24% 98.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2969 1.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 187121 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.385134 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.275235 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::total 189580 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.377277 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.230049 # Number of inst fetches per cycle system.cpu0.decode.IdleCycles 15778 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 17868 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 151448 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 678 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1349 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 468198 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 1349 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16395 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2033 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14616 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 151464 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1264 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 464735 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 19 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 756 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 318331 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 926755 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 700443 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 304259 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 14072 # Number of HB maps that are undone due to squashing +system.cpu0.decode.BlockedCycles 19697 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 152079 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 672 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1354 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 469796 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 1354 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 16409 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2266 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15970 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 152076 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1505 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 466337 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 1001 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 319451 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 929999 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 702902 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 305355 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14096 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 900 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4585 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 148203 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75025 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 72247 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 71998 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 388891 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 968 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 385538 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 23 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12303 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11219 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 409 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 187121 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.060367 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.127018 # Number of insts issued each cycle +system.cpu0.rename.tempSerializingInsts 908 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4587 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 148758 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75265 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 72519 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72258 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 390345 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 967 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 386997 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 24 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 12329 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11208 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 408 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 189580 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.041339 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.140292 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33176 17.73% 17.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4313 2.30% 20.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 73426 39.24% 59.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 72986 39.00% 98.28% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1673 0.89% 99.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 893 0.48% 99.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 397 0.21% 99.86% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 180 0.10% 99.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 77 0.04% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 35140 18.54% 18.54% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4258 2.25% 20.78% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 73622 38.83% 59.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73334 38.68% 98.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1646 0.87% 99.17% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 901 0.48% 99.64% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 423 0.22% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 182 0.10% 99.96% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 74 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 187121 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 189580 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 102 35.29% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 35.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 84 29.07% 64.36% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 91 32.73% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 32.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 84 30.22% 62.95% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 103 37.05% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 163537 42.42% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.42% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 147667 38.30% 80.72% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 74334 19.28% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164205 42.43% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.43% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 148197 38.29% 80.72% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 74595 19.28% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 385538 # Type of FU issued -system.cpu0.iq.rate 1.826459 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000750 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 958509 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 402215 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 383670 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 386997 # Type of FU issued +system.cpu0.iq.rate 1.792574 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 278 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000718 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 963876 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 403692 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 385100 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 385827 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 387275 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 71619 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 71895 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2484 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2491 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 54 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1659 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 12 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.cacheBlocked 9 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1995 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 462536 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 148203 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75025 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 847 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 54 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 324 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1113 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.iewSquashCycles 1354 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2232 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 464248 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 186 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 148758 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75265 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 333 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1104 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1437 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 384525 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 147369 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1013 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 385946 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 147890 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1051 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 72677 # number of nop insts executed -system.cpu0.iew.exec_refs 221564 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76264 # Number of branches executed -system.cpu0.iew.exec_stores 74195 # Number of stores executed -system.cpu0.iew.exec_rate 1.821660 # Inst execution rate -system.cpu0.iew.wb_sent 384046 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 383670 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 227520 # num instructions producing a value -system.cpu0.iew.wb_consumers 230755 # num instructions consuming a value +system.cpu0.iew.exec_nop 72936 # number of nop insts executed +system.cpu0.iew.exec_refs 222349 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76534 # Number of branches executed +system.cpu0.iew.exec_stores 74459 # Number of stores executed +system.cpu0.iew.exec_rate 1.787706 # Inst execution rate +system.cpu0.iew.wb_sent 385475 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 385100 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 228400 # num instructions producing a value +system.cpu0.iew.wb_consumers 231722 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.817609 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.985981 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.783787 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.985664 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13745 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13801 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1199 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 184477 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.432498 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.147629 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1205 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 186928 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.409398 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.152220 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33360 18.08% 18.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75359 40.85% 58.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2024 1.10% 60.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 644 0.35% 60.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 522 0.28% 60.66% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 71315 38.66% 99.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 520 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 246 0.13% 99.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 487 0.26% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 35407 18.94% 18.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 75555 40.42% 59.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1920 1.03% 60.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 633 0.34% 60.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 494 0.26% 60.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 71651 38.33% 99.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 511 0.27% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 494 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 184477 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 448740 # Number of instructions committed -system.cpu0.commit.committedOps 448740 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186928 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 450384 # Number of instructions committed +system.cpu0.commit.committedOps 450384 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 219085 # Number of memory references committed -system.cpu0.commit.loads 145719 # Number of loads committed +system.cpu0.commit.refs 219907 # Number of memory references committed +system.cpu0.commit.loads 146267 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 75253 # Number of branches committed +system.cpu0.commit.branches 75527 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 302590 # Number of committed integer instructions. +system.cpu0.commit.int_insts 303686 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 71985 16.04% 16.04% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 157586 35.12% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 145803 32.49% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 73366 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72259 16.04% 16.04% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 158134 35.11% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 146351 32.49% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 73640 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 448740 # Class of committed instruction -system.cpu0.commit.bw_lim_events 487 # number cycles where commit BW limit reached +system.cpu0.commit.op_class_0::total 450384 # Class of committed instruction +system.cpu0.commit.bw_lim_events 494 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 645314 # The number of ROB reads -system.cpu0.rob.rob_writes 927635 # The number of ROB writes -system.cpu0.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 23964 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 376671 # Number of Instructions Simulated -system.cpu0.committedOps 376671 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.560396 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.560396 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.784452 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.784452 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 687652 # number of integer regfile reads -system.cpu0.int_regfile_writes 310240 # number of integer regfile writes +system.cpu0.rob.rob_reads 649458 # The number of ROB reads +system.cpu0.rob.rob_writes 931043 # The number of ROB writes +system.cpu0.timesIdled 314 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26309 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 378041 # Number of Instructions Simulated +system.cpu0.committedOps 378041 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.571073 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.571073 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.751090 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.751090 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 690199 # number of integer regfile reads +system.cpu0.int_regfile_writes 311415 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 223454 # number of misc regfile reads +system.cpu0.misc_regfile_reads 224240 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.523626 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 147885 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 869.911765 # Average number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 140.939988 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 148370 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 867.660819 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.523626 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.276413 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.276413 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 46 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 0.328125 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 596477 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 596477 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75193 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75193 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 72780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 72780 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 20 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 20 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 147973 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 147973 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 147973 # number of overall hits -system.cpu0.dcache.overall_hits::total 147973 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 482 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 482 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 22 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 22 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1026 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1026 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1026 # number of overall misses -system.cpu0.dcache.overall_misses::total 1026 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15529368 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 15529368 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 32868763 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 32868763 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 428750 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 428750 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 48398131 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 48398131 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 48398131 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 48398131 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 75675 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 75675 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 73324 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 73324 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.tags.occ_blocks::cpu0.data 140.939988 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275273 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275273 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 598524 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 598524 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75399 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75399 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73059 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73059 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 148458 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 148458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 148458 # number of overall hits +system.cpu0.dcache.overall_hits::total 148458 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 514 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 514 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 539 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 539 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1053 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1053 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1053 # number of overall misses +system.cpu0.dcache.overall_misses::total 1053 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17626915 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17626915 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36442515 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 36442515 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 680000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 680000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 54069430 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 54069430 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 54069430 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 54069430 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 75913 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 75913 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 73598 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 73598 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 148999 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 148999 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 148999 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 148999 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006369 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006369 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007419 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007419 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.523810 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006886 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006886 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006886 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006886 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32218.605809 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32218.605809 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 60420.520221 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 60420.520221 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19488.636364 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19488.636364 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 47171.667641 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47171.667641 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 47171.667641 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 754 # number of cycles access was blocked +system.cpu0.dcache.demand_accesses::cpu0.data 149511 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 149511 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 149511 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 149511 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006771 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006771 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007324 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007324 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007043 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007043 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007043 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007043 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 34293.608949 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 34293.608949 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 67611.345083 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 67611.345083 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 32380.952381 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 32380.952381 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 51347.986705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 51347.986705 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 51347.986705 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1036 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 13 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27.925926 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 79.692308 # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 299 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 365 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 365 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 664 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 664 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 664 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 664 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 183 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 179 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 179 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 22 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 22 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 362 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 362 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 362 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6541511 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6541511 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7390227 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7390227 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 383250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 383250 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 13931738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13931738 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13931738 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13931738 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002418 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002418 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002441 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002441 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002430 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002430 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002430 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 35745.961749 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 35745.961749 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41286.184358 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41286.184358 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17420.454545 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17420.454545 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 38485.464088 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 38485.464088 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 330 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 330 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 362 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 362 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 692 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 692 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 692 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 692 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 184 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 184 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 177 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 177 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 361 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 361 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6770753 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6770753 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8530978 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8530978 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 646500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 646500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15301731 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15301731 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15301731 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15301731 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002424 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002405 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002405 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002415 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002415 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002415 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36797.570652 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36797.570652 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48197.615819 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48197.615819 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 30785.714286 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 30785.714286 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42387.066482 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42387.066482 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 319 # number of replacements -system.cpu0.icache.tags.tagsinuse 239.733862 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 6347 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 608 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 10.439145 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 323 # number of replacements +system.cpu0.icache.tags.tagsinuse 240.188663 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 6428 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 614 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 10.469055 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 239.733862 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.468230 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.468230 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 289 # Occupied blocks per task id +system.cpu0.icache.tags.occ_blocks::cpu0.inst 240.188663 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.469118 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.469118 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.564453 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7747 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7747 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 6347 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6347 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 6347 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6347 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 6347 # number of overall hits -system.cpu0.icache.overall_hits::total 6347 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 792 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 792 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 792 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 792 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 792 # number of overall misses -system.cpu0.icache.overall_misses::total 792 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 36432996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 36432996 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 36432996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 36432996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 36432996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 36432996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 7139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7139 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 7139 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7139 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 7139 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7139 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110940 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.110940 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110940 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.110940 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110940 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.110940 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 46001.257576 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 46001.257576 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 46001.257576 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 46001.257576 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 46001.257576 # average overall miss latency +system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.568359 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 7839 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7839 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 6428 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6428 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 6428 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 6428 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 6428 # number of overall hits +system.cpu0.icache.overall_hits::total 6428 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 797 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 797 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 797 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 797 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 797 # number of overall misses +system.cpu0.icache.overall_misses::total 797 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40514746 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40514746 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40514746 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40514746 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40514746 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40514746 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7225 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7225 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7225 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7225 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7225 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7225 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.110311 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.110311 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.110311 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.110311 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.110311 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.110311 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 50834.060226 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 50834.060226 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 50834.060226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 50834.060226 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 50834.060226 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -774,410 +774,410 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 183 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 183 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 183 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 183 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 183 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 183 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 609 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 609 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 609 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 609 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 609 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 609 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 27995751 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 27995751 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 27995751 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 27995751 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 27995751 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 27995751 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085306 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.085306 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085306 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.085306 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 45970.034483 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 45970.034483 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 45970.034483 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 182 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 182 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 182 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 182 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 182 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 182 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 615 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 615 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 615 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 615 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 615 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 615 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31043001 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31043001 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31043001 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31043001 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31043001 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31043001 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.085121 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.085121 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.085121 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.085121 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 50476.424390 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50476.424390 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 50476.424390 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 48230 # Number of BP lookups -system.cpu1.branchPred.condPredicted 44811 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1266 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 41091 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 39963 # Number of BTB hits +system.cpu1.branchPred.lookups 52261 # Number of BP lookups +system.cpu1.branchPred.condPredicted 48386 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1341 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 44394 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 43169 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.254873 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 868 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 97.240618 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 160735 # number of cpu cycles simulated +system.cpu1.numCycles 162232 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 33641 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 261327 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 48230 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 40831 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 122936 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2691 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 31153 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 288417 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52261 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 44075 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 122623 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2833 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1065 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 24854 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 432 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 159000 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.643566 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.124362 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.PendingTrapStallCycles 1159 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 21623 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 472 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156364 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.844523 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.218152 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 63867 40.17% 40.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 48973 30.80% 70.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 8266 5.20% 76.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3472 2.18% 78.35% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1057 0.66% 79.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 27547 17.33% 96.34% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1174 0.74% 97.08% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 753 0.47% 97.55% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3891 2.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 56063 35.85% 35.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 50599 32.36% 68.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 6236 3.99% 72.20% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3531 2.26% 74.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 937 0.60% 75.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 32564 20.83% 95.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1222 0.78% 96.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 843 0.54% 97.21% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4369 2.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 159000 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.300059 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.625825 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17613 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 67674 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 68228 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 4130 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1345 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 247069 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1345 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18292 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33178 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 12317 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 69139 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 24719 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 243777 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 21468 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 22 # Number of times rename has blocked due to LQ full -system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 169834 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 458131 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 358650 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 155489 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 14345 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 29340 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 66237 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 30368 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 32190 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 25244 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 200152 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 7929 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 203048 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12672 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11906 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 679 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 159000 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.277031 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.370207 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 156364 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.322137 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.777806 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 18077 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 54814 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 78767 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3280 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1416 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 271927 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1416 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18807 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 25020 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13667 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 79411 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 18033 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 268621 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 15397 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 31 # Number of times rename has blocked due to LQ full +system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 189765 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 514915 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 401460 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 175087 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 14678 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1212 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 22640 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 74986 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 35614 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 35483 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 30428 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 223482 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 6146 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 225009 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 16 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12719 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10743 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 680 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156364 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.439008 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.385420 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 67764 42.62% 42.62% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 26124 16.43% 59.05% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 29595 18.61% 77.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 29204 18.37% 96.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3405 2.14% 98.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1592 1.00% 99.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 226 0.14% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 210 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 59519 38.06% 38.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 20894 13.36% 51.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35016 22.39% 73.82% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 34585 22.12% 95.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3417 2.19% 98.12% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1600 1.02% 99.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 882 0.56% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 240 0.15% 99.87% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 211 0.13% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 159000 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156364 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 87 24.30% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.30% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 62 17.32% 41.62% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 58.38% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 92 27.88% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 29 8.79% 36.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 101499 49.99% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 71903 35.41% 85.40% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 29646 14.60% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 110922 49.30% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.30% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 79078 35.14% 84.44% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 35009 15.56% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 203048 # Type of FU issued -system.cpu1.iq.rate 1.263247 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 358 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001763 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 565493 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 220798 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 201375 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 225009 # Type of FU issued +system.cpu1.iq.rate 1.386958 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 330 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001467 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 606728 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 242381 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 223369 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 203406 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 225339 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 24951 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30296 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2787 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2626 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1647 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1552 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1345 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 8539 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 241028 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 239 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 66237 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 30368 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1097 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1416 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 7338 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 266019 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 165 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 74986 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 35614 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1009 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1474 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 201951 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 65061 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 34 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 453 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1125 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1578 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 223948 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 74035 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 32947 # number of nop insts executed -system.cpu1.iew.exec_refs 94595 # number of memory reference insts executed -system.cpu1.iew.exec_branches 42219 # Number of branches executed -system.cpu1.iew.exec_stores 29534 # Number of stores executed -system.cpu1.iew.exec_rate 1.256422 # Inst execution rate -system.cpu1.iew.wb_sent 201670 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 201375 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 112178 # num instructions producing a value -system.cpu1.iew.wb_consumers 118722 # num instructions consuming a value +system.cpu1.iew.exec_nop 36391 # number of nop insts executed +system.cpu1.iew.exec_refs 108940 # number of memory reference insts executed +system.cpu1.iew.exec_branches 45914 # Number of branches executed +system.cpu1.iew.exec_stores 34905 # Number of stores executed +system.cpu1.iew.exec_rate 1.380418 # Inst execution rate +system.cpu1.iew.wb_sent 223649 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 223369 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 126652 # num instructions producing a value +system.cpu1.iew.wb_consumers 133295 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.252839 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.944880 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.376849 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.950163 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 14315 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 7250 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1266 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 156398 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.449251 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.979774 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 14380 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 5466 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1341 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 153714 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.636819 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.057713 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 74586 47.69% 47.69% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 38945 24.90% 72.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5214 3.33% 75.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 8053 5.15% 81.07% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1537 0.98% 82.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 24957 15.96% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 851 0.54% 98.56% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 951 0.61% 99.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1304 0.83% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 64759 42.13% 42.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 42554 27.68% 69.81% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5173 3.37% 73.18% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6281 4.09% 77.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1529 0.99% 78.26% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30355 19.75% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 785 0.51% 98.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 966 0.63% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1312 0.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 156398 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 226660 # Number of instructions committed -system.cpu1.commit.committedOps 226660 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 153714 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 251602 # Number of instructions committed +system.cpu1.commit.committedOps 251602 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 92171 # Number of memory references committed -system.cpu1.commit.loads 63450 # Number of loads committed -system.cpu1.commit.membars 6533 # Number of memory barriers committed -system.cpu1.commit.branches 41215 # Number of branches committed +system.cpu1.commit.refs 106422 # Number of memory references committed +system.cpu1.commit.loads 72360 # Number of loads committed +system.cpu1.commit.membars 4751 # Number of memory barriers committed +system.cpu1.commit.branches 44778 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 155506 # Number of committed integer instructions. +system.cpu1.commit.int_insts 173320 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 32002 14.12% 14.12% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 95954 42.33% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.45% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 69983 30.88% 87.33% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 28721 12.67% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 35567 14.14% 14.14% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 104862 41.68% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.81% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 77111 30.65% 86.46% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 34062 13.54% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 226660 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached +system.cpu1.commit.op_class_0::total 251602 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1312 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 395483 # The number of ROB reads -system.cpu1.rob.rob_writes 484550 # The number of ROB writes -system.cpu1.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 1735 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 43282 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 188125 # Number of Instructions Simulated -system.cpu1.committedOps 188125 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.854405 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.854405 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.170405 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.170405 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 343348 # number of integer regfile reads -system.cpu1.int_regfile_writes 161358 # number of integer regfile writes +system.cpu1.rob.rob_reads 417798 # The number of ROB reads +system.cpu1.rob.rob_writes 534614 # The number of ROB writes +system.cpu1.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 5868 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 46290 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 211284 # Number of Instructions Simulated +system.cpu1.committedOps 211284 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.767839 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.767839 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.302357 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.302357 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 386957 # number of integer regfile reads +system.cpu1.int_regfile_writes 181537 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 96189 # number of misc regfile reads +system.cpu1.misc_regfile_reads 110600 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 23.332143 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 34754 # Total number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.579817 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 40184 # Total number of references to valid blocks. system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1241.214286 # Average number of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1435.142857 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 23.332143 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.045571 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.045571 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.579817 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.049961 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.049961 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 275515 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 275515 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 39673 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39673 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 28513 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 28513 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 68186 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 68186 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 68186 # number of overall hits -system.cpu1.dcache.overall_hits::total 68186 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 422 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 422 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu1.dcache.tags.tag_accesses 311400 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 311400 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 43257 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 43257 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 33840 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 33840 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 77097 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 77097 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 77097 # number of overall hits +system.cpu1.dcache.overall_hits::total 77097 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 466 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 466 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 153 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 153 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 559 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 559 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 559 # number of overall misses -system.cpu1.dcache.overall_misses::total 559 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5603617 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 5603617 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2812761 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2812761 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 492507 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 492507 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8416378 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8416378 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8416378 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8416378 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40095 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40095 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 28650 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 28650 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 68745 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 68745 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 68745 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 68745 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010525 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.010525 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004782 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004782 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008132 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.008132 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008132 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.008132 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13278.713270 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 13278.713270 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20531.102190 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 20531.102190 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 8640.473684 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 8640.473684 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15056.132379 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15056.132379 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15056.132379 # average overall miss latency +system.cpu1.dcache.demand_misses::cpu1.data 619 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 619 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 619 # number of overall misses +system.cpu1.dcache.overall_misses::total 619 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9865731 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9865731 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3999011 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3999011 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 673507 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 673507 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13864742 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13864742 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13864742 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13864742 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 43723 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 43723 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 33993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 33993 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 77716 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 77716 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 77716 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 77716 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010658 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.010658 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004501 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004501 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.826087 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.826087 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007965 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007965 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007965 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007965 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21171.096567 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 21171.096567 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26137.326797 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 26137.326797 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 11815.912281 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 11815.912281 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22398.613893 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 22398.613893 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 22398.613893 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1186,519 +1186,519 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 262 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 262 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 296 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 296 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 296 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 160 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 299 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 344 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 344 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 344 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 344 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 167 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 57 # number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1125015 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1125015 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1272489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1272489 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 378493 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 378493 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2397504 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2397504 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2397504 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2397504 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003595 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003595 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003826 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003826 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003826 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 7031.343750 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 7031.343750 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 12354.262136 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 12354.262136 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6640.228070 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6640.228070 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 9115.984791 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 9115.984791 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_misses::cpu1.data 275 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 275 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 275 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1943270 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1943270 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1707489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1707489 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 587993 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 587993 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3650759 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3650759 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3650759 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3650759 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003820 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003820 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003177 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003177 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.826087 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.826087 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003539 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003539 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003539 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11636.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11636.347305 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15810.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15810.083333 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 10315.666667 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 10315.666667 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13275.487273 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13275.487273 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 388 # number of replacements -system.cpu1.icache.tags.tagsinuse 76.215682 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 24292 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 48.779116 # Average number of references to valid blocks. +system.cpu1.icache.tags.replacements 385 # number of replacements +system.cpu1.icache.tags.tagsinuse 83.683741 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 21045 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 497 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 42.344064 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 76.215682 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.148859 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.148859 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id +system.cpu1.icache.tags.occ_blocks::cpu1.inst 83.683741 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.163445 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.163445 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 25352 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 25352 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 24292 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 24292 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 24292 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 24292 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 24292 # number of overall hits -system.cpu1.icache.overall_hits::total 24292 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 562 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 562 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 562 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 562 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 562 # number of overall misses -system.cpu1.icache.overall_misses::total 562 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7960746 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7960746 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7960746 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7960746 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7960746 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7960746 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 24854 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 24854 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 24854 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 24854 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 24854 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 24854 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022612 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.022612 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022612 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.022612 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022612 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.022612 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14165.028470 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14165.028470 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14165.028470 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14165.028470 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14165.028470 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2 # number of cycles access was blocked +system.cpu1.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 22120 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 22120 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 21045 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 21045 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 21045 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 21045 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 21045 # number of overall hits +system.cpu1.icache.overall_hits::total 21045 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 578 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 578 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 578 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 578 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 578 # number of overall misses +system.cpu1.icache.overall_misses::total 578 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14251747 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14251747 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14251747 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14251747 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14251747 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14251747 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 21623 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 21623 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 21623 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 21623 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 21623 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 21623 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026731 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.026731 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026731 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.026731 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026731 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.026731 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24657.001730 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24657.001730 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24657.001730 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24657.001730 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24657.001730 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 114 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 2 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 57 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 64 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 64 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 64 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 64 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 498 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 498 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 498 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6368004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6368004 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6368004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6368004 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6368004 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6368004 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.020037 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.020037 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.020037 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.020037 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12787.156627 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12787.156627 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12787.156627 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 81 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 81 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 81 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 81 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 497 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 497 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 497 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 497 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 497 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 497 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11245503 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11245503 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11245503 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11245503 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11245503 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11245503 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022985 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022985 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022985 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022985 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22626.766600 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22626.766600 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 22626.766600 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 55295 # Number of BP lookups -system.cpu2.branchPred.condPredicted 51520 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1304 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 47890 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 46487 # Number of BTB hits +system.cpu2.branchPred.lookups 51309 # Number of BP lookups +system.cpu2.branchPred.condPredicted 47950 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1280 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 43975 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 43053 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 97.070370 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.903354 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 160375 # number of cpu cycles simulated +system.cpu2.numCycles 161860 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28879 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 309014 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 55295 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 47386 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 123906 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2765 # Number of cycles fetch has spent squashing -system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.icacheStallCycles 31583 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 282068 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 51309 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 43939 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 125716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2717 # Number of cycles fetch has spent squashing +system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1110 # Number of stall cycles due to pending traps -system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 19451 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 461 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 155294 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.989864 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.243889 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1207 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 22884 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 412 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 159877 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.764281 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.167875 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 49501 31.88% 31.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 52893 34.06% 65.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5338 3.44% 69.37% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3457 2.23% 71.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 949 0.61% 72.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 36899 23.76% 95.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1216 0.78% 96.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 841 0.54% 97.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 4200 2.70% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 59518 37.23% 37.23% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 51095 31.96% 69.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7306 4.57% 73.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3438 2.15% 75.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 997 0.62% 76.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 31616 19.78% 96.31% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1254 0.78% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 769 0.48% 97.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3884 2.43% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 155294 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.344786 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.926822 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17746 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 46456 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 86830 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 2870 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1382 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 293603 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1382 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 18442 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 20397 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 12871 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 87967 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14225 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 290431 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 12472 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 29 # Number of times rename has blocked due to LQ full -system.cpu2.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 205748 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 562377 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 437048 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 190737 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 15011 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1169 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1232 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 18731 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 82610 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 39860 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 38981 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34721 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 242796 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 5190 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 242904 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 29 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13134 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12157 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 612 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 155294 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.564156 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.378675 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 159877 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.316996 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.742667 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17468 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 61085 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 76240 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 3716 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1358 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 267722 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1358 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18170 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 29188 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12834 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 77782 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 20535 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 264399 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 18336 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full +system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 185298 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 503121 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 392507 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 170476 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 14822 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1180 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 25168 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 73362 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 34382 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 35300 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 29228 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 218628 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 6983 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 220497 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13020 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 12313 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 622 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 159877 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.379166 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.379581 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 52943 34.09% 34.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 18212 11.73% 45.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39071 25.16% 70.98% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38654 24.89% 95.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3479 2.24% 98.11% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1594 1.03% 99.14% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 891 0.57% 99.71% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 244 0.16% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 206 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 63376 39.64% 39.64% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 23374 14.62% 54.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33553 20.99% 75.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 33206 20.77% 96.02% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3423 2.14% 98.16% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1623 1.02% 99.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 877 0.55% 99.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 230 0.14% 99.87% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 215 0.13% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 155294 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 159877 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 90 25.64% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 25.64% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 52 14.81% 40.46% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 59.54% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 86 23.69% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.69% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 68 18.73% 42.42% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 118122 48.63% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.63% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 85639 35.26% 83.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 39143 16.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 108751 49.32% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.32% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 78120 35.43% 84.75% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 33626 15.25% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 242904 # Type of FU issued -system.cpu2.iq.rate 1.514600 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 351 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001445 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 641482 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 261162 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 241189 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 220497 # Type of FU issued +system.cpu2.iq.rate 1.362270 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 363 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001646 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 601287 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 238674 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 218768 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 243255 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 220860 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34438 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 28926 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2866 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2863 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1666 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1691 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1382 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6074 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 287692 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 198 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 82610 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 39860 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1098 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1358 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 8128 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 261616 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 204 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 73362 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 34382 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 470 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1074 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1544 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 241779 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 81452 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1125 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1045 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1500 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 219377 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 72164 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1120 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 39706 # number of nop insts executed -system.cpu2.iew.exec_refs 120488 # number of memory reference insts executed -system.cpu2.iew.exec_branches 49059 # Number of branches executed -system.cpu2.iew.exec_stores 39036 # Number of stores executed -system.cpu2.iew.exec_rate 1.507585 # Inst execution rate -system.cpu2.iew.wb_sent 241491 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 241189 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 138145 # num instructions producing a value -system.cpu2.iew.wb_consumers 144798 # num instructions consuming a value +system.cpu2.iew.exec_nop 36005 # number of nop insts executed +system.cpu2.iew.exec_refs 105679 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45327 # Number of branches executed +system.cpu2.iew.exec_stores 33515 # Number of stores executed +system.cpu2.iew.exec_rate 1.355350 # Inst execution rate +system.cpu2.iew.wb_sent 219089 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 218768 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 123331 # num instructions producing a value +system.cpu2.iew.wb_consumers 129941 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.503906 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.954053 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.351588 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.949131 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 14779 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 4578 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1304 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 152612 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.787933 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.101313 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 14642 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 6361 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1280 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 157221 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.570534 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.031430 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 57189 37.47% 37.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 45780 30.00% 67.47% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5178 3.39% 70.86% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5403 3.54% 74.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1516 0.99% 75.40% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34396 22.54% 97.94% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 886 0.58% 98.52% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 957 0.63% 99.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1307 0.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 69336 44.10% 44.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 41971 26.70% 70.80% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5151 3.28% 74.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7156 4.55% 78.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1534 0.98% 79.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28975 18.43% 98.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 827 0.53% 98.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 961 0.61% 99.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1310 0.83% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 152612 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 272860 # Number of instructions committed -system.cpu2.commit.committedOps 272860 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 157221 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 246921 # Number of instructions committed +system.cpu2.commit.committedOps 246921 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 117938 # Number of memory references committed -system.cpu2.commit.loads 79744 # Number of loads committed -system.cpu2.commit.membars 3865 # Number of memory barriers committed -system.cpu2.commit.branches 48024 # Number of branches committed +system.cpu2.commit.refs 103190 # Number of memory references committed +system.cpu2.commit.loads 70499 # Number of loads committed +system.cpu2.commit.membars 5644 # Number of memory barriers committed +system.cpu2.commit.branches 44296 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 188084 # Number of committed integer instructions. +system.cpu2.commit.int_insts 169605 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 38815 14.23% 14.23% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 112242 41.14% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.36% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 83609 30.64% 86.00% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 38194 14.00% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 35083 14.21% 14.21% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 103004 41.72% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.92% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 76143 30.84% 86.76% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 32691 13.24% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 272860 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1307 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 246921 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1310 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 438358 # The number of ROB reads -system.cpu2.rob.rob_writes 577962 # The number of ROB writes -system.cpu2.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5081 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 43644 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 230180 # Number of Instructions Simulated -system.cpu2.committedOps 230180 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.696737 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.696737 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.435261 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.435261 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 421380 # number of integer regfile reads -system.cpu2.int_regfile_writes 197053 # number of integer regfile writes +system.cpu2.rob.rob_reads 416888 # The number of ROB reads +system.cpu2.rob.rob_writes 525783 # The number of ROB writes +system.cpu2.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1983 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 46662 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 206194 # Number of Instructions Simulated +system.cpu2.committedOps 206194 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.784989 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.784989 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.273903 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.273903 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 376797 # number of integer regfile reads +system.cpu2.int_regfile_writes 176595 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 122100 # number of misc regfile reads +system.cpu2.misc_regfile_reads 107278 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 25.900864 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 44302 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1582.214286 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 24.051885 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 38880 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1340.689655 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.900864 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050588 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.050588 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.051885 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.046976 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.046976 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 341013 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 341013 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 46548 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 46548 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 37978 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 37978 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 84526 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 84526 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 84526 # number of overall hits -system.cpu2.dcache.overall_hits::total 84526 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 448 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 448 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 149 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 149 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 597 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 597 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 597 # number of overall misses -system.cpu2.dcache.overall_misses::total 597 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7705986 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 7705986 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3669012 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 3669012 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 505508 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 505508 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 11374998 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 11374998 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 11374998 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 11374998 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 46996 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 46996 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 38127 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 38127 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 85123 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 85123 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 85123 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 85123 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009533 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009533 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.003908 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.003908 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.820896 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.820896 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007013 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007013 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007013 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007013 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17200.861607 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17200.861607 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24624.241611 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 24624.241611 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9191.054545 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 9191.054545 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 19053.597990 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 19053.597990 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 19053.597990 # average overall miss latency +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 303893 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 303893 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 42781 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42781 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 32487 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 32487 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 75268 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 75268 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 75268 # number of overall hits +system.cpu2.dcache.overall_hits::total 75268 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 440 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 440 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 133 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 133 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 57 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 573 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 573 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 573 # number of overall misses +system.cpu2.dcache.overall_misses::total 573 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7341783 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 7341783 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2962762 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2962762 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 594005 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 594005 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 10304545 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 10304545 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 10304545 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 10304545 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 43221 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 43221 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 32620 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 32620 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 75841 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 75841 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 75841 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 75841 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010180 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010180 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004077 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004077 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.802817 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007555 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007555 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007555 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007555 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16685.870455 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16685.870455 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22276.406015 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 22276.406015 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10421.140351 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 10421.140351 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17983.499127 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17983.499127 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17983.499127 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1707,519 +1707,518 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 289 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 289 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 41 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 41 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 330 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 330 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 55 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1526276 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1526276 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1511738 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1511738 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 395492 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 395492 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3038014 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3038014 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3038014 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3038014 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003383 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003383 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002833 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002833 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.820896 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.820896 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003137 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003137 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003137 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9599.220126 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9599.220126 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13997.574074 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13997.574074 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7190.763636 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7190.763636 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11378.329588 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11378.329588 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 285 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 285 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 31 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 31 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 316 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 316 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 316 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 316 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 155 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 102 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 57 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 257 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 257 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 257 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1424773 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1424773 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1555988 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1555988 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 508495 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 508495 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2980761 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2980761 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2980761 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2980761 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003586 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003586 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003127 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003127 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003389 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003389 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003389 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 9192.083871 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 9192.083871 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15254.784314 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15254.784314 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8920.964912 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8920.964912 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 11598.291829 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 11598.291829 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.tags.replacements 378 # number of replacements -system.cpu2.icache.tags.tagsinuse 84.872672 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 18881 # Total number of references to valid blocks. -system.cpu2.icache.tags.sampled_refs 490 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 38.532653 # Average number of references to valid blocks. +system.cpu2.icache.tags.replacements 384 # number of replacements +system.cpu2.icache.tags.tagsinuse 78.035025 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 22324 # Total number of references to valid blocks. +system.cpu2.icache.tags.sampled_refs 494 # Sample count of references to valid blocks. +system.cpu2.icache.tags.avg_refs 45.190283 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 84.872672 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.165767 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.165767 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_task_id_blocks::1024 112 # Occupied blocks per task id +system.cpu2.icache.tags.occ_blocks::cpu2.inst 78.035025 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.152412 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.152412 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_task_id_blocks::1024 110 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu2.icache.tags.age_task_id_blocks_1024::1 101 # Occupied blocks per task id -system.cpu2.icache.tags.occ_task_id_percent::1024 0.218750 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 19941 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 19941 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 18881 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 18881 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 18881 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 18881 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 18881 # number of overall hits -system.cpu2.icache.overall_hits::total 18881 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 570 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 570 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 570 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 570 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 570 # number of overall misses -system.cpu2.icache.overall_misses::total 570 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 13340243 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 13340243 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 13340243 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 13340243 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 13340243 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 13340243 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 19451 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 19451 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 19451 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 19451 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 19451 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 19451 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.029304 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.029304 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.029304 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.029304 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.029304 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.029304 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 23403.935088 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 23403.935088 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 23403.935088 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 23403.935088 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 23403.935088 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked +system.cpu2.icache.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id +system.cpu2.icache.tags.occ_task_id_percent::1024 0.214844 # Percentage of cache occupancy per task id +system.cpu2.icache.tags.tag_accesses 23378 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 23378 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 22324 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 22324 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 22324 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 22324 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 22324 # number of overall hits +system.cpu2.icache.overall_hits::total 22324 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 560 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 560 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 560 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 560 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 560 # number of overall misses +system.cpu2.icache.overall_misses::total 560 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8454990 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8454990 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8454990 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8454990 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8454990 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8454990 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 22884 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 22884 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 22884 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 22884 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 22884 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 22884 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.024471 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.024471 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.024471 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.024471 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.024471 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.024471 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15098.196429 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 15098.196429 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 15098.196429 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15098.196429 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 15098.196429 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 42.666667 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 80 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 80 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 80 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 80 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 490 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 490 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 490 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 490 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 490 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10370006 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 10370006 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10370006 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 10370006 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10370006 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 10370006 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.025192 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.025192 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.025192 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.025192 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21163.277551 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21163.277551 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 21163.277551 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 66 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 66 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 66 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 66 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 494 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 494 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 494 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 494 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 494 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 494 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6668508 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6668508 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6668508 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6668508 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6668508 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6668508 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021587 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.021587 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021587 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.021587 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13499.004049 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13499.004049 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13499.004049 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 49708 # Number of BP lookups -system.cpu3.branchPred.condPredicted 46346 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 42456 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 41477 # Number of BTB hits +system.cpu3.branchPred.lookups 49957 # Number of BP lookups +system.cpu3.branchPred.condPredicted 46526 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1263 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 42773 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 41661 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.694083 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 887 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.400229 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 886 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 160031 # number of cpu cycles simulated +system.cpu3.numCycles 161075 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 32677 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 271496 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 49708 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 42364 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 123781 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2713 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 32422 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 272949 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 49957 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 42547 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 124988 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2685 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1129 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 23830 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 414 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 158956 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.707995 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.148637 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1170 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 23669 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 411 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 159935 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.706625 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.149562 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 61281 38.55% 38.55% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 50034 31.48% 70.03% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7755 4.88% 74.91% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3467 2.18% 77.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 1003 0.63% 77.72% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 29472 18.54% 96.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1313 0.83% 97.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 747 0.47% 97.56% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3884 2.44% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 61940 38.73% 38.73% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 50129 31.34% 70.07% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 7684 4.80% 74.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3433 2.15% 77.02% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 1026 0.64% 77.66% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 29810 18.64% 96.30% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1265 0.79% 97.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 775 0.48% 97.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3873 2.42% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 158956 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.310615 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.696521 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17592 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 63734 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 72321 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 3943 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1356 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 257189 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1356 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18288 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 30790 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12415 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 73229 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 22868 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 253914 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 19808 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 26 # Number of times rename has blocked due to LQ full -system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 177532 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 480099 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 375267 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 162743 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 14789 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1176 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1243 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 27539 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69653 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 32298 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33633 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 27116 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 209239 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7471 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 211679 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 49 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 13005 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11959 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 663 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 158956 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.331683 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.377458 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 159935 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.310147 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.694546 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17524 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 64435 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 72722 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3902 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1342 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 258692 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1342 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18198 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 31170 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12771 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 73832 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 22612 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 255419 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 19775 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 23 # Number of times rename has blocked due to LQ full +system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers +system.cpu3.rename.RenamedOperands 178600 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 483471 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 377749 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 164114 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14486 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1167 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1234 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 27248 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 70256 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 32624 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 33902 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 27488 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 210626 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 7365 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 213102 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 40 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 12659 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11687 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 617 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 159935 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.332429 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.375890 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 65156 40.99% 40.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 24774 15.59% 56.58% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 31508 19.82% 76.40% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 31138 19.59% 95.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3432 2.16% 98.15% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1609 1.01% 99.16% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 879 0.55% 99.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 252 0.16% 99.87% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 208 0.13% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 65625 41.03% 41.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 24603 15.38% 56.42% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 31869 19.93% 76.34% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 31495 19.69% 96.03% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3384 2.12% 98.15% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1646 1.03% 99.18% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 880 0.55% 99.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 234 0.15% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 199 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 158956 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 159935 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 91 25.07% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 25.07% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 63 17.36% 42.42% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 57.58% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 83 23.71% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 23.71% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 58 16.57% 40.29% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 59.71% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 105163 49.68% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 74926 35.40% 85.08% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 31590 14.92% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 105687 49.59% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 75490 35.42% 85.02% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 31925 14.98% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 211679 # Type of FU issued -system.cpu3.iq.rate 1.322737 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 363 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001715 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 582726 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 229757 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 209929 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 213102 # Type of FU issued +system.cpu3.iq.rate 1.322999 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 350 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001642 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 586529 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 230693 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 211399 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 212042 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 213452 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 26876 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 27230 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2797 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2740 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1652 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1625 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1356 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 8047 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 61 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 251105 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69653 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 32298 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1093 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewSquashCycles 1342 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 8471 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 252649 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 168 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 70256 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 32624 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1081 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 42 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 461 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1042 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 210537 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 68521 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1142 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 43 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 466 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1012 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1478 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 211973 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 69143 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1129 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34395 # number of nop insts executed -system.cpu3.iew.exec_refs 99995 # number of memory reference insts executed -system.cpu3.iew.exec_branches 43728 # Number of branches executed -system.cpu3.iew.exec_stores 31474 # Number of stores executed -system.cpu3.iew.exec_rate 1.315601 # Inst execution rate -system.cpu3.iew.wb_sent 210248 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 209929 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 117676 # num instructions producing a value -system.cpu3.iew.wb_consumers 124324 # num instructions consuming a value +system.cpu3.iew.exec_nop 34658 # number of nop insts executed +system.cpu3.iew.exec_refs 100953 # number of memory reference insts executed +system.cpu3.iew.exec_branches 44015 # Number of branches executed +system.cpu3.iew.exec_stores 31810 # Number of stores executed +system.cpu3.iew.exec_rate 1.315989 # Inst execution rate +system.cpu3.iew.wb_sent 211700 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 211399 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 118601 # num instructions producing a value +system.cpu3.iew.wb_consumers 125234 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.311802 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.946527 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.312426 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.947035 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 14613 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 6808 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 156309 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.512638 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.007092 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 14249 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 6748 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1263 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157342 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.514834 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.009338 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 71539 45.77% 45.77% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 40455 25.88% 71.65% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5161 3.30% 74.95% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 7618 4.87% 79.82% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1540 0.99% 80.81% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 26903 17.21% 98.02% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 829 0.53% 98.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 953 0.61% 99.16% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1311 0.84% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 72048 45.79% 45.79% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 40652 25.84% 71.63% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5170 3.29% 74.91% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 7572 4.81% 79.73% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1532 0.97% 80.70% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 27266 17.33% 98.03% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 833 0.53% 98.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 969 0.62% 99.17% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1300 0.83% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 156309 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 236439 # Number of instructions committed -system.cpu3.commit.committedOps 236439 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157342 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 238347 # Number of instructions committed +system.cpu3.commit.committedOps 238347 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 97502 # Number of memory references committed -system.cpu3.commit.loads 66856 # Number of loads committed -system.cpu3.commit.membars 6091 # Number of memory barriers committed -system.cpu3.commit.branches 42698 # Number of branches committed +system.cpu3.commit.refs 98515 # Number of memory references committed +system.cpu3.commit.loads 67516 # Number of loads committed +system.cpu3.commit.membars 6034 # Number of memory barriers committed +system.cpu3.commit.branches 42994 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 162319 # Number of committed integer instructions. +system.cpu3.commit.int_insts 163632 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 33485 14.16% 14.16% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 99361 42.02% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.19% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 72947 30.85% 87.04% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 30646 12.96% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 33784 14.17% 14.17% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 100014 41.96% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.14% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 73550 30.86% 86.99% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 30999 13.01% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 236439 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1311 # number cycles where commit BW limit reached +system.cpu3.commit.op_class_0::total 238347 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1300 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 405464 # The number of ROB reads -system.cpu3.rob.rob_writes 504751 # The number of ROB writes -system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1075 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 43988 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 196863 # Number of Instructions Simulated -system.cpu3.committedOps 196863 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 0.812905 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.812905 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.230155 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.230155 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 359772 # number of integer regfile reads -system.cpu3.int_regfile_writes 168916 # number of integer regfile writes +system.cpu3.rob.rob_reads 408052 # The number of ROB reads +system.cpu3.rob.rob_writes 507784 # The number of ROB writes +system.cpu3.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1140 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 47445 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 198529 # Number of Instructions Simulated +system.cpu3.committedOps 198529 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.811342 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.811342 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.232525 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.232525 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 362535 # number of integer regfile reads +system.cpu3.int_regfile_writes 170128 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 101608 # number of misc regfile reads +system.cpu3.misc_regfile_reads 102551 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 24.432858 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 36837 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 1270.241379 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 23.026048 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 37058 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1323.500000 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.432858 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047720 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.047720 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.026048 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.044973 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.044973 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 289352 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 289352 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 41209 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41209 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 30434 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 30434 # number of WriteReq hits +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 291822 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 291822 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 41456 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41456 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 30794 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 30794 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 71643 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 71643 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 71643 # number of overall hits -system.cpu3.dcache.overall_hits::total 71643 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 419 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 419 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 141 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 141 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 560 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 560 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 560 # number of overall misses -system.cpu3.dcache.overall_misses::total 560 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5396537 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 5396537 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2783262 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2783262 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 481005 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 481005 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 8179799 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 8179799 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 8179799 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 8179799 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41628 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41628 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 30575 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 30575 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 72203 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 72203 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 72203 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 72203 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010065 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.010065 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004612 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004612 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007756 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007756 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007756 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007756 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12879.563246 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12879.563246 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19739.446809 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19739.446809 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 8438.684211 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 8438.684211 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 14606.783929 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14606.783929 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 14606.783929 # average overall miss latency +system.cpu3.dcache.demand_hits::cpu3.data 72250 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 72250 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 72250 # number of overall hits +system.cpu3.dcache.overall_hits::total 72250 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 440 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 440 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 137 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 577 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 577 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 577 # number of overall misses +system.cpu3.dcache.overall_misses::total 577 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7521134 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 7521134 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3020012 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3020012 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 589507 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 589507 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 10541146 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 10541146 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 10541146 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 10541146 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41896 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41896 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 30931 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 30931 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 72827 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 72827 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 72827 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 72827 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010502 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.010502 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004429 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004429 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007923 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.007923 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007923 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.007923 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17093.486364 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17093.486364 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22043.883212 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 22043.883212 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10916.796296 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 10916.796296 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18268.883882 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18268.883882 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18268.883882 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2228,106 +2227,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 259 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 259 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 288 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 288 # number of ReadReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 # number of WriteReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 293 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 293 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 293 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 293 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1078521 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1078521 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1312238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1312238 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 366995 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 366995 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2390759 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2390759 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2390759 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2390759 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003844 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003844 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003500 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003500 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003698 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003698 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003698 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6740.756250 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6740.756250 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 12263.906542 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12263.906542 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 6438.508772 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 6438.508772 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8954.153558 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8954.153558 # average overall mshr miss latency +system.cpu3.dcache.demand_mshr_hits::cpu3.data 322 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 322 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 322 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 322 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 152 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 103 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 255 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 255 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1429011 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1429011 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1527238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1527238 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 508493 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 508493 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2956249 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2956249 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2956249 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2956249 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003628 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003628 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003330 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003330 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003501 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003501 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003501 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 9401.388158 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 9401.388158 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14827.553398 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14827.553398 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9416.537037 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9416.537037 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 11593.133333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 11593.133333 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.tags.replacements 386 # number of replacements -system.cpu3.icache.tags.tagsinuse 78.630086 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 23274 # Total number of references to valid blocks. -system.cpu3.icache.tags.sampled_refs 495 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 47.018182 # Average number of references to valid blocks. +system.cpu3.icache.tags.replacements 387 # number of replacements +system.cpu3.icache.tags.tagsinuse 75.442206 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 23109 # Total number of references to valid blocks. +system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. +system.cpu3.icache.tags.avg_refs 46.403614 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 78.630086 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.153574 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.153574 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_task_id_blocks::1024 109 # Occupied blocks per task id +system.cpu3.icache.tags.occ_blocks::cpu3.inst 75.442206 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.147348 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.147348 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_task_id_blocks::1024 111 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id -system.cpu3.icache.tags.occ_task_id_percent::1024 0.212891 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 24325 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 24325 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 23274 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23274 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23274 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23274 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23274 # number of overall hits -system.cpu3.icache.overall_hits::total 23274 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 556 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 556 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 556 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 556 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 556 # number of overall misses -system.cpu3.icache.overall_misses::total 556 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7666496 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7666496 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7666496 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7666496 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7666496 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7666496 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 23830 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 23830 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 23830 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 23830 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 23830 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 23830 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023332 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.023332 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023332 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.023332 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023332 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.023332 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13788.661871 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13788.661871 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13788.661871 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13788.661871 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13788.661871 # average overall miss latency +system.cpu3.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id +system.cpu3.icache.tags.occ_task_id_percent::1024 0.216797 # Percentage of cache occupancy per task id +system.cpu3.icache.tags.tag_accesses 24167 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 24167 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 23109 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 23109 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 23109 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 23109 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 23109 # number of overall hits +system.cpu3.icache.overall_hits::total 23109 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 560 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 560 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 560 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 560 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 560 # number of overall misses +system.cpu3.icache.overall_misses::total 560 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7349496 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 7349496 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 7349496 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 7349496 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 7349496 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 7349496 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 23669 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 23669 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 23669 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 23669 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 23669 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 23669 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.023660 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.023660 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.023660 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.023660 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.023660 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.023660 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13124.100000 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13124.100000 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13124.100000 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13124.100000 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13124.100000 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2336,277 +2335,277 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 61 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 61 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 61 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 61 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 495 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 495 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 495 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 495 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 495 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 495 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5988753 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5988753 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5988753 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5988753 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5988753 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5988753 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.020772 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.020772 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.020772 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.020772 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12098.490909 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12098.490909 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12098.490909 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 62 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 62 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 62 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 62 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6152504 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6152504 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6152504 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6152504 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6152504 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6152504 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.021040 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.021040 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.021040 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.021040 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12354.425703 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12354.425703 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12354.425703 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 421.782597 # Cycle average of tags in use -system.l2c.tags.total_refs 1661 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 531 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 3.128060 # Average number of references to valid blocks. +system.l2c.tags.tagsinuse 421.791819 # Cycle average of tags in use +system.l2c.tags.total_refs 1669 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 536 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 3.113806 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.793367 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 288.136506 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.239710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 7.908939 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.685353 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 57.810668 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 5.358893 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2.126194 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.722968 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.783957 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 289.037601 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 57.982294 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 60.100309 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.287110 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 5.207527 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.713016 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.004391 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.675614 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.004397 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000889 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000882 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000082 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000032 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.004410 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000885 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000917 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000079 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000031 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.006436 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 531 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.008102 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 20025 # Number of tag accesses -system.l2c.tags.data_accesses 20025 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 248 # number of ReadReq hits +system.l2c.tags.occ_task_id_blocks::1024 536 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 348 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 137 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.008179 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 20118 # Number of tag accesses +system.l2c.tags.data_accesses 20118 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 251 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 483 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 409 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 489 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 414 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 481 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 491 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1661 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1669 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 248 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 251 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 483 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 409 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 414 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 481 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 491 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1661 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 248 # number of overall hits +system.l2c.demand_hits::total 1669 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 251 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 483 # number of overall hits -system.l2c.overall_hits::cpu1.data 11 # number of overall hits -system.l2c.overall_hits::cpu2.inst 409 # number of overall hits -system.l2c.overall_hits::cpu2.data 5 # number of overall hits -system.l2c.overall_hits::cpu3.inst 489 # number of overall hits +system.l2c.overall_hits::cpu1.inst 414 # number of overall hits +system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu2.inst 481 # number of overall hits +system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu3.inst 491 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1661 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 81 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 6 # number of ReadReq misses +system.l2c.overall_hits::total 1669 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 364 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 83 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 13 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 7 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 546 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 551 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 78 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 81 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 6 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 364 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 83 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 7 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 677 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 361 # number of overall misses -system.l2c.overall_misses::cpu0.data 168 # number of overall misses -system.l2c.overall_misses::cpu1.inst 15 # number of overall misses -system.l2c.overall_misses::cpu1.data 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 81 # number of overall misses -system.l2c.overall_misses::cpu2.data 20 # number of overall misses -system.l2c.overall_misses::cpu3.inst 6 # number of overall misses +system.l2c.demand_misses::total 682 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 364 # number of overall misses +system.l2c.overall_misses::cpu0.data 169 # number of overall misses +system.l2c.overall_misses::cpu1.inst 83 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 13 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 7 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 677 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 24898500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 5922000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 1027000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 5770000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 523250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 593000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 38883750 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 6920500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 837000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1047250 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 851750 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 9656500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 24898500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 12842500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 1027000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 912000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 5770000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1570500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 593000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 926750 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 48540250 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 24898500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 12842500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 1027000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 912000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 5770000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1570500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 593000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 926750 # number of overall miss cycles -system.l2c.overall_miss_latency::total 48540250 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 609 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 498 # number of ReadReq accesses(hits+misses) +system.l2c.overall_misses::total 682 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 27791500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 6004250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 6396000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 553250 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 1121000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 96750 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 495500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 82500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 42540750 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 8131000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 1125500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 956000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 926750 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 11139250 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 27791500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 14135250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 6396000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1678750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 1121000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1052750 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 495500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 1009250 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 53680000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 27791500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 14135250 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 6396000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1678750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 1121000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1052750 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 495500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1009250 # number of overall miss cycles +system.l2c.overall_miss_latency::total 53680000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 615 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 497 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 490 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 494 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 495 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 498 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2207 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2220 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 81 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 609 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 498 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 490 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 495 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 615 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 497 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 494 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 498 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2338 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 609 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 498 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 490 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 495 # number of overall (read+write) accesses +system.l2c.demand_accesses::total 2351 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 615 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 497 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 494 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 498 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2338 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.592775 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.030120 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.165306 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.012121 # miss rate for ReadReq accesses +system.l2c.overall_accesses::total 2351 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.591870 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.167002 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.026316 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.014056 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.247395 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::total 0.248198 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.962963 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.962025 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.592775 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.030120 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.165306 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.012121 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.591870 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.167002 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.026316 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.014056 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.289564 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.592775 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.030120 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.165306 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.012121 # miss rate for overall accesses +system.l2c.demand_miss_rate::total 0.290089 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.591870 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.167002 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.026316 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.014056 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.289564 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 68970.914127 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 80027.027027 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 68466.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 71234.567901 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 74750 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 98833.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 71215.659341 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 73622.340426 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 69750 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80557.692308 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 70979.166667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 73713.740458 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 68970.914127 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 68466.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 70153.846154 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 71234.567901 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 78525 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 98833.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 71288.461538 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 71699.039882 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 68970.914127 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 76443.452381 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 68466.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 70153.846154 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 71234.567901 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 78525 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 98833.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 71288.461538 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 71699.039882 # average overall miss latency +system.l2c.overall_miss_rate::total 0.290089 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 76350.274725 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 80056.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77060.240964 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 79035.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 86230.769231 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 96750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 70785.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 82500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 77206.442831 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 86500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 86576.923077 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 79666.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 77229.166667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 85032.442748 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 78709.677419 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 76350.274725 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 83640.532544 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 77060.240964 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 83937.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 86230.769231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 80980.769231 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 70785.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 77634.615385 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 78709.677419 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2617,219 +2616,219 @@ system.l2c.fast_writes 0 # nu system.l2c.cache_copies 0 # number of cache copies performed system.l2c.ReadReq_mshr_hits::cpu0.inst 1 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 12 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu0.inst 1 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::total 12 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 12 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 360 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 12 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 76 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 3 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 80 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 5 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 534 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 539 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu1.data 18 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 78 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 76 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 360 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 12 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 76 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 3 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 80 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 5 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 665 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 360 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 12 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 76 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 670 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 80 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 5 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 665 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 20340000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5009000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 701250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 4539000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 436250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 390250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 31540750 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 230023 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 180018 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 200020 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 170017 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 780078 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5761500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 687000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 888250 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 700750 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 8037500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 20340000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 10770500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 701250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 749500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 4539000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 1324500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 390250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 763250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 39578250 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 20340000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 10770500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 701250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 749500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 4539000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 1324500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 390250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 763250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 39578250 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 23217750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 5067250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 5227250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 465250 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 423750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 83750 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 339500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 70000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 34894500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 391522 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 320018 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 303517 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 337019 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 1352076 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6964500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 963500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 806000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 776750 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 9510750 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 23217750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 12031750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 5227250 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1428750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 423750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 889750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 339500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 846750 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 44405250 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 23217750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 12031750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 5227250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1428750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 423750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 889750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 339500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 846750 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 44405250 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.241957 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.242793 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.962963 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.962025 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284431 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.591133 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.024096 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.155102 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006061 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::total 0.284985 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.590244 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160966 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.014170 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284431 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 56500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67689.189189 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 62321.428571 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 59065.074906 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 61292.553191 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57250 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 68326.923077 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 58395.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 61354.961832 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 56500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 64110.119048 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58437.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 57653.846154 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 59723.684211 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66225 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 130083.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 58711.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 59516.165414 # average overall mshr miss latency +system.l2c.overall_mshr_miss_rate::total 0.284985 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67563.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 66464.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 83750 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 67900 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 70000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64739.332096 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17796.454545 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17778.777778 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 17853.941176 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 17737.842105 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17790.473684 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74090.425532 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74115.384615 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 67166.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 64729.166667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 72601.145038 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 63960.743802 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71193.786982 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65340.625000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71437.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 60535.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 68442.307692 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 67900 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 65134.615385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 66276.492537 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 534 # Transaction distribution -system.membus.trans_dist::ReadResp 533 # Transaction distribution -system.membus.trans_dist::UpgradeReq 274 # Transaction distribution -system.membus.trans_dist::UpgradeResp 78 # Transaction distribution -system.membus.trans_dist::ReadExReq 179 # Transaction distribution +system.membus.trans_dist::ReadReq 539 # Transaction distribution +system.membus.trans_dist::ReadResp 538 # Transaction distribution +system.membus.trans_dist::UpgradeReq 276 # Transaction distribution +system.membus.trans_dist::UpgradeResp 76 # Transaction distribution +system.membus.trans_dist::ReadExReq 171 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1729 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42496 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 42496 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 244 # Total snoops (count) -system.membus.snoop_fanout::samples 987 # Request fanout histogram +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1731 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1731 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 42816 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 240 # Total snoops (count) +system.membus.snoop_fanout::samples 986 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 986 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 987 # Request fanout histogram -system.membus.reqLayer0.occupancy 933500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 986 # Request fanout histogram +system.membus.reqLayer0.occupancy 941000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 6348672 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 6.0 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 2754 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2753 # Transaction distribution +system.membus.respLayer1.occupancy 3702674 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 3.4 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2762 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2761 # Transaction distribution system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 411 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 411 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1217 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 584 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 980 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 990 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5861 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38912 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11136 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31360 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31680 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.trans_dist::UpgradeReq 279 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 279 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 401 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 401 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1229 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 583 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 375 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 988 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 996 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5872 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39296 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 31616 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 149632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1023 # Total snoops (count) +system.toL2Bus.pkt_size::total 150464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1012 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3443 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram @@ -2847,23 +2846,23 @@ system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::total 3443 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1734981 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.occupancy 1736971 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2800749 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1466512 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 2243496 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1172003 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2220994 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1183494 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 1.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 2229247 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 2.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1196246 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 1.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 994999 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 532769 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 762997 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 438748 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 744992 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 415244 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 747996 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 406758 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 564228327..67fefac90 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,733 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 262793500 # Number of ticks simulated -final_tick 262793500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000260 # Number of seconds simulated +sim_ticks 260037500 # Number of ticks simulated +final_tick 260037500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1021127 # Simulator instruction rate (inst/s) -host_op_rate 1021105 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 404381057 # Simulator tick rate (ticks/s) -host_mem_usage 299844 # Number of bytes of host memory used -host_seconds 0.65 # Real time elapsed on the host -sim_insts 663567 # Number of instructions simulated -sim_ops 663567 # Number of ops (including micro ops) simulated +host_inst_rate 961598 # Simulator instruction rate (inst/s) +host_op_rate 961579 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 379344878 # Simulator tick rate (ticks/s) +host_mem_usage 302744 # Number of bytes of host memory used +host_seconds 0.69 # Real time elapsed on the host +sim_insts 659142 # Number of instructions simulated +sim_ops 659142 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3904 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3776 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 512 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3904 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 59 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 8 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 16 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 61 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69408109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40183642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14368696 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5357819 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 487074 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3653058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1948298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3896596 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139303293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69408109 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14368696 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 487074 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1948298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86212178 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69408109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40183642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14368696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5357819 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 487074 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3653058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1948298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3896596 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139303293 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 430 # Transaction distribution -system.membus.trans_dist::ReadResp 430 # Transaction distribution -system.membus.trans_dist::UpgradeReq 272 # Transaction distribution -system.membus.trans_dist::UpgradeResp 77 # Transaction distribution -system.membus.trans_dist::ReadExReq 208 # Transaction distribution -system.membus.trans_dist::ReadExResp 142 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 261 # Total snoops (count) -system.membus.snoop_fanout::samples 915 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 915 # Request fanout histogram -system.membus.reqLayer0.occupancy 852796 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 5420500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 2.1 # Layer utilization (%) +system.physmem.bw_read::cpu0.inst 70143729 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40609527 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1722828 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3691775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 15013219 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5660722 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 246118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3691775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 140779695 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 70143729 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1722828 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 15013219 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 246118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 87125895 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 70143729 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40609527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1722828 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3691775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 15013219 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5660722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 246118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3691775 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 140779695 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.046261 # Cycle average of tags in use -system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.889004 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.790402 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.207937 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 51.556867 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 6.123938 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1.773027 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.843763 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 1.030296 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.831027 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003537 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.000093 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000027 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005326 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 15709 # Number of tag accesses -system.l2c.tags.data_accesses 15709 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 182 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 300 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 354 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 8 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses -system.l2c.ReadReq_misses::total 450 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 66 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 23 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::total 592 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 285 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 66 # number of overall misses -system.l2c.overall_misses::cpu1.data 23 # number of overall misses -system.l2c.overall_misses::cpu2.inst 12 # number of overall misses -system.l2c.overall_misses::cpu2.data 16 # number of overall misses -system.l2c.overall_misses::cpu3.inst 9 # number of overall misses -system.l2c.overall_misses::cpu3.data 16 # number of overall misses -system.l2c.overall_misses::total 592 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 14927000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3451500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3434000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 418000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 595000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 103000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 465000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 104500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23498000 # number of ReadReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 5172500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 800500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 746000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 730500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7449500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 14927000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 8624000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3434000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1218500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 595000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 849000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 465000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 835000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30947500 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 14927000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 8624000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3434000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1218500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 595000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 849000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 465000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 835000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30947500 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52375.438596 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52295.454545 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52030.303030 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49583.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 51500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 51666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 52250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52217.777778 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52247.474747 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53366.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53285.714286 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52178.571429 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52461.267606 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52276.182432 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52375.438596 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52266.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52030.303030 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52978.260870 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 49583.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53062.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 51666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52187.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52276.182432 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.inst 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2.data 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3.inst 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.inst 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2.data 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.inst 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2.data 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 59 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 8 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.data 2 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 59 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 22 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 8 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.data 16 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 59 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 22 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 8 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.data 16 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11414500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2640000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 2368500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 320000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 80000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 17223000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 600499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 763992 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3084491 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3962500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 617000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 576500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5716000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 11414500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6602500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 2368500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 897000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 616500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 320000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 640000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22939000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 11414500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6602500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 2368500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 897000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 616500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 320000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 640000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22939000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.181818 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.021798 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.640000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40053.488372 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40033.266667 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40210.105263 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40058.324675 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40025.252525 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41133.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41178.571429 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40253.521127 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40050.877193 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40015.151515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40144.067797 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40772.727273 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41100 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40103.146853 # average overall mshr miss latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.toL2Bus.trans_dist::ReadReq 2225 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 355 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 352 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 401 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 4820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1037 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 2929 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 2929 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 2929 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1473490 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2101500 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1430481 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 1650488 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 1157483 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 1651988 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 1147981 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 1651999 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 0.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 1327473 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 0.5 # Layer utilization (%) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 525587 # number of cpu cycles simulated +system.cpu0.numCycles 520075 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158574 # Number of instructions committed -system.cpu0.committedOps 158574 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 109208 # Number of integer alu accesses +system.cpu0.committedInsts 157392 # Number of instructions committed +system.cpu0.committedOps 157392 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108420 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 26032 # number of instructions that are conditional controls -system.cpu0.num_int_insts 109208 # number of integer instructions +system.cpu0.num_conditional_control_insts 25835 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108420 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 315782 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110814 # number of times the integer registers were written +system.cpu0.num_int_register_reads 313418 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110026 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 74021 # number of memory refs -system.cpu0.num_load_insts 49007 # Number of load instructions -system.cpu0.num_store_insts 25014 # Number of store instructions +system.cpu0.num_mem_refs 73430 # number of memory refs +system.cpu0.num_load_insts 48613 # Number of load instructions +system.cpu0.num_store_insts 24817 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 525586.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 520074.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26897 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23624 14.89% 14.89% # Class of executed instruction -system.cpu0.op_class::IntAlu 60907 38.39% 53.29% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction -system.cpu0.op_class::MemRead 49091 30.95% 84.23% # Class of executed instruction -system.cpu0.op_class::MemWrite 25014 15.77% 100.00% # Class of executed instruction +system.cpu0.Branches 26700 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23427 14.88% 14.88% # Class of executed instruction +system.cpu0.op_class::IntAlu 60513 38.43% 53.31% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction +system.cpu0.op_class::MemRead 48697 30.93% 84.24% # Class of executed instruction +system.cpu0.op_class::MemWrite 24817 15.76% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 158636 # Class of executed instruction -system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.401858 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 158170 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 338.693790 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.401858 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.414847 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 159104 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 159104 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 158170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 158170 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 158170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 158170 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 158170 # number of overall hits -system.cpu0.icache.overall_hits::total 158170 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18148000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18148000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18148000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18148000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18148000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18148000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158637 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158637 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158637 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158637 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38860.813704 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38860.813704 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38860.813704 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38860.813704 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38860.813704 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17214000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17214000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17214000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17214000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17214000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17214000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36860.813704 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36860.813704 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36860.813704 # average overall mshr miss latency -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.op_class::total 157454 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.571907 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73489 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.649829 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 72898 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 440.053892 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 436.514970 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.571907 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284320 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284320 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.649829 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284472 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.284472 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 296317 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 296317 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48827 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48827 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 293953 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 293953 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48433 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48433 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24583 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24583 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73607 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73607 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73607 # number of overall hits -system.cpu0.dcache.overall_hits::total 73607 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 73016 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73016 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73016 # number of overall hits +system.cpu0.dcache.overall_hits::total 73016 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses @@ -738,46 +154,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 353 # system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses system.cpu0.dcache.overall_misses::total 353 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4586981 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4586981 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6973000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 6973000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 360500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 360500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11559981 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11559981 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11559981 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11559981 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48997 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48997 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24963 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24963 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4637996 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4637996 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6976000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 6976000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11613996 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11613996 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11613996 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11613996 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48603 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48603 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24766 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24766 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73960 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73960 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73960 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73960 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003470 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003470 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007331 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007331 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73369 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73369 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73369 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73369 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003498 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003498 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007389 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007389 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004773 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004773 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004773 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004773 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 26982.241176 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 26982.241176 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38103.825137 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38103.825137 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 13865.384615 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32747.821530 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32747.821530 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32747.821530 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004811 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004811 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004811 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004811 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27282.329412 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27282.329412 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38120.218579 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38120.218579 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 32900.838527 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32900.838527 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 32900.838527 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -798,147 +214,355 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 353 system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4237019 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4237019 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6607000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6607000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 308500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10844019 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10844019 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10844019 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10844019 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003470 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003470 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007331 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007331 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4372004 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4372004 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6701500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6701500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11073504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11073504 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11073504 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11073504 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003498 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003498 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007389 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007389 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004773 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004773 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004773 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 24923.641176 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 24923.641176 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36103.825137 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36103.825137 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11865.384615 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30719.600567 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30719.600567 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004811 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004811 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004811 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25717.670588 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25717.670588 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36620.218579 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36620.218579 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12307.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12307.692308 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31369.699717 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31369.699717 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 525586 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 163471 # Number of instructions committed -system.cpu1.committedOps 163471 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 111731 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 29880 # number of instructions that are conditional controls -system.cpu1.num_int_insts 111731 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 289610 # number of times the integer registers were read -system.cpu1.num_int_register_writes 111151 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 58020 # number of memory refs -system.cpu1.num_load_insts 41540 # Number of load instructions -system.cpu1.num_store_insts 16480 # Number of store instructions -system.cpu1.num_idle_cycles 69346.869794 # Number of idle cycles -system.cpu1.num_busy_cycles 456239.130206 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868058 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131942 # Percentage of idle cycles -system.cpu1.Branches 31528 # Number of branches fetched -system.cpu1.op_class::No_OpClass 22316 13.65% 13.65% # Class of executed instruction -system.cpu1.op_class::IntAlu 75095 45.93% 59.58% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.58% # Class of executed instruction -system.cpu1.op_class::MemRead 49612 30.34% 89.92% # Class of executed instruction -system.cpu1.op_class::MemWrite 16480 10.08% 100.00% # Class of executed instruction -system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 163503 # Class of executed instruction -system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 70.017769 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 163138 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 445.732240 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 70.017769 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.136753 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 163870 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 163870 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 163138 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 163138 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 163138 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 163138 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 163138 # number of overall hits -system.cpu1.icache.overall_hits::total 163138 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu0.icache.tags.replacements 215 # number of replacements +system.cpu0.icache.tags.tagsinuse 212.581030 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 156988 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 336.162741 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.581030 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415197 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.415197 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 157922 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 157922 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 156988 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 156988 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 156988 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 156988 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 156988 # number of overall hits +system.cpu0.icache.overall_hits::total 156988 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses +system.cpu0.icache.overall_misses::total 467 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18041500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18041500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18041500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18041500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18041500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18041500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 157455 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 157455 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 157455 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 157455 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 157455 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 157455 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002966 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002966 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002966 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002966 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002966 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002966 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38632.762313 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38632.762313 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38632.762313 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38632.762313 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38632.762313 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17341000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17341000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17341000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17341000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17341000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17341000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002966 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002966 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002966 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002966 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37132.762313 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37132.762313 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 37132.762313 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 520075 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 168980 # Number of instructions committed +system.cpu1.committedOps 168980 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110320 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 637 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 33339 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110320 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 270098 # number of times the integer registers were read +system.cpu1.num_int_register_writes 102062 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_mem_refs 53149 # number of memory refs +system.cpu1.num_load_insts 40825 # Number of load instructions +system.cpu1.num_store_insts 12324 # Number of store instructions +system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles +system.cpu1.num_busy_cycles 452347.998260 # Number of busy cycles +system.cpu1.not_idle_fraction 0.869775 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.130225 # Percentage of idle cycles +system.cpu1.Branches 34992 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25772 15.25% 15.25% # Class of executed instruction +system.cpu1.op_class::IntAlu 74368 44.00% 59.25% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.25% # Class of executed instruction +system.cpu1.op_class::MemRead 56548 33.46% 92.71% # Class of executed instruction +system.cpu1.op_class::MemWrite 12324 7.29% 100.00% # Class of executed instruction +system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu1.op_class::total 169012 # Class of executed instruction +system.cpu1.dcache.tags.replacements 0 # number of replacements +system.cpu1.dcache.tags.tagsinuse 25.995164 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 26990 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 899.666667 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.995164 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050772 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050772 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 212815 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 212815 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 40655 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40655 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 12144 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 12144 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 52799 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 52799 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 52799 # number of overall hits +system.cpu1.dcache.overall_hits::total 52799 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 162 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 270 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 270 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 270 # number of overall misses +system.cpu1.dcache.overall_misses::total 270 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2619475 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2619475 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1982498 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1982498 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 237000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 4601973 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 4601973 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 4601973 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 4601973 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 40817 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 40817 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 12252 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 12252 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 53069 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 53069 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 53069 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 53069 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003969 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003969 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008815 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008815 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005088 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005088 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005088 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005088 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16169.598765 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16169.598765 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18356.462963 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18356.462963 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4232.142857 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 17044.344444 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17044.344444 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 17044.344444 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 162 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2358525 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2358525 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1818502 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1818502 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 153000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4177027 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4177027 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4177027 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4177027 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003969 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003969 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008815 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008815 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005088 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005088 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005088 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14558.796296 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14558.796296 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16837.981481 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16837.981481 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2732.142857 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15470.470370 # average overall mshr miss latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 280 # number of replacements +system.cpu1.icache.tags.tagsinuse 65.697365 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 168647 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 460.784153 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 65.697365 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.128315 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.128315 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id +system.cpu1.icache.tags.tag_accesses 169379 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 169379 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 168647 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 168647 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 168647 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 168647 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 168647 # number of overall hits +system.cpu1.icache.overall_hits::total 168647 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7544488 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7544488 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7544488 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7544488 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7544488 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7544488 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 163504 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 163504 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 163504 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 163504 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 163504 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 163504 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002238 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002238 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002238 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002238 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002238 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002238 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20613.355191 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20613.355191 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20613.355191 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20613.355191 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20613.355191 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5333988 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5333988 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5333988 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5333988 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5333988 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5333988 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 169013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 169013 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 169013 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 169013 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 169013 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 169013 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002166 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002166 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002166 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002166 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002166 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002166 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14573.737705 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14573.737705 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14573.737705 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14573.737705 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14573.737705 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -953,259 +577,259 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6805512 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6805512 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6805512 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6805512 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6805512 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6805512 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002238 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002238 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002238 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002238 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18594.295082 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18594.295082 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18594.295082 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4778012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4778012 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4778012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4778012 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4778012 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4778012 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002166 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002166 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002166 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002166 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13054.677596 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13054.677596 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 13054.677596 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 27.720301 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 35348 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1178.266667 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 27.720301 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.054141 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.054141 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 232288 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 232288 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 41378 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 41378 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 16307 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 16307 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 57685 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 57685 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 57685 # number of overall hits -system.cpu1.dcache.overall_hits::total 57685 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 154 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 154 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 51 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 263 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 263 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 263 # number of overall misses -system.cpu1.dcache.overall_misses::total 263 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2494983 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2494983 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1979500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1979500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 209500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 209500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4474483 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4474483 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4474483 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4474483 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41532 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41532 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 16416 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 16416 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 57948 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 57948 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 57948 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 57948 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003708 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003708 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.006640 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.006640 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.822581 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004539 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004539 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004539 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004539 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16201.188312 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16201.188312 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18160.550459 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18160.550459 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4107.843137 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4107.843137 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17013.243346 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17013.243346 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17013.243346 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 51 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 263 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2170017 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2170017 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1761500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1761500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 107500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 107500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3931517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3931517 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3931517 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3931517 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003708 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003708 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.006640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.006640 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.822581 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.004539 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004539 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.004539 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14091.019481 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14091.019481 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16160.550459 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16160.550459 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2107.843137 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 2107.843137 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14948.733840 # average overall mshr miss latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 525586 # number of cpu cycles simulated +system.cpu2.numCycles 520075 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 164866 # Number of instructions committed -system.cpu2.committedOps 164866 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112988 # Number of integer alu accesses +system.cpu2.committedInsts 164869 # Number of instructions committed +system.cpu2.committedOps 164869 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110069 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 29949 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112988 # number of integer instructions +system.cpu2.num_conditional_control_insts 31409 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110069 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 294363 # number of times the integer registers were read -system.cpu2.num_int_register_writes 112900 # number of times the integer registers were written +system.cpu2.num_int_register_reads 276820 # number of times the integer registers were read +system.cpu2.num_int_register_writes 105549 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 59208 # number of memory refs -system.cpu2.num_load_insts 42171 # Number of load instructions -system.cpu2.num_store_insts 17037 # Number of store instructions -system.cpu2.num_idle_cycles 69603.869304 # Number of idle cycles -system.cpu2.num_busy_cycles 455982.130696 # Number of busy cycles -system.cpu2.not_idle_fraction 0.867569 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.132431 # Percentage of idle cycles -system.cpu2.Branches 31596 # Number of branches fetched -system.cpu2.op_class::No_OpClass 22386 13.58% 13.58% # Class of executed instruction -system.cpu2.op_class::IntAlu 75723 45.92% 59.50% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.50% # Class of executed instruction -system.cpu2.op_class::MemRead 49752 30.17% 89.67% # Class of executed instruction -system.cpu2.op_class::MemWrite 17037 10.33% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 54829 # number of memory refs +system.cpu2.num_load_insts 40701 # Number of load instructions +system.cpu2.num_store_insts 14128 # Number of store instructions +system.cpu2.num_idle_cycles 67985.001739 # Number of idle cycles +system.cpu2.num_busy_cycles 452089.998261 # Number of busy cycles +system.cpu2.not_idle_fraction 0.869278 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.130722 # Percentage of idle cycles +system.cpu2.Branches 33062 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23842 14.46% 14.46% # Class of executed instruction +system.cpu2.op_class::IntAlu 74244 45.02% 59.48% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::MemRead 52687 31.95% 91.43% # Class of executed instruction +system.cpu2.op_class::MemWrite 14128 8.57% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 164898 # Class of executed instruction +system.cpu2.op_class::total 164901 # Class of executed instruction +system.cpu2.dcache.tags.replacements 0 # number of replacements +system.cpu2.dcache.tags.tagsinuse 27.767003 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 30481 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1051.068966 # Average number of references to valid blocks. +system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.767003 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054232 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.054232 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 219531 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 219531 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40534 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40534 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 13949 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 13949 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 54483 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 54483 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 54483 # number of overall hits +system.cpu2.dcache.overall_hits::total 54483 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 159 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 267 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 267 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 267 # number of overall misses +system.cpu2.dcache.overall_misses::total 267 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2767480 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2767480 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2022500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2022500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 237000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 237000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 4789980 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4789980 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4789980 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4789980 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40693 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40693 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 14057 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 14057 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 54750 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 54750 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 54750 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 54750 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003907 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003907 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007683 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.007683 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004877 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004877 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004877 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004877 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17405.534591 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 17405.534591 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18726.851852 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18726.851852 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4232.142857 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4232.142857 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17940 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17940 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17940 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17940 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 159 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 267 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2514020 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2514020 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1860500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1860500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 153000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 153000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4374520 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 4374520 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4374520 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 4374520 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003907 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003907 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007683 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007683 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004877 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004877 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004877 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15811.446541 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15811.446541 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17226.851852 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17226.851852 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2732.142857 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2732.142857 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 16383.970037 # average overall mshr miss latency +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 67.625211 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164533 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 70.145256 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 164536 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 449.543716 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 449.551913 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 67.625211 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.132080 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.132080 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.145256 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137002 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.137002 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165265 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165265 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 164533 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164533 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164533 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164533 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164533 # number of overall hits -system.cpu2.icache.overall_hits::total 164533 # number of overall hits +system.cpu2.icache.tags.tag_accesses 165268 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 165268 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 164536 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 164536 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 164536 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 164536 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 164536 # number of overall hits +system.cpu2.icache.overall_hits::total 164536 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5251988 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5251988 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5251988 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5251988 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5251988 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5251988 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 164899 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 164899 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 164899 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 164899 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 164899 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 164899 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7445997 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7445997 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7445997 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7445997 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7445997 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7445997 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 164902 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 164902 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 164902 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 164902 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 164902 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 164902 # number of overall (read+write) accesses system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002220 # miss rate for ReadReq accesses system.cpu2.icache.ReadReq_miss_rate::total 0.002220 # miss rate for ReadReq accesses system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002220 # miss rate for demand accesses system.cpu2.icache.demand_miss_rate::total 0.002220 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002220 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.002220 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14349.693989 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14349.693989 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14349.693989 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14349.693989 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14349.693989 # average overall miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20344.254098 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 20344.254098 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 20344.254098 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20344.254098 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 20344.254098 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1220,259 +844,259 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 4510012 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 4510012 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4510012 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 4510012 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4510012 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 4510012 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6894003 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6894003 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6894003 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6894003 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6894003 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6894003 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002220 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.002220 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002220 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.002220 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12322.437158 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12322.437158 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12322.437158 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 18836.073770 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18836.073770 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 18836.073770 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 26.763988 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 36347 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1253.344828 # Average number of references to valid blocks. -system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.763988 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.052273 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.052273 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 237038 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 237038 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 42011 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42011 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 16865 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 16865 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 10 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58876 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58876 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58876 # number of overall hits -system.cpu2.dcache.overall_hits::total 58876 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 152 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 152 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 50 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 50 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 262 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 262 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 262 # number of overall misses -system.cpu2.dcache.overall_misses::total 262 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2128981 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2128981 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1929500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 1929500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 204500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 204500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4058481 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4058481 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4058481 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4058481 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42163 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42163 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16975 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16975 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 60 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 60 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 59138 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 59138 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 59138 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 59138 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003605 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003605 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006480 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006480 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004430 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004430 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004430 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004430 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 14006.453947 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 14006.453947 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17540.909091 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17540.909091 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4090 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4090 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 15490.385496 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15490.385496 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 15490.385496 # average overall miss latency -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 152 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 110 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 110 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 50 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1809019 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1809019 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1709500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1709500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 104500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 104500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3518519 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3518519 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3518519 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3518519 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003605 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003605 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006480 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006480 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.833333 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.833333 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004430 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004430 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004430 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11901.440789 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 11901.440789 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15540.909091 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15540.909091 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2090 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2090 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13429.461832 # average overall mshr miss latency -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 525586 # number of cpu cycles simulated +system.cpu3.numCycles 520075 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 176656 # Number of instructions committed -system.cpu3.committedOps 176656 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 108218 # Number of integer alu accesses +system.cpu3.committedInsts 167901 # Number of instructions committed +system.cpu3.committedOps 167901 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 110672 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 38223 # number of instructions that are conditional controls -system.cpu3.num_int_insts 108218 # number of integer instructions +system.cpu3.num_conditional_control_insts 32621 # number of instructions that are conditional controls +system.cpu3.num_int_insts 110672 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 242179 # number of times the integer registers were read -system.cpu3.num_int_register_writes 89182 # number of times the integer registers were written +system.cpu3.num_int_register_reads 274378 # number of times the integer registers were read +system.cpu3.num_int_register_writes 104026 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 46164 # number of memory refs -system.cpu3.num_load_insts 39753 # Number of load instructions -system.cpu3.num_store_insts 6411 # Number of store instructions -system.cpu3.num_idle_cycles 69867.868801 # Number of idle cycles -system.cpu3.num_busy_cycles 455718.131199 # Number of busy cycles -system.cpu3.not_idle_fraction 0.867067 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.132933 # Percentage of idle cycles -system.cpu3.Branches 39890 # Number of branches fetched -system.cpu3.op_class::No_OpClass 30652 17.35% 17.35% # Class of executed instruction -system.cpu3.op_class::IntAlu 73353 41.52% 58.86% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.86% # Class of executed instruction -system.cpu3.op_class::MemRead 66272 37.51% 96.37% # Class of executed instruction -system.cpu3.op_class::MemWrite 6411 3.63% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 54219 # number of memory refs +system.cpu3.num_load_insts 41000 # Number of load instructions +system.cpu3.num_store_insts 13219 # Number of store instructions +system.cpu3.num_idle_cycles 68239.001738 # Number of idle cycles +system.cpu3.num_busy_cycles 451835.998262 # Number of busy cycles +system.cpu3.not_idle_fraction 0.868790 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.131210 # Percentage of idle cycles +system.cpu3.Branches 34277 # Number of branches fetched +system.cpu3.op_class::No_OpClass 25056 14.92% 14.92% # Class of executed instruction +system.cpu3.op_class::IntAlu 74547 44.39% 59.31% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.31% # Class of executed instruction +system.cpu3.op_class::MemRead 55111 32.82% 92.13% # Class of executed instruction +system.cpu3.op_class::MemWrite 13219 7.87% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 176688 # Class of executed instruction +system.cpu3.op_class::total 167933 # Class of executed instruction +system.cpu3.dcache.tags.replacements 0 # number of replacements +system.cpu3.dcache.tags.tagsinuse 26.810589 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 28657 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 988.172414 # Average number of references to valid blocks. +system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.810589 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052364 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.052364 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 217093 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 217093 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40832 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40832 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 13038 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 13038 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 53870 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 53870 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 53870 # number of overall hits +system.cpu3.dcache.overall_hits::total 53870 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 160 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 160 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses +system.cpu3.dcache.overall_misses::total 268 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2513476 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2513476 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2024000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2024000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 244500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 244500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4537476 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4537476 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4537476 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4537476 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 40992 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 40992 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 13146 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 13146 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 54138 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 54138 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 54138 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 54138 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003903 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003903 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008215 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.008215 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.816901 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004950 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004950 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004950 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004950 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15709.225000 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 15709.225000 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18740.740741 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18740.740741 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4215.517241 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4215.517241 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 16930.880597 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16930.880597 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 16930.880597 # average overall miss latency +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2256524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2256524 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1862000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1862000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 157500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 157500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4118524 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4118524 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4118524 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4118524 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003903 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003903 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008215 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008215 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004950 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004950 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004950 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14103.275000 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 14103.275000 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17240.740741 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17240.740741 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2715.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2715.517241 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 15367.626866 # average overall mshr miss latency +system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 65.598702 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 176322 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 67.819588 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 167567 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 480.441417 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 456.585831 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.598702 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128122 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.128122 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 67.819588 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.132460 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.132460 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 177056 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 177056 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 176322 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 176322 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 176322 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 176322 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 176322 # number of overall hits -system.cpu3.icache.overall_hits::total 176322 # number of overall hits +system.cpu3.icache.tags.tag_accesses 168301 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 168301 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 167567 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 167567 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 167567 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 167567 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 167567 # number of overall hits +system.cpu3.icache.overall_hits::total 167567 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5147499 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5147499 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5147499 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5147499 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5147499 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5147499 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 176689 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 176689 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 176689 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 176689 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 176689 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 176689 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002077 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002077 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002077 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002077 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002077 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002077 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14025.882834 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14025.882834 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14025.882834 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14025.882834 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14025.882834 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5144490 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5144490 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5144490 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5144490 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5144490 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5144490 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 167934 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 167934 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 167934 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 167934 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 167934 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 167934 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002185 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002185 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002185 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002185 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002185 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002185 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14017.683924 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14017.683924 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14017.683924 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14017.683924 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14017.683924 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1487,148 +1111,524 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4412501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4412501 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4412501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4412501 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4412501 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4412501 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002077 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002077 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002077 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002077 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12023.163488 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12023.163488 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12023.163488 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4586010 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4586010 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4586010 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4586010 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4586010 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4586010 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002185 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002185 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002185 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002185 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12495.940054 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12495.940054 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12495.940054 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.915188 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 15020 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 517.931034 # Average number of references to valid blocks. -system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.915188 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050616 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050616 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 184905 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 184905 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 39563 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 39563 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 6216 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 6216 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 45779 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 45779 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 45779 # number of overall hits -system.cpu3.dcache.overall_hits::total 45779 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 183 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 183 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 69 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 69 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 288 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 288 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 288 # number of overall misses -system.cpu3.dcache.overall_misses::total 288 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3156473 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 3156473 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2099000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2099000 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 280000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 280000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 5255473 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 5255473 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 5255473 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 5255473 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 39746 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 39746 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 6321 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 6321 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 88 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 88 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 46067 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 46067 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 46067 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 46067 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.004604 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.016611 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.016611 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.784091 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.784091 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006252 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.006252 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006252 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.006252 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17248.486339 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 17248.486339 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19990.476190 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19990.476190 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4057.971014 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4057.971014 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 18248.170139 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18248.170139 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 18248.170139 # average overall miss latency -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 183 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 183 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 288 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 288 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 288 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 288 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2772527 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2772527 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1889000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1889000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 142000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 142000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4661527 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4661527 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4661527 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4661527 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.016611 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.016611 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.784091 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.784091 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.006252 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.006252 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.006252 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15150.420765 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15150.420765 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17990.476190 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17990.476190 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 2057.971014 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 2057.971014 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16185.857639 # average overall mshr miss latency -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 0 # number of replacements +system.l2c.tags.tagsinuse 349.350598 # Cycle average of tags in use +system.l2c.tags.total_refs 1220 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.843823 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 0.890412 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 231.950361 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.237281 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.226273 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.814088 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 47.344433 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.154120 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.888026 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.845603 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003539 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000095 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.000012 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000722 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005331 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 15709 # Number of tag accesses +system.l2c.tags.data_accesses 15709 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 352 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 302 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 3 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 302 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 182 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 352 # number of overall hits +system.l2c.overall_hits::cpu1.data 9 # number of overall hits +system.l2c.overall_hits::cpu2.inst 302 # number of overall hits +system.l2c.overall_hits::cpu2.data 3 # number of overall hits +system.l2c.overall_hits::cpu3.inst 358 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 64 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 8 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 9 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses +system.l2c.ReadReq_misses::total 450 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 17 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 77 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 15 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3.data 14 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 285 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 64 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.data 16 # number of demand (read+write) misses +system.l2c.demand_misses::total 592 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 285 # number of overall misses +system.l2c.overall_misses::cpu0.data 165 # number of overall misses +system.l2c.overall_misses::cpu1.inst 14 # number of overall misses +system.l2c.overall_misses::cpu1.data 16 # number of overall misses +system.l2c.overall_misses::cpu2.inst 64 # number of overall misses +system.l2c.overall_misses::cpu2.data 23 # number of overall misses +system.l2c.overall_misses::cpu3.inst 9 # number of overall misses +system.l2c.overall_misses::cpu3.data 16 # number of overall misses +system.l2c.overall_misses::total 592 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 14963000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 3465000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 714500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 104000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 3356500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 420000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 458000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 103500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 23584500 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5197500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 744000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 791500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 740000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7473000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 14963000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 8662500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 714500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 848000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 3356500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1211500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 458000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 843500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 31057500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 14963000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 8662500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 714500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 848000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 3356500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1211500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 458000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 843500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 31057500 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 79 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 15 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3.data 14 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 142 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 26 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.974684 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.174863 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.038251 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.174863 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.884615 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52501.754386 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51035.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 52445.312500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50888.888889 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 51750 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52410 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52500 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53142.857143 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52766.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52857.142857 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52626.760563 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 52500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51035.714286 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 53000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 52445.312500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52673.913043 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 50888.888889 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 52718.750000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52461.993243 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52501.754386 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 52500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51035.714286 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 53000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 52445.312500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52673.913043 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 50888.888889 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52718.750000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52461.993243 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.inst 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.inst 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3.data 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 20 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.inst 285 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 66 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 61 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 8 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 17 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 77 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 14 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 15 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3.data 14 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 142 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 285 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 165 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 61 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 23 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.data 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 572 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 285 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 165 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 61 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 23 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.data 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 572 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 11542500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 2673000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 283500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 2475000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 324000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 17419500 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1134000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 649996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 648000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 688500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3120496 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4009500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 575500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 611500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 571000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5767500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 11542500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6682500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 283500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 616000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 2475000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 935500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 40500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 611500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 23187000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 11542500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6682500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 283500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 616000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 2475000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 935500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 40500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 611500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 23187000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.727273 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.974684 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.166667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40510.465116 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40624.750000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40525.922078 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40500 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41107.142857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40766.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40785.714286 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40616.197183 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41066.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40573.770492 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40673.913043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40766.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40536.713287 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 430 # Transaction distribution +system.membus.trans_dist::ReadResp 430 # Transaction distribution +system.membus.trans_dist::UpgradeReq 272 # Transaction distribution +system.membus.trans_dist::UpgradeResp 77 # Transaction distribution +system.membus.trans_dist::ReadExReq 208 # Transaction distribution +system.membus.trans_dist::ReadExResp 142 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 261 # Total snoops (count) +system.membus.snoop_fanout::samples 914 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 914 # Request fanout histogram +system.membus.reqLayer0.occupancy 679142 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) +system.membus.respLayer1.occupancy 2961502 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.1 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 2217 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2217 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 934 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 732 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 734 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 4812 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1029 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2921 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 2921 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 2921 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1466989 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 503996 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 552488 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 431973 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 550497 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 423980 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 554490 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 428476 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index a27123aa4..4a7304d33 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,195 +1,195 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.001493 # Number of seconds simulated -sim_ticks 1493307500 # Number of ticks simulated -final_tick 1493307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000729 # Number of seconds simulated +sim_ticks 728722500 # Number of ticks simulated +final_tick 728722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 295462472 # Simulator tick rate (ticks/s) -host_mem_usage 222068 # Number of bytes of host memory used -host_seconds 5.05 # Real time elapsed on the host +host_tick_rate 162031375 # Simulator tick rate (ticks/s) +host_mem_usage 277108 # Number of bytes of host memory used +host_seconds 4.50 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 74794 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 78736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 78807 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 78188 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 77250 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 74477 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78325 # Number of bytes read from this memory -system.physmem.bytes_read::total 619989 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 384000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5518 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5402 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5514 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5530 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5340 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5402 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory -system.physmem.bytes_written::total 427483 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10974 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10915 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6000 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5518 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5402 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5400 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5514 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5530 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5340 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5402 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49483 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 50086134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 52725912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 52773458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 52358941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 51730806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 49873854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 53178599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 52450684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 415178388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 257147306 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 3695153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 3617473 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 3616134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 3692475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 3703189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 3575955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 3617473 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 3600732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 286265890 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 257147306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 53781288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 56343385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 56389592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 56051416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 55433995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 53449809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 56796072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 56051416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 701444277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 79470 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 78418 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 80729 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80022 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 80096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 78976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 78470 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 78262 # Number of bytes read from this memory +system.physmem.bytes_read::total 634443 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 400000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5381 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5473 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5390 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5494 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5433 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5395 # Number of bytes written to this memory +system.physmem.bytes_written::total 443379 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10873 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10934 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11041 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87540 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5381 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5473 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5390 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5494 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5433 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5395 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49629 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 109053858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 107610236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 110781539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 109811348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 109912896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 108375959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 107681593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 107396162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 870623591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 548905791 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7384155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 7470608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7510403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 7396506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 7367688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7539221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7455513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7403367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 608433251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 548905791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 116438013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 115080844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 118291942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 117207853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 117280583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 115915180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 115137106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 114799529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479056843 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99767 # number of read accesses completed -system.cpu0.num_writes 55259 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22696 # number of replacements -system.cpu0.l1c.tags.tagsinuse 395.365301 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13357 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 23083 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.578651 # Average number of references to valid blocks. +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 54791 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22240 # number of replacements +system.cpu0.l1c.tags.tagsinuse 394.087405 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13441 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.593789 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 395.365301 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.772198 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.772198 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 272 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 339665 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 339665 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8708 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8708 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1150 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1150 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9858 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9858 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9858 # number of overall hits -system.cpu0.l1c.overall_hits::total 9858 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36982 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36982 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23775 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23775 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60757 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60757 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60757 # number of overall misses -system.cpu0.l1c.overall_misses::total 60757 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 2501825237 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 2501825237 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1853114266 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1853114266 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 4354939503 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 4354939503 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 4354939503 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 4354939503 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45690 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45690 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24925 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24925 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70615 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70615 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70615 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70615 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809411 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.809411 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953862 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953862 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860398 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860398 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860398 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860398 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67649.809015 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 67649.809015 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 77943.817708 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 77943.817708 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 71677.987771 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 71677.987771 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 71677.987771 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 71677.987771 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 2197094 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 394.087405 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.769702 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.769702 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337290 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337290 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8682 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8682 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1111 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1111 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9793 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9793 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9793 # number of overall hits +system.cpu0.l1c.overall_hits::total 9793 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36727 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36727 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23639 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23639 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60366 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60366 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60366 # number of overall misses +system.cpu0.l1c.overall_misses::total 60366 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1016702315 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1016702315 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 918792240 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 918792240 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1935494555 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1935494555 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1935494555 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1935494555 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45409 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24750 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24750 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70159 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70159 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70159 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70159 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808804 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808804 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955111 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955111 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860417 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860417 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860417 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860417 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27682.694339 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 27682.694339 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38867.644147 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 38867.644147 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 32062.660355 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 32062.660355 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 32062.660355 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 32062.660355 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1074391 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 60506 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61970 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.312002 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.337276 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9747 # number of writebacks -system.cpu0.l1c.writebacks::total 9747 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36982 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36982 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23775 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23775 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60757 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60757 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60757 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60757 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2423727133 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2423727133 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1803343082 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1803343082 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 4227070215 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 4227070215 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4227070215 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 4227070215 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1077807594 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1077807594 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 4091615147 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 4091615147 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5169422741 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5169422741 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953862 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953862 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860398 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860398 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65538.022092 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65538.022092 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 75850.392513 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 75850.392513 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9656 # number of writebacks +system.cpu0.l1c.writebacks::total 9656 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36727 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36727 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23639 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23639 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60366 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60366 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60366 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60366 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 960514497 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 960514497 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 882874166 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 882874166 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1843388663 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1843388663 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1843388663 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1843388663 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 755586835 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 755586835 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1939842714 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1939842714 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2695429549 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2695429549 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808804 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808804 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955111 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955111 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860417 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860417 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26152.816647 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26152.816647 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37348.202800 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37348.202800 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 54988 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22397 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.796271 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13630 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22804 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.597702 # Average number of references to valid blocks. +system.cpu1.num_reads 99410 # number of read accesses completed +system.cpu1.num_writes 55132 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22295 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.820804 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13496 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22679 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.595088 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.796271 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.773040 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.773040 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 269 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338465 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338465 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8882 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8882 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1141 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1141 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 10023 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 10023 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 10023 # number of overall hits -system.cpu1.l1c.overall_hits::total 10023 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36639 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36639 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23767 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23767 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60406 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60406 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60406 # number of overall misses -system.cpu1.l1c.overall_misses::total 60406 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 2485954076 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 2485954076 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1862028208 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1862028208 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 4347982284 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 4347982284 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 4347982284 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 4347982284 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24908 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70429 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70429 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70429 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70429 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804881 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.804881 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954191 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954191 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857686 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857686 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857686 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857686 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67849.943394 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 67849.943394 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78345.109101 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 78345.109101 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 71979.311393 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 71979.311393 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 71979.311393 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 71979.311393 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 2202198 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.820804 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.769181 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.769181 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338268 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338268 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8726 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8726 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1171 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1171 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9897 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9897 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9897 # number of overall hits +system.cpu1.l1c.overall_hits::total 9897 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36573 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36573 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23897 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23897 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60470 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60470 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60470 # number of overall misses +system.cpu1.l1c.overall_misses::total 60470 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1020722242 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1020722242 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 921634198 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 921634198 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1942356440 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1942356440 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1942356440 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1942356440 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45299 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25068 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70367 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70367 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70367 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70367 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807369 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807369 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953287 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953287 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859352 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859352 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859352 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859352 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27909.174582 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 27909.174582 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38566.941373 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 38566.941373 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 32120.992889 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 32120.992889 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 32120.992889 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 32120.992889 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1066797 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 60277 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61607 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.534632 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.316165 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks -system.cpu1.l1c.writebacks::total 9809 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36639 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36639 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23767 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23767 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60406 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60406 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60406 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60406 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2408616840 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2408616840 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1812196150 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1812196150 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4220812990 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 4220812990 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4220812990 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 4220812990 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1084723149 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1084723149 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 4036922188 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 4036922188 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5121645337 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5121645337 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804881 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804881 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954191 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954191 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857686 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857686 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65739.153361 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65739.153361 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76248.417975 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76248.417975 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9694 # number of writebacks +system.cpu1.l1c.writebacks::total 9694 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36573 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36573 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23897 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23897 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60470 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60470 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60470 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60470 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 964784026 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 964784026 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 885327122 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 885327122 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1850111148 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1850111148 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1850111148 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1850111148 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 740106955 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740106955 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1954561172 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1954561172 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2694668127 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2694668127 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807369 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807369 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953287 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953287 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859352 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859352 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26379.679709 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26379.679709 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37047.626146 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37047.626146 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99645 # number of read accesses completed -system.cpu2.num_writes 55347 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22638 # number of replacements -system.cpu2.l1c.tags.tagsinuse 395.541236 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13666 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.593323 # Average number of references to valid blocks. +system.cpu2.num_reads 99274 # number of read accesses completed +system.cpu2.num_writes 54884 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22456 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.843880 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13581 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22857 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.594172 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 395.541236 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.772541 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.772541 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 271 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339287 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339287 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8844 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8844 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1130 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9974 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9974 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9974 # number of overall hits -system.cpu2.l1c.overall_hits::total 9974 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36761 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36761 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23865 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23865 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60626 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60626 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60626 # number of overall misses -system.cpu2.l1c.overall_misses::total 60626 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 2497854261 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 2497854261 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1869962350 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1869962350 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 4367816611 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 4367816611 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 4367816611 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 4367816611 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45605 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45605 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70600 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70600 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70600 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70600 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806074 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806074 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954791 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954791 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858725 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858725 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858725 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858725 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67948.485106 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 67948.485106 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78355.849571 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 78355.849571 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 72045.271187 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 72045.271187 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 72045.271187 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 72045.271187 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 2198319 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 393.843880 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.769226 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.769226 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 373 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337451 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337451 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8813 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8813 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1134 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1134 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9947 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9947 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9947 # number of overall hits +system.cpu2.l1c.overall_hits::total 9947 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36457 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36457 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23816 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23816 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60273 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60273 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60273 # number of overall misses +system.cpu2.l1c.overall_misses::total 60273 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1014308258 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1014308258 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 924910230 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 924910230 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1939218488 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1939218488 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1939218488 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1939218488 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45270 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45270 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24950 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70220 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70220 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70220 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70220 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805324 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805324 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954549 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954549 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858345 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858345 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858345 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858345 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27822.043997 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 27822.043997 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38835.666359 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 38835.666359 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 32173.916812 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 32173.916812 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 32173.916812 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 32173.916812 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1061117 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 60200 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61178 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.516927 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.344748 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9871 # number of writebacks -system.cpu2.l1c.writebacks::total 9871 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36761 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36761 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23865 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23865 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60626 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60626 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60626 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60626 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2420242117 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2420242117 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1819999216 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1819999216 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4240241333 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 4240241333 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4240241333 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 4240241333 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1065167222 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1065167222 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3984850744 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3984850744 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 5050017966 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 5050017966 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806074 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806074 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954791 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954791 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858725 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858725 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65837.221974 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65837.221974 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76262.275969 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76262.275969 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9940 # number of writebacks +system.cpu2.l1c.writebacks::total 9940 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36457 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36457 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23816 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23816 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60273 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60273 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60273 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60273 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 958559384 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958559384 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 888663772 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 888663772 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1847223156 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1847223156 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847223156 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1847223156 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 735013046 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 735013046 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1939097223 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1939097223 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2674110269 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2674110269 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805324 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805324 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954549 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954549 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858345 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858345 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26292.876101 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26292.876101 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37313.729090 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37313.729090 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98252 # number of read accesses completed -system.cpu3.num_writes 55235 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22381 # number of replacements -system.cpu3.l1c.tags.tagsinuse 396.107709 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13213 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22778 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.580077 # Average number of references to valid blocks. +system.cpu3.num_reads 99869 # number of read accesses completed +system.cpu3.num_writes 54874 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22370 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.431339 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13240 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22771 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.581441 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 396.107709 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.773648 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.773648 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 335638 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 335638 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8470 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8470 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1156 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1156 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9626 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9626 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9626 # number of overall hits -system.cpu3.l1c.overall_hits::total 9626 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36183 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36183 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23969 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23969 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60152 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60152 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60152 # number of overall misses -system.cpu3.l1c.overall_misses::total 60152 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 2454128819 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 2454128819 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1887224651 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1887224651 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 4341353470 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 4341353470 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 4341353470 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 4341353470 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44653 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44653 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25125 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25125 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69778 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69778 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69778 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69778 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.810315 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.810315 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953990 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953990 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.862048 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.862048 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.862048 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.862048 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67825.465522 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 67825.465522 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78736.061204 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 78736.061204 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 72173.052766 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 72173.052766 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 72173.052766 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 72173.052766 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 2184377 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.431339 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.768421 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.768421 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336829 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336829 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8648 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8648 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1128 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1128 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9776 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9776 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9776 # number of overall hits +system.cpu3.l1c.overall_hits::total 9776 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36458 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36458 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23788 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23788 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60246 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60246 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60246 # number of overall misses +system.cpu3.l1c.overall_misses::total 60246 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1012578921 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1012578921 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 920459168 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 920459168 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1933038089 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1933038089 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1933038089 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1933038089 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45106 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45106 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24916 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24916 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70022 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70022 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70022 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70022 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808274 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808274 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954728 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954728 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860387 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860387 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860387 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860387 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27773.847194 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 27773.847194 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38694.264671 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 38694.264671 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 32085.749909 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 32085.749909 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 32085.749909 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 32085.749909 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1072737 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 59819 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61848 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.516441 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.344732 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9931 # number of writebacks -system.cpu3.l1c.writebacks::total 9931 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36183 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36183 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23969 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60152 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60152 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60152 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60152 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2377731501 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2377731501 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1837004571 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1837004571 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4214736072 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 4214736072 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4214736072 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 4214736072 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1072192160 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1072192160 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 4016794612 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 4016794612 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 5088986772 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 5088986772 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.810315 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.810315 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953990 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953990 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.862048 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.862048 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.862048 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.862048 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65714.050825 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.050825 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76640.851558 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76640.851558 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 70068.095358 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9757 # number of writebacks +system.cpu3.l1c.writebacks::total 9757 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36458 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36458 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23788 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23788 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60246 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60246 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60246 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60246 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 956791627 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 956791627 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 884289164 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 884289164 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1841080791 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1841080791 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1841080791 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1841080791 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 756050699 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 756050699 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1926314708 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1926314708 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2682365407 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2682365407 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808274 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808274 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954728 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954728 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860387 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860387 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860387 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860387 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26243.667426 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26243.667426 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37173.749958 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37173.749958 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99562 # number of read accesses completed -system.cpu4.num_writes 54813 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22626 # number of replacements -system.cpu4.l1c.tags.tagsinuse 395.713168 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13359 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 23019 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.580347 # Average number of references to valid blocks. +system.cpu4.num_reads 98774 # number of read accesses completed +system.cpu4.num_writes 54829 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22505 # number of replacements +system.cpu4.l1c.tags.tagsinuse 395.050000 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13373 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22916 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.583566 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 395.713168 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.772877 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.772877 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337886 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337886 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8660 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8660 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1130 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9790 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9790 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9790 # number of overall hits -system.cpu4.l1c.overall_hits::total 9790 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36748 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36748 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23725 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23725 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60473 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60473 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60473 # number of overall misses -system.cpu4.l1c.overall_misses::total 60473 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 2479360793 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 2479360793 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1851125976 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1851125976 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 4330486769 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 4330486769 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 4330486769 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 4330486769 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45408 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45408 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24855 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24855 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70263 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70263 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70263 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70263 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809285 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.809285 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954536 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954536 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.860666 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.860666 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.860666 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.860666 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67469.271607 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 67469.271607 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78024.277176 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 78024.277176 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 71610.251997 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 71610.251997 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 71610.251997 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 71610.251997 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 2193235 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 395.050000 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.771582 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.771582 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337873 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337873 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8531 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8531 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1209 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1209 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9740 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9740 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9740 # number of overall hits +system.cpu4.l1c.overall_hits::total 9740 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36518 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36518 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24001 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24001 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60519 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60519 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60519 # number of overall misses +system.cpu4.l1c.overall_misses::total 60519 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1017641988 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1017641988 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 934552595 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 934552595 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1952194583 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1952194583 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1952194583 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1952194583 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25210 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25210 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70259 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70259 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70259 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70259 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.810628 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.810628 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952043 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952043 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.861370 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.861370 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.861370 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.861370 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27866.859850 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 27866.859850 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38938.069039 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 38938.069039 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 32257.548588 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 32257.548588 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 32257.548588 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 32257.548588 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1063629 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 60223 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61473 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.418561 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 17.302377 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9708 # number of writebacks -system.cpu4.l1c.writebacks::total 9708 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36748 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36748 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23725 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23725 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60473 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60473 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60473 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60473 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2401684855 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2401684855 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1801504708 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1801504708 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4203189563 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 4203189563 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4203189563 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 4203189563 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1091799507 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1091799507 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 4121360584 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 4121360584 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5213160091 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5213160091 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809285 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809285 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954536 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954536 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860666 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.860666 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860666 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.860666 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65355.525607 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65355.525607 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 75932.759031 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 75932.759031 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69505.226514 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9914 # number of writebacks +system.cpu4.l1c.writebacks::total 9914 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36518 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36518 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24001 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24001 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60519 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60519 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60519 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60519 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 961775196 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 961775196 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 898026173 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 898026173 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1859801369 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1859801369 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1859801369 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1859801369 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 728267014 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 728267014 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1921671690 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1921671690 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2649938704 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2649938704 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.810628 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.810628 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952043 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952043 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861370 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.861370 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861370 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.861370 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26337.017252 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26337.017252 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37416.198200 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37416.198200 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98672 # number of read accesses completed -system.cpu5.num_writes 54809 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22472 # number of replacements -system.cpu5.l1c.tags.tagsinuse 396.252013 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13351 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22867 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.583854 # Average number of references to valid blocks. +system.cpu5.num_reads 99305 # number of read accesses completed +system.cpu5.num_writes 54996 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22529 # number of replacements +system.cpu5.l1c.tags.tagsinuse 394.380527 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13364 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.582792 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 396.252013 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.773930 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.773930 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 336301 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 336301 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8563 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8563 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1084 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1084 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9647 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9647 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9647 # number of overall hits -system.cpu5.l1c.overall_hits::total 9647 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36411 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36411 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23882 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23882 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60293 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60293 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60293 # number of overall misses -system.cpu5.l1c.overall_misses::total 60293 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 2486246489 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 2486246489 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1881159650 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1881159650 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 4367406139 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 4367406139 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 4367406139 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 4367406139 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44974 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44974 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24966 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24966 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69940 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69940 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69940 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69940 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.809601 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.809601 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956581 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.956581 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.862067 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.862067 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.862067 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.862067 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 68282.840048 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 68282.840048 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78768.932669 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 78768.932669 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 72436.371370 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 72436.371370 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 72436.371370 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 72436.371370 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 2200429 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 394.380527 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.770274 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.770274 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337468 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337468 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8640 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8640 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1161 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1161 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9801 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9801 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9801 # number of overall hits +system.cpu5.l1c.overall_hits::total 9801 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36580 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36580 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23798 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23798 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60378 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60378 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60378 # number of overall misses +system.cpu5.l1c.overall_misses::total 60378 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1015127570 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1015127570 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 927119253 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 927119253 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1942246823 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1942246823 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1942246823 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1942246823 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45220 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45220 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24959 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70179 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70179 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70179 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70179 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808934 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808934 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953484 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953484 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860343 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860343 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860343 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860343 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27750.890377 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 27750.890377 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38957.864232 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 38957.864232 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 32168.121220 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 32168.121220 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 32168.121220 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 32168.121220 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1066593 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 60083 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61522 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.623155 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 17.336774 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9941 # number of writebacks -system.cpu5.l1c.writebacks::total 9941 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36411 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36411 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23882 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23882 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60293 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60293 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60293 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60293 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 2409268523 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 2409268523 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1831238342 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1831238342 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 4240506865 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 4240506865 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 4240506865 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 4240506865 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1068031665 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1068031665 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 3938248323 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 3938248323 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 5006279988 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 5006279988 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.809601 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.809601 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956581 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956581 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.862067 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.862067 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.862067 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.862067 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 66168.699651 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 66168.699651 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76678.600703 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76678.600703 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 70331.661470 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9775 # number of writebacks +system.cpu5.l1c.writebacks::total 9775 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36580 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36580 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23798 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23798 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60378 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60378 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 959195658 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 959195658 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 890981649 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 890981649 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1850177307 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1850177307 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1850177307 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1850177307 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 738489342 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 738489342 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1963680665 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1963680665 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2702170007 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2702170007 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808934 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808934 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953484 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953484 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860343 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860343 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860343 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860343 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26221.860525 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26221.860525 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37439.349903 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37439.349903 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30643.236063 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99484 # number of read accesses completed -system.cpu6.num_writes 54995 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22115 # number of replacements -system.cpu6.l1c.tags.tagsinuse 396.164371 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13666 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22491 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.607621 # Average number of references to valid blocks. +system.cpu6.num_reads 99342 # number of read accesses completed +system.cpu6.num_writes 54737 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22276 # number of replacements +system.cpu6.l1c.tags.tagsinuse 393.125800 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13636 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.601155 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 396.164371 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.773759 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.773759 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 376 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338129 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338129 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8797 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8797 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1207 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1207 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 10004 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 10004 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 10004 # number of overall hits -system.cpu6.l1c.overall_hits::total 10004 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36456 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36456 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23912 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23912 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60368 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60368 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60368 # number of overall misses -system.cpu6.l1c.overall_misses::total 60368 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 2466938162 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 2466938162 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1877191258 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1877191258 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 4344129420 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 4344129420 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 4344129420 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 4344129420 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45253 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45253 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25119 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805604 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805604 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951949 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.951949 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.857841 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.857841 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.857841 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.857841 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 67668.920397 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 67668.920397 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78504.150970 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 78504.150970 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 71960.797442 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 71960.797442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 71960.797442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 71960.797442 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 2202006 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 393.125800 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.767824 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.767824 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337855 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337855 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8799 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8799 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1154 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1154 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9953 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9953 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9953 # number of overall hits +system.cpu6.l1c.overall_hits::total 9953 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36552 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36552 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23805 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23805 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60357 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60357 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60357 # number of overall misses +system.cpu6.l1c.overall_misses::total 60357 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1017275565 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1017275565 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 923819144 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 923819144 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1941094709 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1941094709 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1941094709 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1941094709 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45351 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45351 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24959 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70310 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70310 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805980 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805980 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953764 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953764 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858441 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858441 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858441 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858441 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27830.913903 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 27830.913903 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38807.777526 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 38807.777526 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 32160.225144 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 32160.225144 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 32160.225144 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 32160.225144 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1069531 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 60316 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61695 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 36.507825 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 17.335781 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9723 # number of writebacks -system.cpu6.l1c.writebacks::total 9723 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36456 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23912 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23912 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60368 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60368 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 2389944958 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 2389944958 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1827130108 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1827130108 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 4217075066 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 4217075066 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 4217075066 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 4217075066 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1090860454 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1090860454 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 4034817264 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 4034817264 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 5125677718 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 5125677718 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805604 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805604 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951949 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951949 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857841 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.857841 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857841 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.857841 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 65556.971637 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 65556.971637 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76410.593342 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76410.593342 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 69856.133481 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9809 # number of writebacks +system.cpu6.l1c.writebacks::total 9809 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36552 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36552 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23805 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23805 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60357 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60357 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60357 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60357 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 961362717 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 961362717 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 887609672 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 887609672 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1848972389 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1848972389 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1848972389 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1848972389 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 744037855 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 744037855 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1951627727 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1951627727 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2695665582 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2695665582 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805980 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805980 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953764 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953764 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858441 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858441 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858441 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858441 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26301.234324 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26301.234324 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37286.690695 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37286.690695 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30633.934573 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98571 # number of read accesses completed -system.cpu7.num_writes 54904 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22064 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.954913 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13425 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22470 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.597463 # Average number of references to valid blocks. +system.cpu7.num_reads 99062 # number of read accesses completed +system.cpu7.num_writes 54686 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22200 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.753023 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13454 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22591 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.595547 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.954913 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.771396 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.771396 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 334895 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 334895 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8604 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8604 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1157 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1157 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9761 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9761 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9761 # number of overall hits -system.cpu7.l1c.overall_hits::total 9761 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35973 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35973 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23939 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23939 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59912 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59912 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59912 # number of overall misses -system.cpu7.l1c.overall_misses::total 59912 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 2452832630 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 2452832630 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1890055104 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1890055104 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 4342887734 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 4342887734 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 4342887734 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 4342887734 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44577 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44577 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25096 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25096 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69673 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69673 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69673 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69673 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806986 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806986 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953897 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953897 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859903 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859903 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859903 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859903 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 68185.378756 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 68185.378756 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78952.968127 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 78952.968127 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 72487.777641 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 72487.777641 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 72487.777641 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 72487.777641 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 2195658 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 394.753023 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.771002 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.771002 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337139 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337139 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8690 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8690 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1182 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9872 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9872 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9872 # number of overall hits +system.cpu7.l1c.overall_hits::total 9872 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36466 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36466 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60256 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60256 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60256 # number of overall misses +system.cpu7.l1c.overall_misses::total 60256 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1009807130 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1009807130 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 916976125 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 916976125 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1926783255 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1926783255 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1926783255 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1926783255 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24972 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70128 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70128 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70128 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70128 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807556 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807556 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952667 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.952667 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859229 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859229 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859229 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859229 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27691.743816 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 27691.743816 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38544.603825 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 38544.603825 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 31976.620668 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 31976.620668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 31976.620668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 31976.620668 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1063264 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 59807 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61445 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 36.712392 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 17.304321 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9796 # number of writebacks -system.cpu7.l1c.writebacks::total 9796 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35973 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35973 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23939 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23939 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59912 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59912 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59912 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59912 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 2376889288 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 2376889288 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1839857154 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1839857154 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 4216746442 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 4216746442 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 4216746442 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 4216746442 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1084884512 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1084884512 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 4029557689 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 4029557689 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 5114442201 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5114442201 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806986 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806986 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953897 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953897 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859903 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859903 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859903 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859903 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 66074.258138 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 66074.258138 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76856.057229 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76856.057229 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 70382.334791 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9819 # number of writebacks +system.cpu7.l1c.writebacks::total 9819 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36466 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36466 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60256 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60256 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60256 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60256 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 953998318 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 953998318 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 880753723 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 880753723 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1834752041 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1834752041 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1834752041 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1834752041 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 752742732 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 752742732 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1947143716 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1947143716 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2699886448 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2699886448 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807556 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807556 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952667 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952667 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859229 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859229 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859229 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859229 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26161.309658 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26161.309658 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37022.014418 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37022.014418 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30449.283739 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency @@ -1037,566 +1037,565 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 12730 # number of replacements -system.l2c.tags.tagsinuse 780.951688 # Cycle average of tags in use -system.l2c.tags.total_refs 149721 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 13527 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.068308 # Average number of references to valid blocks. +system.l2c.tags.replacements 13121 # number of replacements +system.l2c.tags.tagsinuse 779.163229 # Cycle average of tags in use +system.l2c.tags.total_refs 150276 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 13897 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.813557 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.352338 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 5.728717 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.680211 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.211499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 5.648633 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.142733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 5.860524 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.858945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.468088 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.713235 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.005594 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006524 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.005516 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.005999 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.005723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006698 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.762648 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 424 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.778320 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1954074 # Number of tag accesses -system.l2c.tags.data_accesses 1954074 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10705 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10659 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10665 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10689 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10651 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10616 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85337 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 75478 # number of Writeback hits -system.l2c.Writeback_hits::total 75478 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 365 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 341 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 333 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 340 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 338 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2772 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1956 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1860 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1936 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1874 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1916 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1840 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1899 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1911 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15192 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12601 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12589 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12550 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12527 # number of demand (read+write) hits -system.l2c.demand_hits::total 100529 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12661 # number of overall hits -system.l2c.overall_hits::cpu1 12519 # number of overall hits -system.l2c.overall_hits::cpu2 12601 # number of overall hits -system.l2c.overall_hits::cpu3 12563 # number of overall hits -system.l2c.overall_hits::cpu4 12589 # number of overall hits -system.l2c.overall_hits::cpu5 12519 # number of overall hits -system.l2c.overall_hits::cpu6 12550 # number of overall hits -system.l2c.overall_hits::cpu7 12527 # number of overall hits -system.l2c.overall_hits::total 100529 # number of overall hits -system.l2c.ReadReq_misses::cpu0 637 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 698 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 718 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 649 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 657 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 655 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 700 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 686 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5400 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1869 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1879 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1945 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1927 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1931 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2008 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1996 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1999 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15554 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4360 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4327 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4376 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4482 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4415 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4364 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4427 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4401 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35152 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 4997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5025 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5094 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5131 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5072 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5019 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5127 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5087 # number of demand (read+write) misses -system.l2c.demand_misses::total 40552 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 4997 # number of overall misses -system.l2c.overall_misses::cpu1 5025 # number of overall misses -system.l2c.overall_misses::cpu2 5094 # number of overall misses -system.l2c.overall_misses::cpu3 5131 # number of overall misses -system.l2c.overall_misses::cpu4 5072 # number of overall misses -system.l2c.overall_misses::cpu5 5019 # number of overall misses -system.l2c.overall_misses::cpu6 5127 # number of overall misses -system.l2c.overall_misses::cpu7 5087 # number of overall misses -system.l2c.overall_misses::total 40552 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 37351962 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 41387952 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 42368449 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 38023954 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 38587461 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 38640955 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 40955466 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 40550959 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 317867158 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 53532000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 54034500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 55090000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 53743000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 53806000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 57327000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 56366500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 57375499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 441274499 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 232668482 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 231079974 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 233454479 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 239997471 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 235674978 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 232806977 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 236584974 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 235413970 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1877681305 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 270020444 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 272467926 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 275822928 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 278021425 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 274262439 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 271447932 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 277540440 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 275964929 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2195548463 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 270020444 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 272467926 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 275822928 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 278021425 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 274262439 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 271447932 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 277540440 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 275964929 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2195548463 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11342 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11357 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11383 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11338 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11330 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11334 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11351 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11302 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 90737 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 75478 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 75478 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2234 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2220 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2308 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2276 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2264 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2348 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2334 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2342 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18326 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6316 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6187 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6331 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6204 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6326 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50344 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17658 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17544 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17695 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17694 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17661 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17538 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17677 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17614 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 141081 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17658 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17544 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17695 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17694 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17661 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17538 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17677 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17614 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 141081 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.056163 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.061460 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.063077 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.057241 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.057988 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.057791 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.061669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.060697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.059513 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.836616 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.846396 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.842721 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.846661 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852915 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.855196 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.855184 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.853544 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.848739 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.690310 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.699370 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.693283 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.705160 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.697362 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.703417 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.699810 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.697243 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.698236 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.282988 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.286423 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.287878 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.289985 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.287186 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.286179 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.290038 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.288804 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.287438 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.282988 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.286423 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.287878 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.289985 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.287186 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.286179 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.290038 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.288804 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.287438 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 58637.302983 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 59295.060172 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 59008.981894 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 58588.526965 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 58732.817352 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 58993.824427 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 58507.808571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59112.185131 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 58864.288519 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28642.054575 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28757.051623 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28323.907455 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27889.465490 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 27864.319006 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28549.302789 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28239.729459 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28702.100550 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28370.483413 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53364.330734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53404.200139 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53348.829753 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53546.959170 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53380.515968 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53347.153300 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53441.376553 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53491.017950 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53416.058972 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54036.510706 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54222.472836 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54146.628975 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54184.647242 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54073.824724 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54084.066946 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54133.107080 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54249.052290 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54141.558074 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54036.510706 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54222.472836 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54146.628975 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54184.647242 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54073.824724 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54084.066946 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54133.107080 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54249.052290 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54141.558074 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 6543 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 725.457797 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.718013 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.568954 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.219418 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.731947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.474998 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.998802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.991847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.001453 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.708455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006561 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006074 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006323 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006835 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006837 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.760902 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 566 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1961425 # Number of tag accesses +system.l2c.tags.data_accesses 1961425 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10766 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10683 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10671 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10889 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10673 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85829 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 75598 # number of Writeback hits +system.l2c.Writeback_hits::total 75598 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 323 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 342 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 356 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 330 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2745 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1821 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1892 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1893 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1922 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1886 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1863 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15171 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12615 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12658 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12630 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12554 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12639 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12593 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12775 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12536 # number of demand (read+write) hits +system.l2c.demand_hits::total 101000 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12615 # number of overall hits +system.l2c.overall_hits::cpu1 12658 # number of overall hits +system.l2c.overall_hits::cpu2 12630 # number of overall hits +system.l2c.overall_hits::cpu3 12554 # number of overall hits +system.l2c.overall_hits::cpu4 12639 # number of overall hits +system.l2c.overall_hits::cpu5 12593 # number of overall hits +system.l2c.overall_hits::cpu6 12775 # number of overall hits +system.l2c.overall_hits::cpu7 12536 # number of overall hits +system.l2c.overall_hits::total 101000 # number of overall hits +system.l2c.ReadReq_misses::cpu0 705 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 721 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 716 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 685 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 694 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 690 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 691 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 715 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5617 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1952 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1970 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1832 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1968 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1954 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1963 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1919 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15493 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4418 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4338 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4348 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4457 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4447 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4501 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4407 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 35289 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5059 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5064 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5142 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5141 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5191 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5098 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5088 # number of demand (read+write) misses +system.l2c.demand_misses::total 40906 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5123 # number of overall misses +system.l2c.overall_misses::cpu1 5059 # number of overall misses +system.l2c.overall_misses::cpu2 5064 # number of overall misses +system.l2c.overall_misses::cpu3 5142 # number of overall misses +system.l2c.overall_misses::cpu4 5141 # number of overall misses +system.l2c.overall_misses::cpu5 5191 # number of overall misses +system.l2c.overall_misses::cpu6 5098 # number of overall misses +system.l2c.overall_misses::cpu7 5088 # number of overall misses +system.l2c.overall_misses::total 40906 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 42571447 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 44584934 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 43709432 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 42098938 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 42802932 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 42467936 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 42434429 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 44394419 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 345064467 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 57799000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 58024000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 57179999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53990500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 56201500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 57084499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 56659000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 56222499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 453160997 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 241579958 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 237098460 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 238347956 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 243950461 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 243322462 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 246152957 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 241076464 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 238492966 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1930021684 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 284151405 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 281683394 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 282057388 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 286049399 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 286125394 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 288620893 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 283510893 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 282887385 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2275086151 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 284151405 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 281683394 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 282057388 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 286049399 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 286125394 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 288620893 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 283510893 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 282887385 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2275086151 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11499 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11487 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11386 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11361 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11388 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91446 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 75598 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 75598 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2258 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2312 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2166 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2324 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2284 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2324 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2265 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18238 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6239 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6230 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6295 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6350 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6394 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6423 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6293 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6236 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50460 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17738 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17694 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17780 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17784 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17873 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17624 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 141906 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17738 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17694 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17780 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17784 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17873 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17624 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141906 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.061310 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.062767 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.062813 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060374 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.060952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.060734 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.059672 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.062785 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.061424 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.846855 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.856953 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.852076 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.845799 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.846816 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.855517 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.844664 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.847241 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849490 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.708126 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.696308 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.690707 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.701890 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.695496 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.700763 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.700302 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.701251 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.699346 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.288815 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.285545 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.286199 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.290574 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.289145 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.291892 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.285235 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.288697 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.288261 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.288815 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.285545 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.286199 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.290574 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.289145 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.291892 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.285235 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.288697 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.288261 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60385.031206 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61837.633842 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 61046.692737 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61458.303650 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61675.694524 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61547.733333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61410.172214 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 62090.096503 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61432.164323 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29610.143443 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29986.563307 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29025.380203 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29470.796943 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28557.672764 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29214.175537 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28863.474274 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29297.810839 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29249.402763 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 54680.841557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 54656.168741 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54817.837167 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54734.229527 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 54716.092197 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54688.504110 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54703.077831 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54537.609421 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54691.878036 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55465.821784 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55679.658826 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55698.536335 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55629.988137 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55655.591130 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55600.249085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55612.179874 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55598.935731 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55617.419229 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55465.821784 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55679.658826 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55698.536335 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55629.988137 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55655.591130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55600.249085 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55612.179874 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55598.935731 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55617.419229 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 10446 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 914 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1464 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.158643 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.135246 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6000 # number of writebacks -system.l2c.writebacks::total 6000 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 14 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 1 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 6250 # number of writebacks +system.l2c.writebacks::total 6250 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 1 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 15 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 6 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 35 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 6 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 35 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 635 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 695 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 716 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 643 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 657 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 651 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 698 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 684 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5379 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1869 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1879 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1943 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1926 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1931 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2008 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1995 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1999 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15550 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4360 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4323 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4372 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4482 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4414 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4363 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4425 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4399 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35138 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 4995 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5018 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5088 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5125 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5071 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5014 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5123 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5083 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40517 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 4995 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5018 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5088 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5125 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5071 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5014 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5123 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5083 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40517 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 29596962 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 32869452 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 33629449 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 29976455 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 30615961 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 30583955 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 32395466 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 32146959 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 251814659 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76123000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76358500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 79146000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78403000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 78530000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81677500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 81182000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 81450499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 632870499 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 179654482 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 178405975 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 180144979 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 185516471 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 181991978 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 179667478 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 182702975 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 181859470 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1449943808 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 209251444 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 211275427 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 213774428 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 215492926 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 212607939 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 210251433 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 215098441 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 214006429 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1701758467 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 209251444 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 211275427 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 213774428 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 215492926 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 212607939 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 210251433 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 215098441 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 214006429 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1701758467 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 401930986 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 402911994 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 395709487 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 399023483 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 405620989 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 396449489 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 404605985 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 402179993 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3208432406 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 228006492 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 223295497 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 223196996 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 228513495 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 229209992 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 220676995 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 224532992 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 222245997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1799678456 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 629937478 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 626207491 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 618906483 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 627536978 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 634830981 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 617126484 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 629138977 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 624425990 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5008110862 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055987 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.061196 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062901 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.056712 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.057988 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.057438 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.061492 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060520 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.059281 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.836616 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.846396 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.841854 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.846221 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.852915 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855196 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.854756 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853544 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.848521 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690310 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.698723 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.692649 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.705160 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.697204 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.703256 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.699494 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.697958 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.287190 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.287190 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46609.388976 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 47294.175540 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46968.504190 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 46619.681182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46599.636225 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46979.961598 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46411.842407 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46998.478070 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46814.400260 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40729.266988 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40637.839276 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40733.916624 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40707.684320 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40668.047644 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40676.045817 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40692.731830 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40745.622311 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40699.067460 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41205.156422 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41269.020356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41204.249543 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41391.448237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41230.624830 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41179.802430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41288.807910 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41341.093430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41264.266834 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 64 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 698 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 714 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 712 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 688 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 687 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 684 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 709 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5568 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1951 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1935 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1970 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1832 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1968 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1954 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1963 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1919 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15492 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4416 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4335 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4345 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4456 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4447 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4499 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4406 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4370 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 35274 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5114 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5049 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5057 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5132 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5135 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5186 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5090 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5079 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40842 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5114 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5049 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5057 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5132 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5135 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5186 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5090 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5079 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40842 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 33845945 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 35679430 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 34970423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 33623934 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 34265930 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 34048934 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 33977929 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 35572914 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 275985439 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81779494 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81207491 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 82576991 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 76840996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 82448987 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81922493 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82161995 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80384488 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 649322935 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 187970446 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 184467447 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 185588937 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189921941 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 189397436 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 191605943 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 187621956 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 185423942 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1501998048 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 221816391 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 220146877 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 220559360 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 223545875 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 223663366 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 225654877 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 221599885 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 220996856 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1777983487 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 221816391 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 220146877 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 220559360 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 223545875 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 223663366 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 225654877 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 221599885 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 220996856 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1777983487 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 420548415 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 410318426 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 408411942 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 419559934 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 403725937 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 410458428 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413026934 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 417703437 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3303753453 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 230815972 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 233216955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 233429960 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229986451 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230895448 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 235553969 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233378955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230983963 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1858261673 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 651364387 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 643535381 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 641841902 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 649546385 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 634621385 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 646012397 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 646405889 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 648687400 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5162015126 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.060701 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.062157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059580 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060425 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.060470 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059067 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.062259 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.060888 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.846421 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.856953 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.852076 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.845799 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.846816 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855517 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.844664 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.847241 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.849435 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.707806 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.695827 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.690230 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.701732 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695496 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.700452 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.700143 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.700770 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.699049 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.287810 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.287810 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48489.892550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49971.190476 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49115.762640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49739.547337 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49805.130814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49561.767103 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49675.334795 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50173.362482 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49566.350395 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41916.706304 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41967.695607 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41917.254315 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.775109 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41894.810467 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41925.533777 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41855.320937 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41888.737884 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41913.434999 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42565.771286 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42553.044291 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42713.219102 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42621.620512 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42589.933888 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42588.562569 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42583.285520 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42431.108009 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42580.882463 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -1625,109 +1624,108 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 122833 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 120785 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 123722 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 121674 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 83923 # Transaction distribution -system.membus.trans_dist::ReadResp 83923 # Transaction distribution -system.membus.trans_dist::WriteReq 43483 # Transaction distribution -system.membus.trans_dist::WriteResp 43481 # Transaction distribution -system.membus.trans_dist::Writeback 6000 # Transaction distribution +system.membus.trans_dist::ReadReq 84424 # Transaction distribution +system.membus.trans_dist::ReadResp 84420 # Transaction distribution +system.membus.trans_dist::WriteReq 43379 # Transaction distribution +system.membus.trans_dist::WriteResp 43377 # Transaction distribution +system.membus.trans_dist::Writeback 6250 # Transaction distribution system.membus.trans_dist::UpgradeReq 58661 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47607 # Transaction distribution -system.membus.trans_dist::ReadExReq 50527 # Transaction distribution -system.membus.trans_dist::ReadExResp 3086 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 420691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1047472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1047472 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 58495 # Total snoops (count) -system.membus.snoop_fanout::samples 122833 # Request fanout histogram +system.membus.trans_dist::UpgradeResp 47649 # Transaction distribution +system.membus.trans_dist::ReadExReq 50299 # Transaction distribution +system.membus.trans_dist::ReadExResp 3116 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 421575 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1077818 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1077818 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 58193 # Total snoops (count) +system.membus.snoop_fanout::samples 123722 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 122833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 123722 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 122833 # Request fanout histogram -system.membus.reqLayer0.occupancy 472878500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 31.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 318922500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 21.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 559080 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 259825 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 297207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 123722 # Request fanout histogram +system.membus.reqLayer0.occupancy 350831336 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 48.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 312389376 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 42.9 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 560254 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 259972 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 298234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 370692 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370683 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43483 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43481 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 75478 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29380 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29380 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161449 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161449 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120254 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120627 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119815 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119764 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 961915 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1743799 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1739946 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1755311 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1759542 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1748105 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1744654 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1747573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 13981678 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 323561 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 559080 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.688315 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.176863 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 371185 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371180 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43379 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43375 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 75598 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29248 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29247 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161278 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161272 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120544 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120292 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120320 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120179 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120443 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120589 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 963055 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1746802 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1746902 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1761658 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751012 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1764505 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756981 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1763838 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1750408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14042106 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322707 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 560254 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.690126 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.177666 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 52722 9.43% 9.43% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 250233 44.76% 54.19% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141253 25.27% 79.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 69107 12.36% 91.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 29981 5.36% 97.18% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11505 2.06% 99.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3559 0.64% 99.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 720 0.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 52995 9.46% 9.46% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 250263 44.67% 54.13% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141259 25.21% 79.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 69446 12.40% 91.74% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 30460 5.44% 97.17% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 11695 2.09% 99.26% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 3486 0.62% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 650 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 559080 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1490758741 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 99.8 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 160617515 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 10.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 159518006 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 159700003 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 158882050 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 159826982 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 158824012 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 159298538 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 158114013 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 10.6 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 560254 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 719277462 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100586935 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100589620 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 100255865 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100593415 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100466351 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100465013 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 100397923 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100485866 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index f348549bd..b29e580fa 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,195 +1,195 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000667 # Number of seconds simulated -sim_ticks 667077000 # Number of ticks simulated -final_tick 667077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000476 # Number of seconds simulated +sim_ticks 475552000 # Number of ticks simulated +final_tick 475552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 152389795 # Simulator tick rate (ticks/s) -host_mem_usage 222064 # Number of bytes of host memory used -host_seconds 4.38 # Real time elapsed on the host +host_tick_rate 102852654 # Simulator tick rate (ticks/s) +host_mem_usage 276856 # Number of bytes of host memory used +host_seconds 4.62 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 82891 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 81142 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 81431 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 77551 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 82816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77581 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 78240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78400 # Number of bytes read from this memory -system.physmem.bytes_read::total 640052 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 398656 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5632 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5599 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5418 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5436 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5426 # Number of bytes written to this memory -system.physmem.bytes_written::total 442654 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11008 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10834 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10927 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87353 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6229 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5632 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5599 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5418 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5436 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5426 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 124260018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 121638132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 122071365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 116254945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 124147587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 116299917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 117287809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 117527662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 959487435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 597616167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 8184962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 8442803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 8393334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 8122001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 8238929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 8148984 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 8291397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 8133994 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 663572571 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 597616167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 132444980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 130080935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 130464699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 124376946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 132386516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 124448902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 125579206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 125661655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1623060007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 82626 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 79372 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 82635 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 78892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79911 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 82560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 82806 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 80499 # Number of bytes read from this memory +system.physmem.bytes_read::total 649301 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 411072 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5529 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5498 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5527 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5416 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5415 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5350 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5500 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5539 # Number of bytes written to this memory +system.physmem.bytes_written::total 454846 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10995 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10947 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88160 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6423 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5529 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5527 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5416 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5415 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5350 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5500 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5539 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 173747561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 166904986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 173766486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 165895633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 168038406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 173608775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 174126068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 169274864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1365362778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 864410201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 11626489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 11561301 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 11622283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 11388870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 11386767 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 11250084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 11565507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 11647517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 956459020 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 864410201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 185374050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 178466288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 185388769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 177284503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 179425173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 184858859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 185691575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 180922381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2321821799 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 55151 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22523 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.206747 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13668 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22921 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596309 # Average number of references to valid blocks. +system.cpu0.num_writes 55373 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22370 # number of replacements +system.cpu0.l1c.tags.tagsinuse 390.859535 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13365 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.587292 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.206747 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.767982 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.767982 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338453 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338453 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8785 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8785 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1208 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1208 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9993 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9993 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9993 # number of overall hits -system.cpu0.l1c.overall_hits::total 9993 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36702 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36702 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23741 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23741 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60443 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60443 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60443 # number of overall misses -system.cpu0.l1c.overall_misses::total 60443 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 964033198 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 964033198 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 878854454 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 878854454 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1842887652 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1842887652 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1842887652 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1842887652 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45487 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45487 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24949 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24949 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70436 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70436 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70436 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70436 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806868 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.806868 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951581 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.951581 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858127 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858127 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858127 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858127 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26266.503133 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 26266.503133 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37018.426098 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 37018.426098 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.678739 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 30489.678739 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.678739 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 30489.678739 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1018774 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 390.859535 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.763398 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.763398 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338979 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338979 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8642 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8642 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1137 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1137 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9779 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9779 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9779 # number of overall hits +system.cpu0.l1c.overall_hits::total 9779 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36791 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36791 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23910 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23910 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60701 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60701 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60701 # number of overall misses +system.cpu0.l1c.overall_misses::total 60701 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 598271123 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 598271123 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 653921249 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 653921249 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1252192372 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1252192372 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1252192372 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1252192372 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45433 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45433 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25047 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25047 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70480 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70480 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70480 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70480 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809786 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809786 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954605 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954605 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861251 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861251 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861251 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861251 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16261.344432 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16261.344432 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27349.278503 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 27349.278503 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20628.859030 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20628.859030 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20628.859030 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20628.859030 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 775639 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 63007 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66482 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.169219 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.666902 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9806 # number of writebacks -system.cpu0.l1c.writebacks::total 9806 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36702 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36702 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23741 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23741 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60443 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60443 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 885636434 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 885636434 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 828679478 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 828679478 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1714315912 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1714315912 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1714315912 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1714315912 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 700887059 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 700887059 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1711925608 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1711925608 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2412812667 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2412812667 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806868 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806868 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951581 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951581 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858127 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858127 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24130.467931 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24130.467931 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34904.994651 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34904.994651 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9788 # number of writebacks +system.cpu0.l1c.writebacks::total 9788 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36791 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36791 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23910 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23910 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60701 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60701 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60701 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60701 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 540766367 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 540766367 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 617095733 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 617095733 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1157862100 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1157862100 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1157862100 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1157862100 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 641214054 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 641214054 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 990476120 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 990476120 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1631690174 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1631690174 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809786 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809786 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954605 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954605 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861251 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861251 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14698.332935 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14698.332935 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25809.106357 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25809.106357 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99761 # number of read accesses completed -system.cpu1.num_writes 55328 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22642 # number of replacements -system.cpu1.l1c.tags.tagsinuse 394.589952 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13581 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.589632 # Average number of references to valid blocks. +system.cpu1.num_reads 99552 # number of read accesses completed +system.cpu1.num_writes 55312 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22247 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.170580 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13534 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.597712 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 394.589952 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.770684 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.770684 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 339246 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 339246 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8788 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8788 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1121 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9909 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9909 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9909 # number of overall hits -system.cpu1.l1c.overall_hits::total 9909 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36866 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36866 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23806 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23806 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60672 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60672 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60672 # number of overall misses -system.cpu1.l1c.overall_misses::total 60672 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 969094954 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 969094954 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 879252966 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 879252966 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1848347920 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1848347920 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1848347920 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1848347920 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45654 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45654 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24927 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24927 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70581 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70581 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70581 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70581 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807509 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807509 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955029 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955029 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859608 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859608 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859608 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859608 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26286.956925 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 26286.956925 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 36934.090817 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 36934.090817 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 30464.595200 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 30464.595200 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 30464.595200 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 30464.595200 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1015089 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 391.170580 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.764005 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.764005 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338702 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338702 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8670 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8670 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1145 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1145 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9815 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9815 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9815 # number of overall hits +system.cpu1.l1c.overall_hits::total 9815 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36464 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36464 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 24184 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 24184 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60648 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60648 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60648 # number of overall misses +system.cpu1.l1c.overall_misses::total 60648 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 591998971 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 591998971 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 660686123 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 660686123 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1252685094 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1252685094 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1252685094 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1252685094 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45134 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45134 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25329 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25329 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70463 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70463 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70463 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70463 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807905 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807905 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954795 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954795 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860707 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860707 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860707 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860707 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16235.162654 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16235.162654 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27319.141705 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 27319.141705 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20655.010784 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20655.010784 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20655.010784 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20655.010784 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 776857 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62996 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66458 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.113547 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.689443 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9956 # number of writebacks -system.cpu1.l1c.writebacks::total 9956 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36866 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36866 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23806 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23806 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60672 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60672 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60672 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60672 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 890415084 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 890415084 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 828850208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 828850208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1719265292 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1719265292 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1719265292 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1719265292 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 690509167 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 690509167 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1720529946 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1720529946 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2411039113 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2411039113 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807509 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807509 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955029 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859608 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859608 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24152.744643 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24152.744643 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34816.861632 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34816.861632 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9776 # number of writebacks +system.cpu1.l1c.writebacks::total 9776 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36464 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36464 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24184 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 24184 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60648 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60648 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 534984781 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 534984781 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 623377675 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 623377675 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1158362456 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1158362456 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1158362456 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1158362456 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 640712682 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 640712682 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 989782156 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 989782156 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1630494838 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1630494838 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807905 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807905 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954795 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954795 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860707 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860707 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14671.587895 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14671.587895 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25776.450339 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25776.450339 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99243 # number of read accesses completed -system.cpu2.num_writes 55132 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22573 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.676253 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13694 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22978 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.595961 # Average number of references to valid blocks. +system.cpu2.num_reads 99606 # number of read accesses completed +system.cpu2.num_writes 55482 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22450 # number of replacements +system.cpu2.l1c.tags.tagsinuse 391.646892 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13596 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22843 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.595193 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.676253 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.770852 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.770852 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338823 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338823 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8940 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8940 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1180 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1180 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 10120 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 10120 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 10120 # number of overall hits -system.cpu2.l1c.overall_hits::total 10120 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36529 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36529 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23864 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23864 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60393 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60393 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60393 # number of overall misses -system.cpu2.l1c.overall_misses::total 60393 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 963156898 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 963156898 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 890183991 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 890183991 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1853340889 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1853340889 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1853340889 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1853340889 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45469 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45469 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25044 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25044 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70513 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70513 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70513 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70513 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803383 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.803383 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952883 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.952883 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856480 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856480 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856480 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856480 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26366.911166 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 26366.911166 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37302.379777 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 37302.379777 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 30688.008362 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 30688.008362 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 30688.008362 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 30688.008362 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1016015 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 391.646892 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.764935 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.764935 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338700 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338700 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1179 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1179 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9940 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9940 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9940 # number of overall hits +system.cpu2.l1c.overall_hits::total 9940 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36421 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36421 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24109 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24109 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60530 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60530 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60530 # number of overall misses +system.cpu2.l1c.overall_misses::total 60530 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 592390101 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 592390101 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 664239589 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 664239589 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1256629690 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1256629690 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1256629690 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1256629690 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45182 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45182 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25288 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25288 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70470 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70470 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70470 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70470 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806095 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.806095 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953377 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953377 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858947 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858947 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858947 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858947 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16265.069630 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16265.069630 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27551.519723 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 27551.519723 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 20760.444243 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 20760.444243 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 20760.444243 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 20760.444243 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 773028 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 62631 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66120 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.222238 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.691289 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9915 # number of writebacks -system.cpu2.l1c.writebacks::total 9915 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36529 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36529 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23864 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23864 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60393 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60393 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60393 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60393 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 885079158 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 885079158 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 839760037 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 839760037 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1724839195 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1724839195 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1724839195 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1724839195 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 685753748 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 685753748 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1712116464 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1712116464 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2397870212 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2397870212 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803383 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803383 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952883 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952883 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856480 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856480 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24229.493225 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24229.493225 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35189.408188 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35189.408188 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9975 # number of writebacks +system.cpu2.l1c.writebacks::total 9975 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36421 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36421 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24109 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24109 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60530 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60530 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60530 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60530 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535479769 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535479769 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 627082203 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 627082203 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162561972 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1162561972 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162561972 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1162561972 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 634925616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 634925616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 991782664 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 991782664 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1626708280 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1626708280 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806095 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806095 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953377 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953377 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858947 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858947 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14702.500453 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14702.500453 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26010.295035 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26010.295035 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99256 # number of read accesses completed -system.cpu3.num_writes 54955 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22662 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.489449 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13390 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 23054 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.580810 # Average number of references to valid blocks. +system.cpu3.num_reads 99549 # number of read accesses completed +system.cpu3.num_writes 55104 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22310 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.032656 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13513 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22709 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.595050 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.489449 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770487 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770487 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337690 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337690 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8629 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8629 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1137 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1137 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9766 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9766 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9766 # number of overall hits -system.cpu3.l1c.overall_hits::total 9766 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36563 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36563 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23903 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23903 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60466 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60466 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60466 # number of overall misses -system.cpu3.l1c.overall_misses::total 60466 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 960736157 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 960736157 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 887839747 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 887839747 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1848575904 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1848575904 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1848575904 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1848575904 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45192 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45192 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25040 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25040 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70232 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70232 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70232 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70232 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809059 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.809059 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954593 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954593 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860947 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860947 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860947 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860947 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26276.185133 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 26276.185133 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 37143.444212 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 37143.444212 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 30572.154665 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 30572.154665 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 30572.154665 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 30572.154665 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1022448 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.032656 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.763736 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.763736 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 338332 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338332 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8654 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8654 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1182 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9836 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9836 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9836 # number of overall hits +system.cpu3.l1c.overall_hits::total 9836 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36530 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36530 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 24013 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 24013 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60543 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60543 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60543 # number of overall misses +system.cpu3.l1c.overall_misses::total 60543 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 590001438 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 590001438 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 660132360 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 660132360 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1250133798 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1250133798 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1250133798 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1250133798 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45184 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45184 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25195 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25195 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70379 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70379 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70379 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70379 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808472 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808472 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953086 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953086 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860242 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860242 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860242 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860242 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16151.148043 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16151.148043 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27490.624245 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 27490.624245 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20648.692632 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20648.692632 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20648.692632 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20648.692632 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 774871 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 63227 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66332 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.171066 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.681707 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9928 # number of writebacks -system.cpu3.l1c.writebacks::total 9928 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36563 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36563 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23903 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23903 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60466 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60466 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60466 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60466 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 882571457 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 882571457 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 837312821 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 837312821 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1719884278 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1719884278 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1719884278 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1719884278 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 700068981 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 700068981 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1667398980 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1667398980 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2367467961 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2367467961 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809059 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809059 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954593 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954593 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860947 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860947 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24138.376419 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24138.376419 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 35029.612224 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35029.612224 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9907 # number of writebacks +system.cpu3.l1c.writebacks::total 9907 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36530 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36530 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24013 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 24013 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60543 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60543 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60543 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60543 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 532881722 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 532881722 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 623079094 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 623079094 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1155960816 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1155960816 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155960816 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1155960816 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 642783574 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 642783574 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 972713175 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 972713175 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1615496749 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1615496749 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808472 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808472 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953086 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953086 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860242 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860242 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14587.509499 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14587.509499 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25947.573981 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25947.573981 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99292 # number of read accesses completed -system.cpu4.num_writes 54781 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22192 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.392100 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13471 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22589 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.596352 # Average number of references to valid blocks. +system.cpu4.num_reads 99755 # number of read accesses completed +system.cpu4.num_writes 55257 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22302 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.084224 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13540 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.596660 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.392100 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.768344 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.768344 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 369 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 336466 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 336466 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8698 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8698 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1159 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1159 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9857 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9857 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9857 # number of overall hits -system.cpu4.l1c.overall_hits::total 9857 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36438 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36438 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23701 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23701 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60139 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60139 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60139 # number of overall misses -system.cpu4.l1c.overall_misses::total 60139 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 959750489 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 959750489 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 883613878 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 883613878 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1843364367 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1843364367 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1843364367 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1843364367 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45136 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45136 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24860 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24860 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69996 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69996 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69996 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69996 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807294 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807294 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953379 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953379 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859178 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859178 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859178 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859178 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26339.274631 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 26339.274631 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37281.712924 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 37281.712924 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 30651.729610 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 30651.729610 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 30651.729610 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 30651.729610 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1023771 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 391.084224 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.763836 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.763836 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338305 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338305 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8852 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8852 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1084 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1084 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9936 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9936 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9936 # number of overall hits +system.cpu4.l1c.overall_hits::total 9936 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36600 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36600 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23847 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23847 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60447 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60447 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60447 # number of overall misses +system.cpu4.l1c.overall_misses::total 60447 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 590829220 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 590829220 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 656323200 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 656323200 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1247152420 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1247152420 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1247152420 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1247152420 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45452 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45452 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24931 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24931 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70383 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70383 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70383 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70383 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805245 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805245 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956520 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.956520 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858830 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858830 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858830 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858830 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16142.874863 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16142.874863 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27522.254372 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 27522.254372 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20632.164045 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20632.164045 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20632.164045 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20632.164045 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 780817 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 62867 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66569 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.284712 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.729439 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9698 # number of writebacks -system.cpu4.l1c.writebacks::total 9698 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36438 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36438 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23701 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23701 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60139 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60139 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60139 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60139 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 881959493 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 881959493 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 833428166 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 833428166 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1715387659 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1715387659 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1715387659 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1715387659 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 703007482 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 703007482 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1705988496 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1705988496 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2408995978 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2408995978 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807294 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807294 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953379 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953379 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859178 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859178 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24204.388084 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24204.388084 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35164.261677 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35164.261677 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9856 # number of writebacks +system.cpu4.l1c.writebacks::total 9856 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36600 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36600 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23847 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23847 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60447 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60447 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 533635904 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 533635904 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 619552810 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 619552810 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1153188714 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1153188714 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1153188714 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1153188714 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 651255905 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 651255905 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 973411350 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 973411350 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1624667255 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1624667255 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805245 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805245 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956520 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956520 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858830 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858830 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14580.215956 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14580.215956 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25980.324988 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25980.324988 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99672 # number of read accesses completed -system.cpu5.num_writes 54824 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22459 # number of replacements -system.cpu5.l1c.tags.tagsinuse 393.671106 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13533 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22853 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.592176 # Average number of references to valid blocks. +system.cpu5.num_reads 99495 # number of read accesses completed +system.cpu5.num_writes 54912 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22132 # number of replacements +system.cpu5.l1c.tags.tagsinuse 389.508075 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13369 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22545 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.592992 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 393.671106 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.768889 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.768889 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337969 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337969 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8696 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8696 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1170 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9866 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9866 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9866 # number of overall hits -system.cpu5.l1c.overall_hits::total 9866 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36658 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36658 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23786 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23786 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60444 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60444 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60444 # number of overall misses -system.cpu5.l1c.overall_misses::total 60444 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 958216057 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 958216057 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 885896912 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 885896912 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1844112969 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1844112969 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1844112969 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1844112969 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45354 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45354 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24956 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24956 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70310 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70310 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808264 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808264 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953117 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.953117 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859679 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859679 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859679 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859679 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26139.343581 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 26139.343581 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37244.467838 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 37244.467838 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 30509.446248 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 30509.446248 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 30509.446248 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 30509.446248 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1026604 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 389.508075 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.760758 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.760758 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 409 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.806641 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337023 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337023 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8615 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8615 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1193 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1193 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9808 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9808 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9808 # number of overall hits +system.cpu5.l1c.overall_hits::total 9808 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36426 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36426 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23853 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23853 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60279 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60279 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60279 # number of overall misses +system.cpu5.l1c.overall_misses::total 60279 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 593740716 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 593740716 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 656837719 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 656837719 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1250578435 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1250578435 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1250578435 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1250578435 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45041 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45041 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25046 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25046 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70087 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70087 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70087 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70087 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808730 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808730 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952368 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952368 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860060 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860060 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860060 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860060 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16299.915335 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16299.915335 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27536.901815 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 27536.901815 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20746.502679 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20746.502679 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20746.502679 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20746.502679 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 781949 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 63359 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66475 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.202970 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.763054 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9812 # number of writebacks -system.cpu5.l1c.writebacks::total 9812 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36658 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36658 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23786 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23786 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60444 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60444 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60444 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60444 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 879872261 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 879872261 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 835586106 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 835586106 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1715458367 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1715458367 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1715458367 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1715458367 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 707107291 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 707107291 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1680181552 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1680181552 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2387288843 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2387288843 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808264 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808264 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953117 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953117 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859679 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859679 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24002.189454 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24002.189454 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35129.324224 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35129.324224 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9742 # number of writebacks +system.cpu5.l1c.writebacks::total 9742 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36426 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36426 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23853 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23853 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60279 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60279 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60279 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60279 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 536794980 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 536794980 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 620108209 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 620108209 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156903189 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1156903189 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156903189 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1156903189 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648821919 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648821919 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 955346733 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 955346733 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1604168652 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1604168652 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808730 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808730 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952368 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952368 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860060 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860060 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14736.588700 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14736.588700 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 25997.074121 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 25997.074121 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99511 # number of read accesses completed -system.cpu6.num_writes 54977 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22541 # number of replacements -system.cpu6.l1c.tags.tagsinuse 393.448229 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13464 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.586948 # Average number of references to valid blocks. +system.cpu6.num_reads 99492 # number of read accesses completed +system.cpu6.num_writes 55188 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22041 # number of replacements +system.cpu6.l1c.tags.tagsinuse 390.749630 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13460 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22445 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.599688 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 393.448229 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.768454 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.768454 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337704 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337704 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8641 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8641 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1220 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1220 # number of WriteReq hits +system.cpu6.l1c.tags.occ_blocks::cpu6 390.749630 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.763183 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.763183 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337459 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337459 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8703 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8703 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1158 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1158 # number of WriteReq hits system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits system.cpu6.l1c.overall_hits::total 9861 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36671 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36671 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23713 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23713 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60384 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60384 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60384 # number of overall misses -system.cpu6.l1c.overall_misses::total 60384 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 960694665 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 960694665 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 879536054 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 879536054 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1840230719 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1840230719 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1840230719 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1840230719 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45312 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45312 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24933 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24933 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70245 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70245 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70245 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70245 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.809300 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.809300 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951069 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.951069 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859620 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859620 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26197.667503 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 26197.667503 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37090.880698 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 37090.880698 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 30475.468982 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 30475.468982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 30475.468982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 30475.468982 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1019991 # number of cycles access was blocked +system.cpu6.l1c.ReadReq_misses::cpu6 36430 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36430 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23907 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23907 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60337 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60337 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60337 # number of overall misses +system.cpu6.l1c.overall_misses::total 60337 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 592106528 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 592106528 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 650271582 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 650271582 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1242378110 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1242378110 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1242378110 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1242378110 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45133 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45133 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25065 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25065 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70198 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70198 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70198 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70198 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807170 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807170 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953800 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953800 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859526 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859526 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859526 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859526 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16253.267307 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16253.267307 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27200.049442 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 27200.049442 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 20590.651010 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 20590.651010 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 20590.651010 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 20590.651010 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 773385 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62969 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66167 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.198304 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.688379 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9771 # number of writebacks -system.cpu6.l1c.writebacks::total 9771 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36671 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36671 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23713 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23713 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60384 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60384 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60384 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60384 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 882425777 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 882425777 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 829351266 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 829351266 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1711777043 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1711777043 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1711777043 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1711777043 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702299487 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702299487 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1717296024 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1717296024 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2419595511 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2419595511 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.809300 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.809300 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951069 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951069 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24063.313708 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24063.313708 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34974.539957 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34974.539957 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9775 # number of writebacks +system.cpu6.l1c.writebacks::total 9775 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36430 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36430 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23907 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23907 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60337 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60337 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60337 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60337 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 535158836 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 535158836 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 613445646 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 613445646 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1148604482 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1148604482 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148604482 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1148604482 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 648116847 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 648116847 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 997038722 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 997038722 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1645155569 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1645155569 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807170 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807170 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953800 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953800 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859526 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859526 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14690.058633 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14690.058633 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25659.666458 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25659.666458 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98836 # number of read accesses completed -system.cpu7.num_writes 54806 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22352 # number of replacements -system.cpu7.l1c.tags.tagsinuse 393.572142 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13400 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22745 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.589140 # Average number of references to valid blocks. +system.cpu7.num_reads 99953 # number of read accesses completed +system.cpu7.num_writes 55743 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22636 # number of replacements +system.cpu7.l1c.tags.tagsinuse 393.668569 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13591 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 23039 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.589913 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 393.572142 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.768696 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.768696 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 363 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 336509 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 336509 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8699 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8699 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1106 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1106 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9805 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9805 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9805 # number of overall hits -system.cpu7.l1c.overall_hits::total 9805 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36228 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36228 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23958 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23958 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60186 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60186 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60186 # number of overall misses -system.cpu7.l1c.overall_misses::total 60186 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 952764751 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 952764751 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 890612165 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 890612165 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1843376916 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1843376916 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1843376916 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1843376916 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44927 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44927 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25064 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25064 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69991 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69991 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69991 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69991 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806375 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806375 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955873 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955873 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859911 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859911 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859911 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859911 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26299.126394 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 26299.126394 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37173.894524 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 37173.894524 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 30628.001794 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 30628.001794 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 30628.001794 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 30628.001794 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1021665 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 393.668569 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.768884 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.768884 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 340053 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 340053 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8802 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8802 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1188 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9990 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9990 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9990 # number of overall hits +system.cpu7.l1c.overall_hits::total 9990 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36601 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36601 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24152 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24152 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60753 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60753 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60753 # number of overall misses +system.cpu7.l1c.overall_misses::total 60753 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 595212008 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 595212008 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 656742976 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 656742976 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1251954984 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1251954984 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1251954984 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1251954984 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45403 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45403 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25340 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25340 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70743 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70743 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70743 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70743 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806136 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.806136 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953118 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953118 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858785 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858785 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858785 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858785 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16262.178848 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16262.178848 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27192.074197 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 27192.074197 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 20607.294850 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 20607.294850 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 20607.294850 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 20607.294850 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 772653 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 62785 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66243 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.272438 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.663919 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9931 # number of writebacks -system.cpu7.l1c.writebacks::total 9931 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36228 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36228 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23958 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23958 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60186 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60186 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60186 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60186 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 875407713 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 875407713 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 839967251 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 839967251 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1715374964 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1715374964 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1715374964 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1715374964 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 702238586 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 702238586 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1694350083 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1694350083 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2396588669 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2396588669 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806375 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806375 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955873 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955873 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859911 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859911 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24163.843243 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24163.843243 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35059.990442 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35059.990442 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9979 # number of writebacks +system.cpu7.l1c.writebacks::total 9979 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36601 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36601 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24152 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24152 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60753 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60753 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60753 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60753 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 538040158 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 538040158 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 619565494 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 619565494 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1157605652 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1157605652 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1157605652 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1157605652 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639132078 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639132078 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 986824111 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 986824111 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1625956189 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1625956189 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806136 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806136 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953118 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953118 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858785 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858785 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14700.149122 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14700.149122 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25652.761428 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25652.761428 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency @@ -1037,567 +1037,566 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13277 # number of replacements -system.l2c.tags.tagsinuse 783.059977 # Cycle average of tags in use -system.l2c.tags.total_refs 151520 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14056 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.779738 # Average number of references to valid blocks. +system.l2c.tags.replacements 13510 # number of replacements +system.l2c.tags.tagsinuse 783.849989 # Cycle average of tags in use +system.l2c.tags.total_refs 151949 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14294 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.630264 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 729.095705 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.040995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.066153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.783419 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.143521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.879919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.083313 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.867349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.099602 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.712008 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006901 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006624 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006976 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.005941 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.005957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.764707 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 779 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 598 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.760742 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1976800 # Number of tag accesses -system.l2c.tags.data_accesses 1976800 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10861 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10871 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10670 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10859 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10920 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10735 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86470 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76237 # number of Writeback hits -system.l2c.Writeback_hits::total 76237 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 346 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 369 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 358 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 342 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 326 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 336 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 356 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2777 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1915 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1982 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1977 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1958 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1937 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1931 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15500 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12853 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12710 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12857 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12666 # number of demand (read+write) hits -system.l2c.demand_hits::total 101970 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12644 # number of overall hits -system.l2c.overall_hits::cpu1 12776 # number of overall hits -system.l2c.overall_hits::cpu2 12853 # number of overall hits -system.l2c.overall_hits::cpu3 12647 # number of overall hits -system.l2c.overall_hits::cpu4 12710 # number of overall hits -system.l2c.overall_hits::cpu5 12817 # number of overall hits -system.l2c.overall_hits::cpu6 12857 # number of overall hits -system.l2c.overall_hits::cpu7 12666 # number of overall hits -system.l2c.overall_hits::total 101970 # number of overall hits -system.l2c.ReadReq_misses::cpu0 765 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 708 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 735 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 684 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 695 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 674 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5719 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1992 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1980 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1951 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2012 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1975 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1990 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2015 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15885 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4350 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4268 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4371 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4368 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4431 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4387 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4359 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4476 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35010 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5115 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5100 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5076 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5166 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5071 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5054 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5150 # number of demand (read+write) misses -system.l2c.demand_misses::total 40729 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5115 # number of overall misses -system.l2c.overall_misses::cpu1 4997 # number of overall misses -system.l2c.overall_misses::cpu2 5100 # number of overall misses -system.l2c.overall_misses::cpu3 5076 # number of overall misses -system.l2c.overall_misses::cpu4 5166 # number of overall misses -system.l2c.overall_misses::cpu5 5071 # number of overall misses -system.l2c.overall_misses::cpu6 5054 # number of overall misses -system.l2c.overall_misses::cpu7 5150 # number of overall misses -system.l2c.overall_misses::total 40729 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 46620930 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 44960918 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 44432427 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 43382432 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 44487433 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 41294425 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 42419930 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 41189936 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 348788431 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 57711996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 58106496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 57659498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 57666495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 55433497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 57841495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 59041000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 57235498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 460695975 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 234061451 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 229252453 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 235963436 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 234901447 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 238651447 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 236178452 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 234894949 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 241135947 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1885039582 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 280682381 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 274213371 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 280395863 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 278283879 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 283138880 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 277472877 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 277314879 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 282325883 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2233828013 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 280682381 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 274213371 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 280395863 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 278283879 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 283138880 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 277472877 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 277314879 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 282325883 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2233828013 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11509 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11590 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11600 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11378 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11545 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11543 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11615 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11409 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 92189 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 76237 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 76237 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2336 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2320 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2370 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18662 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6250 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6183 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6353 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6345 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6331 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6345 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6296 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6407 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50510 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17759 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17773 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17953 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17723 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17876 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17888 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17911 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17816 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142699 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17953 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17723 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17876 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17888 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17911 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17816 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142699 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.066470 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.062899 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.062845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.062225 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.063664 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.059257 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.059836 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.059076 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.062036 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.852740 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.851247 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.840948 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.848945 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852395 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.859240 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.857082 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.846948 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.851195 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.696000 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.690280 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.688021 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.688416 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.699889 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.691411 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.692344 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.698611 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.693130 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.288023 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.281157 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.284075 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.286407 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.288991 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.283486 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.282173 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.289066 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.285419 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.288023 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.281157 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.284075 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.286407 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.288991 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.283486 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.282173 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.289066 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.285419 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60942.392157 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 61674.784636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 60949.831276 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 61274.621469 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 60527.119728 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 60371.966374 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61035.870504 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 61112.664688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 60987.660605 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28971.885542 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 29346.715152 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29553.817529 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 28661.279821 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28067.593418 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29066.077889 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29300.744417 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29053.552284 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29001.949953 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53807.230115 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53714.257966 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53983.856326 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53777.803800 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53859.500564 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53835.981764 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53887.347786 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53873.089142 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53842.890089 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54874.365787 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54875.599560 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54979.580980 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54823.459220 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54808.145567 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54717.585683 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54870.375742 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54820.559806 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54846.129613 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54874.365787 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54875.599560 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54979.580980 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54823.459220 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54808.145567 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54717.585683 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54870.375742 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54820.559806 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54846.129613 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 11130 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 725.717756 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.606207 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.042760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.314362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.280142 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.903512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.337678 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.211948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.435623 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.708709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007428 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006878 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007143 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006742 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765479 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 680 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1986932 # Number of tag accesses +system.l2c.tags.data_accesses 1986932 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10772 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10720 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10796 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10828 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10876 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10784 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10741 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86242 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77037 # number of Writeback hits +system.l2c.Writeback_hits::total 77037 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 331 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 373 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 321 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 366 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2816 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2031 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1999 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1974 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2000 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1993 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1980 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1967 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1970 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15914 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12803 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12770 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12828 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12869 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12764 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12711 # number of demand (read+write) hits +system.l2c.demand_hits::total 102156 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12803 # number of overall hits +system.l2c.overall_hits::cpu1 12719 # number of overall hits +system.l2c.overall_hits::cpu2 12770 # number of overall hits +system.l2c.overall_hits::cpu3 12828 # number of overall hits +system.l2c.overall_hits::cpu4 12869 # number of overall hits +system.l2c.overall_hits::cpu5 12764 # number of overall hits +system.l2c.overall_hits::cpu6 12692 # number of overall hits +system.l2c.overall_hits::cpu7 12711 # number of overall hits +system.l2c.overall_hits::total 102156 # number of overall hits +system.l2c.ReadReq_misses::cpu0 731 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 674 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 746 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 694 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 702 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 746 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 727 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5742 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1949 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2075 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2001 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2024 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1976 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1982 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1991 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1901 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15899 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4324 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4508 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4412 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4451 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4429 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4405 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 35131 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5104 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 4998 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5254 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5106 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5153 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5175 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 4951 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5132 # number of demand (read+write) misses +system.l2c.demand_misses::total 40873 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5104 # number of overall misses +system.l2c.overall_misses::cpu1 4998 # number of overall misses +system.l2c.overall_misses::cpu2 5254 # number of overall misses +system.l2c.overall_misses::cpu3 5106 # number of overall misses +system.l2c.overall_misses::cpu4 5153 # number of overall misses +system.l2c.overall_misses::cpu5 5175 # number of overall misses +system.l2c.overall_misses::cpu6 4951 # number of overall misses +system.l2c.overall_misses::cpu7 5132 # number of overall misses +system.l2c.overall_misses::total 40873 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 45095926 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 41549422 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 46449929 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 42922928 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 43252423 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 45919927 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 44260438 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 44979437 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 354430430 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 56379995 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 59258495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 58685995 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 56511495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 59771492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 56753497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 61514994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 54850495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 463726458 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 240858936 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 238452262 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 247966448 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 242840437 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 244973443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 243557270 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 233129438 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 242077945 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1933856179 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 285954862 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 280001684 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 294416377 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 285763365 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 288225866 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 289477197 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 277389876 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 287057382 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2288286609 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 285954862 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 280001684 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 294416377 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 285763365 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 288225866 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 289477197 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 277389876 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 287057382 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2288286609 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11503 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11394 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11542 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11522 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11578 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11530 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11447 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11468 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91984 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77037 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77037 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2280 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2448 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2364 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2377 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2297 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2345 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2337 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2267 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18715 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6404 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6482 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6444 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6409 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6196 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6375 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51045 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17907 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18024 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17934 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17939 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17843 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143029 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17907 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18024 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17934 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17939 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17843 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143029 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.063549 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.059154 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.064634 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060233 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.060632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.064701 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.063073 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.063394 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.062424 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.854825 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.847631 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.846447 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.851493 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.860253 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.845203 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.851947 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.838553 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849532 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.682854 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.683853 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.695464 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.688085 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.690720 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.691059 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.682537 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.690980 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.688236 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.285028 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.282102 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.291500 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.284711 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.285928 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.288478 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.280621 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.287620 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.285767 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.285028 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.282102 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.291500 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.284711 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.285928 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.288478 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.280621 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.287620 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.285767 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 61690.733242 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61646.026706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 62265.320375 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61848.599424 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61613.138177 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61554.861930 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61302.545706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 61869.927098 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61725.954371 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28927.652642 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28558.310843 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29328.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27920.699111 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 30248.730769 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28634.458628 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 30896.531391 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 28853.495529 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29167.020442 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55078.649897 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55146.221554 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55005.866903 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55040.896872 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55037.843855 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54991.481147 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55126.374557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54955.265607 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55047.000626 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56025.639107 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56022.745898 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56036.615341 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55966.189777 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55933.604890 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55937.622609 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56027.040194 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55934.797740 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55985.286350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56025.639107 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56022.745898 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56036.615341 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55966.189777 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55933.604890 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55937.622609 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56027.040194 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55934.797740 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55985.286350 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17581 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1567 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3250 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.102744 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.409538 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6229 # number of writebacks -system.l2c.writebacks::total 6229 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 11 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6423 # number of writebacks +system.l2c.writebacks::total 6423 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 21 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 39 # number of ReadExReq MSHR hits system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 758 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 722 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 718 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 704 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 730 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 673 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 692 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 669 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5666 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1992 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1980 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1951 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2012 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1974 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1990 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2015 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1969 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15883 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4346 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4265 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4369 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4364 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4430 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4383 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4358 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4474 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34989 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5104 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4987 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5087 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5068 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5160 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5050 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5143 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40655 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5104 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4987 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5087 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5068 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5160 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5056 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5050 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5143 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40655 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 37179930 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 35966920 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 35314428 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 34763932 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 35492434 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 32731425 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 33928930 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 32969437 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 278347436 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81798995 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81126494 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80135996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 82599489 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81068996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81609993 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82618495 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80871496 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 651829954 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 181281952 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 177509453 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 183001436 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 181913947 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 184978447 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 182997452 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 182077949 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 186899447 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1460660083 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 218461882 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 213476373 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 218315864 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 216677879 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 220470881 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 215728877 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 216006879 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 219868884 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1739007519 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 218461882 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 213476373 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 218315864 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 216677879 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 220470881 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 215728877 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 216006879 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 219868884 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1739007519 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 407707447 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 401123946 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 397019445 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 405812955 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407128948 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 410535950 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 408564954 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406637950 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3244531595 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 230392811 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237768794 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 237208468 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229246463 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 232269476 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230268468 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 234242974 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 227836970 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1859234424 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 638100258 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 638892740 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 634227913 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 635059418 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 639398424 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 640804418 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 642807928 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 634474920 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5103766019 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.065861 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.062295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.061897 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061874 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063231 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058304 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059578 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.058638 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.061461 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852740 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.851247 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.840948 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.848945 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.851964 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.859240 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.857082 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.846518 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.851088 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.695360 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689795 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.687707 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687786 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.699731 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690780 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.692186 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.698299 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.692714 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284900 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284900 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49050.039578 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49815.678670 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49184.440111 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49380.585227 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48619.772603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48635.104012 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49030.245665 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49281.669656 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49125.915284 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41063.752510 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40972.976768 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41074.318811 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41053.423956 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41068.387031 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41010.046734 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41001.734491 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41072.369731 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41039.473273 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41712.368155 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41620.035873 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41886.343786 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41685.139093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41755.857111 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41751.643167 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41780.162689 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41774.574654 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41746.265483 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 100 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 725 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 661 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 738 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 690 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 692 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 741 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 711 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 723 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5681 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1949 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2074 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2001 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2023 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1976 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1982 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1991 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1901 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15897 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4368 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4317 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4505 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4406 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4442 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4423 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4402 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 35092 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5093 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 4978 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5096 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5134 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5164 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4940 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5125 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40773 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5093 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 4978 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5243 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5096 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5134 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5164 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4940 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5125 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40773 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 36140918 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 33131910 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 37333917 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 34463914 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 34507911 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 36862423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 35293427 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 36098935 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 283833355 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 82188451 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 87682473 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 84603955 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 85652462 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 83560954 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83969963 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 84367474 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80329284 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 672355016 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 188025870 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 186115345 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 193429372 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189404867 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 191140359 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 189945201 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 182082372 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 188836863 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1508980249 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 224166788 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 219247255 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 230763289 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 223868781 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 225648270 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 226807624 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 217375799 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 224935798 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1792813604 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 224166788 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 219247255 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 230763289 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 223868781 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 225648270 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 226807624 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 217375799 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 224935798 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1792813604 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 419997297 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 420394389 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 416554764 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 421667758 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 426680271 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 424776767 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 425015068 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 419160275 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3374246589 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 245735705 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 245037892 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 243130891 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 240328902 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 241689545 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 236933897 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 244635896 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 245230718 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1942723446 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 665733002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 665432281 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 659685655 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 661996660 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 668369816 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 661710664 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 669650964 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 664390993 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5316970035 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.063027 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.058013 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.063940 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059885 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.059769 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.064267 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.062112 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063045 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.061761 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854825 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847222 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.846447 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851073 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.860253 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845203 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.851947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838553 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.849426 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.682074 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682746 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.695002 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687149 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.689323 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690123 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.682537 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.690510 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.687472 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285068 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285068 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49849.542069 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50123.918306 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50587.963415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49947.701449 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49866.923410 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49746.859649 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49639.137834 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49929.370678 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49961.864989 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42169.548999 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42276.987946 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42280.837081 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42339.328720 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42287.932186 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42366.278002 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42374.421899 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42256.330352 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42294.459080 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43046.215659 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43112.194811 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42936.597558 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42987.940763 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43030.247411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42944.879267 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43055.656656 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42897.969786 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43000.691012 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -1626,64 +1625,64 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 84242 # Transaction distribution -system.membus.trans_dist::ReadResp 84239 # Transaction distribution -system.membus.trans_dist::WriteReq 43998 # Transaction distribution -system.membus.trans_dist::WriteResp 43998 # Transaction distribution -system.membus.trans_dist::Writeback 6229 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58563 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47765 # Transaction distribution -system.membus.trans_dist::ReadExReq 50044 # Transaction distribution -system.membus.trans_dist::ReadExResp 3111 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 422189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 422189 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1082703 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1082703 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57731 # Total snoops (count) -system.membus.snoop_fanout::samples 123701 # Request fanout histogram +system.membus.trans_dist::ReadReq 84922 # Transaction distribution +system.membus.trans_dist::ReadResp 84916 # Transaction distribution +system.membus.trans_dist::WriteReq 43774 # Transaction distribution +system.membus.trans_dist::WriteResp 43771 # Transaction distribution +system.membus.trans_dist::Writeback 6423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58524 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47755 # Transaction distribution +system.membus.trans_dist::ReadExReq 50059 # Transaction distribution +system.membus.trans_dist::ReadExResp 3238 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 423382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 423382 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1104141 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1104141 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57586 # Total snoops (count) +system.membus.snoop_fanout::samples 124108 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123701 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 124108 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123701 # Request fanout histogram -system.membus.reqLayer0.occupancy 290076020 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 43.5 # Layer utilization (%) -system.membus.respLayer0.occupancy 312416500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 46.8 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 371224 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371216 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43998 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43997 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 76237 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29460 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29459 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161009 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161004 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120675 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121112 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120671 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120387 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120891 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120940 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120505 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 965857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1759071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1770038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776630 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1763929 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1758071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1768584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1767034 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1770802 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14134159 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 321748 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 561380 # Request fanout histogram +system.membus.snoop_fanout::total 124108 # Request fanout histogram +system.membus.reqLayer0.occupancy 285888056 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 60.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 306910429 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 64.5 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 371514 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371497 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43774 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43771 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 77037 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29480 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29478 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162492 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162484 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121222 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 121316 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 121170 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 121269 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120825 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 121366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 969045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1773466 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1761542 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1792162 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785037 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1774053 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1756466 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1780883 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14206666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322486 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 565861 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1694,29 +1693,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 561380 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 565861 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 561380 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 655414034 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 160915376 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 161401861 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 160885313 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 160977419 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 160313901 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 24.0 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 161018393 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 160998320 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 160391036 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 24.0 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 565861 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 447470354 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 94.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102002382 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101806870 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101634818 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101702738 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101696707 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101422885 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101516818 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101999422 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt index 0808c4e4e..5b3332128 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 8581932612 # Simulator tick rate (ticks/s) -host_mem_usage 264172 # Number of bytes of host memory used -host_seconds 11.65 # Real time elapsed on the host +host_tick_rate 8616438631 # Simulator tick rate (ticks/s) +host_mem_usage 263800 # Number of bytes of host memory used +host_seconds 11.61 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 106649408 # Number of bytes read from this memory @@ -278,15 +278,15 @@ system.cpu.retryTicks 0 # Ti system.membus.trans_dist::ReadReq 1666397 # Transaction distribution system.membus.trans_dist::ReadResp 1666397 # Transaction distribution system.membus.trans_dist::WriteReq 1666879 # Transaction distribution -system.membus.trans_dist::WriteResp 1666879 # Transaction distribution -system.membus.pkt_count_system.monitor-master::system.physmem.port 6666552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 6666552 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::WriteResp 1666878 # Transaction distribution +system.membus.pkt_count_system.monitor-master::system.physmem.port 6666551 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 6666551 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.monitor-master::system.physmem.port 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 213329664 # Cumulative packet size per connected master and slave (bytes) system.membus.reqLayer0.occupancy 11679751447 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 11.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 11428907481 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 11.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 11028299087 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 11.0 # Layer utilization (%) system.monitor.readBurstLengthHist::samples 1666397 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets @@ -339,8 +339,8 @@ system.monitor.writeBurstLengthHist::76-79 0 0.00% 100.00% # system.monitor.writeBurstLengthHist::total 1666879 # Histogram of burst lengths of transmitted packets system.monitor.readBandwidthHist::samples 100 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::mean 1066494080 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::gmean 1063154535.263763 # Histogram of read bandwidth per sample period (bytes/s) -system.monitor.readBandwidthHist::stdev 107915844.091091 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::gmean 1063154851.723305 # Histogram of read bandwidth per sample period (bytes/s) +system.monitor.readBandwidthHist::stdev 107909478.113936 # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::0-1.34218e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::1.34218e+08-2.68435e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) system.monitor.readBandwidthHist::2.68435e+08-4.02653e+08 0 0.00% 0.00% # Histogram of read bandwidth per sample period (bytes/s) @@ -392,55 +392,55 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 1066802560 0.00% 0.00% # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 106680256 # Number of bytes written system.monitor.readLatencyHist::samples 1666397 # Read request-response latency -system.monitor.readLatencyHist::mean 75229.617239 # Read request-response latency -system.monitor.readLatencyHist::gmean 69644.568825 # Read request-response latency -system.monitor.readLatencyHist::stdev 40693.683003 # Read request-response latency +system.monitor.readLatencyHist::mean 78736.863581 # Read request-response latency +system.monitor.readLatencyHist::gmean 73318.978124 # Read request-response latency +system.monitor.readLatencyHist::stdev 40691.515724 # Read request-response latency system.monitor.readLatencyHist::0-32767 22 0.00% 0.00% # Read request-response latency -system.monitor.readLatencyHist::32768-65535 444791 26.69% 26.69% # Read request-response latency -system.monitor.readLatencyHist::65536-98303 1023501 61.42% 88.11% # Read request-response latency -system.monitor.readLatencyHist::98304-131071 76998 4.62% 92.73% # Read request-response latency -system.monitor.readLatencyHist::131072-163839 56964 3.42% 96.15% # Read request-response latency -system.monitor.readLatencyHist::163840-196607 25239 1.51% 97.67% # Read request-response latency -system.monitor.readLatencyHist::196608-229375 9180 0.55% 98.22% # Read request-response latency -system.monitor.readLatencyHist::229376-262143 7794 0.47% 98.69% # Read request-response latency -system.monitor.readLatencyHist::262144-294911 7780 0.47% 99.15% # Read request-response latency -system.monitor.readLatencyHist::294912-327679 7547 0.45% 99.61% # Read request-response latency -system.monitor.readLatencyHist::327680-360447 3313 0.20% 99.80% # Read request-response latency -system.monitor.readLatencyHist::360448-393215 1429 0.09% 99.89% # Read request-response latency -system.monitor.readLatencyHist::393216-425983 850 0.05% 99.94% # Read request-response latency -system.monitor.readLatencyHist::425984-458751 662 0.04% 99.98% # Read request-response latency -system.monitor.readLatencyHist::458752-491519 284 0.02% 100.00% # Read request-response latency -system.monitor.readLatencyHist::491520-524287 42 0.00% 100.00% # Read request-response latency -system.monitor.readLatencyHist::524288-557055 1 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::32768-65535 439224 26.36% 26.36% # Read request-response latency +system.monitor.readLatencyHist::65536-98303 1018381 61.11% 87.47% # Read request-response latency +system.monitor.readLatencyHist::98304-131071 80826 4.85% 92.32% # Read request-response latency +system.monitor.readLatencyHist::131072-163839 59766 3.59% 95.91% # Read request-response latency +system.monitor.readLatencyHist::163840-196607 27643 1.66% 97.57% # Read request-response latency +system.monitor.readLatencyHist::196608-229375 9933 0.60% 98.16% # Read request-response latency +system.monitor.readLatencyHist::229376-262143 7785 0.47% 98.63% # Read request-response latency +system.monitor.readLatencyHist::262144-294911 7834 0.47% 99.10% # Read request-response latency +system.monitor.readLatencyHist::294912-327679 7851 0.47% 99.57% # Read request-response latency +system.monitor.readLatencyHist::327680-360447 3709 0.22% 99.79% # Read request-response latency +system.monitor.readLatencyHist::360448-393215 1488 0.09% 99.88% # Read request-response latency +system.monitor.readLatencyHist::393216-425983 851 0.05% 99.93% # Read request-response latency +system.monitor.readLatencyHist::425984-458751 701 0.04% 99.98% # Read request-response latency +system.monitor.readLatencyHist::458752-491519 330 0.02% 100.00% # Read request-response latency +system.monitor.readLatencyHist::491520-524287 51 0.00% 100.00% # Read request-response latency +system.monitor.readLatencyHist::524288-557055 2 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::557056-589823 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::589824-622591 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::622592-655359 0 0.00% 100.00% # Read request-response latency system.monitor.readLatencyHist::total 1666397 # Read request-response latency -system.monitor.writeLatencyHist::samples 1666879 # Write request-response latency -system.monitor.writeLatencyHist::mean 10556.022655 # Write request-response latency -system.monitor.writeLatencyHist::gmean 10498.307841 # Write request-response latency -system.monitor.writeLatencyHist::stdev 1185.079839 # Write request-response latency -system.monitor.writeLatencyHist::0-1023 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::1024-2047 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::2048-3071 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::3072-4095 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::4096-5119 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::5120-6143 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::6144-7167 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::7168-8191 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::8192-9215 0 0.00% 0.00% # Write request-response latency -system.monitor.writeLatencyHist::9216-10239 1276777 76.60% 76.60% # Write request-response latency -system.monitor.writeLatencyHist::10240-11263 91385 5.48% 82.08% # Write request-response latency -system.monitor.writeLatencyHist::11264-12287 111087 6.66% 88.74% # Write request-response latency -system.monitor.writeLatencyHist::12288-13311 90448 5.43% 94.17% # Write request-response latency -system.monitor.writeLatencyHist::13312-14335 61415 3.68% 97.85% # Write request-response latency -system.monitor.writeLatencyHist::14336-15359 31809 1.91% 99.76% # Write request-response latency -system.monitor.writeLatencyHist::15360-16383 3958 0.24% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::16384-17407 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::17408-18431 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::18432-19455 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::19456-20479 0 0.00% 100.00% # Write request-response latency -system.monitor.writeLatencyHist::total 1666879 # Write request-response latency +system.monitor.writeLatencyHist::samples 1666878 # Write request-response latency +system.monitor.writeLatencyHist::mean 17579.367741 # Write request-response latency +system.monitor.writeLatencyHist::gmean 17571.346759 # Write request-response latency +system.monitor.writeLatencyHist::stdev 555.431458 # Write request-response latency +system.monitor.writeLatencyHist::0-2047 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::2048-4095 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::4096-6143 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::6144-8191 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::8192-10239 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::10240-12287 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::12288-14335 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::14336-16383 0 0.00% 0.00% # Write request-response latency +system.monitor.writeLatencyHist::16384-18431 1620268 97.20% 97.20% # Write request-response latency +system.monitor.writeLatencyHist::18432-20479 30675 1.84% 99.04% # Write request-response latency +system.monitor.writeLatencyHist::20480-22527 12936 0.78% 99.82% # Write request-response latency +system.monitor.writeLatencyHist::22528-24575 2999 0.18% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::24576-26623 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::26624-28671 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::28672-30719 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::30720-32767 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::32768-34815 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::34816-36863 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::36864-38911 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::38912-40959 0 0.00% 100.00% # Write request-response latency +system.monitor.writeLatencyHist::total 1666878 # Write request-response latency system.monitor.ittReadRead::samples 1666396 # Read-to-read inter transaction time system.monitor.ittReadRead::mean 60009.683149 # Read-to-read inter transaction time system.monitor.ittReadRead::stdev 42949.620471 # Read-to-read inter transaction time @@ -526,12 +526,12 @@ system.monitor.ittReqReq::min_value 28000 # Re system.monitor.ittReqReq::max_value 1041309 # Request-to-request inter transaction time system.monitor.ittReqReq::total 3333275 # Request-to-request inter transaction time system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions -system.monitor.outstandingReadsHist::mean 1.210000 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 1.260000 # Outstanding read transactions system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions -system.monitor.outstandingReadsHist::stdev 1.281532 # Outstanding read transactions -system.monitor.outstandingReadsHist::0 27 27.00% 27.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::1 46 46.00% 73.00% # Outstanding read transactions -system.monitor.outstandingReadsHist::2 18 18.00% 91.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 1.284091 # Outstanding read transactions +system.monitor.outstandingReadsHist::0 26 26.00% 26.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 43 43.00% 69.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 22 22.00% 91.00% # Outstanding read transactions system.monitor.outstandingReadsHist::3 4 4.00% 95.00% # Outstanding read transactions system.monitor.outstandingReadsHist::4 1 1.00% 96.00% # Outstanding read transactions system.monitor.outstandingReadsHist::5 3 3.00% 99.00% # Outstanding read transactions @@ -551,11 +551,11 @@ system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Ou system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions -system.monitor.outstandingWritesHist::mean 0.190000 # Outstanding write transactions +system.monitor.outstandingWritesHist::mean 0.320000 # Outstanding write transactions system.monitor.outstandingWritesHist::gmean 0 # Outstanding write transactions -system.monitor.outstandingWritesHist::stdev 0.394277 # Outstanding write transactions -system.monitor.outstandingWritesHist::0 81 81.00% 81.00% # Outstanding write transactions -system.monitor.outstandingWritesHist::1 19 19.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::stdev 0.468826 # Outstanding write transactions +system.monitor.outstandingWritesHist::0 68 68.00% 68.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::1 32 32.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions -- 2.30.2